Electrical circuit carrier plate structure based on surface layer of metal substrate core and preparation method of electrical circuit carrier plate structure

Abstract

The invention discloses an electrical circuit carrier plate structure based on a metal substrate core surface layer and a preparation method thereof, the electrical circuit carrier plate structure comprises a metal core plate embedded with an upper half plastic package layer and a lower half plastic package layer, and the upper half surface of the metal core plate is sequentially provided with a first front insulation layer, a second front insulation layer and a third front insulation layer from bottom to top. A first front surface conductive layer is embedded in the first front surface insulating layer and the second front surface insulating layer, a first front surface metal layer is adaptively arranged on the front surface of the first front surface conductive layer, a second front surface conductive layer is embedded in the third front surface insulating layer, and a second front surface metal layer is adaptively arranged on the front surface of the second front surface conductive layer. According to the electrical circuit carrier plate structure based on the surface layer of the metal substrate core, the number of I / O required by multiple functions can be effectively maintained, the direct heat dissipation capability better than that of an organic substrate is provided, the manufacturing method shortens the technological process, and meanwhile the effects of multiple functions, high wire number, high heat dissipation and low cost can be achieved.

Description

Technical Field

[0001] The present invention relates to an electrical circuit carrier structure based on the surface of a metal substrate core and a preparation method thereof, and more particularly to a structure and method for manufacturing a single-layer or multi-layer circuit carrier on the surface of a completed metal hollow lead frame. The present invention relates to a structure and method for manufacturing a single-layer or multi-layer circuit carrier on the surface of a completed metal core board, wherein the graphic structure of the hollow of the metal lead frame is filled with thermosetting epoxy resin, and then UV light-curing insulating ink is sprayed on the surface of the copper-based metal lead frame, supplemented by copper electroplating technology, to achieve the preparation of a single-sided single-layer or multi-layer, double-sided single-layer or multi-layer circuit interconnection structure using a metal material as the surface of the substrate core. The present invention belongs to the field of semiconductor chip packaging. Background Art

[0002] The structure of the traditional metal hollow lead frame only has a pin structure and is a single-layer structure (such as Figure 1 The metal hollow lead frame is manufactured by die punching and chemical etching, which has a simple structure but cannot produce structurally complex and high-density multi-layer circuits.

[0003] In the existing traditional technology, the metal hollow lead frame is made by chemical etching: metal copper sheet → coating with photoresist film → mask shielding → UV exposure → chemical development → chemical dissolution of the part to be etched → chemical etching → removal of photoresist film → cleaning / drying → coating with photoresist film → mask shielding → UV exposure → chemical development → chemical dissolution of the part to be electroplated → surface electroplating (such as silver, gold, nickel / palladium / gold) → removal of photoresist film → cleaning / drying → surface treatment (such as soaking in antioxidant). There are about 18 main processes (different requirements may increase or decrease), The surface graphics can be varied, and the production cycle of new design layouts is short, with finished products available in about 20 days, making it suitable for small-scale and diversified production. However, there are certain shortcomings: 1) A single-layer structure requires about 18 steps to produce, which is a complex process. 2) Due to the complex process, a wide variety of equipment and materials are used, the production space is large, and the labor force is high, resulting in high production and management costs. 3) The chemically etched hollow metal lead frame has an etching depth-to-width ratio of approximately 1:2 or above (1 times the material thickness / 2 times the material thickness of the etching width), making it difficult to produce high-density spacing.

[0004] The structure and production process of traditional organic circuit substrates are relatively complex. They can present high-density circuit spacing and can also achieve complex graphics of multi-layer circuits (such as Figure 2 The structure of a traditional organic substrate is basically divided into the chip side, the core side, and the solder ball side. That is, multiple circuit layers are manufactured starting from the core side (Core) toward the chip side (Top side) and the solder ball side (Bottom side).

[0005] In the existing traditional technology, the main production process of a two-layer metal circuit organic substrate is as follows: First, preparation work: metal core board (BT or FR4) → coating upper prepreg (PP) → gluing upper copper foil → coating lower prepreg (PP) → gluing lower copper foil → lamination baking (high temperature and high pressure baking) → cleaning → optical inspection (AOI) → drilling (interconnecting the first layer of copper foil and the second layer of copper foil of the core board) → cleaning interconnection holes → chemical copper deposition interconnection holes → drawing circuit mask template for photolithography → making circuit mask template → optical inspection (AOI), there are 14 main processes (different requirements may vary). Increase or decrease); Secondly, the interconnection between the first and second metal layers: coating with photoresist film → covering with circuit mask → UV lithography (exposure) → chemical development → chemical dissolution of the parts that need to be chemically etched → chemical etching → chemical removal of photoresist film → roughening of metal lines (chemical micro-etching) → optical inspection (AOI) → coating with insulating film → pasting the second layer of copper foil → lamination and baking (high temperature and high pressure baking) → drilling (interconnection between the first and second layers of metal copper foil) → cleaning of interconnection holes → coating with prepreg → covering with mask → UV lithography → chemical development → chemical dissolution of the parts that need to be chemically deposited copper → baking the prepreg → chemical deposition Copper interconnect hole → solder mask coating → surface treatment (such as immersion gold, OSP) → optical inspection (AOI) → electrical circuit testing → dry packaging / warehousing, there are 25 main processes (different requirements may increase or decrease), although the etching technology depth-to-width ratio is 1:2 (1 times the material thickness / 2 times the material thickness of the etching width), because the thickness of the copper foil is about 10μm, it can produce a line pitch within 50μm or even within 20μm. Because of the use of multi-layer prepreg and ultra-thin copper foil lamination, it can produce a thickness of about 30μm per layer; however, there are certain shortcomings: 1) The existing organic substrate structure contains core 1) The thickness of the core board is 50 to 100 μm, which increases according to the process requirements, thereby increasing the overall thickness; 2) The lamination process must not only be carried out under high temperature and high pressure, but also in a vacuum environment to prevent bubbles from appearing between layers or surface oxidation of the metal copper foil; 3) The core board of the organic substrate may have different upper and lower layers or uneven circuit density, resulting in warping or distortion of the organic substrate; 4) The total process for double-layer and multi-layer circuits is no less than 39, which is too complicated, with very high management costs and more difficult to control quality; 5) The overall process is complex, and the overall cost of the organic substrate is high, which is at least 5 times higher than that of the chemically etched metal lead frame.

[0006] Given the high-computing power of artificial intelligence, high-G communications, the Internet of Things, new energy storage, high-load data storage, and data centers, all require the use of numerous I / O multi-layer circuits and high heat dissipation capabilities in chip packaging. However, the existing organic substrate structure and working methods of traditional technologies, with their physical properties of 0.3-5W / mK thermal conductivity, are increasingly unable to cope with the increasing functionality, increasing density, and increasing heat dissipation capabilities. Limited by the structure and manufacturing methods of traditional technologies, the organic substrate sales market has also experienced increasing price pressure, significantly reducing economic benefits. Therefore, there is an urgent need for an electrical circuit substrate structure based on the surface of a metal substrate core and its preparation method to solve the above problems. Summary of the Invention

[0007] To address at least one of the aforementioned problems with the prior art, the present invention provides an electrical circuit carrier structure based on a metal substrate core surface layer and a method for fabricating the same. These structures can effectively maintain the number of I / Os required for multi-functions and provide better direct heat dissipation capabilities than organic substrates. Furthermore, the fabrication method shortens the process steps while also achieving multi-functions, a high line count, high heat dissipation, and low cost.

[0008] To achieve the above objectives, the present invention adopts the following technical solution: an electrical circuit carrier structure based on a metal substrate core surface layer, comprising: a metal core board, an upper half layer of the metal core board being embedded with an upper half layer of plastic sealing layer, a lower half layer of the metal core board being embedded with a lower half layer of plastic sealing layer, and the upper half layer of plastic sealing layer being connected to the lower half layer of plastic sealing layer;

[0009] The upper half surface of the metal core board is provided with a first front insulating layer, a second front insulating layer and a third front insulating layer in sequence from bottom to top. The first front insulating layer is connected to the upper half plastic sealing layer. The first front insulating layer and the second front insulating layer are embedded with a first front conductive layer. The first front conductive layer is adapted to have a first front metal layer on its front surface and is embedded in the first front insulating layer and the second front insulating layer. The third front insulating layer is embedded with a second front conductive layer. The second front conductive layer is adapted to have a second front metal layer on its front surface and is embedded in the third front insulating layer. The second front conductive layer is also connected to the first front metal layer.

[0010] Preferably, a surface treatment layer is further provided on the back surface of the metal core plate.

[0011] Preferably, the first front conductive layer includes a plurality of first conductive segments arranged at intervals, each of the first conductive segments is configured as a concave bridge-shaped structure, and the concave portion is embedded in the first front insulating layer, and the two ends are embedded in the second front insulating layer, the first front metal layer is adaptively arranged with the first front conductive layer, and the concave portion of the first front metal layer is connected to the second front insulating layer in a concave cavity.

[0012] Preferably, the second front conductive layer includes a plurality of second conductive segments arranged at intervals, each second conductive segment is in a straight-line structure, and the second front metal layer is adaptively arranged to the second front conductive layer.

[0013] Preferably, the lower half surface of the metal core board is provided with a first back insulating layer and a second back insulating layer in sequence from top to bottom, and the first back insulating layer is connected to the lower half plastic sealing layer; the first back insulating layer is embedded with a first back conductive layer and a first back metal layer in sequence from top to bottom; the back surface of the first back metal layer is connected to the second back conductive layer, and the back surface of the second back conductive layer is connected to the second back metal layer, and the second back conductive layer and the second back metal layer are embedded in the first back insulating layer and the second back insulating layer.

[0014] Preferably, the second back conductive layer includes a plurality of fourth conductive segments arranged at intervals, each of the fourth conductive segments is arranged into an arched bridge structure, and the arched portion is embedded in the first back insulating layer and the two ends are embedded in the second back insulating layer; the second back metal layer is adaptively arranged with the second back conductive layer.

[0015] Preferably, the first back conductive layer includes a plurality of third conductive segments arranged at intervals, each of the third conductive segments is in a straight line structure, and the second back metal layer is adapted to be arranged to match the second back conductive layer.

[0016] The present invention also provides a method for preparing an electrical circuit carrier structure based on a metal substrate core surface layer, comprising the following steps:

[0017] (1) Prepare metal plates;

[0018] (2) making an upper half-layer hollow pattern structure on the metal plate, cleaning and drying it to form a metal lead frame;

[0019] (3) filling the upper half of the hollow pattern structure with a plastic sealing material to form an upper half of the plastic sealing layer to obtain a metal core board;

[0020] (4) The upper and lower surfaces of the metal core board are covered with a single-layer or multi-layer circuit structure;

[0021] (5) The lower half of the metal core plate is made into a hollow graphic structure;

[0022] (6) filling the lower half of the hollow pattern structure with a plastic sealing material to form an upper half of the plastic sealing layer;

[0023] (7) IR (far infrared) baking curing;

[0024] (8) performing surface treatment on the front and / or back surface of the multi-layer circuit structure to form a surface treatment layer;

[0025] (9) Automated optical inspection;

[0026] (10) Electrical circuit testing;

[0027] (11) Dry packaging and storage.

[0028] Preferably, the order of making the lower half layer of the hollow graphic structure on the lower half layer of the metal core plate in the above step (5) can be adjusted to after making the upper half layer of the hollow graphic structure on the upper half layer of the metal plate in step (2) or after filling the upper half layer of the hollow graphic structure with plastic packaging material in step (3).

[0029] Preferably, the steps for preparing the multi-layer circuit structure coated on the upper half surface of the metal core board in step (4) are as follows:

[0030] (4-1) The non-circuit area of ​​the upper half of the surface of the metal core board is coated with insulating ink to form a first front insulating layer;

[0031] (4-2) The upper surface of the metal core board and the electrical circuit portion of the first front insulating layer are coated with conductive ink to form a first front conductive layer;

[0032] (4-3) coating a metal circuit on the first front conductive layer to form a first front metal layer;

[0033] (4-4) coating the first front insulating layer and the non-circuit areas around the first front conductive layer and the first front metal layer with insulating ink to form a second front insulating layer;

[0034] (4-5) coating the second front insulating layer and the electrical circuit portion of the second front insulating layer with conductive ink to form a second front conductive layer;

[0035] (4-6) coating a metal circuit on the second front conductive layer to form a second front metal layer;

[0036] (4-7) Insulating ink is coated on the non-circuit areas of the second front insulating layer and the second front metal layer to form a third front insulating layer.

[0037] Preferably, the method further includes step (12) covering the lower half surface of the metal core board with a multi-layer circuit structure, and adding a previous process of performing IR baking and curing in step (7), that is, a process before performing IR baking and curing in step (7) is step (12) covering the lower half surface of the metal core board with a multi-layer circuit structure.

[0038] Preferably, the steps for preparing the multi-layer circuit structure coated on the lower half surface of the metal core plate in step (12) are as follows:

[0039] (12-1) coating the electrical circuit portion of the lower half surface of the metal core board with conductive ink to form a first back conductive layer;

[0040] (12-2) coating a first layer of metal circuits on the first back conductive layer to form a first back metal layer;

[0041] (12-3) coating insulating ink on the lower half surface of the metal core board and the non-circuit portion of the first back metal layer to form a first back insulating layer;

[0042] (12-4) coating the electrical circuit portions of the first back insulating layer and the first back metal layer with conductive ink to form a second back conductive layer;

[0043] (12-5) coating the second back conductive layer with a second metal circuit to form a second back metal layer;

[0044] (12-6) A second layer of insulating ink is coated on the non-circuit areas of the first back insulating layer and the second back metal layer to form a second back insulating layer.

[0045] Preferably, the filling method of the plastic encapsulation material in the hollow graphic structure on the upper half surface and the hollow graphic structure on the lower half surface is a transfer molding method or a UV resin spraying method; when the transfer molding method is used for filling, the temperature is used according to the type and characteristics of the plastic encapsulation material, and when the UV resin spraying method is used for filling, UV light irradiation is required to be carried out simultaneously during the spraying process to quickly fix it and prevent it from flowing.

[0046] Preferably, the molding material is thermosetting epoxy resin.

[0047] Preferably, the insulating ink is coated using a UV insulating ink spraying method. The UV insulating ink adopts a precise program graphic spraying mode and is sprayed on local positions that do not need to be protected, that is, non-line positions. The thickness of the spraying is determined according to the load pressure requirement, and UV light irradiation is performed simultaneously during the spraying process to quickly fix the ink and prevent it from flowing.

[0048] Preferably, the insulating ink is UV insulating ink.

[0049] Preferably, the conductive ink is coated by spraying UV conductive ink, and the UV conductive ink adopts a precise program graphic spraying mode. The spraying thickness is adjusted according to the actual functional requirements. The coating position belongs to the position of the subsequent metal circuit, that is, the electrical circuit part. UV light irradiation is performed while the conductive ink is sprayed, so that the UV conductive ink is quickly fixed to avoid diffusion.

[0050] Preferably, the conductive ink is UV conductive ink.

[0051] Preferably, the metal circuit is coated by chemical deposition, electroplating or sputtering coating. The material of the coating can be, but is not limited to, gold, silver, copper, titanium, nickel, etc. according to actual needs. The thickness of the metal layer is selected according to the actual needs of the current carrier.

[0052] Preferably, the front and / or back surface of the multi-layer circuit structure is treated by chemical deposition, electroplating or sputtering coating.

[0053] Preferably, the front and back surfaces of the metal core plate are made by precision mechanical engraving or chemical etching, and are designed according to the actual requirements of chip characteristics.

[0054] The metal plate of the present invention is prepared according to the material actually needed. The metal plate can be, but not limited to, iron-nickel alloy plate, iron plate, copper alloy plate, pure copper plate, aluminum plate, etc. The thickness of the metal plate is also prepared according to actual needs. The length and width of the metal plate can be, but not limited to, 300×300mm, 400×600mm, 600×600mm or the size actually required, etc. After the metal core plate is completed, it can be divided into strips according to actual needs.

[0055] Beneficial effects of the present invention:

[0056] 1. The present invention utilizes a metal substrate core surface layer for an electrical circuit carrier structure with multiple layers of circuits while also achieving high heat dissipation performance. By utilizing a metal substrate and supplementing the multi-layer circuitry with high I / O, the heat from high-capacity or high-power chips can be effectively and rapidly directed out of the package periphery.

[0057] 2. The thermal conductivity of the copper material used in the present invention is 260 to 398 W / mK, which far exceeds the thermal conductivity of traditional organic substrates, which is 0.3 to 5 W / mK.

[0058] 3. The present invention's method for preparing an electrical circuit carrier structure based on a metal substrate core surface layer shortens the work process and reduces costs: preparing two layers of circuits using a metal substrate as the core surface layer requires only seventeen process steps, which is 22 steps shorter than the 39 process steps of a traditional organic substrate, a reduction of more than 50%; preparing four layers of circuits using a metal substrate as the core surface layer requires only 24 process steps, which is 41 steps shorter than the 65 process steps of a traditional organic substrate, a reduction of more than 60%, greatly reducing production costs.

[0059] 4. The method for preparing an electrical circuit carrier structure based on the surface of a metal substrate core of the present invention also enhances environmental protection: no materials need to be discarded during the production process and most chemical production methods are reduced, which fully protects the green environment and reduces the cost of chemical treatment. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] Figure 1 It is a cross-sectional view of a metal hollow lead frame structure in the prior art;

[0061] Figure 2 It is a cross-sectional view of an organic circuit substrate structure in the prior art;

[0062] Figure 3 A cross-sectional view of a metal substrate core surface single-sided double-layer circuit carrier structure according to the present invention;

[0063] Figure 4 A cross-sectional view of a metal base core surface double-sided double-layer circuit carrier structure of the present invention;

[0064] Figure 5 This is a manufacturing process diagram of the metal base core surface single-sided double-layer circuit carrier structure of the present invention;

[0065] Figure 6 This is a manufacturing process diagram of the metal base core surface double-sided double-layer circuit carrier structure of the present invention;

[0066] Figure 7 A cross-sectional view of a chip packaging structure with a metal substrate core and a single-sided double-layer circuit surface according to the present invention;

[0067] Figure 8 This is a cross-sectional view of a WBBGA chip upright wire bonding packaging structure with a metal substrate core surface layer and single-sided double-layer circuits according to the present invention;

[0068] Figure 9 This is a cross-sectional view of the FCBGA chip flip-chip bump bonding packaging structure with a single-sided double-layer circuit on the surface of the metal substrate core of the present invention.

[0069] In the figure: 1. inner pin, 2. base island, 3. cutting path, 4. metal core board, 5. semi-cured layer, 6. metal interconnection hole, 7. metal layer, 8. insulating layer, 9. upper half plastic sealing layer, 10. first front insulating layer, 11. first front conductive layer, 12. first front metal layer, 13. second front insulating layer, 14. second front conductive layer, 15. second front metal layer, 16. third front insulating layer, 17. lower half plastic sealing layer, 18. surface treatment layer, 19. first back conductive layer, 20. first back metal layer, 21. first back insulating layer, 22. second back conductive layer, 23. second back metal layer, 24. second back insulating layer, 25. adhesive layer, 26. chip, 27. metal wire. DETAILED DESCRIPTION

[0070] The following is a clear and complete description of the technical solutions in the implementation of the present invention in conjunction with the accompanying drawings. The described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. If specific conditions are not specified in the embodiments, they are carried out according to conventional conditions or the conditions recommended by the manufacturer.

[0071] Metal plate: refers to the finished product with a metal lead frame hollow structure that has not yet been completed; metal lead frame: refers to the finished product with a hollow structure that has completed the graphic structure; metal core board: refers to the structure of the flat metal lead frame hollow that has been filled after the metal lead frame has been pre-filled and plastic-sealed, and the metal core board; upper half layer / lower half layer: refers to the upper / lower layer structure of the metal plate, metal lead frame or metal core board.

[0072] Example 1

[0073] The present embodiment provides an electrical circuit carrier structure based on the surface layer of a metal substrate core. The electrical circuit carrier structure is a circuit carrier structure with multiple layers of circuits on a single side. The metal core plate 4 is used as the surface layer of the metal substrate core. A multi-layer circuit structure is provided on the front surface of the metal core plate 4. The front surface of the metal core plate 4 is the upper half surface of the metal core plate 4. In the present embodiment, a two-layer circuit structure is provided on the front surface of the metal core plate 4. Figure 3As shown, the metal core board 4 is an upper half-layer hollow graphic structure set in the upper half of the metal lead frame, and the upper half-layer plastic sealing layer 9 is filled in the upper half-layer hollow graphic structure. The metal core board 4 is an upper half-layer hollow graphic structure set in the upper half of the metal lead frame, and the lower half-layer plastic sealing layer 17 is filled in the lower half-layer hollow graphic structure. The filled upper half-layer plastic sealing layer 9 corresponds to the lower half-layer plastic sealing layer 17 and is connected to each other. Thermosetting epoxy resin is used as the plastic sealing material of the upper half-layer plastic sealing layer 9. The first front insulating layer 10, the second front insulating layer 13 and the third front insulating layer 16 are sequentially arranged on the upper half surface of the metal core board 4 from bottom to top. UV type insulating ink is used as the insulating material of the first front insulating layer 10, the second front insulating layer 13 and the third front insulating layer 16. The first front insulating layer 10 is connected to the filled upper half-layer plastic sealing layer 9. The first A first front conductive layer 11 and a first front metal layer 12 are provided in the front insulating layer 10 and the second front insulating layer 13. The first front metal layer 12 is adapted to be provided on the front surface of the first front conductive layer 11. A second front conductive layer 14 and a second front metal layer 15 are embedded in the third front insulating layer 16. The second front metal layer 15 is adapted to be provided on the front surface of the second front conductive layer 14. The front surface of the second front metal layer 15 and the front surface of the third front insulating layer 16 are in the same horizontal plane. UV conductive ink is used as the conductive material of the first front conductive layer 11 and the second front conductive layer 14. The back surface of the second front conductive layer 14 is connected to the front surface of the first front metal layer 12 and the front surface of the second front insulating layer 13. The back surface of the second front conductive layer 14 and the front surface of the second front insulating layer 13 are in the same horizontal plane.

[0074] A further technical solution of this embodiment is to provide a surface treatment layer 18 on the lower half surface of the metal core plate 4 .

[0075] A further technical solution of this embodiment is that the first front conductive layer 11 includes a plurality of first conductive segments arranged at intervals, each first conductive segment has a concave bridge-shaped structure, the concave portion of each first conductive segment is embedded in the first front insulating layer 10, the back surfaces of the two ends of each first conductive segment are attached to the front surface of the first front insulating layer 10, and are embedded in the second front insulating layer 13; the first front metal layer 12 and the first front conductive layer 11 are adapted to each other, the inner cavity of the concave structure of the first front metal layer 12 is connected to the second front insulating layer 13, and the front surfaces of all ends of the first front metal layer 12 are on the same horizontal plane as the front surface of the second front insulating layer 13.

[0076] A further technical solution of this embodiment is that the second front conductive layer 14 includes a plurality of second conductive segments arranged at intervals, each second conductive segment has a straight-line structure, and each second conductive segment is embedded in the third front insulating layer 16, so that the second front conductive layer 14 is connected to the first front metal layer 12 and the second front insulating layer 13, the second front metal layer 15 and the second front conductive layer 14 are adapted to each other, and the second front metal layer 15 is embedded in the third front insulating layer 16.

[0077] It should also be emphasized that the upper half surface of the metal core board 4 is not limited to the first front insulating layer, the second front insulating layer, and the third front insulating layer. It can be set according to actual needs and can include the fourth front insulating layer, the fifth front insulating layer and even more, but each front insulating layer is embedded with a conductive layer and a metal layer arranged on the conductive layer; in addition, the upper half layer of the metal core board 4 can also be any of the above-mentioned front insulating layers, that is, a single-layer insulating layer is set, and a conductive layer and a metal layer arranged on the conductive layer are embedded in the single-layer insulating layer, that is, a single-layer circuit structure is formed.

[0078] Example 2

[0079] The present embodiment provides an electrical circuit carrier structure based on the surface of a metal substrate core. The electrical circuit carrier structure is a circuit carrier structure with multi-layer circuits on both sides. Multi-layer circuit structures are arranged on the upper and lower half surfaces of the metal core board 4. The upper half surface of the metal core board 4 is the front surface of the metal core board 4, and the lower half surface of the metal core board 4 is the back surface of the metal core board 4. In this embodiment, two-layer circuit structures are arranged on the upper and lower half layers of the metal core board 4. Figure 4As shown, the metal core board 4 is an upper half-layer hollow graphic structure set on the upper half of the metal lead frame, and the upper half-layer plastic sealing layer 9 is filled in the upper half-layer hollow graphic structure. The metal core board 4 is an upper half-layer hollow graphic structure set on the upper half of the metal lead frame, and the lower half-layer plastic sealing layer 17 is filled in the lower half-layer hollow graphic structure. The filled upper half-layer plastic sealing layer 9 corresponds to the lower half-layer plastic sealing layer 17 and is connected to each other. The two-layer circuit structure on the upper half surface of this embodiment is the same as the two-layer circuit structure on the upper half surface of Example 1. Based on the two-layer circuit structure on the upper half surface of Example 1, this embodiment further provides a technical solution In the lower half of the hollow graphic structure of the metal core board 4, a first back insulating layer 21 and a second back insulating layer 24 are arranged from top to bottom in sequence. The first back insulating layer 21 is embedded with a first back conductive layer 19 and a first back metal layer 20. The first back metal layer 20 is adapted to be arranged on the back surface of the first back conductive layer 19. The second back conductive layer 22 and the second back metal layer 23 are embedded in the first back insulating layer 21 and the second back insulating layer 24. The second back metal layer 23 is adapted to be arranged on the back surface of the second back conductive layer 22. The second back conductive layer 22 is connected to the first back insulating layer 21 and the first back metal layer 20.

[0080] A further technical solution of this embodiment is that the first back conductive layer 19 includes a plurality of third conductive segments arranged at intervals, each third conductive segment has a straight-line structure, and each third conductive segment is embedded in the first back insulating layer 21, so that the first back conductive layer 19 is connected to the metal core board 4 and the lower half plastic layer 17, the first back metal layer 20 and the first back conductive layer 19 are adapted to each other, and the first back metal layer 20 is embedded in the first back insulating layer 21.

[0081] A further technical solution of this embodiment is that the second back conductive layer 22 includes a plurality of fourth conductive segments arranged at intervals, each fourth conductive segment has an arched bridge structure, the arched portion of each fourth conductive segment is embedded in the first back insulating layer 21, and the two ends of each fourth conductive segment are embedded in the second back insulating layer 24, the front surfaces of the two ends of each fourth conductive segment are connected to the back surface of the first back insulating layer 21, the second back metal layer 23 and the second back conductive layer 22 are adapted to each other, and the inner cavity of the arched structure of the second back metal layer 23 is exposed.

[0082] It should also be emphasized that the lower half surface of the metal core board 4 is not limited to the first back insulating layer and the second back insulating layer. It can be set according to actual needs and can include a third back insulating layer, a fourth back insulating layer, a third back insulating layer and even more, but each back insulating layer is embedded with a conductive layer and a metal layer arranged on the conductive layer; in addition, the lower half layer of the metal core board 4 can also be any of the above-mentioned back insulating layers, that is, a single-layer insulating layer is set, and a conductive layer and a metal layer arranged on the conductive layer are embedded in the single-layer insulating layer, that is, a single-layer circuit structure is formed; or no circuit may be set, that is, no insulating layer is set.

[0083] Example 3

[0084] Based on Example 1, this embodiment provides a method for preparing an electrical circuit carrier structure based on the surface layer of a metal substrate core. The steps of the preparation method are as follows. The process roadmap for preparing each component of the electrical circuit carrier structure is as follows: Figure 5 Steps 1) to 12) and 14) are shown as follows:

[0085] 1) Take a 300×300mm pure copper metal plate as an example;

[0086] 2) Using precision mechanical engraving methods, a hollow pattern structure is created on the upper layer of the metal plate according to the pattern and the actual requirements of the chip characteristics. This is then cleaned with pure water at a temperature of 60-80°C to remove surface dirt and improve the reliability and bonding ability of the plastic filling compound. The metal lead frame is then dried.

[0087] 3) Using thermosetting epoxy resin as a plastic encapsulation material, a mobile molding method is used to fill the upper half of the hollow pattern structure with thermosetting epoxy resin according to the temperature of the thermosetting epoxy resin to form an upper half plastic encapsulation layer 9, thereby obtaining a metal core board 4;

[0088] 4) Using UV insulating ink as the insulating material, a precision program graphic spraying mode is used to spray the ink onto the non-circuit areas on the upper half of the metal core board 4 where the circuits do not need to be protected. The thickness of the ink is determined based on the current carrying capacity. UV light irradiation is performed simultaneously with the spraying process to quickly fix the ink and prevent it from flowing, thereby forming a first front insulating layer 10.

[0089] 5) Using UV conductive ink as the conductive base dielectric material, a precise program graphic spraying pattern is used to spray the ink onto the upper surface of the metal core board 4 and the first front insulating layer 10 at locations where subsequent metal circuits are required, i.e., electrical circuit locations. The thickness of the ink is determined based on the current carrying capacity. UV light irradiation is performed simultaneously with the spraying process to quickly solidify the ink and prevent it from flowing and spreading, thereby forming the first front conductive layer 11.

[0090] 6) Using copper as the metal material, electroplating is performed on the first front conductive layer 11 to form a copper plating layer using an electroplating mode. The thickness of the copper plating layer is selected according to the actual current carrying requirements to form the first front metal layer 12;

[0091] 7) Using UV insulating ink as the insulating material, a precision program graphic spraying mode is used to spray the first front insulating layer 10 and the non-circuit protection local areas around the first front conductive layer 11 and the first front metal layer 12, i.e., the non-circuit areas. The spraying thickness is determined according to the current carrying requirements. UV light irradiation is performed simultaneously during the spraying process to quickly fix the ink and prevent it from flowing, thereby forming the second front insulating layer 13;

[0092] 8) Using UV conductive ink as the conductive base dielectric material, a precision-programmed base dielectric spraying mode is used to spray the ink onto the second front insulating layer 13 and the first front metal layer 12 at locations where subsequent metal circuits are required, i.e., electrical circuit locations. The thickness of the ink is determined based on the current carrying capacity. UV light irradiation is performed simultaneously with the spraying process to quickly solidify the ink and prevent it from flowing and spreading, thereby forming the second front conductive layer 14.

[0093] 9) Using copper as the metal material, electroplating is performed on the second front conductive layer 14 to form a copper plating layer using an electroplating mode. The thickness of the copper plating layer is selected according to the actual current carrying requirements to form the second front metal layer 15;

[0094] 10) Using UV insulating ink as the insulating material, a precision-programmed base medium spraying mode is used to spray the ink onto the second front insulating layer 13 and the non-circuit protection areas around the second front metal layer 15 and the second front conductive layer 14. The thickness of the ink is determined based on the current carrying capacity. UV light irradiation is performed simultaneously with the spraying process to quickly set the ink and prevent it from flowing, thereby forming a third front insulating layer 16.

[0095] 11) Using a precision mechanical engraving method, a lower half layer of hollow graphic structure is made on the lower half layer of the metal core plate 4 according to the produced graphics and the actual requirements of the chip characteristics;

[0096] 12) Using thermosetting epoxy resin as a plastic encapsulation material, a mobile molding method is used to fill the lower half of the hollowed pattern structure with thermosetting epoxy resin according to the temperature of the thermosetting epoxy resin, thereby forming a lower half plastic encapsulation layer 17;

[0097] 13) Based on the UV light irradiation in the above step and the first stage of baking, this process uses an oxygen-free oven with IR as the baking mode to carry out the second stage of IR permanent curing baking. The baking temperature and time are set according to the characteristics and thickness of the ink.

[0098] 14) Using copper as the metal material, a copper plating layer is electroplated on the back surface of the metal core board 4 at the exposed metal locations of the input and output terminals of the entire carrier board. The thickness of the plating layer is selected based on the actual current requirements, forming a surface treatment layer 18;

[0099] 15) Optical Inspection (AOI): After completing all the above processes, an optical inspection step is required to check whether the relevant dimensions of the input and output terminals of the metal circuit layer are within the designed specifications. The inspection equipment can use manual optical measurement models or automatic optical inspection models for measurement;

[0100] 16) Electrical circuit test: The main purpose of electrical circuit test is to measure the electrical properties of the metal layer at the input end and the metal layer at the output end, to confirm whether the electrical properties from the input end to the output end of the metal layer are conductive and there is no break, and on the basis of conductivity, whether its parasitic resistance, parasitic capacitance and parasitic inductance are within the design range; the measuring equipment can be automatic test equipment or manual test equipment.

[0101] 17) forming a circuit board structure based on a single-sided double-layer metal layer on the surface of a metal substrate core, such as Figure 3 As shown, dry pack and put into storage.

[0102] In this embodiment, the metal plate is prepared according to the material actually needed, and can be, but not limited to, iron-nickel alloy plate, iron plate, copper alloy plate, aluminum plate, etc. The thickness of the metal plate is also prepared according to actual needs. The length and width of the metal plate can also be, but not limited to, 400×600mm, 600×600mm, etc. After the metal core plate is completed, it can be divided into strips according to actual needs.

[0103] In this embodiment, the manufacturing method of the upper and lower half layers of the metal core board can also adopt chemical etching, but is not limited thereto, and can be designed according to the actual requirements of chip characteristics.

[0104] In this embodiment, the filling method of the thermosetting epoxy resin can also adopt, but is not limited to, a UV resin spraying method. During the spraying process, UV light irradiation needs to be performed simultaneously to quickly fix the resin and prevent it from flowing.

[0105] In this embodiment, the coating method of the metal circuit can also adopt, but is not limited to, chemical deposition or sputtering. The material of the coating can also be gold, silver, titanium, nickel, etc. according to actual needs. The thickness of the metal layer is selected according to the actual needs of the current carrier.

[0106] In this embodiment, the front and / or back surface treatment methods of the multi-layer circuit structure can also adopt, but are not limited to, chemical deposition or sputtering coating methods. The material of the coating can also be, but is not limited to, gold, silver, titanium, nickel, nickel gold, nickel palladium gold, tin, etc. according to actual needs. The thickness of the metal layer is selected according to the actual needs of the current carrier.

[0107] Example 4

[0108] Based on Example 2, this embodiment provides a method for preparing an electrical circuit carrier structure based on the surface layer of a metal substrate core. The steps of the preparation method are as follows: the process route for preparing each component of the electrical circuit carrier structure is as follows: Figure 6 Steps 1) to 18) shown:

[0109] 1) Take 300×300mm pure copper metal plate as an example;

[0110] 2) Using precision mechanical engraving methods, a hollow pattern structure is created on the upper layer of the metal plate according to the pattern and the actual requirements of the chip characteristics. This is then cleaned with pure water at a temperature of 60-80°C to remove surface dirt and improve the reliability and bonding ability of the plastic filling compound. The metal lead frame is then dried.

[0111] 3) Using thermosetting epoxy resin as a plastic encapsulation material, a mobile molding method is used to fill the upper half of the hollow pattern structure with thermosetting epoxy resin according to the temperature of the thermosetting epoxy resin to form an upper half plastic encapsulation layer 9, thereby obtaining a metal core board 4;

[0112] 4) Using UV insulating ink as the insulating material, a precision program graphic spraying pattern is used to spray the ink onto the non-circuit areas on the upper half of the metal core board 4. The thickness of the ink is determined based on the load pressure. UV light irradiation is performed simultaneously with the spraying process to quickly set the ink and prevent it from flowing, thereby forming the first front insulating layer 10.

[0113] 5) Using UV conductive ink as the conductive base dielectric material, a precise program graphic spraying pattern is used to spray the ink onto the upper surface of the metal core board 4 and the first front insulating layer 10 at locations where subsequent metal circuits are required, i.e., electrical circuit locations. The thickness of the ink is determined based on the current carrying capacity. UV light irradiation is performed simultaneously with the spraying process to quickly solidify the ink and prevent it from flowing and spreading, thereby forming the first front conductive layer 11.

[0114] 6) Using copper as the metal material, electroplating is performed on the first front conductive layer 11 to form a copper plating layer using an electroplating mode. The thickness of the copper plating layer is selected according to the actual current carrying requirements to form the first front metal layer 12;

[0115] 7) Using UV insulating ink as the insulating material, a precision program graphic spraying mode is used to spray the first front insulating layer 10 and the non-circuit protection local areas around the first front conductive layer 11 and the first front metal layer 12, i.e., the non-circuit areas. The spraying thickness is determined according to the current carrying requirements. UV light irradiation is performed simultaneously during the spraying process to quickly fix the ink and prevent it from flowing, thereby forming the second front insulating layer 13;

[0116] 8) Using UV conductive ink as the conductive base dielectric material, a precise program graphic spraying mode is used to spray the ink onto the second front insulating layer 13 and the first front metal layer 12 at locations where subsequent metal circuits are required, i.e., electrical circuit locations. The thickness of the ink is determined based on the current carrying capacity. UV light irradiation is performed simultaneously with the spraying process to quickly solidify the ink and prevent it from flowing and spreading, thereby forming the second front conductive layer 14.

[0117] 9) Using copper as the metal material, electroplating is performed on the second front conductive layer 14 to form a copper plating layer using an electroplating mode. The thickness of the copper plating layer is selected according to the actual current carrying requirements to form the second front metal layer 15;

[0118] 10) Using UV insulating ink as the insulating material, a precision program graphic spraying mode is used to spray the ink onto the second front insulating layer 13 and the non-circuit protection areas around the second front conductive layer 14 and the second front metal layer 15, i.e., the non-circuit areas. The thickness of the ink is determined based on the current carrying capacity. UV light irradiation is performed simultaneously with the spraying process to quickly fix the ink and prevent it from flowing, thereby forming a third front insulating layer 16.

[0119] 11) Using a precision mechanical engraving method to design a lower half layer of hollow graphic structure on the lower half layer of the metal core board 4 according to the produced graphics and the actual requirements of the chip characteristics;

[0120] 12) Using thermosetting epoxy resin as a plastic encapsulation material, a mobile molding method is used to fill the lower half of the hollowed pattern structure with thermosetting epoxy resin according to the temperature of the thermosetting epoxy resin, thereby forming a lower half plastic encapsulation layer 17;

[0121] 13) Using UV conductive ink as the conductive base dielectric material, a precise program graphic spraying pattern is used to spray the ink onto the lower half of the metal core board 4 where subsequent metal circuits are required, i.e., the electrical circuits. The thickness of the ink is determined based on the current carrying capacity. UV light irradiation is performed simultaneously with the spraying process to quickly solidify the ink and prevent it from flowing and spreading, thereby forming a first back conductive layer 19.

[0122] 14) Using copper as the metal material, electroplating is performed on the first back conductive layer 19 to form a copper plating layer using an electroplating mode. The thickness of the copper plating layer is selected according to the actual current carrying requirements to form a first back metal layer 20;

[0123] 15) Using UV insulating ink as the insulating material, a precise program graphic spraying mode is used to spray the ink onto the lower half of the surface of the metal core board 4 and the non-circuit protection areas around the first back conductive layer 19 and the first back metal layer 20. The thickness of the ink is determined based on the current carrying capacity. UV light irradiation is performed simultaneously with the spraying process to quickly fix the ink and prevent it from flowing, thereby forming the first back insulating layer 21.

[0124] 16) Using UV conductive ink as the conductive base dielectric material, a precision program graphic spraying mode is used to spray the ink onto the first back insulating layer 21 and the first back metal layer 20 at locations where subsequent metal circuits are required, i.e., electrical circuit locations. The thickness of the ink is determined based on the current carrying capacity. UV light irradiation is performed simultaneously with the spraying process to quickly solidify the ink and prevent it from flowing and spreading, thereby forming the second back conductive layer 22.

[0125] 17) Using copper as the metal material, electroplating is performed on the second back conductive layer 22 to form a copper plating layer using an electroplating mode. The thickness of the copper plating layer is selected according to the actual current carrying requirements to form a second back metal layer 23;

[0126] 18) Using UV insulating ink as the insulating material, a precision program graphic spraying mode is used to spray the ink onto the first back insulating layer 21 and the non-circuit protection areas around the second back conductive layer 22 and the second back metal layer 23, i.e., the non-circuit areas. The thickness of the ink is determined based on the current carrying capacity. UV light irradiation is performed simultaneously with the spraying process to quickly fix the ink and prevent it from flowing, thereby forming the second back insulating layer 24.

[0127] 19) Based on the UV light irradiation in the above step and the first stage of baking, this process uses an oxygen-free oven with IR as the baking mode to carry out the second stage of IR permanent curing baking. The baking temperature and time are set according to the characteristics of the ink and the thickness of the ink;

[0128] 20) Optical Inspection: After completing all the above processes, an optical inspection step is required to check whether the relevant dimensions of the input and output ends of the metal circuit layer are within the designed specifications. The inspection equipment can use manual optical measurement models or automatic optical inspection models for measurement;

[0129] 21) Electrical circuit test: The main purpose of electrical circuit test is to measure the electrical properties of the metal layer at the input end and the metal layer at the output end, to confirm whether the electrical properties from the input end to the output end of the metal layer are conductive and there is no break, and on the basis of conductivity, whether its parasitic resistance, parasitic capacitance and parasitic inductance are within the design range; the measuring equipment can be automatic test equipment or manual test equipment.

[0130] 22) forming a circuit board structure with double-sided double-layer metal layers based on the surface of the metal substrate core, such as Figure 4 As shown, dry pack and put into storage.

[0131] In this embodiment, the front and back surfaces of the metal core board can also be surface treated before optical inspection: using copper as the metal material, electroplating mode is used to electroplate the copper plating layer on the front and back surfaces of the double-sided double-layer metal circuit carrier at the metal positions exposed at the input and output ends of the entire carrier. The thickness of the copper plating layer is selected according to the actual current carrying needs to form a surface treatment layer 18.

[0132] In this embodiment, the metal plate is prepared according to the material actually needed, and can be, but not limited to, iron-nickel alloy plate, iron plate, copper alloy plate, aluminum plate, etc. The thickness of the metal plate is also prepared according to actual needs. The length and width of the metal plate can also be, but not limited to, 400×600mm, 600×600mm, etc. After the metal core plate is completed, it can be divided into strips according to actual needs.

[0133] In this embodiment, the manufacturing method of the upper and lower layers of the metal core board can also be adopted, but is not limited to chemical etching, and is designed according to the actual requirements of the chip characteristics.

[0134] In this embodiment, the filling method of the thermosetting epoxy resin can also adopt the UV resin spraying method. During the spraying process, UV light irradiation needs to be performed simultaneously to make it quickly set and prevent it from flowing.

[0135] In this embodiment, the coating method of the metal circuit can also be, but is not limited to, chemical deposition or sputtering coating. The material of the coating can also be, but is not limited to, gold, silver, titanium, nickel, nickel gold, nickel palladium gold, tin, etc. according to actual needs. The thickness of the metal layer is selected according to the actual needs of the current carrier.

[0136] In this embodiment, the front and / or back surface treatment method of the multi-layer circuit structure can also adopt chemical deposition or sputtering coating method. The material of the coating can also be, but not limited to, gold, silver, titanium, nickel, etc. according to actual needs. The thickness of the metal layer is selected according to the actual needs of the current carrier.

[0137] According to the above process steps, the number of circuit layers can be single, double, triple or even more layers according to the circuit structure of the metal core board. The production process of the circuit layers can be appropriately adjusted to increase or decrease to prepare the circuit carrier structure actually required.

[0138] It should also be emphasized that hollow graphic structures can be prepared on the upper and lower layers of the metal plate first, and then the plastic packaging materials can be filled in sequence to arrange the multi-layer circuit structure on the upper and lower surfaces of the metal core plate in sequence.

[0139] Example 5

[0140] Based on Examples 1 and 2, this embodiment provides a chip packaging structure based on an electrical circuit carrier structure on the surface of a metal substrate core. The preparation method steps are as follows: Figures 7 to 9 As shown:

[0141] A glue layer 25 is applied on the front base island of the circuit carrier board with double-sided double metal layers on the copper-based core board. The material used for the glue layer 25 can be conductive glue or non-conductive glue. A chip 26 is set on the glue layer 25, and a metal wire 27 is set between the chip 26 and the second front metal layer 15. The metal wire 27 electrically connects the chip 26 and the circuit carrier board. Then, the front of the circuit carrier board is encapsulated with epoxy resin to form a Figure 7 The circuit chip packaging structure shown is a single-sided double-layer metal layer.

[0142] A glue layer 25 is applied on the front base island of the circuit carrier board with double-sided double metal layers on the copper-based core board. The material used for the glue layer 25 can be conductive glue or non-conductive glue. A chip 26 is set on the glue layer 25, and a metal wire 27 is set between the chip 26 and the second front metal layer 15. The metal wire 27 electrically connects the chip 26 and the circuit carrier board. Then, the front of the circuit carrier board is encapsulated with epoxy resin to form a Figure 8 The WBBGA chip with double-sided double-layer metal layer is mounted on the metal wire bonding packaging structure.

[0143] Without using metal wire bonding, the copper-based core board with double-sided double-layer metal layer is flipped on the front base island of the circuit carrier board, and the flip-chip bump bonding package is used to form Figure 9 The FCBGA chip flip-chip bump bonding packaging structure with double-sided double-layer metal layers is shown.

[0144] In summary, the electrical circuit carrier structure on the surface of the metal substrate core has multi-layer circuits and also takes into account high heat dissipation efficiency: using a metal material as a substrate, assisted by multi-layer circuit high I / O production, can effectively and quickly conduct heat from high-capacity or high-power chips directly to the periphery of the package; the preparation method shortens the working process and reduces costs: preparing two layers of circuits with a metal substrate as the core surface requires only 17 process steps, which is 22 steps shorter than the 39 process steps of traditional organic substrates, a reduction of approximately 50% or more process steps; preparing four layers of circuits with a metal substrate as the core surface requires only 24 process steps, which is 41 steps shorter than the 65 process steps of traditional organic substrates, a reduction of approximately 60% or more process steps, greatly reducing production costs; no materials need to be discarded in the production process and most chemical production methods are reduced, fully protecting the green environment and reducing the cost of chemical treatment.

[0145] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the present invention can be embodied in other specific forms without departing from the spirit and essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations that come within the meaning and range of equivalents of the claims be embraced therein.

[0146] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. An electrical circuit carrier structure based on a metal substrate core surface layer, characterized in that: include: A metal core plate, wherein the upper and lower halves of the metal core plate are respectively embedded with an upper half plastic sealing layer and a lower half plastic sealing layer, and the upper half plastic sealing layer is connected to the lower half plastic sealing layer; A first front insulating layer is provided on the upper surface of the metal core board and is connected to the upper plastic sealing layer; a second front insulating layer, disposed on a front surface of the first front insulating layer; a third front insulating layer, disposed on a front surface of the second front insulating layer; A first front conductive layer is embedded in the first front insulating layer and the second front insulating layer; A first front metal layer is provided on the front surface of the first front conductive layer and is embedded in the first front insulating layer and the second front insulating layer; a second front conductive layer embedded in the third front insulating layer, the second front conductive layer also being connected to the first front metal layer; The second front metal layer is arranged on the front surface of the second front conductive layer and is embedded in the third front insulating layer.

2. The electrical circuit carrier structure based on the metal substrate core surface layer according to claim 1, characterized in that: A surface treatment layer is also provided on the lower half surface of the metal core plate.

3. The electrical circuit carrier structure based on the metal substrate core surface layer according to claim 1, characterized in that: The first front conductive layer includes a plurality of first conductive segments arranged at intervals, each of the first conductive segments is configured as a concave bridge-shaped structure, with the concave portion embedded in the first front insulating layer and both ends embedded in the second front insulating layer. The first front metal layer is adaptively arranged with the first front conductive layer, and the concave portion of the first front metal layer is connected to the second front insulating layer. The second front conductive layer includes a plurality of second conductive segments arranged at intervals, each second conductive segment is in a straight line structure, and the second front metal layer is adaptively arranged with the second front conductive layer.

4. The electrical circuit carrier structure based on the metal substrate core surface layer according to claim 1, characterized in that: The lower half surface of the metal core board is provided with a first back insulating layer and a second back insulating layer in sequence from top to bottom, and the first back insulating layer is connected to the lower half plastic sealing layer; A first back conductive layer and a first back metal layer are sequentially embedded in the first back insulating layer from top to bottom; The back surface of the first back metal layer is connected to the second back conductive layer, the back surface of the second back conductive layer is connected to the second back metal layer, and the second back conductive layer and the second back metal layer are embedded in the first back insulating layer and the second back insulating layer.

5. The electrical circuit carrier structure based on the metal substrate core surface layer according to claim 4, characterized in that: The second back conductive layer includes a plurality of fourth conductive segments arranged at intervals, each of the fourth conductive segments is configured as an arched bridge structure, with the arched portion embedded in the first back insulating layer and both ends embedded in the second back insulating layer; the second back metal layer is adaptively configured to the second back conductive layer; The first back conductive layer includes a plurality of third conductive segments arranged at intervals, each of the third conductive segments is in a straight line structure, and the second back metal layer is adapted to be arranged with the second back conductive layer.

6. A method for preparing an electrical circuit carrier structure based on a metal substrate core surface layer according to claim 1, characterized in that: The following steps are involved: (1) Prepare metal plates; (2) making an upper half-layer hollow pattern structure on the metal plate, cleaning and drying it to form a metal lead frame; (3) filling the upper half of the hollow pattern structure with a plastic sealing material to form an upper half of the plastic sealing layer to obtain a metal core board; (4) The upper and lower surfaces of the metal core board are covered with a single-layer or multi-layer circuit structure; (5) The lower half of the metal core plate is made into a hollow graphic structure; (6) filling the lower half-layer hollow pattern structure with a plastic sealing material to form a lower half-layer plastic sealing layer; (7) IR baking curing; (8) performing surface treatment on the front and / or back surface of the multi-layer circuit structure to form a surface treatment layer; (9) Automated optical inspection; (10) Electrical circuit testing; (11) Drying, packaging and storage; The order of step (5) can be adjusted according to actual conditions, and can be adjusted to after step (2) or after step (3).

7. The method for preparing an electrical circuit carrier structure based on a metal substrate core surface layer according to claim 6, characterized in that: Step (4) The preparation steps of coating the upper half surface of the metal core board with a multilayer circuit structure are as follows: (4-1) The non-circuit area of ​​the upper half of the surface of the metal core board is coated with insulating ink to form a first front insulating layer; (4-2) The upper surface of the metal core board and the electrical circuit portion of the first front insulating layer are coated with conductive ink to form a first front conductive layer; (4-3) coating a metal circuit on the first front conductive layer to form a first front metal layer; (4-4) coating the first front insulating layer and the non-circuit areas around the first front conductive layer and the first front metal layer with insulating ink to form a second front insulating layer; (4-5) coating the second front insulating layer and the electrical circuit portion of the second front insulating layer with conductive ink to form a second front conductive layer; (4-6) coating a metal circuit on the second front conductive layer to form a second front metal layer; (4-7) Insulating ink is coated on the non-circuit areas of the second front insulating layer and the second front metal layer to form a third front insulating layer.

8. The method for preparing an electrical circuit carrier structure based on a metal substrate core surface layer according to claim 6, characterized in that: The method further includes step (12) of coating the lower half surface of the metal core board with a multi-layer circuit structure, which is added between the steps of filling the lower half hollow pattern structure with a plastic encapsulation material in step (6) and performing IR baking and curing in step (7); the preparation steps of the lower half surface of the metal core board coated with a multi-layer circuit structure are as follows: (12-1) coating the electrical circuit portion of the lower half surface of the metal core board with conductive ink to form a first back conductive layer; (12-2) coating a first layer of metal circuits on the first back conductive layer to form a first back metal layer; (12-3) coating insulating ink on the lower half surface of the metal core board and the non-circuit portion of the first back metal layer to form a first back insulating layer; (12-4) coating the electrical circuit portions of the first back insulating layer and the first back metal layer with conductive ink to form a second back conductive layer; (12-5) coating the second back conductive layer with a second metal circuit to form a second back metal layer; (12-6) A second layer of insulating ink is coated on the non-circuit areas of the first back insulating layer and the second back metal layer to form a second back insulating layer.

9. The method for preparing an electrical circuit carrier structure based on a metal substrate core surface layer according to claim 7 or 8, characterized in that: The insulating ink is coated by a UV insulating ink spraying method; the insulating ink is a UV insulating ink; Preferably, the conductive ink is coated by spraying UV conductive ink; the conductive ink is UV conductive ink; The metal circuit is coated by chemical deposition, electroplating or sputtering.

10. The method for preparing an electrical circuit carrier structure based on a metal substrate core surface layer according to claim 6, characterized in that: The upper and lower hollow graphic structures are filled with a plastic encapsulation material by a transfer molding method or a UV resin spraying method; the plastic encapsulation material is a thermosetting epoxy resin; The front and / or back surface treatment method of the multi-layer circuit structure is a chemical deposition method, an electroplating method or a sputtering coating method; The front and back of the metal core plate are made by a precision mechanical engraving method or a chemical etching method.

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