Chip packaging structure and electronic equipment

Abstract

The invention relates to a chip packaging structure and electronic equipment. Comprising a substrate, a packaging chip and an insulating layer, the packaging chip and the insulating layer are located on the same side of the substrate, a bonding pad and a circuit layer are arranged on the first surface, facing one side of the packaging chip, of the substrate in the thickness direction of the substrate, and the bonding pad is electrically connected with the packaging chip; along the thickness direction of the substrate, in a projection area of the packaging chip on the substrate, the insulating layer is arranged on the first surface, the insulating layer comprises a first area and a second area, the circuit layer corresponding to the first area is exposed, the bonding pad is correspondingly arranged in the first area, and a coating is further arranged on at least part of the surface of the circuit layer in the first area. The surface of the circuit layer in the second region is covered by the insulating layer. According to the chip packaging structure, the insulating layer is arranged on the surface of the circuit layer in the second region, so that the setting area of the coating on the circuit layer is reduced, the influence of the coating material after high-temperature cracking on the packaging chip is reduced, and the reliability of the chip packaging structure is improved.

Description

Technical Field

[0001] The present application relates to the field of radio frequency, and in particular to a chip packaging structure and an electronic device including the chip packaging structure. Background Art

[0002] In the chip packaging process, the packaged chip usually needs to be electrically connected to the pads of the substrate before the packaging process. In order to ensure that the pads are not oxidized before welding, a coating is usually provided on the surface of the pads.

[0003] But the coating may affect the working performance of the packaged chip. Summary of the Invention

[0004] In view of the above-mentioned deficiencies in the prior art, the purpose of this application is to provide a solution to ensure reliability, which specifically includes the following technical solutions:

[0005] In a first aspect, embodiments of the present application provide a chip packaging structure, comprising a substrate, a packaged chip, and an insulating layer located on the same side of the substrate, wherein a first surface of the substrate facing the packaged chip is provided with a bonding pad and a circuit layer along the thickness direction of the substrate, wherein the bonding pad is electrically connected to the packaged chip;

[0006] Along the thickness direction of the substrate, within the projection area of ​​the packaged chip on the substrate, the insulating layer is arranged on the first surface, the insulating layer includes a first area and a second area, the circuit layer corresponding to the first area is exposed, the solder pad is arranged correspondingly in the first area, at least part of the surface of the circuit layer in the first area is also provided with a coating, and the surface of the circuit layer in the second area is covered by the insulating layer.

[0007] The chip packaging structure provided herein provides solder pads on the first surface of a substrate, electrically connecting the packaged chip to the solder pads. This facilitates electrical communication between the external circuit and the packaged chip via the solder pads. Furthermore, at least a portion of the circuit layer on the first surface of the substrate is electrically connected to the solder pads, thereby enabling the filtering and frequency modulation functions of the chip packaging structure provided herein.

[0008] The chip packaging structure provided herein also provides an insulating layer on the first surface, and then on the surface of the circuit layer in the second region, so that only the circuit layer in the first region is coated. This reduces the coating area on the circuit layer, thereby minimizing the impact of the coating material on the packaged chip after high-temperature decomposition, thereby improving the reliability of the chip packaging structure provided herein.

[0009] In one embodiment, at least a portion of the surface of the circuit layer in the first area is provided with a coating, and the surface of the circuit layer in the second area is directly bonded to the insulating layer.

[0010] In one embodiment, a functional device is provided on the second surface of the packaged chip facing the substrate side along the thickness direction of the substrate, the functional device is separated from the insulating layer, the projection of the insulating layer on the second surface covers the functional device, and the projection of the functional device on the insulating layer is located in the second area; wherein, at least a portion of the circuit layer in the second area is not coated.

[0011] In one embodiment, the pads are spaced apart from the functional devices along the plane direction of the first surface, and along the thickness direction of the substrate, the projected area of ​​the functional devices on the substrate is less than or equal to the area of ​​the insulating layer covered by the projection of the packaged chip on the substrate.

[0012] In one embodiment, along the plane direction of the first surface, the distance between the pad and the insulating layer is greater than or equal to 25 μm.

[0013] In one embodiment, the thickness of the coating is greater than or equal to 0.1 μm and less than or equal to 0.5 μm.

[0014] In one embodiment, within the projection area of ​​the packaged chip on the substrate, the ratio of the area of ​​the circuit layer in the second region to the total area of ​​the circuit layer with and without the coating is greater than or equal to 0.6 and less than or equal to 0.8.

[0015] In one embodiment, along the thickness direction of the substrate, a functional device is provided on the second surface of the packaged chip facing the side of the substrate, a plurality of pads are provided in the first area, and the pads are spaced apart from each other along the plane direction of the first surface; the insulating layer includes a first insulating portion and a second insulating portion spaced apart from each other, and the first insulating portion is arranged around the second insulating portion, and along the thickness direction of the substrate, the projection of the second insulating portion on the second surface covers the functional device, and in the area corresponding to the second insulating portion, no coating is provided on at least part of the circuit layer.

[0016] In one embodiment, a plurality of pads surround the outer edge of the functional device; or, the first region includes a first sub-region and a second sub-region spaced apart from each other, the first sub-region is arranged between the first insulating portion and the second insulating portion, the second sub-region is located within the second insulating portion, and the second sub-region corresponds to the functional device; wherein, a coating is provided on the corresponding pads and / or circuit layers in the first sub-region and the second sub-region, and no coating is provided on the circuit layer in the area corresponding to the second insulating portion.

[0017] In one embodiment, the second sub-area is set to be multiple, the multiple second sub-areas are spaced apart, and each second sub-area is also provided with a pad, the pad in the second sub-area is electrically connected to the pad in the functional device, and each second sub-area is provided with a coating.

[0018] In one embodiment, along the plane direction of the first surface, the spacing between the first insulating portion and the second insulating portion is greater than or equal to 30 μm and less than or equal to 300 μm, and the width of the corresponding coating between the first insulating portion and the second insulating portion is greater than or equal to 30 μm and less than or equal to 300 μm.

[0019] In one embodiment, along the plane direction of the first surface, the spacing between the first insulating portion and the second insulating portion is greater than or equal to 60 μm and less than or equal to 200 μm, and the width of the coating between the first insulating portion and the second insulating portion is greater than or equal to 50 μm and less than or equal to 200 μm.

[0020] In one embodiment, the first insulating portion is spaced apart from the second surface along the thickness direction of the substrate; the packaged chip is further bonded and fixed to the first insulating portion by dispensing glue, and the dispensing glue surrounds the edge of the packaged chip.

[0021] In one embodiment, along the thickness direction of the substrate, the glue spots are located on the surface of the first insulating part away from the substrate; or, along the thickness direction of the substrate, a portion of the glue spots are located on the surface of the first insulating part away from the substrate, and another portion of the glue spots are located on the coating between the first insulating part and the second insulating part.

[0022] In one embodiment, along the thickness direction of the substrate, a distance between the first insulating portion and the second surface is greater than or equal to 1 μm and less than or equal to 30 μm.

[0023] In one embodiment, along the thickness direction of the substrate, the thickness of the first insulating portion is greater than or equal to the thickness of the second insulating portion.

[0024] In one embodiment, the thickness of the first insulating portion is greater than or equal to 15 μm and less than or equal to 35 μm; and / or the thickness of the second insulating portion is greater than or equal to 10 μm and less than or equal to 20 μm.

[0025] In one embodiment, the coating comprises at least one of triazoline, imidazole organic crystalline base, nickel gold, and nickel palladium gold.

[0026] In one embodiment, the chip packaging structure further includes a plastic packaging layer. Along the thickness direction of the substrate, the plastic packaging layer is located on a side of the substrate where the packaged chip is mounted, and the plastic packaging layer covers the packaged chip.

[0027] In a second aspect, an embodiment of the present application provides a chip packaging structure, including a substrate, an insulating layer, a packaged chip, and glue. Along the thickness direction of the substrate, the insulating layer is provided on the first surface of the substrate, and the first surface is provided with a solder pad, which is conductively connected to the packaged chip;

[0028] The insulating layer is provided with a groove. The projection of the packaged chip on the substrate covers the groove along the thickness direction of the substrate. Glue is dispensed around the outside of the groove along the plane direction of the first surface and adhered between the insulating layer and the packaged chip. A circuit layer is also provided on the first surface. The circuit layer extends along the plane direction of the first surface. A coating is provided on the surface of the circuit layer located within the groove. At least a portion of the circuit layer located outside the groove is directly bonded to the insulating layer.

[0029] Along the thickness direction of the substrate, a distance between the notch of the groove and the packaged chip is greater than or equal to 1 μm and less than or equal to 30 μm.

[0030] The chip packaging structure provided herein provides solder pads on the first surface of a substrate, electrically connecting the packaged chip to the solder pads. This facilitates electrical communication between the external circuit and the packaged chip via the solder pads. The circuit layer on the first surface of the substrate is used to transmit electrical signals and / or external signals, thereby enabling the filtering and frequency modulation functions of the chip packaging structure provided herein.

[0031] The chip packaging structure provided herein also includes an insulating layer having a groove on its first surface, with the groove located within the gap between the packaged chip and the substrate. This prevents the adhesive from extending onto the packaged chip and affecting its performance when the insulating layer and the packaged chip are bonded together using adhesive. This ensures the reliability of the chip packaging structure.

[0032] At the same time, at least part of the circuit layer outside the groove is directly bonded to the insulating layer, which also reduces the area of ​​the coating on the circuit layer surface and reduces the impact of high-temperature cracking of the coating on the packaged chip, further ensuring the reliability of the chip packaging structure of the present application.

[0033] In one embodiment, a functional device is provided on the second surface of the packaged chip facing the substrate side along the thickness direction of the substrate, the functional device is separated from the insulating layer, and a groove is provided around the functional device along the plane direction of the first surface; wherein, a coating is provided on the pads and circuit layers in at least part of the groove area.

[0034] In one embodiment, there are multiple grooves, and the multiple grooves surround the outer edge of the functional device, and the grooves are spaced apart from each other; or, the shape of the groove is annular, and the groove surrounds the outer edge of the functional device.

[0035] In one embodiment, the groove is annular in shape, and along the plane direction of the first surface, the groove divides the insulating layer into a first insulating portion and a second insulating portion spaced apart from each other. The first insulating portion is used to form an outer groove wall of the groove, and the second insulating portion is used to form an inner groove wall of the groove. Along the thickness direction of the substrate, the thickness dimension of the first insulating portion is greater than or equal to the thickness dimension of the second insulating portion; wherein, in the area corresponding to the first insulating portion, at least a portion of the circuit layer is provided with a coating, and in the area corresponding to the second insulating portion, at least a portion of the circuit layer is not provided with a coating.

[0036] In one embodiment, there are multiple pads, at least some of which are exposed through the grooves, and along the plane direction of the first surface, the spacing between the pads received in the grooves and the groove walls on both sides of the grooves is greater than or equal to 25 μm.

[0037] In a third aspect, embodiments of the present application provide a chip packaging structure, comprising a substrate, a packaging chip, and an insulating layer located on the same side of the substrate, wherein a first surface of the substrate facing the packaging chip is electrically connected to the packaging chip along the thickness direction of the substrate, and a circuit layer is provided on the first surface;

[0038] Along the thickness direction of the substrate, within the projection area of ​​the packaged chip on the substrate, an insulating layer is arranged on the first surface. The insulating layer includes a first area and a second area. The circuit layer corresponding to the first area is exposed, and the surface of the circuit layer in the first area is also provided with a coating. The surface of the circuit layer in the second area is covered by the insulating layer. The ratio of the area of ​​the circuit layer in the first area to the area of ​​the circuit layer in the second area is between 1.5 and 4.

[0039] The chip packaging structure provided herein is electrically connected to the packaged chip via the first surface of the substrate, facilitating electrical communication between the external circuit and the packaged chip via the substrate. The circuit layer on the first surface of the substrate is used to transmit signals, thereby enabling the filtering and frequency modulation functions of the chip packaging structure of the present invention.

[0040] The chip packaging structure provided herein also provides an insulating layer on the first surface, leaving at least a portion of the circuit layer in the second region covered by the insulating layer, while the circuit layer in the first region is exposed and coated. This reduces the coating area required on the circuit layer surface and mitigates the impact of high-temperature cracking of the coating on the packaged chip. This ensures the reliability of the chip packaging structure provided herein.

[0041] At the same time, the chip packaging structure provided in the present application also limits the area ratio of the circuit layer in the first area and the second area to ensure the setting area of ​​the circuit layer with the insulating layer, thereby ensuring the reliability of the chip packaging structure of the present application.

[0042] In one embodiment, the insulating layer further includes a groove, which separates the insulating layer and forms a first insulating portion and a second insulating portion, wherein the first insulating portion is arranged around the second insulating portion; along the thickness direction of the substrate, a functional device is provided on the second surface of the packaged chip facing the side of the substrate, and the projection of the second insulating portion on the second surface covers the functional device; and in the area corresponding to the second insulating portion, no coating is provided on at least part of the circuit layer.

[0043] In one embodiment, along the plane direction of the first surface, the spacing between the first insulating portion and the second insulating portion is greater than or equal to 30 μm and less than or equal to 300 μm, and the width of the coating between the first insulating portion and the second insulating portion is greater than or equal to 30 μm and less than or equal to 300 μm.

[0044] In one embodiment, the first surface is further provided with a solder pad, which is conductively connected to the packaged chip; the groove includes a first section and a second section that are connected, the solder pad is arranged in the first section, and along the plane direction of the first surface, the distance between the first insulating part and the second insulating part in the first section is greater than or equal to the distance between the first insulating part and the second insulating part in the second section, and a coating is provided on the corresponding circuit layers in the first section and the second section.

[0045] In one embodiment, the second insulating portion further includes a second groove, which is arranged near the central area of ​​the functional device. There are multiple pads, some of which are arranged in the first section, and another part of the pads are arranged in the second groove. A coating is provided on the circuit layer in the second groove.

[0046] In a fourth aspect, an embodiment of the present application provides an electronic device including a chip packaging structure.

[0047] It can be understood that the electronic device provided in the fourth aspect of the present application also ensures working reliability because it adopts the chip packaging structure provided in the first to third aspects of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 This is a schematic structural diagram of an electronic device provided in one embodiment of the present application;

[0049] Figure 2 A schematic cross-sectional view of a chip packaging structure provided in one embodiment of the present application;

[0050] Figure 3 A schematic diagram of a partial structure of a chip packaging structure provided in one embodiment of the present application;

[0051] Figure 4 This is another cross-sectional structural diagram of a chip packaging structure provided in one embodiment of the present application;

[0052] Figure 5 This is another partial structural diagram of a chip packaging structure provided in one embodiment of the present application;

[0053] Figure 6 This is another schematic cross-sectional view of a chip packaging structure provided in one embodiment of the present application;

[0054] Figure 7 A schematic diagram of a partial cross-sectional structure of a chip packaging structure provided in one embodiment of the present application;

[0055] Figure 8 This is another partial structural diagram of a chip packaging structure provided in one embodiment of the present application;

[0056] Figure 9 This is another partial structural diagram of the chip packaging structure provided in one embodiment of the present application;

[0057] Figure 10 A schematic diagram of a partial external structure of a chip packaging structure provided in one embodiment of the present application;

[0058] Figure 11 This is another schematic cross-sectional view of a chip packaging structure provided in one embodiment of the present application;

[0059] Figure 12 This is another partial structural diagram of the chip packaging structure provided in one embodiment of the present application;

[0060] Figure 13 This is another partial structural diagram of a chip packaging structure provided in one embodiment of the present application;

[0061] Figure 14 This is a schematic structural diagram of a chip packaging structure provided in one embodiment of the present application;

[0062] Figure 15 This is another partial structural diagram of the chip packaging structure provided in one embodiment of the present application;

[0063] Figure 16 A schematic diagram of a partial top view of a chip packaging structure provided in one embodiment of the present application;

[0064] Figure 17 This is another partial top view schematic diagram of the chip packaging structure provided in one embodiment of the present application. DETAILED DESCRIPTION

[0065] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The accompanying drawings illustrate preferred embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the disclosure of the present application.

[0066] The following descriptions of the embodiments are with reference to the attached diagrams to illustrate specific embodiments that the present application can be used to implement. The serial numbers of the components herein, such as "first", "second", etc., are only used to distinguish the objects described and do not have any order or technical meaning. The "connection" and "coupling" mentioned in the present application include direct and indirect connections (couplings) unless otherwise specified. The directional terms mentioned in the present application, such as "up", "down", "front", "back", "left", "right", "inside", "outside", "side", etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are for better and clearer explanation and understanding of the present application, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

[0067] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections; they can refer to direct connections, indirect connections through an intermediary, or internal connections between two components. A person of ordinary skill in the art will understand the specific meanings of these terms in this application based on the specific circumstances. It should be noted that the terms "first," "second," and so on, in the specification, claims, and drawings of this application are used to distinguish between different objects, not to describe a specific order. Furthermore, the terms "include," "may include," "comprise," or "may include" as used in this application indicate the presence of the corresponding functions, operations, components, etc. disclosed, and do not limit the presence or absence of one or more additional functions, operations, components, etc. Furthermore, the terms "include" or "comprising" indicate the presence of the corresponding features, numbers, steps, operations, elements, components, or combinations thereof disclosed in the specification, and do not exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, and are intended to cover non-exclusive inclusions.

[0068] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0069] See also Figure 1 The figure shows a schematic structural diagram of an electronic device 200 provided in one embodiment of the present application.

[0070] like Figure 1 As shown, the electronic device 200 of the present application includes a substrate 201 and a chip packaging structure 100, wherein the chip packaging structure 100 is mounted on the substrate 201. The substrate 201 and the chip packaging structure 100 are electrically connected.

[0071] In one embodiment, substrate 201 is a printed circuit board. The electronic device 200 of the present application receives and / or transmits signals via the chip package structure 100. Exemplarily, the electronic device 200 includes at least one of a computer, a mobile phone, a tablet computer, a smartwatch, and a navigation device, although this application does not specifically limit this.

[0072] See also Figure 2 and Figure 3 ,in Figure 2 1 is a schematic cross-sectional view of a chip packaging structure 100 provided in one embodiment of the present application. Figure 3 FIG1 is a partial structural diagram of a chip package structure 100 provided in one embodiment of the present application. In order to facilitate the description of the internal structure of the chip package structure 100, Figure 3 Part of the structure of the chip packaging structure 100 is omitted, and the area where the packaged chip 20 is located is indicated by a dotted line.

[0073] like Figure 2 and Figure 3 As shown, the chip packaging structure 100 of the present application includes a substrate 10, a packaged chip 20 and an insulating layer 30. Along the thickness direction of the substrate 10, the packaged chip 20 and the insulating layer 30 are located on the same side of the substrate 10. The first surface 11 of the substrate 10 facing the packaged chip 20 is provided with a solder pad 40 and a circuit layer 50. Figure 2 In the illustrated example, the pads 40 protrude relative to the first surface 11 to facilitate electrical connection with the packaged chip 20. In another embodiment, the pads 40 are embedded in the first surface 11 and flush with the first surface 11. In another embodiment, the pads 40 are embedded in the first surface 11 and recessed relative to the first surface 11.

[0074] exist Figure 3 In the illustrated example, a portion of the wiring pattern in the circuit layer 50 is connected to the pad 40, while another portion of the wiring pattern in the circuit layer 50 is separated from the pad 40. In the embodiment of the present application, the circuit layer 50 connected to the pad 40 is used to transmit signals to the packaged chip 20, and the circuit layer 50 separated from the pad 40 is used to transmit signals to other components on the substrate 10, thereby achieving the functional use of the chip packaging structure 100 of the present application.

[0075] In the present embodiment and subsequent embodiments, the packaged chip 20 is a filter chip. Accordingly, the circuit layer 50 connected to the pad 40 is used to transmit signals to the packaged chip 20 to implement the filtering and frequency modulation functions of the chip packaging structure 100 of the present application. The circuit layer 50, separated from the pad 40, also serves to constrain the electric field generated by the packaged chip 20 during operation and reduce impedance. In other embodiments, the packaged chip 20 can also be other types of chips. For example, the packaged chip 20 is an amplifier chip. This application does not impose any particular restrictions on this.

[0076] In the embodiment of the present application, along the thickness direction of the substrate 10, within the projection area of ​​the packaged chip 20 on the substrate 10, the insulating layer 30 is disposed on the first surface 11. Figure 3 In the illustrated example, the insulating layer 30 includes a first region 31 and a second region 32 disposed on one side of the first region 31 . Optionally, along the plane direction of the first surface 11 , the first region 31 is connected to the second region 32 .

[0077] The first region 31 is used to expose a portion of the first surface 11 of the substrate 10, and to expose a portion or all of the circuit layer 50 within the first surface 11. The solder pads 40 are disposed on the first surface 11 within the first region 31. This prevents the insulating layer 30 from interfering with the electrical connection between the solder pads 40 and the packaged chip 20, thereby facilitating the fabrication of the chip package structure 100 of the present application.

[0078] like Figure 4 As shown, within the first region 31, on the exposed portion of the first surface 11 of the substrate 10, at least the surface of the circuit layer 50 is provided with a coating 60. During the preparation of the chip package structure 100 of the present application, it is necessary to provide the coating 60 on the surface of the pad 40 to prevent oxidation of the pad 40 before soldering the pad 40 to the packaged chip 20, thereby reducing the connection strength between the pad 40 and the packaged chip 20.

[0079] Because the first region 31 exposes a portion of the first surface 11, the circuit layer 50 and pads 40 on the first surface 11 are also exposed. During the preparation of the chip package structure 100 of the present application, when the coating 60 is applied to the surface of the pads 40, the portion of the circuit layer 50 exposed by the first region 31 is also coated with the coating 60. This prevents oxidation of the circuit layer 50 and affects its performance, thereby ensuring the reliability of the chip package structure 100 of the present application.

[0080] In the embodiments of this application, Figure 4As shown, the surface of the circuit layer 50 corresponding to the second area 32 is covered by the insulating layer 30. The insulating layer 30 is used to protect the circuit layer 50 corresponding to the second area 32, so as to prevent the circuit layer 50 corresponding to the second area 32 from being oxidized and affecting its performance, thereby ensuring the reliability of the chip packaging structure 100 of the present application.

[0081] That is, the surface of the circuit layer 50 of the chip packaging structure 100 of the present application is protected from oxidation by providing a coating 60 or an insulating layer 30 , thereby ensuring the performance of the circuit layer 50 and improving the reliability of the chip packaging structure 100 of the present application.

[0082] However, in the high-temperature and high-pressure environment during the manufacturing process and use, the coating 60 will crack and form volatile gases. These gases will escape to the surface of the packaged chip 20 or the interior of the packaged chip 20, resulting in reduced reliability of the packaged chip 20 and affecting the operating performance of the packaged chip 20. It can be understood that compared to the solution of providing a coating on the entire circuit layer surface, the chip packaging structure 100 of the present application provides an insulating layer 30 on the first surface 11 and provides the insulating layer 30 on the surface of the circuit layer 50 in the second area 32, thereby reducing the installation area of ​​the coating 60 on the circuit layer 50 and reducing the impact of the coating 60 material after high-temperature cracking on the packaged chip 20, thereby improving the reliability of the chip packaging structure 100 of the present application.

[0083] It is worth noting that, during the manufacturing process of the chip package structure 100 of the present application, the coating 60 disposed on the surface of the pad 40 may be lost as the soldering process proceeds. In the present embodiment and subsequent embodiments, the coating 60 is disposed on a portion of the circuit layer 50 corresponding to the first region 31. That is, the coating 60 in the present embodiment and subsequent embodiments is the coating 60 disposed on the circuit layer 50. In actual practice, the surface of the pad 40 may or may not have the coating 60. The above-mentioned different solutions are all within the scope of protection of the present application and will not be described in detail here.

[0084] In one embodiment, at least a portion of the surface of the circuit layer 50 in the first region 31 is provided with a coating 60, while the surface of the circuit layer 50 in the second region 32 is directly bonded to the insulating layer 30. That is, within the circuit layer 50 disposed on the first surface 11, the surface of the circuit layer 50 corresponding to the first region 31 is provided only with the coating 60, while the surface of the circuit layer 50 corresponding to the second region 32 is provided only with the insulating layer 30 without the coating 60.

[0085] Therefore, according to the structure of the chip packaging structure 100 provided in the present application, while ensuring the packaging performance, the setting area of ​​the coating 60 on the surface of the circuit layer 50 can be effectively reduced, thereby reducing the impact of the coating 60 material after high-temperature decomposition on the packaged chip 20, thereby improving the reliability of the chip packaging structure 100 of the present application.

[0086] In one embodiment, if Figure 2 As shown, along the thickness direction of the substrate 10, a functional device 22 is provided on the second surface 21 of the packaged chip 20, which faces the side of the substrate 10. Specifically, the functional device 22 can be arranged to protrude relative to the second surface 21, or to be arranged to be recessed relative to the second surface 21, or to be arranged flush with the second surface 21. The following examples are described using the example of the functional device 22 being arranged protruding on the second surface 21. The functional device 22 is spaced apart from the insulating layer 30 to prevent the insulating layer 30 from affecting the performance of the functional device 22, thereby ensuring the performance of the packaged chip 20 and thus ensuring the reliability of the chip packaging structure 100 of the present application.

[0087] exist Figure 2 In the illustrated example, the projection of the insulating layer 30 on the second surface 21 covers the functional device 22, and the projection of the functional device 22 on the insulating layer 30 is located within the second region 32; wherein, at least a portion of the circuit layer 50 within the second region 32 is not provided with the coating 60. That is, along the thickness direction of the substrate 10, the surface of the portion of the circuit layer 50 covered by the projection of the functional device 22 on the first surface 11 is not provided with the coating 60. Optionally, within the entire area corresponding to the second region 32, the circuit layer 50 within the second region 32 is not provided with the coating 60. Because the second region 32 is directly opposite the functional device 22 above, and the coating 60 is not provided within the second region 32, the impact of gases generated by the high-temperature decomposition of the coating 60 on the functional device 22 can be effectively reduced, thereby ensuring the reliability of the chip packaging structure 100 of the present application.

[0088] In one embodiment, along the thickness direction of the substrate 10, the projection of the pad 40 on the second surface 21 is spaced apart from the functional device 22, and along the thickness direction of the substrate 10, the projection area of ​​the functional device 22 on the substrate 10 is less than or equal to the area of ​​the insulating layer 30 covered by the projection of the packaged chip 20 on the substrate 10.

[0089] exist Figure 2 and Figure 3In the illustrated example, along the thickness direction of the substrate 10, the projection of the solder pad 40 on the second surface 21 is spaced apart from the functional device 22, such that the projection of the functional device 22 on the first surface 11 is spaced apart from the first region 31. Because the first region 31 is located within the gap between the packaged chip 20 and the substrate 10, it is understood that the projection area of ​​the functional device 22 on the first surface 11 is less than or equal to the area of ​​the insulating layer 30 covered by the projection of the packaged chip 20 on the first surface 11. This results in a relatively large area of ​​the insulating layer 30 within the gap between the packaged chip 20 and the substrate 10, which helps ensure that the circuit layer 50 provided with the coating 60 has a smaller area. This ensures the reliability of the chip packaging structure 100 of the present application.

[0090] Please see Figure 5 Another partial structural diagram of a chip packaging structure 100 provided by an embodiment of the present application is shown. Figure 5 Part of the structure of the packaged chip 20 is omitted, and the relative positions of the functional devices 22 are indicated by dotted lines.

[0091] like Figure 5 As shown, along the plane of the first surface 11, the spacing between the pad 40 and the insulating layer 30 is a first spacing D1, and the first spacing D1 is greater than or equal to 25 μm. In the embodiment of the present application, the first spacing D1 is used to limit the manufacturing error of the pad 40. Setting the first spacing D1 greater than or equal to 25 μm can ensure the accuracy of the manufacturing position of the pad 40, so that the position of the pad 40 on the substrate 10 can match the corresponding connection structure on the packaged chip 20. This ensures the connection reliability and yield of the chip packaging structure 100 of the present application.

[0092] In the embodiment of the present application, the width of the coating 60 between the pad 40 and the insulating layer 30 is a first width W1, which is greater than or equal to 15 μm and less than or equal to 50 μm. Specifically, the first width W1 can be set to 25 μm, 35 μm, or 40 μm. Due to the protective effect of the coating 60 on the circuit layer 50 and the impact of volatile gases generated by the decomposition of the coating 60 in a high temperature and high pressure environment on the functional device 22, setting the coating 60 with a width greater than or equal to 15 μm and less than or equal to 50 μm can, on the one hand, ensure that the coating 60 reliably protects the circuit layer 50 and ensures the reliability of the chip packaging structure 100 of the present application, and on the other hand, can effectively reduce the area of ​​the coating 60 within the first region 31, thereby further ensuring the reliability of the chip packaging structure 100 of the present application.

[0093] It is worth noting that in the present embodiment and subsequent embodiments, if only one circuit layer 50 is disposed in the region, when determining the width of the coating layer 60 on the circuit layer 50, the first width W1 of the coating layer 60 is the width of the coating layer 60 on a single metal trace in the circuit layer 50. In other embodiments, if multiple circuit layers 50 are disposed side by side in the region, the first width W1 of the coating layer 60 is the sum of the widths of all coating layers 60 on all circuit layers 50 in the region.

[0094] Please see Figure 6 and Figure 7 ,in Figure 6 This is another cross-sectional structural diagram of a chip packaging structure 100 provided by an embodiment of the present application. Figure 7 This is a schematic diagram of a partial cross-sectional structure of a chip packaging structure 100 provided in one embodiment of the present application. Figure 6 The cross-sectional structure diagram shown is Figure 2 The cross-sectional structure diagram shown is based on Figure 3 The cross-sectional structure diagram formed by different cutting lines is convenient for simultaneously showing the pad 40, the circuit layer 50 and the coating 60. Figure 5 The corresponding cutting line and Figure 2 The corresponding cutting lines intersect.

[0095] like Figure 6 and Figure 7 As shown, the coating 60 has a first thickness H1, which is greater than or equal to 0.1 μm and less than or equal to 0.5 μm. For example, the first thickness H1 is any one of 0.1 μm, 0.3 μm, and 0.5 μm. This ensures that the coating 60 provides protection for the circuit layer 50 while preventing the coating 60 from being too thick, which would result in excessive volatile gas content generated by the high-temperature decomposition of the coating 60 and thus affect the use of the functional device 22. This further ensures the reliability of the chip package structure 100 of the present application.

[0096] In one embodiment, within the projection area of ​​the packaged chip 20 on the substrate 10, the ratio of the area of ​​the circuit layer 50 in the second area 32 to the total area of ​​the circuit layer 50 with and without the coating 60 is greater than or equal to 0.6 and less than or equal to 0.8. On the one hand, the spacing between the pad 40 and the insulating layer 30 along the plane direction of the first surface 11 is ensured, and on the other hand, the setting area of ​​the coating 60 is limited, thereby further ensuring the reliability of the chip packaging structure 100 of the present application.

[0097] Specifically, compared to the solution of providing a coating on the entire circuit layer surface, the chip packaging structure 100 of the present application has a ratio of the area of ​​the circuit layer 50 in the second zone 32 to the total area of ​​the circuit layer 50 with and without the coating 60 that is greater than or equal to 0.6 and less than or equal to 0.8, so that the high-temperature failure rate of the chip packaging structure 100 of the present application is greater than or equal to 0% and less than or equal to 5%.

[0098] For example, in the process of testing the high-temperature failure rate, the ratio of the area of ​​the circuit layer 50 in the second zone 32 of the chip packaging structure 100 of the present application to the total area of ​​the circuit layer 50 with and without the coating 60 is 0.7. 300 product samples with the above ratio of 0.7 were selected for testing, and the high-temperature failure rate of the chip packaging structure 100 corresponding to this ratio was found to drop to 1.3%.

[0099] Please see Figure 8 FIG. 1 is another partial structural diagram of a chip package structure 100 provided by an embodiment of the present application. In order to facilitate the description of the position of the pad 40, Figure 8 The circuit layer 50 shown in the following figures is connected to the pad 40 .

[0100] like Figure 8 As shown, a plurality of solder pads 40 are provided within the first region 31. The solder pads 40 are spaced apart from one another along the plane of the first surface 11. Along the thickness of the substrate 10, the solder pads 40 are electrically connected between the packaged chip 20 and the substrate 10. During operation of the chip package structure 100 of the present application, the solder pads 40 are used to allow signals to be transmitted between the packaged chip 20 and the substrate 10, thereby achieving the signal transmission and filtering and frequency modulation functions of the chip package structure 100 of the present application.

[0101] At the same time, since the packaged chip 20 is connected to the substrate 10 via the pads 40, the provision of multiple pads 40 not only ensures the reliability of the electrical connection between the pads 40 and the substrate 10, but also ensures the reliability of the pads 40 supporting the packaged chip 20. This ensures the connection reliability of the chip packaging structure 100 of the present application.

[0102] In the embodiment of the present application, the insulating layer 30 includes a first insulating portion 33 and a second insulating portion 34 spaced apart from each other, and the first insulating portion 33 is arranged around the second insulating portion 34 to ensure space between the first insulating portion 33 and the second insulating portion 34 to facilitate the installation of the pad 40.

[0103] exist Figure 8In the illustrated example, along the thickness direction of the substrate 10, the projection of the second insulating portion 34 on the second surface 21 covers the functional device 22, and within the area corresponding to the second insulating portion 34, at least a portion of the circuit layer 50 is not provided with the coating 60. That is, the second insulating portion 34 is opposite the functional device 22, and the area of ​​the second insulating portion 34 is greater than or equal to the area of ​​the functional device 22. The coating 60 is not provided on the circuit layer 50 corresponding to the second insulating portion 34. This further reduces the impact of the decomposition of the coating 60 on the functional device 22, further ensuring the reliability of the chip package structure 100 of the present application.

[0104] In one embodiment, if Figure 8 As shown, multiple pads 40 surround the outer edge of the functional device 22 so that each pad 40 can cooperate with each other to ensure reliable support for the packaged chip 20 while achieving electrical connection between the packaged chip 20 and the substrate 10.

[0105] Please see Figure 9 FIG. 1 is another partial structural diagram of a chip packaging structure 100 provided by an embodiment of the present application.

[0106] like Figure 9 As shown, the first area 31 includes a first sub-area 311 and a second sub-area 312 spaced apart from each other. The first sub-area 311 is arranged between the first insulating part 33 and the second insulating part 34, and the second sub-area 312 is located in the second insulating part 34. The second sub-area 312 corresponds to the functional device 22; wherein, a coating 60 is provided on the corresponding pads 40 and / or circuit layer 50 in the first sub-area 311 and the second sub-area 312, and no coating 60 is provided on the circuit layer 50 in the area corresponding to the second insulating part 34.

[0107] That is, the first sub-region 311 is used to separate the insulating layer 30 and form the first insulating portion 33 and the second insulating portion 34, and the first sub-region 311 surrounds the periphery of the second sub-region 312. Figure 9 In the embodiment, the first sub-area 311 is arranged as a circle. Exemplarily, the first sub-area 311 is shaped as a rectangular ring or other ring shape. The second sub-area 312 is a closed circular ring. It is understood that the arrangement of the first sub-area 311 and the second sub-area 312 can match the different positions of different bonding pads 40, facilitating the manufacture of the chip package structure 100 of the present application.

[0108] The second insulating portion 34 is aligned with the functional device 22 , and the coating 60 is not provided on the circuit layer 50 corresponding to the second insulating portion 34 , thereby further reducing the impact of the coating 60 cracking on the functional device 22 and further ensuring the reliability of the chip packaging structure 100 of the present application.

[0109] In one embodiment, if Figure 10As shown, a plurality of second sub-regions 312 are provided, and the plurality of second sub-regions 312 are spaced apart from each other. A pad 40 is also provided in each second sub-region 312. The pad 40 in the second sub-region 312 is electrically connected to the pad in the functional device 22. A coating 60 is also provided in each second sub-region 312. The coating 60 is not provided on the circuit layer 50 corresponding to the second insulating portion 34 outside the second sub-region 312, thereby reducing the area occupied by the coating 60 and further ensuring the reliability of the chip package structure 100 of the present application.

[0110] As can be understood, the provision of multiple second sub-regions 312 facilitates the fabrication of solder pads 40 within the area where the second insulating portion 34 is located, and enables electrical connection between these solder pads 40 and the solder pads within the functional device 22, thereby ensuring the signal transmission and filtering and frequency modulation functions of the chip package structure 100 of the present application. The provision of the coating 60 within each second sub-region 312 facilitates protection of the corresponding circuit layer 50.

[0111] On the other hand, the provision of the plurality of second sub-regions 312 can cooperate with the first sub-regions 311 to block the diffusion of the dispensing glue 70 along the plane of the first surface 11 during the manufacturing process of the chip package structure 100 of the present application, thereby limiting the flow range of the dispensing glue 70 and preventing the dispensing glue 70 from flowing onto the functional device 22 and affecting the performance of the functional device 22. This further ensures the reliability of the chip package structure 100 of the present application.

[0112] It is worth mentioning that, compared with a solution in which no groove is used to block the flow of the glue, the matching arrangement of the groove 35 and the second groove 341 can reduce the glue overflow rate of the glue 70 by more than 90%.

[0113] In one embodiment, if Figure 9 As shown, along the plane direction of the first surface 11, the distance between the first insulating portion 33 and the second insulating portion 34 is a second distance D2, and the second distance D2 is greater than or equal to 30 μm and less than or equal to 300 μm. Exemplarily, the second distance D2 is any one of 30 μm, 50 μm, 100 μm, 200 μm, and 300 μm.

[0114] In the embodiment of the present application, since the pad 40 is disposed between the first insulating portion 33 and the second insulating portion 34, a second spacing D2 greater than or equal to 30 μm and less than or equal to 300 μm is provided. This not only facilitates the manufacture of the pad 40 but also limits the area for disposing the coating 60 between the first insulating portion 33 and the second insulating portion 34. This further ensures the reliability of the chip package structure 100 of the present application.

[0115] In the embodiment of the present application, the width of the coating layer 60 between the first insulating portion 33 and the second insulating portion 34 is a second width W2, and the second width W2 is greater than or equal to 30 μm and less than or equal to 300 μm. Exemplarily, the second width W2 is any one of 30 μm, 50 μm, 100 μm, 200 μm, and 300 μm.

[0116] Due to the influence of volatile gases generated by the decomposition of the coating 60 in a high temperature and high pressure environment on the functional device 22, setting a coating 60 greater than or equal to 30μm and less than or equal to 300μm can effectively reduce the area of ​​the coating 60 between the first insulating part 33 and the second insulating part 34 while ensuring the coverage of the coating 60 on the circuit layer 50, thereby further ensuring the reliability of the chip packaging structure 100 of the present application.

[0117] In one embodiment, along the plane of the first surface 11, a second distance D2 between the first insulating portion 33 and the second insulating portion 34 is greater than or equal to 60 μm and less than or equal to 200 μm. Exemplarily, the second distance D2 is any one of 60 μm, 100 μm, 150 μm, and 200 μm.

[0118] In the embodiment of the present application, since the pad 40 is disposed between the first insulating portion 33 and the second insulating portion 34, a second spacing D2 greater than or equal to 60 μm and less than or equal to 200 μm is provided. This not only facilitates the manufacture of the pad 40, but also limits the area for disposing the coating 60 between the first insulating portion 33 and the second insulating portion 34. This further ensures the reliability of the chip package structure 100 of the present application.

[0119] The second width W2 of the coating layer 60 between the first insulating portion 33 and the second insulating portion 34 is greater than or equal to 50 μm and less than or equal to 200 μm. For example, the second width W2 is any one of 60 μm, 100 μm, 150 μm, and 200 μm.

[0120] Due to the influence of volatile gases generated by the decomposition of the coating 60 in a high temperature and high pressure environment on the functional device 22, setting a coating 60 greater than or equal to 60 μm and less than or equal to 200 μm can effectively reduce the area of ​​the coating 60 between the first insulating part 33 and the second insulating part 34 while ensuring the coverage of the coating 60 on the circuit layer 50, thereby further ensuring the reliability of the chip packaging structure 100 of the present application.

[0121] In one embodiment, see Figure 2 , along the thickness direction of the substrate 10 , the first insulating portion 33 is spaced apart from the second surface 21 ; the packaged chip 20 is also bonded and fixed to the first insulating portion 33 by adhesive 70 , and the adhesive 70 surrounds the edge of the packaged chip 20 .

[0122] In the embodiment of the present application, a portion of the first insulating portion 33 is located within the gap between the packaged chip 20 and the substrate 10. The adhesive 70 is used to bond and secure the first insulating portion 33 and the packaged chip 20, thereby sealing the functional device 22. In other words, the adhesive 70 can enhance the connection and support strength between the packaged chip 20 and the substrate 10, ensuring the connection reliability of the chip package structure 100 of the present application.

[0123] On the other hand, the glue 70 surrounds the edge of the packaged chip 20, and the first insulating portion 33 surrounds the outer edge of the functional device 22. The glue 70 cooperates with the first insulating portion 33 to seal the functional device 22, preventing external impurities from entering and affecting the function of the packaged chip 20. This further improves the reliability of the chip packaging structure 100 of the present application.

[0124] In the embodiment of the present application, since the first insulating portion 33 and the second insulating portion 34 are spaced apart, the first insulating portion 33 surrounds the outer edge of the second insulating portion 34. During the manufacturing process of the chip package structure 100 of the present application, the adhesive 70 has fluidity. It is understood that the gap between the first insulating portion 33 and the second insulating portion 34 is used to accommodate a portion of the adhesive 70, thereby preventing the adhesive 70 from diffusing into the functional device 22 and affecting its function. This further improves the reliability of the chip package structure 100 of the present application.

[0125] In one embodiment, along the thickness direction of the substrate 10, the glue dots 70 are located on the surface of the first insulating portion 33 away from the substrate 10. Alternatively, along the thickness direction of the substrate 10, a portion of the glue dots 70 are located on the surface of the first insulating portion 33 away from the substrate 10, and another portion of the glue dots 70 are located on the coating 60 between the first insulating portion 33 and the second insulating portion 34.

[0126] That is, during the manufacturing process of the chip package structure 100 of the present application, based on the fluidity of the adhesive 70, some of the adhesive 70 may flow between the first insulating portion 33 and the second insulating portion 34, or the adhesive 70 may be entirely located on the surface of the first insulating portion 33 away from the substrate 10. In the present embodiment and subsequent embodiments, the description is based on the assumption that the adhesive 70 is entirely located on the surface of the first insulating portion 33 away from the substrate 10.

[0127] In one embodiment, if Figure 2 As shown, along the thickness direction of the substrate 10, the spacing between the first insulating portion 33 and the second surface 21 is a third spacing D3, and the third spacing D3 is greater than or equal to 1 μm and less than or equal to 30 μm. On the one hand, it avoids the third spacing D3 being too small, which causes the glue 70 to flow to the functional device 22 due to capillary phenomenon, thereby ensuring the working performance of the chip packaging structure 100 of the present application.

[0128] On the other hand, the difficulty of bonding the packaged chip 20 to the first insulating portion 33 by the adhesive 70 is avoided due to an excessively large third distance D3, thereby facilitating the manufacture of the chip package structure 100 of the present application. Furthermore, the third distance D3 can effectively control the overall thickness of the chip package structure 100, facilitating miniaturization of the chip package structure 100 of the present application.

[0129] In one embodiment, along the thickness direction of the substrate 10, the thickness of the first insulating portion 33 is greater than or equal to the thickness of the second insulating portion 34. Since the functional device 22 is provided on the second surface 21, the second insulating portion 34 having a smaller thickness than the first insulating portion 33 can be provided. This can prevent the glue 70 from contacting the functional device 22 when it flows onto the second insulating portion 34, while ensuring a blocking effect on the glue 70. This further ensures the reliability of the chip package structure 100 of the present application.

[0130] On the other hand, providing a relatively thick first insulating portion 33 can reduce the possibility of the coating 60 volatilizing onto the packaged chip 20 through the first insulating portion 33, thereby further ensuring the reliability of the chip packaging structure 100 of the present application.

[0131] In one embodiment, the thickness of the first insulating portion 33 is greater than or equal to 15 μm and less than or equal to 35 μm. This prevents the first insulating portion 33 from being too thick, which would result in the third distance D3 being too small, thereby causing the dispensing glue 70 to flow to the functional device 22 due to capillary action. This ensures the operating performance of the chip package structure 100 of the present application. Furthermore, the third distance D3 is reduced, facilitating the manufacture of the chip package structure 100 of the present application.

[0132] In one embodiment, the thickness of the second insulating portion 34 is greater than or equal to 10 μm and less than or equal to 20 μm. This prevents the second insulating portion 34 from being too thick, which would result in a small spacing between the functional device 22 and the second insulating portion 34. This would allow the adhesive 70 to flow to the functional device 22 due to capillary action when it diffuses onto the surface of the second insulating portion 34, thereby ensuring the performance of the chip package structure 100 of the present application. Furthermore, the second insulating portion 34 also ensures its blocking effect on the adhesive 70, thereby further improving the reliability of the chip package structure 100 of the present application.

[0133] In one embodiment, the coating 60 includes at least one of triazoline, imidazole organic crystalline base, nickel gold, and nickel palladium gold.

[0134] In one embodiment, if Figure 2As shown, the chip package structure 100 further includes a plastic encapsulation layer 80. Along the thickness direction of the substrate 10, the plastic encapsulation layer 80 is located on the side of the substrate 10 on which the packaged chip 20 is mounted. The plastic encapsulation layer 80 covers the packaged chip 20 to protect the packaged chip 20 and prevent external impurities from damaging the packaged chip 20. This further improves the reliability of the chip package structure 100 of the present application.

[0135] See also Figure 11 and Figure 12 ,in Figure 11 This is another cross-sectional structural diagram of the chip packaging structure 100 provided by an embodiment of the present application. Figure 12 This is another partial structural diagram of the chip packaging structure 100 provided in one embodiment of the present application.

[0136] like Figure 11 and Figure 12 As shown, the chip packaging structure 100 of the present application includes a substrate 10, a packaged chip 20, an insulating layer 30 and a glue 70. Along the thickness direction of the substrate 10, the insulating layer 30 is provided on the first surface 11 of the substrate 10. The first surface 11 is provided with a solder pad 40, and the solder pad 40 is conductively connected to the packaged chip 20. Figure 11 In the illustrated example, the pads 40 protrude relative to the first surface 11 to facilitate electrical connection with the packaged chip 20. In another embodiment, the pads 40 are embedded in the first surface 11 and flush with the first surface 11. In another embodiment, the pads 40 are embedded in the first surface 11 and recessed relative to the first surface 11.

[0137] The first surface 11 is further provided with a circuit layer 50, which extends along the plane direction of the first surface 11. Figure 12 In the illustrated example, a portion of the wiring pattern in the circuit layer 50 is connected to the pad 40, while another portion of the wiring pattern in the circuit layer 50 is spaced apart from the pad 40. In the embodiment of the present application, the circuit layer 50 connected to the pad 40 is used to transmit signals to the packaged chip 20, while the circuit layer 50 spaced apart from the pad 40 is used to transmit signals to other components on the substrate 10, thereby achieving the filtering and frequency modulation function of the chip packaging structure 100 of the present application.

[0138] In the present embodiment and subsequent embodiments, the packaged chip 20 is a filter chip. Accordingly, the circuit layer 50 connected to the pad 40 is used to transmit signals to the packaged chip 20 to implement the filtering and frequency modulation functions of the chip packaging structure 100 of the present application. The circuit layer 50, separated from the pad 40, also serves to constrain the electric field generated by the packaged chip 20 during operation and reduce impedance. In other embodiments, the packaged chip 20 can also be other types of chips. For example, the packaged chip 20 is an amplifier chip. This application does not impose any particular restrictions on this.

[0139] In the embodiment of the present application, the insulating layer 30 is provided with a groove 35. Along the thickness direction of the substrate 10, the projection of the packaged chip 20 on the substrate 10 covers the groove 35. Along the plane of the first surface 11, the adhesive 70 surrounds the outside of the groove 35 and adheres between the insulating layer 30 and the packaged chip 20. In other words, the adhesive 70 cooperates with the insulating layer 30 to seal the packaged chip 20, preventing external impurities from entering and affecting the functionality of the packaged chip 20. This further enhances the reliability of the chip package structure 100 of the present application.

[0140] On the other hand, since the adhesive 70 is fluid during the manufacturing process of the chip package structure 100 of the present application, it is understandable that the provision of the groove 35 can accommodate a portion of the adhesive 70 during the manufacturing process of the chip package structure 100 of the present application, thereby preventing the adhesive 70 from diffusing to the packaged chip 20 and affecting the functional use of the packaged chip 20. This improves the reliability of the chip package structure 100 of the present application.

[0141] In the embodiment of the present application, a coating 60 is provided on the surface of the circuit layer 50 located within the groove 35, and at least a portion of the circuit layer 50 located outside the groove 35 is directly bonded to the insulating layer 30. In other words, the coating 60 and the insulating layer 30 are used to prevent oxidation of the circuit layer 50 and thus affect its performance, thereby ensuring the reliability of the chip package structure 100 of the present application.

[0142] On the other hand, since the coating 60 will decompose and form volatile gases, these gases will escape to the surface of the packaged chip 20 and affect the operating performance of the packaged chip 20. It is understandable that, compared to the prior art solution of providing a coating on the entire circuit layer surface, the chip packaging structure 100 of the present application provides an insulating layer 30 on the first surface 11 and also provides the insulating layer 30 on the surface of the circuit layer 50 not within the groove 35, so that all circuit layers 50 within the groove 35 are provided with the coating 60. This reduces the area of ​​the coating 60 on the circuit layer 50, thereby reducing the impact of the coating 60 material after high-temperature decomposition on the packaged chip 20, thereby improving the reliability of the chip packaging structure 100 of the present application.

[0143] In one embodiment, within the projection area of ​​the packaged chip 20 on the substrate 10, the ratio of the area of ​​the circuit layer 50 in the second area 32 to the total area of ​​the circuit layer 50 with and without the coating 60 is greater than or equal to 0.6 and less than or equal to 0.8. On the one hand, the spacing between the pad 40 and the insulating layer 30 along the plane direction of the first surface 11 is ensured, and on the other hand, the setting area of ​​the coating 60 is limited, thereby further ensuring the reliability of the chip packaging structure 100 of the present application.

[0144] In one embodiment, along the thickness direction of the substrate 10 , the distance between the notch of the groove 35 and the packaged chip 20 is a fourth distance D4 , and the fourth distance D4 is greater than or equal to 1 μm and less than or equal to 30 μm.

[0145] Since the projection of the packaged chip 20 on the substrate 10 covers the groove 35, it is understandable that setting the fourth distance D4 greater than or equal to 1 μm and less than or equal to 30 μm can, on the one hand, prevent the fourth distance D4 from being too small, which may cause the dispensing glue 70 to flow to the second surface 21 of the packaged chip 20 facing the first surface 11 due to capillary phenomenon, thereby ensuring the working performance of the chip packaging structure 100 of the present application.

[0146] On the other hand, the fourth distance D4 is too large, which would increase the difficulty of the adhesive 70 in bonding the packaged chip 20 to the insulating layer 30, thereby facilitating the manufacture of the chip package structure 100 of the present application. Furthermore, the fourth distance D4 can effectively control the overall thickness of the chip package structure 100, facilitating the miniaturization of the chip package structure 100 of the present application.

[0147] In one embodiment, a functional device 22 is provided on the second surface 21 of the packaged chip 20, which faces the side of the substrate 10, along the thickness direction of the substrate 10. Specifically, the functional device 22 can be provided protrudingly relative to the second surface 21, or recessed relative to the second surface 21, or flush with the second surface 21. The following examples are described using the example of the functional device 22 being provided protrudingly on the second surface 21. The functional device 22 is spaced apart from the insulating layer 30 to prevent the insulating layer 30 from affecting the performance of the functional device 22, thereby ensuring the performance of the packaged chip 20 and, therefore, the reliability of the chip packaging structure 100 of the present application.

[0148] exist Figure 12 In the illustrated example, along the plane of first surface 11, recess 35 surrounds functional device 22. Coating 60 is provided on at least a portion of pad 40 and circuit layer 50 within recess 35. That is, along the thickness of substrate 10, coating 60 is provided on the portion of circuit layer 50 not covered by the projection of functional device 22 on first surface 11. This reduces the impact of gases generated by high-temperature decomposition of coating 60 on functional device 22, further ensuring the reliability of the chip package structure 100 of the present application.

[0149] On the other hand, within the region where the groove 35 is located, a portion of the circuit layer 50 is provided with a coating 60. For example, along the plane of the first surface 11, for all circuit layers 50 within the region where the groove 35 is located, the circuit layers 50 located near the pad 40 are not provided with the coating 60, while the circuit layers 50 in other regions are provided with the coating 60. This prevents the high temperature at the pad 60 from causing the surrounding coating 60 to volatilize during operation of the chip package structure 100 of the present application. This reduces the impact of gases generated by the high-temperature decomposition of the coating 60 on the functional device 22, thereby further ensuring the reliability of the chip package structure 100 of the present application.

[0150] In one embodiment, if Figure 12 As shown, there are multiple grooves 35 , and the multiple grooves 35 surround the outer edge of the functional device 22 , and the grooves 35 are spaced apart from each other.

[0151] In one embodiment, if Figure 13 As shown, the groove 35 is annular in shape, and surrounds the outer edge of the functional device 22 .

[0152] In the above two embodiments, along the planar direction of the first surface 11, the groove 35 is spaced apart from the functional device 22 to reduce the impact of the gas generated by the high-temperature decomposition of the coating 60 in the groove 35 on the functional device 22, thereby further ensuring the reliability of the chip packaging structure 100 of the present application.

[0153] It is worth mentioning that when the shape of the groove 35 is annular, it does not only mean that the shape of the groove 35 is circular. In the embodiment of the present application and subsequent embodiments, the shape of the groove 35 is annular, which refers to a closed ring structure formed around a central area. For example, Figure 13 As shown, the shape of the annular groove 35 is similar to a rectangle.

[0154] In one embodiment, if Figure 13 As shown, the groove 35 is in the shape of a closed ring. Along the plane direction of the first surface 11, the groove 35 divides the insulating layer into a first insulating portion 33 and a second insulating portion 34 spaced apart from each other. The first insulating portion 33 is used to form the outer groove wall of the groove 35, and the second insulating portion 34 is used to form the inner groove wall of the groove 35. Along the thickness direction of the substrate 10, the thickness dimension of the first insulating portion 33 is greater than or equal to the thickness dimension of the second insulating portion 34.

[0155] Because the functional device 22 is protruding from the second surface 21, the second insulating portion 34 having a smaller thickness than the first insulating portion 33 is provided. This prevents the dispensing glue 70 from contacting the functional device 22 when it flows onto the second insulating portion 34, while ensuring a blocking effect on the dispensing glue 70. This further ensures the reliability of the chip package structure 100 of the present application.

[0156] On the other hand, in the area corresponding to the first insulating portion 33, at least a portion of the circuit layer 50 is provided with a coating 60, and in the area corresponding to the second insulating portion 34, at least a portion of the circuit layer 50 is not provided with a coating 60. Figure 13 In the illustrated example, the second insulating portion 34 is closer to the functional device 22 than the first insulating portion 33, and no coating 60 is provided on the circuit layer 50 corresponding to the second insulating portion 34, thereby further reducing the impact of the cracking of the coating 60 on the functional device 22, and further ensuring the reliability of the chip packaging structure 100 of the present application.

[0157] In one embodiment, there are multiple pads 40, at least some of which are exposed through the groove 35. Along the plane direction of the first surface 11, the spacing between the pads 40 accommodated in the groove 35 and the groove walls on both sides of the groove 35 is greater than or equal to 25 μm. In the embodiment of the present application, the spacing between the pads 40 accommodated in the groove 35 and the groove walls on both sides of the groove 35 is used to limit the manufacturing error of the pads 40. Setting the spacing between the pads 40 and the groove walls on both sides of the groove 35 to be greater than or equal to 25 μm can ensure the accuracy of the manufacturing position of the pads 40, so that the position of the pads 40 on the substrate 10 can match the corresponding connection structure on the packaged chip 20. This ensures the connection reliability and yield of the chip packaging structure 100 of the present application.

[0158] In the embodiment of the present application, the width of the coating 60 between the pad 40 and the insulating layer 30 is greater than or equal to 15 μm and less than or equal to 50 μm. Due to the protective effect of the coating 60 on the circuit layer 50 and the impact of volatile gases generated by the decomposition of the coating 60 in a high-temperature and high-pressure environment on the functional device 22, providing a coating 60 with a width greater than or equal to 15 μm and less than or equal to 50 μm can, on the one hand, ensure that the coating 60 reliably protects the circuit layer 50 and ensures the reliability of the chip packaging structure 100 of the present application, and on the other hand, effectively reduce the area of ​​the coating 60 within the groove 35, thereby further ensuring the reliability of the chip packaging structure 100 of the present application.

[0159] See also Figure 14 and Figure 15 ,in Figure 14 This is a schematic structural diagram of a chip packaging structure 100 provided in one embodiment of the present application. Figure 15 This is another partial structural diagram of the chip packaging structure 100 provided in one embodiment of the present application.

[0160] like Figure 14 and Figure 15As shown, the chip package structure 100 of the present application includes a substrate 10, a packaged chip 20, and an insulating layer 30. Along the thickness direction of the substrate 10, the packaged chip 20 and the insulating layer 30 are located on the same side of the substrate 10. A circuit layer 50 is provided on the first surface 11 of the substrate 10 facing the packaged chip 20.

[0161] exist Figure 15 In the illustrated example, the first surface 11 is electrically connected to the packaged chip 20 via the pads 40. A portion of the wiring pattern in the circuit layer 50 is connected to the pads 40, while another portion of the wiring pattern in the circuit layer 50 is spaced apart from the pads 40. In the embodiment of the present application, the circuit layer 50 connected to the pads 40 is used to transmit signals to the packaged chip 20, while the circuit layer 50 spaced apart from the pads 40 is used to transmit signals to other components on the substrate 10, thereby achieving the functional use of the chip package structure 100 of the present application.

[0162] In the present embodiment and subsequent embodiments, the packaged chip 20 is a filter chip. Accordingly, the circuit layer 50 connected to the pad 40 is used to transmit signals to the packaged chip 20 to implement the filtering and frequency modulation functions of the chip packaging structure 100 of the present application. The circuit layer 50, separated from the pad 40, also serves to constrain the electric field generated by the packaged chip 20 during operation and reduce impedance. In other embodiments, the packaged chip 20 can also be other types of chips. For example, the packaged chip 20 is an amplifier chip. This application does not impose any particular restrictions on this.

[0163] In the embodiment of the present application, along the thickness direction of the substrate 10, within the projection area of ​​the packaged chip 20 on the substrate 10, the insulating layer 30 is disposed on the first surface 11. Figure 14 In the illustrated example, the insulating layer 30 includes a first region 31 and a second region 32 disposed on one side of the first region 31 . Optionally, along the plane direction of the first surface 11 , the first region 31 is connected to the second region 32 .

[0164] The first region 31 is used to expose a portion of the first surface 11 of the substrate 10, and to expose a portion or all of the circuit layer 50 within the first surface 11. The solder pads 40 are disposed on the first surface 11 within the first region 31. This prevents the insulating layer 30 from interfering with the electrical connection between the solder pads 40 and the packaged chip 20, thereby facilitating the fabrication of the chip package structure 100 of the present application.

[0165] In the first region 31, on the exposed portion of the first surface 11 of the substrate 10, at least the surface of the circuit layer 50 is provided with a coating 60. During the preparation of the chip package structure 100 of the present application, the coating 60 is required on the surface of the pad 40 to prevent oxidation of the pad 40 before soldering the pad 40 to the packaged chip 20, thereby reducing the connection strength between the pad 40 and the packaged chip 20.

[0166] Because the first region 31 exposes a portion of the first surface 11, the circuit layer 50 and pads 40 on the first surface 11 are also exposed. During the preparation of the chip package structure 100 of the present application, when the coating 60 is applied to the surface of the pads 40, the portion of the circuit layer 50 exposed by the first region 31 is also coated with the coating 60. This prevents oxidation of the circuit layer 50 and affects its performance, thereby ensuring the reliability of the chip package structure 100 of the present application.

[0167] In the embodiment of the present application, the surface of the circuit layer 50 corresponding to the second area 32 is covered by the insulating layer 30. The insulating layer 30 is used to protect the circuit layer 50 corresponding to the second area 32, thereby preventing the circuit layer 50 corresponding to the second area 32 from being oxidized and affecting its performance, thereby ensuring the reliability of the chip packaging structure 100 of the present application.

[0168] That is, the surface of the circuit layer 50 of the chip packaging structure 100 of the present application is protected from oxidation by providing a coating 60 or an insulating layer 30 , thereby ensuring the performance of the circuit layer 50 and improving the reliability of the chip packaging structure 100 of the present application.

[0169] In the embodiment of the present application, the ratio of the area of ​​the circuit layer 50 in the first region 31 to the area of ​​the circuit layer 50 in the second region 32 is between 1.5 and 4. For example, the ratio of the area of ​​the circuit layer 50 in the first region 31 to the area of ​​the circuit layer 50 in the second region 32 is any one of 2, 3, and 4. Due to the high temperature and high pressure environment during the manufacturing process and use, the coating 60 will decompose and generate volatile gases. These gases will escape to the surface of the packaged chip 20 and affect the operating performance of the packaged chip 20.

[0170] It is understood that, compared to a solution in which the entire circuit layer surface is coated, the chip package structure 100 of the present application disposes the insulating layer 30 on the surface of the circuit layer 50 in the second region 32 and the coating 60 on the surface of the circuit layer 50 in the first region 31, with the ratio of the area of ​​the circuit layer 50 in the first region 31 to the area of ​​the circuit layer 50 in the second region 32 being between 1.5 and 4. By utilizing the insulating layer 30, the coating 60 area on the circuit layer 50 is reduced, thereby reducing the impact of the coating 60 material after high-temperature decomposition on the packaged chip 20, thereby improving the reliability of the chip package structure 100 of the present application.

[0171] In one embodiment, the thickness of the coating 60 is greater than or equal to 0.1 μm and less than or equal to 0.5 μm. Exemplarily, the first thickness H1 is any one of 0.1 μm, 0.3 μm, and 0.5 μm. This ensures that the coating 60 provides protection for the circuit layer 50 while preventing the coating 60 from being too thick, which would result in excessive volatile gas content generated by the high-temperature decomposition of the coating 60 and affect the use of the functional device 22. This further ensures the reliability of the chip package structure 100 of the present application.

[0172] In one embodiment, the insulating layer 30 further includes a groove 35, which separates the insulating layer 30 and forms a first insulating portion 33 and a second insulating portion 34, wherein the first insulating portion 33 is disposed around the second insulating portion 34. Along the thickness direction of the substrate 10, a functional device 22 is provided on the second surface 21 of the packaged chip 20 facing the side of the substrate 10. Specifically, the functional device 22 may be disposed protrudingly relative to the second surface 21, or concavely relative to the second surface 21, or flush with the second surface 21. The following examples are illustrative of an example in which the functional device 22 is disposed protrudingly on the second surface 21. The projection of the second insulating portion 34 on the second surface 21 covers the functional device 22; and in the area corresponding to the second insulating portion 34, at least a portion of the circuit layer 50 is not provided with a coating 60.

[0173] That is, the second insulating portion 34 is opposite to the functional device 22, and the area of ​​the second insulating portion 34 is greater than or equal to the area of ​​the functional device 22. No coating 60 is provided on the circuit layer 50 corresponding to the second insulating portion 34, thereby further reducing the impact of the cracking of the coating 60 on the functional device 22, and further ensuring the reliability of the chip packaging structure 100 of the present application.

[0174] In one embodiment, the distance between the first insulating portion 33 and the second insulating portion 34 is greater than or equal to 30 μm and less than or equal to 300 μm along the plane of the first surface 11. In the embodiment of the present application, the width of the coating 60 between the first insulating portion 33 and the second insulating portion 34 is greater than or equal to 30 μm and less than or equal to 300 μm.

[0175] In the embodiment of the present application, since the pad 40 is disposed between the first insulating portion 33 and the second insulating portion 34, the groove 35 is used to separate the first insulating portion 33 and the second insulating portion 34. Setting the groove width of the groove 35 to be greater than or equal to 30 μm and less than or equal to 300 μm not only facilitates the manufacture of the pad 40 but also limits the area for the coating 60 between the first insulating portion 33 and the second insulating portion 34. This further ensures the reliability of the chip package structure 100 of the present application.

[0176] Due to the influence of volatile gases generated by the decomposition of the coating 60 in a high temperature and high pressure environment on the functional device 22, setting a coating 60 greater than or equal to 30μm and less than or equal to 300μm can effectively reduce the area of ​​the coating 60 between the first insulating part 33 and the second insulating part 34 while ensuring the coverage of the coating 60 on the circuit layer 50, thereby further ensuring the reliability of the chip packaging structure 100 of the present application.

[0177] In one embodiment, if Figure 15 As shown, the first surface 11 is further provided with a solder pad 40, which is electrically connected to the packaged chip 20. The solder pad 40 protrudes relative to the first surface 11 to facilitate electrical connection with the packaged chip 20. In another embodiment, the solder pad 40 is embedded in the first surface 11 and is arranged flush with the first surface 11. In another embodiment, the solder pad 40 is embedded in the first surface 11 and is recessed relative to the first surface 11.

[0178] like Figure 16 As shown, the groove 35 includes a first section 351 and a second section 352 connected to each other, and the pad 40 is arranged in the first section 351. Along the plane direction of the first surface 11, the distance between the first insulating portion 33 and the second insulating portion 34 in the first section 351 is greater than or equal to the distance between the first insulating portion 33 and the second insulating portion 34 in the second section 352, and a coating 60 is provided on the corresponding circuit layers 50 in the first section 351 and the second section 352.

[0179] During the manufacturing process of the chip package structure 100 of the present application, it is generally necessary to ensure that the placement tolerance of the pads 40 is within a certain range. The width of the groove 35 corresponding to the first section 351 is greater than or equal to the width of the groove 35 corresponding to the second section 352. This facilitates the fabrication of the pads 40 within the first section 351, thereby facilitating the manufacture of the chip package structure 100 of the present application.

[0180] Please see Figure 17 FIG. 1 is another partial top view schematic diagram of a chip package structure 100 provided by an embodiment of the present application.

[0181] like Figure 17 As shown, the second insulating part 34 also includes a second groove 341, which is arranged near the middle area of ​​the functional device 22. There are multiple pads 40, a part of the pads 40 is arranged in the first section 351, and another part of the pads 40 is arranged in the second groove 341. A coating 60 is provided on the circuit layer 50 in the second groove 341.

[0182] It is understood that the provision of the second groove 341 facilitates the fabrication of the pad 40 within the region where the second insulating portion 34 is located, and enables electrical connection between the pad 40 and the pad within the functional device 22, thereby ensuring the filtering and frequency modulation functions of the chip package structure 100 of the present application. The provision of the coating 60 within the second groove 341 facilitates protection of the corresponding circuit layer 50.

[0183] On the other hand, the provision of the groove 35 and the second groove 341 can prevent the diffusion of the dispensing glue 70 along the plane of the first surface 11 during the manufacturing process of the chip package structure 100 of the present application, thereby limiting the flow range of the dispensing glue 70 and preventing the dispensing glue 70 from flowing onto the functional device 22 and affecting the performance of the functional device 22. This further ensures the reliability of the chip package structure 100 of the present application.

[0184] It is worth noting that, compared to a solution without using grooves to block the flow of the dispensed glue, the matching arrangement of the groove 35 and the second groove 341 can reduce the overflow rate of the dispensed glue 70 by more than 90%. It is understood that in other embodiments, the number of grooves 35 and the second groove 341 can be multiple, so as to cooperate with each other to further block the flow of the dispensed glue 70 and further ensure the reliability of the chip package structure 100 of the present application.

[0185] It should be understood that the terms "first," "second," etc. are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of the embodiments of this application, "plurality" means two or more, unless otherwise specifically defined.

[0186] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with an embodiment or example is included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0187] It should be understood that the application of this application is not limited to the above examples. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the scope of protection of the claims appended to this application. Those skilled in the art will understand that implementing all or part of the processes of the above embodiments and making equivalent changes in accordance with the claims of this invention still fall within the scope of this invention.

Claims

1. A chip packaging structure, characterized in that: include: A substrate, and a packaged chip and an insulating layer located on the same side of the substrate, wherein a solder pad and a circuit layer are provided on the first surface of the substrate facing the packaged chip along the thickness direction of the substrate, and the solder pad is electrically connected to the packaged chip; Along the thickness direction of the substrate, within the projection area of ​​the packaged chip on the substrate, the insulating layer is arranged on the first surface, and the insulating layer includes a first area and a second area. The circuit layer corresponding to the first area is exposed, and the solder pad is arranged correspondingly in the first area. At least part of the surface of the circuit layer in the first area is also provided with a coating, and the surface of the circuit layer in the second area is covered by the insulating layer.

2. The chip packaging structure according to claim 1, wherein: At least a portion of the surface of the circuit layer in the first area is provided with a coating, and the surface of the circuit layer in the second area is directly bonded to the insulating layer.

3. The chip packaging structure according to claim 1, wherein: A functional device is provided on the second surface of the packaged chip facing the substrate along the thickness direction of the substrate, the functional device is spaced apart from the insulating layer, the projection of the insulating layer on the second surface covers the functional device, and the projection of the functional device on the insulating layer is located within the second area; Wherein, at least a portion of the circuit layer in the second area is not provided with the coating layer.

4. The chip packaging structure according to claim 3, wherein: Along the plane direction of the first surface, the pad is spaced apart from the functional device, and along the thickness direction of the substrate, the projection area of ​​the functional device on the substrate is less than or equal to the area of ​​the insulating layer covered by the projection of the packaged chip on the substrate.

5. The chip packaging structure according to claim 1, wherein: Along the plane direction of the first surface, a distance between the pad and the insulating layer is greater than or equal to 25 μm.

6. The chip packaging structure according to claim 1, wherein: The coating layer has a thickness greater than or equal to 0.1 μm and less than or equal to 0.5 μm.

7. The chip packaging structure according to claim 1, wherein: Within the projection area of ​​the packaged chip on the substrate, the ratio of the area of ​​the circuit layer in the second zone to the total area of ​​the circuit layer with and without the coating is greater than or equal to 0.6 and less than or equal to 0.

8.

8. The chip packaging structure according to any one of claims 1 to 7, characterized in that: Along the thickness direction of the substrate, a functional device is provided on the second surface of the packaged chip facing the side of the substrate, a plurality of pads are provided in the first area, and along the plane direction of the first surface, the pads are spaced apart from each other; The insulating layer includes a first insulating portion and a second insulating portion spaced apart from each other, and the first insulating portion is arranged around the second insulating portion. Along the thickness direction of the substrate, the projection of the second insulating portion on the second surface covers the functional device, and in the area corresponding to the second insulating portion, the coating is not provided on at least part of the circuit layer.

9. The chip packaging structure according to claim 8, wherein: A plurality of the pads surround the outer edge of the functional device; or, The first region includes a first sub-region and a second sub-region spaced apart from each other, the first sub-region is arranged between the first insulating portion and the second insulating portion, the second sub-region is located within the second insulating portion, and the second sub-region corresponds to the functional device; The coating is provided on the corresponding pads and / or the circuit layer in the first sub-area and the second sub-area, and the coating is not provided on the circuit layer in the area corresponding to the second insulating portion.

10. The chip packaging structure according to claim 9, wherein: The second sub-area is set to be multiple, the multiple second sub-areas are spaced apart, and each second sub-area is also provided with the pad, the pad in the second sub-area is electrically connected to the pad in the functional device, and each second sub-area is provided with the coating.

11. The chip packaging structure according to claim 8, wherein: Along the plane direction of the first surface, the distance between the first insulating part and the second insulating part is greater than or equal to 30 μm and less than or equal to 300 μm, and the width of the coating corresponding to the first insulating part and the second insulating part is greater than or equal to 30 μm and less than or equal to 300 μm.

12. The chip packaging structure according to claim 8, wherein: Along the plane direction of the first surface, the distance between the first insulating part and the second insulating part is greater than or equal to 60 μm and less than or equal to 200 μm, and the width of the coating between the first insulating part and the second insulating part is greater than or equal to 50 μm and less than or equal to 200 μm.

13. The chip packaging structure according to claim 8, wherein: Along the thickness direction of the substrate, the first insulating portion is spaced apart from the second surface; The packaged chip is also bonded and fixed to the first insulating portion by glue, and the glue surrounds the edge of the packaged chip.

14. The chip packaging structure according to claim 13, wherein: Along the thickness direction of the substrate, the glue spot is located on the surface of the first insulating part away from the substrate; or, Along the thickness direction of the substrate, a portion of the glue dots is located on the surface of the first insulating portion away from the substrate, and another portion of the glue dots is located on the coating between the first insulating portion and the second insulating portion.

15. The chip packaging structure according to claim 13, wherein: Along a thickness direction of the substrate, a distance between the first insulating portion and the second surface is greater than or equal to 1 μm and less than or equal to 30 μm.

16. The chip packaging structure according to claim 8, wherein: Along the thickness direction of the substrate, the thickness of the first insulating portion is greater than or equal to the thickness of the second insulating portion.

17. The chip packaging structure according to claim 16, wherein: The thickness of the first insulating portion is greater than or equal to 15 μm and less than or equal to 35 μm; and / or the thickness of the second insulating portion is greater than or equal to 10 μm and less than or equal to 20 μm.

18. The chip packaging structure according to any one of claims 1 to 7, characterized in that: The coating layer includes at least one of triazoline, imidazole organic crystalline base, nickel gold and nickel palladium gold.

19. The chip packaging structure according to any one of claims 1 to 7, characterized in that: The chip packaging structure further includes a plastic packaging layer. Along the thickness direction of the substrate, the plastic packaging layer is located on a side of the substrate where the packaged chip is mounted, and the plastic packaging layer covers the packaged chip.

20. A chip packaging structure, characterized in that: The device comprises a substrate, an insulating layer, a packaged chip and glue, wherein the insulating layer is provided on a first surface of the substrate along the thickness direction of the substrate, the first surface is provided with a solder pad, and the solder pad is conductively connected to the packaged chip; The insulating layer is provided with a groove, and along the thickness direction of the substrate, the projection of the packaged chip on the substrate covers the groove, and along the plane direction of the first surface, the glue surrounds the outside of the groove and adheres between the insulating layer and the packaged chip; The first surface is further provided with a circuit layer, the circuit layer extending along the plane direction of the first surface, the surface of the circuit layer located in the groove is provided with a coating, and at least a portion of the circuit layer located outside the groove is directly bonded to the insulating layer; Along the thickness direction of the substrate, a distance between the notch of the groove and the packaged chip is greater than or equal to 1 μm and less than or equal to 30 μm.

21. The chip packaging structure according to claim 20, wherein: A functional device is provided on the second surface of the packaged chip facing the substrate along the thickness direction of the substrate, the functional device is spaced apart from the insulating layer, and the groove is provided around the functional device along the plane direction of the first surface; Wherein, the coating is provided on the pad and the circuit layer in at least a portion of the groove area.

22. The chip packaging structure according to claim 21, wherein: There are multiple grooves, and the multiple grooves surround the outer edge of the functional device, and the grooves are spaced apart from each other; or The groove is annular in shape and surrounds the outer edge of the functional device.

23. The chip packaging structure according to claim 22, wherein: The groove is annular in shape. Along the plane of the first surface, the groove divides the insulating layer into a first insulating portion and a second insulating portion that are spaced apart from each other. The first insulating portion is used to form an outer groove wall of the groove, and the second insulating portion is used to form an inner groove wall of the groove. Along the thickness direction of the substrate, the thickness of the first insulating portion is greater than or equal to the thickness of the second insulating portion. Wherein, in the region corresponding to the first insulating portion, at least a portion of the circuit layer is provided with the coating, and in the region corresponding to the second insulating portion, at least a portion of the circuit layer is not provided with the coating.

24. The chip packaging structure according to any one of claims 20 to 23, characterized in that: There are multiple pads, at least some of which are exposed through the groove. Along the plane direction of the first surface, the distance between the pads received in the groove and the groove walls on both sides of the groove is greater than or equal to 25 μm.

25. A chip packaging structure, characterized in that: The device comprises a substrate, a package chip and an insulating layer located on the same side of the substrate, wherein along the thickness direction of the substrate, a first surface of the substrate facing the package chip is electrically connected to the package chip, and a circuit layer is provided on the first surface; Along the thickness direction of the substrate, within the projection area of ​​the packaged chip on the substrate, the insulating layer is arranged on the first surface, and the insulating layer includes a first area and a second area. The circuit layer corresponding to the first area is exposed, and the surface of the circuit layer in the first area is also provided with a coating. The surface of the circuit layer in the second area is covered by the insulating layer, and the ratio of the area of ​​the circuit layer in the first area to the area of ​​the circuit layer in the second area is between 1.5 and 4.

26. The chip packaging structure according to claim 25, characterized in that: The insulating layer further includes a groove, the groove separating the insulating layer and forming a first insulating portion and a second insulating portion, wherein the first insulating portion is arranged around the second insulating portion; A functional device is provided on the second surface of the packaged chip facing the substrate along the thickness direction of the substrate, and a projection of the second insulating portion on the second surface covers the functional device; Furthermore, in an area corresponding to the second insulating portion, the coating is not provided on at least a portion of the circuit layer.

27. The chip packaging structure according to claim 26, wherein: Along the plane direction of the first surface, the distance between the first insulating part and the second insulating part is greater than or equal to 30 μm and less than or equal to 300 μm, and the width of the coating between the first insulating part and the second insulating part is greater than or equal to 30 μm and less than or equal to 300 μm.

28. The chip packaging structure according to claim 26, wherein: The first surface is further provided with a pad, and the pad is electrically connected to the packaged chip; The groove includes a first and a second connected section, the pad is arranged in the first section, and along the plane direction of the first surface, the distance between the first insulating portion and the second insulating portion in the first section is greater than or equal to the distance between the first insulating portion and the second insulating portion in the second section, and the coating is provided on the corresponding circuit layers in the first section and the second section.

29. The chip packaging structure according to claim 28, wherein: The second insulating part also includes a second groove, which is arranged near the central area of ​​the functional device. There are multiple pads, some of which are arranged in the first section, and another part of the pads are arranged in the second groove. The coating is provided on the circuit layer in the second groove.

30. An electronic device, characterized in that: Comprising the chip packaging structure according to any one of claims 1-29.

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