MOS (Metal Oxide Semiconductor) tube chip and packaging method of MOS tube chip

Abstract

The embodiment of the invention provides an MOS tube chip and a packaging method of the MOS tube chip, the MOS tube chip comprises at least two sub-chips, a plurality of inter-chip interconnecting pieces, a plurality of pins and a packaging layer, the at least two sub-chips are vertically stacked, each sub-chip comprises at least one MOS tube, the same poles of the MOS tubes in the at least two sub-chips are electrically connected through the inter-chip interconnecting pieces, and the pins are electrically connected with the packaging layer through the inter-chip interconnecting pieces. Different poles of the MOS tube are electrically connected with different inter-chip interconnectors, the packaging layer wraps the at least two sub-chips and the plurality of inter-chip interconnectors, first ends of the pins are electrically connected with the inter-chip interconnectors, second ends of the pins are exposed out of the packaging layer, and each inter-chip interconnector is electrically connected with at least one pin. According to the MOS tube chip provided by the embodiment of the invention, the vertical stacking interconnection between the chips without being limited by the chip area and the routing packaging rule can be realized.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor packaging technology, and in particular to a MOS transistor chip and a packaging method for a MOS transistor chip. Background Art

[0002] MOS transistor chips, due to their excellent switching characteristics, low on-resistance, and high integration, can provide overcurrent, overvoltage, and undervoltage protection for batteries, ensuring safe and efficient operation. In battery protection applications, multiple MOS transistor chips are often connected in parallel to meet the needs of different power levels.

[0003] At present, the vertical stacking interconnection of MOS tube chips is achieved by stacking small-area chips on a large-area chip and interconnecting them through wire bonding, or by overlapping the pads of some areas of the upper and lower chips face to face and using the pads of the non-overlapping parts to lead out the interconnection.

[0004] However, when the lower chip is larger than the upper chip and the two chips are interconnected, or when there is non-overlapping surface interconnection between the two chips, the vertical stacking of the chips is limited by the chip area and wire bonding rules, and the space utilization of the chip package is low. Summary of the Invention

[0005] In view of this, embodiments of the present application provide a MOS transistor chip and a packaging method for the MOS transistor chip to at least partially solve the above-mentioned problems.

[0006] According to a first aspect of an embodiment of the present application, a MOS tube chip is provided, comprising: at least two sub-chips, a plurality of inter-chip interconnects, a plurality of pins and a packaging layer; the at least two sub-chips are vertically stacked, and each sub-chip comprises at least one MOS tube; the same poles of the MOS tubes in the at least two sub-chips are electrically connected via the inter-chip interconnects, and different poles of the MOS tubes are electrically connected to different inter-chip interconnects; the packaging layer covers the at least two sub-chips and the plurality of inter-chip interconnects; a first end of the pin is electrically connected to the inter-chip interconnect, a second end of the pin is exposed outside the packaging layer, and each inter-chip interconnect is electrically connected to at least one pin.

[0007] In one possible implementation, the sub-chip includes: a bare chip, a back metal layer and a connection layer; the back side of the bare chip is bonded to the back metal layer, and the front side of the bare chip is bonded to the lower surface of the connection layer; the connection layer is provided with a plurality of electrical connection columns, the first end of the electrical connection column is electrically connected to one pole of the MOS tube in the bare chip, and the second end of the electrical connection column is electrically connected to the inter-chip interconnect or the pin.

[0008] In one possible implementation, the sub-chip also includes a first redistribution layer; the first redistribution layer is adhered to the upper surface of the connection layer; the first redistribution layer is provided with a plurality of first metal traces, the lower surface of the first metal trace is electrically connected to the second end of the electrical connection column, the first metal trace is electrically connected to the inter-chip interconnection, and the electrical connection columns connected to different poles of the MOS tube in the bare chip are electrically connected to different first metal traces.

[0009] In a possible implementation, the at least two sub-chips include a first sub-chip and a second sub-chip; the back metal layer included in the first sub-chip and the back metal layer included in the second sub-chip are bonded via an adhesive layer.

[0010] In a possible implementation, when the first sub-chip is located at the bottom of the at least two sub-chips that are vertically stacked, the pin is electrically connected to an upper surface of the first metal trace in the first sub-chip.

[0011] In one possible implementation, the at least two sub-chips include a third sub-chip and a fourth sub-chip; the third sub-chip and the fourth sub-chip are adjacently arranged, and the bare die included in the third sub-chip is opposite to the back metal layer included in the fourth sub-chip.

[0012] In a possible implementation, when the third sub-chip is located at the bottom of the at least two sub-chips that are vertically stacked, the pin is electrically connected to the upper surface of the first metal trace in the fourth sub-chip.

[0013] In one possible implementation, the at least two sub-chips include a fifth sub-chip and a sixth sub-chip; the fifth sub-chip and the sixth sub-chip are arranged adjacent to each other, the first redistribution layer included in the fifth sub-chip is adhered to the first redistribution layer included in the sixth sub-chip, and the fifth sub-chip and the sixth sub-chip are electrically connected through the first metal routing included in the fifth sub-chip and the first metal routing included in the sixth sub-chip.

[0014] In one possible implementation, the MOS tube chip also includes a second redistribution layer; when the fifth sub-chip is located at the bottom of the at least two sub-chips stacked vertically, the second redistribution layer is arranged on the top of the sixth sub-chip, and the packaging layer covers the second redistribution layer; the second redistribution layer includes a plurality of second metal traces, the second metal traces are electrically connected to the inter-chip interconnects, the first ends of the pins are electrically connected to the second metal traces, and the inter-chip interconnects connected to different poles of the MOS tubes in the bare chip are electrically connected to different second metal traces.

[0015] According to a second aspect of an embodiment of the present application, a method for packaging a MOS tube chip is provided, the method comprising: vertically stacking at least two sub-chips, and electrically connecting the MOS tubes included in the at least two sub-chips through a plurality of inter-chip interconnects, wherein each of the sub-chips includes at least one MOS tube, and different poles of the MOS tube are electrically connected to different inter-chip interconnects; electrically connecting the inter-chip interconnects to first ends of pins, and each inter-chip interconnect is electrically connected to at least one pin; and encapsulating the at least two sub-chips and the plurality of inter-chip interconnects with a packaging layer, and exposing the second ends of the pins outside the packaging layer, to obtain a MOS tube chip.

[0016] In one possible implementation, the electrically connecting the MOS tubes included in the at least two sub-chips through multiple inter-chip interconnects includes: setting a plurality of electrical connection columns on the front side of the bare chip of the sub-chip, and the first end of the electrical connection column is electrically connected to one pole of at least one MOS tube included in the bare chip, wherein the sub-chip includes the bare chip and a back metal layer; and electrically connecting the second end of the electrical connection column to the multiple inter-chip interconnects or the pins through multiple first metal traces.

[0017] In one possible implementation, the encapsulation layer encapsulates the at least two sub-chips and the plurality of inter-chip interconnects, comprising: placing a first sub-chip on a temporary carrier, encapsulating the first sub-chip with a first encapsulation layer, opening a first through hole in the first encapsulation layer on a side of the first sub-chip, and providing a first inter-chip interconnect in the first through hole to be electrically connected to the first sub-chip, and encapsulating the first sub-chip and the first inter-chip interconnect with a second encapsulation layer; peeling off the temporary carrier and flipping the first sub-chip, providing an adhesive layer on the back metal layer included in the first sub-chip, and vertically stacking the second sub-chip on top of the first sub-chip, An adhesive layer bonds the back metal layer included in the second sub-chip to the back metal layer included in the first sub-chip, wherein the back metal layer included in the first sub-chip is opposite to the back metal layer included in the second sub-chip; a third packaging layer is used to cover the second sub-chip, a second through hole is opened in the third packaging layer on the side of the second sub-chip, and a second inter-chip interconnection is set in the second through hole to be electrically connected to the second sub-chip; a fourth packaging layer is used to cover the second sub-chip and the second inter-chip interconnection, wherein the first through hole and the second through hole are connected in a vertical direction, and the first inter-chip interconnection and the second inter-chip interconnection are electrically connected.

[0018] In one possible implementation, the inter-chip interconnect is electrically connected to the first end of the pin, and each inter-chip interconnect is electrically connected to at least one pin, including: when the first sub-chip is located at the bottom of the at least two sub-chips stacked vertically, the pin is set on the upper surface of the first metal trace of the first sub-chip, and the first inter-chip interconnect is electrically connected to the first end of the pin through the first metal trace.

[0019] In one possible implementation, the encapsulating layer encapsulating the at least two sub-chips and the multiple inter-chip interconnects includes: placing a third sub-chip on a fifth encapsulating layer, encapsulating the third sub-chip with a sixth encapsulating layer, opening a third through-hole in the sixth encapsulating layer on the side of the third sub-chip, and arranging a third inter-chip interconnect in the third through-hole to electrically connect with the third sub-chip; vertically stacking a fourth sub-chip on the upper surface of the sixth encapsulating layer, wherein the bare chip included in the third sub-chip is opposite to the back metal layer included in the fourth sub-chip; encapsulating the fourth sub-chip with a seventh encapsulating layer, opening a fourth through-hole in the seventh encapsulating layer on the side of the fourth sub-chip, and arranging a fourth inter-chip interconnect in the fourth through-hole to electrically connect with the fourth sub-chip; and encapsulating the fourth sub-chip and the fourth inter-chip interconnect with an eighth encapsulating layer, wherein the third through-hole and the fourth through-hole are vertically connected, and the third inter-chip interconnect and the fourth inter-chip interconnect are electrically connected.

[0020] In one possible implementation, the inter-chip interconnect is electrically connected to the first end of the pin, and each inter-chip interconnect is electrically connected to at least one pin, including: when the fourth sub-chip is located on top of the at least two sub-chips stacked vertically, the pin is set on the upper surface of the first metal trace of the fourth sub-chip, and the fourth inter-chip interconnect is electrically connected to the first end of the pin through the first metal trace.

[0021] In one possible implementation, the encapsulation layer encapsulating the at least two sub-chips and the plurality of inter-chip interconnects includes: vertically stacking the fifth sub-chip and the sixth sub-chip and then encapsulating them with a ninth encapsulation layer, wherein the bare die included in the fifth sub-chip is opposite to the bare die included in the sixth sub-chip; and opening a fifth through hole in the ninth encapsulation layer on the side of the fifth sub-chip and the sixth sub-chip, and arranging a fifth inter-chip interconnect in the fifth through hole to electrically connect the fifth sub-chip and the sixth sub-chip.

[0022] In one possible implementation, the inter-chip interconnect is electrically connected to the first end of the pin, and each inter-chip interconnect is electrically connected to at least one pin, including: when the sixth sub-chip is located on top of the at least two sub-chips stacked vertically, a plurality of second metal traces are set on the upper surface of the ninth packaging layer to be electrically connected to the fifth inter-chip interconnect, the tenth packaging layer is used to cover the plurality of second metal traces, the pins are set on the upper surface of the plurality of second metal traces, and the fifth inter-chip interconnect is electrically connected to the first end of the pin through the second metal traces.

[0023] According to the MOS tube chip provided in the embodiment of the present application, the MOS tube chip includes at least two sub-chips, multiple inter-chip interconnects, multiple pins and a packaging layer. At least two sub-chips are stacked vertically, each sub-chip includes at least one MOS tube, the same poles of the MOS tubes in at least two sub-chips are electrically connected through the inter-chip interconnects, and different poles of the MOS tubes are electrically connected to different inter-chip interconnects. The packaging layer covers the at least two sub-chips and the multiple inter-chip interconnects. The first end of the pin is electrically connected to the inter-chip interconnect, and the second end of the pin is exposed outside the packaging layer. Each inter-chip interconnect is electrically connected to at least one pin, which can realize vertical stacking and interconnection of at least two sub-chips to form a high-density integrated MOS tube chip. In addition, the electrical connection between the vertically stacked sub-chips is realized through an advanced packaging copper interconnect process, which can reduce the parasitic impedance of the routing and improve the performance and function of the chip. Compared with the prior art, the vertically stacked MOS tube chip structure provided by the present solution is not limited by the chip area and wire bonding packaging rules, can improve the space utilization of the chip packaging, and reduce the packaging cost of the MOS tube chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0025] Figure 1 This is a schematic diagram of a MOS transistor chip provided in an embodiment of the present application;

[0026] Figure 2 is a schematic diagram of a sub-chip provided in an embodiment of the present application;

[0027] Figure 3 is a schematic diagram of another sub-chip provided in an embodiment of the present application;

[0028] Figure 4 This is a schematic diagram of another MOS transistor chip provided in an embodiment of the present application;

[0029] Figure 5 This is a schematic diagram of another MOS transistor chip provided in an embodiment of the present application;

[0030] Figure 6 Schematic diagram of another MOS transistor chip provided in an embodiment of the present application;

[0031] Figure 7 Schematic diagram of another MOS transistor chip provided in an embodiment of the present application;

[0032] Figure 8 This is a flow chart of a packaging method for a MOS transistor chip provided in an embodiment of the present application;

[0033] Figure 9 This is a schematic diagram of a packaging method for a MOS transistor chip provided in an embodiment of the present application;

[0034] Figure 10 This is a schematic diagram of another MOS transistor chip packaging method provided in an embodiment of the present application;

[0035] Figure 11 This is a schematic diagram of another MOS tube chip packaging method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0036] In order to enable those skilled in the art to better understand the technical solutions in the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the embodiments of the present application, all other embodiments obtained by ordinary technicians in this field should fall within the scope of protection of the embodiments of the present application.

[0037] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. As used in this application and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0038] It should be understood that although the terms first, second, third, etc. may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0039] As mentioned above, MOS tube chips can provide overcurrent, overvoltage and undervoltage protection for batteries due to their excellent switching characteristics, low on-resistance and high integration, ensuring the safe and efficient operation of the battery. In battery protection applications, multiple MOS tube chips are usually connected in parallel to meet the needs of different power levels. At present, the vertical stacking interconnection of MOS tube chips is achieved by stacking small-area chips on a large-area chip through wire bonding, or by overlapping the pads of some areas of the upper and lower chips face to face, and interconnecting them using the pads of the non-overlapping parts. However, when the lower chip is larger than the upper chip for stacking interconnection or the two chips have non-overlapping surface interconnection at the same time, the vertical stacking of chips is limited by the chip area and wire bonding rules, and the space utilization rate of the chip package is low.

[0040] An embodiment of the present application provides a MOS transistor chip, which includes at least two sub-chips, multiple inter-chip interconnects, multiple pins, and a packaging layer. The at least two sub-chips are vertically stacked, each sub-chip includes at least one MOS transistor, the same poles of the MOS transistors in the at least two sub-chips are electrically connected through the inter-chip interconnects, and the different poles of the MOS transistors are electrically connected to different inter-chip interconnects. The packaging layer covers the at least two sub-chips and the multiple inter-chip interconnects. The first ends of the pins are electrically connected to the inter-chip interconnects, and the second ends of the pins are exposed outside the packaging layer. Each inter-chip interconnect is electrically connected to at least one pin, which can achieve vertical stacking and interconnection of the at least two sub-chips to form a high-density integrated MOS transistor chip. In addition, the electrical connection between the vertically stacked sub-chips is achieved through an advanced packaging copper interconnect process, which can reduce routing parasitic impedance and improve chip performance and functionality. Compared with the prior art, the vertically stacked MOS transistor chip structure provided by this solution is not limited by chip area and wire bonding packaging rules, can improve chip packaging space utilization, and reduce MOS transistor chip packaging costs.

[0041] The MOS transistor chip provided by this application is described below through examples.

[0042] Figure 1 This is a schematic diagram of a MOS tube chip provided in an embodiment of the present application. Figure 1As shown, the MOS transistor chip 100 includes at least two sub-chips 101 , a plurality of inter-chip interconnects 102 , a plurality of pins 103 and a packaging layer 104 . Figure 1 As an example, a MOS transistor chip 100 including two sub-chips 101 is shown. In other embodiments, the MOS transistor chip 100 may include a larger number of sub-chips 101. The sub-chips 101 included in the MOS transistor chip 100 are stacked vertically. Each sub-chip 101 includes at least one MOS transistor. The same poles of the MOS transistors in at least two sub-chips 101 are electrically connected through an inter-chip interconnect 102, and different poles of the MOS transistors are electrically connected to different inter-chip interconnects 102. The packaging layer 104 covers the at least two sub-chips 101 and the multiple inter-chip interconnects 102. The first end of the pin 103 is electrically connected to the inter-chip interconnect 102, and the second end of the pin 103 is exposed outside the packaging layer 104. Each inter-chip interconnect 102 is electrically connected to at least one pin 103.

[0043] At least two sub-chips 101 are stacked vertically to form the MOS transistor chip 100. Specifically, two or more sub-chips 101 can be stacked vertically to form the MOS transistor chip 100 according to the actual use scenario requirements. Each sub-chip 101 includes at least one MOS transistor structure. It is understood that in order to ensure the functional integrity of the sub-chip 101, the sub-chip 101 may also include but is not limited to a protection circuit and / or a heat dissipation structure, etc., which are not limited here.

[0044] Multiple inter-chip interconnects 102 are formed through a copper interconnect process and are used to electrically connect the vertically stacked sub-chips 101. The multiple inter-chip interconnects 102 are arranged on the sides of at least two sub-chips 101, and the projections of the inter-chip interconnects 102 and the at least two sub-chips 101 on a plane perpendicular to the stacking direction of the at least two sub-chips 101 do not intersect. The same poles of the MOS transistors in at least two sub-chips 101 are electrically connected through the inter-chip interconnects 102, and different poles of the MOS transistors are electrically connected to different inter-chip interconnects 102. In one example, the source of the MOS transistors in the two sub-chips 101 is electrically connected to the first inter-chip interconnect, the drain of the MOS transistors in the two sub-chips 101 is electrically connected to the second inter-chip interconnect, and the gate of the MOS transistors in the two sub-chips 101 is electrically connected to the third inter-chip interconnect. The first inter-chip interconnect, the second inter-chip interconnect, and the third inter-chip interconnect are different inter-chip interconnect structures.

[0045] The encapsulation layer 104 encapsulates at least two sub-chips 101 and multiple inter-chip interconnects 102 to form a package structure. The encapsulation layer 104 surrounds each sub-chip 101 except for necessary electrical connection components to protect each sub-chip 101 from physical damage. In one example, the encapsulation layer 104 is made of plastic. The first ends of the pins 103 are electrically connected to the inter-chip interconnects 102, and each inter-chip interconnect 102 is electrically connected to at least one pin 103. The second ends of the pins 103 are exposed outside the encapsulation layer 104, and the remaining areas of the pins 103 are also encapsulated by the encapsulation layer 104.

[0046] In an embodiment of the present application, the MOS transistor chip 100 includes at least two sub-chips 101, a plurality of inter-chip interconnects 102, a plurality of pins 103 and a packaging layer 104. At least two sub-chips 101 are stacked vertically, and each sub-chip 101 includes at least one MOS transistor. The same poles of the MOS transistors in at least two sub-chips 101 are electrically connected through the inter-chip interconnects 102, and different poles of the MOS transistors are electrically connected to different inter-chip interconnects 102. The packaging layer 104 covers at least two sub-chips 101 and the plurality of inter-chip interconnects 102. The first end of the pin 103 is electrically connected to the inter-chip interconnect 102, and the first end of the pin 103 is electrically connected to the inter-chip interconnect 102. The two ends are exposed outside the packaging layer 104, and each inter-chip interconnect 102 is electrically connected to at least one pin 103, which can realize vertical stacking and interconnection of at least two sub-chips 101 to form a high-density integrated MOS tube chip 100. In addition, the electrical connection between the vertically stacked sub-chips 101 is realized through an advanced packaging copper interconnect process, which can reduce the parasitic impedance of the routing and improve the performance and function of the chip. Compared with the existing technology, the structure of the vertically stacked MOS tube chip 100 provided by this solution is not limited by the chip area and wire bonding packaging rules, which can improve the space utilization of the chip packaging and reduce the packaging cost of the MOS tube chip.

[0047] Figure 2 is a schematic diagram of a sub-chip provided in an embodiment of the present application, such as Figure 2 As shown, the sub-chip 101 includes a bare chip 1011, a back metal layer 1012 and a connection layer 1013. The back of the bare chip 1011 is bonded to the back metal layer 1012, and the front of the bare chip 1011 is bonded to the lower surface of the connection layer 1013. The connection layer 1013 is provided with multiple electrical connection columns, and the first end of the electrical connection column is electrically connected to one pole of the MOS tube in the bare chip 1011, and the second end of the electrical connection column is electrically connected to the inter-chip interconnect 103 or the pin 103.

[0048] Bare die 1011 is the core component of the chip's functionality. The front of die 1011 integrates at least one MOS transistor structure and other electronic components. A back metal layer 1012 is used for electrical connection and heat dissipation. The back of die 1011 is bonded to back metal layer 1012. Back metal layer 1012 can be a single metal such as silver, copper, or titanium, or a multilayer structure composed of multiple metals, without limitation. In one example, die 1011 is a silicon wafer.

[0049] The front surface of die 1011 is bonded to the bottom surface of connection layer 1013. Connection layer 1013 is provided with multiple electrical connection posts for leading out the electrodes of the MOS transistors in die 1011. The first end of the electrical connection post is electrically connected to one electrode of the MOS transistor in die 1011. The second end of the electrical connection post is electrically connected to the inter-chip interconnect 102 to establish an electrical connection between the vertically stacked sub-chips 101, or is electrically connected to the pin 103 to establish an electrical connection with an external circuit interface. In one example, the electrical connection post is a copper post.

[0050] In an embodiment of the present application, the sub-chip 101 includes a bare chip 1011, a back metal layer 1012 and a connection layer 1013. The back of the bare chip 1011 is bonded to the back metal layer 1012, and the front of the bare chip 1011 is bonded to the lower surface of the connection layer 1013. The connection layer 1013 is provided with multiple electrical connection columns. The first end of the electrical connection column is electrically connected to one pole of the MOS tube in the bare chip 1011, and the second end of the electrical connection column is electrically connected to the inter-chip interconnection 102 or the pin 103. An electrical connection can be established between the vertically stacked sub-chips 101 and between the MOS tube chip 100 and the external circuit, thereby realizing high-density interconnection between the sub-chips 101, reducing the equivalent impedance per unit area of ​​the chip, and improving the performance of the MOS tube chip.

[0051] Figure 3 is a schematic diagram of another sub-chip provided in an embodiment of the present application, such as Figure 3 As shown, the sub-chip 101 also includes a first redistribution layer 1014, which is adhered to the upper surface of the connection layer 1013. The first redistribution layer 1014 is provided with a plurality of first metal traces. The lower surface of the first metal trace is electrically connected to the second end of the electrical connection column. The first metal trace is electrically connected to the inter-chip interconnection 102, and the electrical connection columns connected to different poles of the MOS tube in the bare chip 1011 are electrically connected to different first metal traces.

[0052] The first redistribution layer 1014 is bonded to the upper surface of the connection layer 1013, and the first redistribution layer 1014 is provided with a plurality of first metal traces. In one example, the first metal trace is a copper wire. The lower surface of the first metal trace is electrically connected to the second end of the electrical connection column of the connection layer 1013, and the first metal trace is electrically connected to the inter-chip interconnect 102. The electrical connection columns connected to different poles of the MOS tube in the bare chip 1011 are electrically connected to different first metal traces, and are electrically connected to different inter-chip interconnects 102 through different first metal traces. It can be understood that the multiple electrical connection columns in the connection layer 1013 provide point-to-point electrical connections in the vertical direction, and the first redistribution layer 1014 can rearrange the contact points on the top of the multiple electrical connection columns through the horizontal first metal traces and connect them to the pre-planned inter-chip interconnect 102. In one example, the electrical connection column of the source of the sub-chip 101 is electrically connected to the first metal trace and connected to the first inter-chip interconnect 102, and the electrical connection column of the drain of the sub-chip 101 is electrically connected to the second metal trace and connected to the second inter-chip interconnect 102, wherein the first metal trace and the second metal trace are different metal traces.

[0053] In an embodiment of the present application, the sub-chip 101 also includes a first redistribution layer 1014, which is adhered to the upper surface of the connection layer 1013. The first redistribution layer 1014 is provided with multiple first metal traces, and the lower surface of the first metal trace is electrically connected to the second end of the electrical connection column. The first metal trace is electrically connected to the inter-chip interconnection 102, and the electrical connection columns connected to different poles of the MOS tube in the bare chip 1011 are electrically connected to different first metal traces. By integrating the first redistribution layer 1014 on the upper surface of the connection layer 1013, the signal paths of the second ends of the multiple electrical connection columns in the connection layer 1013 are flexibly extended and connected, so that the interconnection between the sub-chips 101 is not restricted by the original fixed layout of the front electrodes of the bare chip 1011, and the electrodes of the MOS tubes in the sub-chip 101 are connected to the corresponding inter-chip interconnections 102 as needed, thereby realizing high-precision interconnection between vertically stacked sub-chips 101.

[0054] Figure 4 is a schematic diagram of another MOS tube chip provided in an embodiment of the present application. Figure 4 As an example, a MOS transistor chip 100 including two sub-chips 101 including a first sub-chip 201 and a second sub-chip 301 is shown. Figure 4 As shown, at least two sub-chips 101 include a first sub-chip 201 and a second sub-chip 301 , and the back metal layer 2012 included in the first sub-chip 201 and the back metal layer 3012 included in the second sub-chip 301 are bonded together via an adhesive layer.

[0055] The back metal layer 2012 of the first sub-chip 201 is opposite to the back metal layer 3012 of the second sub-chip 301, i.e., the first sub-chip 201 and the second sub-chip 301 are stacked back-to-back. The back metal layer 2012 of the first sub-chip 201 is bonded to the back metal layer 3012 of the second sub-chip 301 via an adhesive layer, wherein the adhesive layer can be a conductive material or a non-conductive material, which is not limited here.

[0056] In an embodiment of the present application, at least two sub-chips 101 include a first sub-chip 201 and a second sub-chip 301. The back metal layer 2012 included in the first sub-chip 201 and the back metal layer 3012 included in the second sub-chip 301 are bonded together through an adhesive layer, so that the first sub-chip 201 and the second sub-chip 301 can be mechanically connected, and the relative positions of the first sub-chip 201 and the second sub-chip 301 can be fixed, so as to facilitate the accurate establishment of the electrical connection between the first sub-chip 201 and the second sub-chip 301. At the same time, a vertical stacking form is provided for the vertical stacking of the sub-chips 101, in which the back metal layer 1012 of one sub-chip 101 is relative to the back metal layer 1012 of another sub-chip 101, which provides a basis for vertically stacking multiple sub-chips 101 to form a MOS tube chip 100 structure.

[0057] In one possible implementation, Figure 4 As shown, when the first sub-chip 201 is located at the bottom of at least two sub-chips 101 vertically stacked, the pin 103 is electrically connected to the upper surface of the first metal trace in the first sub-chip 201 .

[0058] In one example, the first sub-chip 201 is located at the bottom of two vertically stacked sub-chips 101 (the first sub-chip 201 and the second sub-chip 301), and the pin 103 is electrically connected to the upper surface of the first metal trace in the first sub-chip 201 through pin electroplating. Optionally, it can also be electrically connected to the pin 103 through the upper surface of the first metal trace in the second sub-chip 301.

[0059] In an embodiment of the present application, when the first sub-chip 201 is located at the bottom of at least two vertically stacked sub-chips 101, the pin 103 is electrically connected to the upper surface of the first metal trace in the first sub-chip 201, which can establish a connection path between the internal and external circuits of the vertically stacked chip, so that the internal circuits of the vertically stacked chip can communicate and transmit data with the external circuits, thereby realizing the function of the MOS tube chip 100.

[0060] Figure 5 This is a schematic diagram of another MOS tube chip provided in an embodiment of the present application. Figure 5As an example, a MOS transistor chip 100 including two sub-chips 101 including a third sub-chip 401 and a fourth sub-chip 501 is shown. Figure 5 As shown, at least two sub-chips 101 include a third sub-chip 401 and a fourth sub-chip 501 . The third sub-chip 401 and the fourth sub-chip 501 are adjacently arranged, and the bare die 4011 included in the third sub-chip 401 is opposite to the back metal layer 5012 included in the fourth sub-chip 501 .

[0061] The third sub-chip 401 and the fourth sub-chip 501 are adjacently arranged, and the bare die 4011 included in the third sub-chip 401 is opposite to the back metal layer 5012 included in the fourth sub-chip 501 , that is, the third sub-chip 401 and the fourth sub-chip 501 are stacked face-to-back.

[0062] In an embodiment of the present application, at least two sub-chips 101 include a third sub-chip 401 and a fourth sub-chip 501. The third sub-chip 401 and the fourth sub-chip 501 are adjacent to each other, and the bare chip 4011 included in the third sub-chip 401 is opposite to the back metal layer 5012 included in the fourth sub-chip 501, which can achieve tight integration and efficient interconnection of the third sub-chip 401 and the fourth sub-chip 501. At the same time, a vertical stacking form is provided for vertical stacking between sub-chips 101, in which the back metal layer 1012 of one sub-chip 101 is opposite to the bare chip 1011 of another sub-chip 101, which provides a basis for vertical stacking of multiple sub-chips 101 to form a MOS tube chip 100 structure.

[0063] In one possible implementation, Figure 5 As shown, when the third sub-chip 401 is located at the bottom of at least two vertically stacked sub-chips 101 , the pin 103 is electrically connected to the upper surface of the first metal trace in the fourth sub-chip 501 .

[0064] In one example, the third sub-chip 401 is located at the bottom of two vertically stacked sub-chips 101 (the third sub-chip 401 and the fourth sub-chip 501). On the structure in which the bare die 4011 included in the third sub-chip 401 and the back metal layer 5012 included in the fourth sub-chip 501 are relatively vertically stacked and electrically connected, the pin 103 is electrically connected to the upper surface of the first metal trace in the fourth sub-chip 501 through pin electroplating.

[0065] In an embodiment of the present application, when the third sub-chip 401 is located at the bottom of at least two vertically stacked sub-chips 101, the pin 103 is electrically connected to the upper surface of the first metal trace in the fourth sub-chip 501, which can establish a connection path between the internal and external circuits of the vertically stacked chip, so that the internal circuits of the vertically stacked chip can communicate and transmit data with the external circuits, thereby realizing the function of the MOS tube chip 100.

[0066] Figure 6 Schematic diagram of another MOS tube chip provided in an embodiment of the present application. Figure 6 As an example, a MOS transistor chip 100 including two sub-chips 101 including a fifth sub-chip 601 and a sixth sub-chip 701 is shown. Figure 6 As shown, at least two sub-chips 101 include a fifth sub-chip 601 and a sixth sub-chip 701, the fifth sub-chip 601 and the sixth sub-chip 701 are arranged adjacent to each other, the first redistribution layer 6014 included in the fifth sub-chip 601 is adhered to the first redistribution layer 7014 included in the sixth sub-chip 701, and the fifth sub-chip 601 and the sixth sub-chip 701 are electrically connected through the first metal routing included in the fifth sub-chip 601 and the first metal routing included in the sixth sub-chip 701.

[0067] The fifth sub-chip 601 and the sixth sub-chip 701 are arranged adjacent to each other. The first redistribution layer 6014 included in the fifth sub-chip 601 is aligned with the first redistribution layer 7014 included in the sixth sub-chip 701. That is, the fifth sub-chip 601 and the sixth sub-chip 701 are stacked face-to-face. The fifth sub-chip 601 and the sixth sub-chip 701 are electrically connected via the first metal trace included in the fifth sub-chip 601 and the first metal trace included in the sixth sub-chip 701.

[0068] It should be noted that the first redistribution layer 1014 is composed of a metal layer (such as copper) formed by non-overlapping first metal traces and an insulating layer (such as polyimide or silicon dioxide). By pre-designing the first redistribution layer 1014, exposed metal areas are reserved for locations where interconnection is required, and non-connected areas are isolated by an insulating layer. When the fifth sub-chip 601 and the sixth sub-chip 701 are bonded, the first redistribution layer 6014 included in the fifth sub-chip 601 and the metal area reserved in the first redistribution layer included in the sixth sub-chip 701 are electrically connected to each other through the first metal trace included in the fifth sub-chip 601 and the first metal trace included in the sixth sub-chip 701. Since the metal contact points of the two sub-chips are electrically connected only in the reserved metal areas, the remaining areas remain insulated and isolated, and there will be no short circuit between the two sub-chips.

[0069] In an embodiment of the present application, at least two sub-chips 101 include a fifth sub-chip 601 and a sixth sub-chip 701, and the fifth sub-chip 601 and the sixth sub-chip 701 are adjacent to each other. The first redistribution layer 6014 included in the fifth sub-chip 601 is adhered to the first redistribution layer 7014 included in the sixth sub-chip 701, and the fifth sub-chip 601 and the sixth sub-chip 701 are electrically connected through the first metal trace included in the fifth sub-chip 601 and the first metal trace included in the sixth sub-chip 701, so as to achieve precise interconnection between the fifth sub-chip 601 and the sixth sub-chip 701. At the same time, a vertical stacking form of one sub-chip 101 bare die 1011 relative to another sub-chip 101 bare die 1011 is provided for vertical stacking between sub-chips 101, which provides a basis for vertical stacking of multiple sub-chips 101 to form a MOS tube chip 100 structure.

[0070] Figure 7 Schematic diagram of another MOS tube chip provided in an embodiment of the present application, such as Figure 7 As shown, the MOS tube chip 100 also includes a second redistribution layer 1015. When the fifth sub-chip 601 is located at the bottom of at least two sub-chips 101 stacked vertically, the second redistribution layer 1015 is arranged on the top of the sixth sub-chip 701, and the packaging layer 104 covers the second redistribution layer 1015. The second redistribution layer 1015 includes a plurality of second metal traces, and the second metal traces are electrically connected to the inter-chip interconnection 102. The first end of the pin 103 is electrically connected to the second metal trace, and the inter-chip interconnection 102 connected to different poles of the MOS tube in the bare chip is electrically connected to different second metal traces.

[0071] In one example, the fifth sub-chip 601 is located at the bottom of two vertically stacked sub-chips 101 (the fifth sub-chip 601 and the sixth sub-chip 701), and the second redistribution layer 1015 is disposed on top of the sixth sub-chip 701 and is covered by the packaging layer 104. The second redistribution layer 1015 includes a plurality of second metal traces, which are electrically connected to the inter-chip interconnects 102 and the first ends of the pins 103 to electrically connect the inter-chip interconnects 102 and the first ends of the pins 103, wherein the inter-chip interconnects 102 connected to different poles of the MOS tubes in the bare die are electrically connected to different second metal traces.

[0072] In an embodiment of the present application, the MOS tube chip 100 also includes a second redistribution layer 1015. When the fifth sub-chip 601 is located at the bottom of at least two vertically stacked sub-chips 101, the second redistribution layer 1015 is arranged on the top of the sixth sub-chip 701, and the packaging layer 104 covers the second redistribution layer 1015. The second redistribution layer 1015 includes multiple second metal traces, and the second metal traces are electrically connected to the inter-chip interconnection 102. The first end of the pin 103 is electrically connected to the second metal trace, and the inter-chip interconnection 102 connected to different poles of the MOS tube in the bare chip is electrically connected to different second metal traces. A connection path between the internal and external circuits of the vertically stacked chip can be established, so that the internal circuits of the vertically stacked chip can communicate and transmit data with the external circuit, thereby realizing the function of the MOS tube chip 100.

[0073] Figure 8 This is a flow chart of a packaging method for a MOS tube chip provided in an embodiment of the present application. Figure 8 As shown, the packaging method of the MOS transistor chip includes the following steps 801 to 803:

[0074] Step 801: vertically stack at least two sub-chips, and electrically connect the MOS transistors included in the at least two sub-chips through a plurality of inter-chip interconnects.

[0075] At least two sub-chips are stacked vertically, wherein adjacent sub-chips can be stacked face-to-face, back-to-back, or face-to-back. MOS transistors included in the at least two sub-chips are electrically connected via a plurality of inter-chip interconnects, wherein each sub-chip includes at least one MOS transistor, and the same poles of the MOS transistors are electrically connected via the inter-chip interconnects, while different poles of the MOS transistors are electrically connected to different inter-chip interconnects.

[0076] Step 802: electrically connect the inter-chip interconnects to the first ends of the pins, wherein each inter-chip interconnect is electrically connected to at least one pin.

[0077] Pins are provided on the vertical stacking structure of at least two sub-chips, and the inter-chip interconnection is electrically connected to the first end of the pin. Each inter-chip interconnection is electrically connected to at least one pin to establish an electrical connection between the external circuit and the inter-chip interconnection.

[0078] Step 803: Encapsulate at least two sub-chips and a plurality of inter-chip interconnects with a packaging layer, and expose the second ends of the pins outside the packaging layer to obtain a MOS transistor chip.

[0079] The encapsulation layer encapsulates at least two sub-chips and multiple inter-chip interconnects to protect them from physical damage. The encapsulation layer also covers most of the pins, leaving only the second ends of the pins exposed. This protects the pins while providing an electrical connection path between the external circuit and the MOS transistor chip.

[0080] In an embodiment of the present application, at least two sub-chips are stacked vertically, and the MOS tubes included in the at least two sub-chips are electrically connected through multiple inter-chip interconnects, the inter-chip interconnects are electrically connected to the first ends of the pins, and each inter-chip interconnect is electrically connected to at least one pin. The at least two sub-chips and the multiple inter-chip interconnects are covered with a packaging layer, and the second ends of the pins are exposed outside the packaging layer to obtain a MOS tube chip. The vertical stacking and interconnection of the at least two sub-chips can be achieved, and the high-density integration of the MOS tube chip can be achieved. Compared with the prior art, the packaging method of the vertically stacked MOS tube chip provided by the present solution is not limited by the chip area and wire bonding packaging rules, and can improve the space utilization of the chip packaging and reduce the packaging cost of the MOS tube chip.

[0081] In one possible implementation, when the MOS tubes included in at least two sub-chips are electrically connected through multiple inter-chip interconnects, multiple electrical connection columns can be set on the front side of the bare chip of the sub-chip, and the first end of the electrical connection column is electrically connected to one pole of at least one MOS tube included in the bare chip, wherein the sub-chip includes a bare chip and a back metal layer, and the second end of the electrical connection column is electrically connected to multiple inter-chip interconnects or pins through multiple first metal traces.

[0082] The sub-chip includes a bare die and a backside metal layer, with the backside of the bare die bonded to the backside metal layer. Multiple electrical connection posts are provided on the front side of the bare die of the sub-chip. In one example, copper is deposited or transferred onto pads on the chip substrate by mechanical or physical means to form the copper posts. In another example, a copper seed layer is first deposited on the surface of the chip substrate, and then the copper posts are formed on the seed layer by electroplating or chemical plating. The first end of the electrical connection post is electrically connected to one electrode of at least one MOS transistor included in the bare die, and the second end of the electrical connection post is electrically connected to multiple inter-chip interconnects or pins via multiple first metal traces.

[0083] In an embodiment of the present application, a plurality of electrical connection columns are provided on the front side of the bare chip of the sub-chip, and a first end of the electrical connection column is electrically connected to one pole of at least one MOS tube included in the bare chip, wherein the sub-chip includes a bare chip and a back metal layer, and a second end of the electrical connection column is electrically connected to a plurality of inter-chip interconnects or pins through a plurality of first metal traces, and an electrical connection between the sub-chip and the inter-chip interconnects or pins can be established through the electrical connection column, thereby realizing high-density interconnection between the sub-chips and improving the performance of the MOS tube chip.

[0084] In one possible implementation, when a MOS tube chip is obtained by encapsulating at least two sub-chips and a plurality of inter-chip interconnects with a packaging layer and exposing the second ends of the pins outside the packaging layer, the first sub-chip can be placed on a temporary carrier, the first sub-chip can be encapsulated with a first packaging layer, a first through-hole can be opened in the first packaging layer on the side of the first sub-chip, and a first inter-chip interconnect can be set in the first through-hole to be electrically connected to the first sub-chip, the first sub-chip and the first inter-chip interconnect can be encapsulated with a second packaging layer, the temporary carrier can be peeled off and the first sub-chip can be turned over, and after an adhesive layer is provided on the back metal layer included in the first sub-chip, the second sub-chip can be placed on the back metal layer of the first sub-chip. The chips are stacked vertically above the first sub-chip, and the back metal layer included in the second sub-chip is bonded to the back metal layer included in the first sub-chip through an adhesive layer, wherein the back metal layer included in the first sub-chip is opposite to the back metal layer included in the second sub-chip, and the second sub-chip is covered with a third packaging layer, a second through hole is opened in the third packaging layer on the side of the second sub-chip, and a second inter-chip interconnection is set in the second through hole to be electrically connected to the second sub-chip, and the second sub-chip and the second inter-chip interconnection are covered with a fourth packaging layer, wherein the first through hole and the second through hole are connected in the vertical direction, and the first inter-chip interconnection and the second inter-chip interconnection are electrically connected.

[0085] Figure 9 Schematic diagram of a packaging method for a MOS tube chip provided in an embodiment of the present application, such as Figure 9As shown, after copper pillars are formed on the chip substrate, the chip substrate is divided into independent chips through a dicing process and rearranged on a temporary carrier to form a first sub-chip. The first sub-chip is encapsulated with a first packaging layer and polished to expose the second end of the copper pillar on the first sub-chip. A first through-hole is opened in the first packaging layer on the side of the first sub-chip using a laser. The first through-hole is filled with interconnect metal through a copper electroplating process to form a first inter-chip interconnect. A first metal trace is formed through a copper interconnect process to electrically connect the second end of the copper pillar on the first sub-chip to the first inter-chip interconnect. After the first sub-chip and the first inter-chip interconnect are encapsulated with a second packaging layer, the temporary carrier is peeled off. The first sub-chip is flipped over, and after applying an adhesive layer to the back metal layer of the first sub-chip, the back metal layer of the second sub-chip is vertically stacked on top of the first sub-chip relative to the back metal layer of the first sub-chip. The back metal layer of the second sub-chip is bonded to the back metal layer of the first sub-chip via the adhesive layer. The second sub-chip is encapsulated with a third packaging layer. A second through-hole is formed in the third packaging layer on the side of the second sub-chip, perpendicular to the first through-hole. A second inter-chip interconnect is provided in the second through-hole to electrically connect it to the first inter-chip interconnect. The second sub-chip and the second inter-chip interconnect are electrically connected via the first metal trace on the second sub-chip. The second sub-chip and the second inter-chip interconnect are then covered with a fourth packaging layer. Information is marked on the packaged MOS transistor chip, and the MOS transistor chip is divided into multiple independent chips for electrical testing. The chips are then sorted according to the test results.

[0086] In an embodiment of the present application, a first sub-chip is placed on a temporary carrier, the first sub-chip is covered with a first packaging layer, a first through-hole is opened in the first packaging layer on the side of the first sub-chip, and a first inter-chip interconnection is set in the first through-hole to be electrically connected to the first sub-chip, the first sub-chip and the first inter-chip interconnection are covered with a second packaging layer, the temporary carrier is peeled off and the first sub-chip is flipped over, and after an adhesive layer is set on the back metal layer included in the first sub-chip, the second sub-chip is vertically stacked above the first sub-chip, and the back metal layer included in the second sub-chip is bonded to the back metal layer included in the first sub-chip through the adhesive layer, wherein the back metal layer included in the first sub-chip and the back metal layer included in the second sub-chip are bonded to the back metal layer included in the second sub-chip. The back metal layer is opposite, and a third packaging layer is used to cover the second sub-chip. A second through hole is opened in the third packaging layer on the side of the second sub-chip, and a second inter-chip interconnection is set in the second through hole to be electrically connected to the second sub-chip. The fourth packaging layer is used to cover the second sub-chip and the second inter-chip interconnection, wherein the first through hole and the second through hole are connected in the vertical direction, and the first inter-chip interconnection and the second inter-chip interconnection are electrically connected, which can realize back-to-back vertical stacking and interconnection between the two sub-chips, providing a basis for vertical stacking of multiple sub-chips to form a MOS tube chip, and using advanced packaging copper interconnection process for electrical connection between the stacked sub-chips, which can reduce the parasitic impedance of the routing and improve the performance of the MOS tube chip.

[0087] In one possible implementation, when the inter-chip interconnect is electrically connected to the first end of the pin and each inter-chip interconnect is electrically connected to at least one pin, when the first sub-chip is located at the bottom of at least two sub-chips stacked vertically, a pin is set on the upper surface of the first metal trace of the first sub-chip, and the first inter-chip interconnect is electrically connected to the first end of the pin through the first metal trace.

[0088] like Figure 9 As shown, the first sub-chip is located at the bottom of two vertically stacked sub-chips (the first sub-chip and the second sub-chip). Before the first sub-chip is flipped over, pin metal is set on the upper surface of the first metal trace of the first sub-chip by pin electroplating, and the first inter-chip interconnection is electrically connected to the first end of the pin through the first metal trace.

[0089] In an embodiment of the present application, when the first sub-chip is located at the bottom of at least two sub-chips stacked vertically, a pin is set on the upper surface of the first metal trace of the first sub-chip, and the first inter-chip interconnection member is electrically connected to the first end of the pin through the first metal trace. A connection path between the internal and external circuits of the vertically stacked chip can be established through the pin, thereby realizing communication and data transmission between the internal circuit of the MOS tube chip and the external circuit.

[0090] In one possible implementation, when at least two sub-chips and multiple inter-chip interconnects are covered by a packaging layer, the third sub-chip can be placed on the fifth packaging layer, the third sub-chip can be covered by the sixth packaging layer, a third through hole can be opened in the sixth packaging layer on the side of the third sub-chip, and a third inter-chip interconnect can be set in the third through hole to be electrically connected to the third sub-chip, and the fourth sub-chip can be stacked vertically on the upper surface of the sixth packaging layer, wherein the bare chip included in the third sub-chip is opposite to the back metal layer included in the fourth sub-chip, the fourth sub-chip can be covered by the seventh packaging layer, a fourth through hole can be opened in the seventh packaging layer on the side of the fourth sub-chip, and a fourth inter-chip interconnect can be set in the fourth through hole to be electrically connected to the fourth sub-chip, and the fourth sub-chip and the fourth inter-chip interconnect can be covered by the eighth packaging layer, wherein the third through hole and the fourth through hole are connected in the vertical direction, and the third inter-chip interconnect and the fourth inter-chip interconnect are electrically connected.

[0091] Figure 10 FIG. 1 is a schematic diagram of another MOS tube chip packaging method provided in an embodiment of the present application. Figure 10As shown, the chip substrate is placed on the fifth packaging layer, a copper seed layer is first deposited on the upper surface of the bare chip, and then a copper pillar is formed on the seed layer by electroplating or chemical plating. After the first metal trace is arranged on the copper pillar, the third sub-chip is formed. After the third sub-chip is covered with the sixth packaging layer, a third through hole is opened in the sixth packaging layer on the side of the third sub-chip, and a third inter-chip interconnect is set in the third through hole to be electrically connected to the first metal trace, and the third inter-chip interconnect is subjected to a chemical mechanical polishing (CMP) process. The back metal layer included in the fourth sub-chip and the bare chip included in the third sub-chip are relatively stacked vertically on the upper surface of the sixth packaging layer, and the fourth sub-chip is covered with the seventh packaging layer. A fourth through-hole is provided in the seventh packaging layer on the side of the fourth sub-chip, perpendicularly connected to the third through-hole. A fourth inter-chip interconnect is provided in the fourth through-hole, electrically connected to the third inter-chip interconnect, and the fourth inter-chip interconnect is subjected to a CMP process. After the fourth sub-chip and the fourth inter-chip interconnect are electrically connected via a first metal trace on the fourth sub-chip, the fourth sub-chip and the fourth inter-chip interconnect are encapsulated with the eighth packaging layer. Optionally, a through-hole can be provided in the sixth packaging layer above the third sub-chip, and an inter-chip interconnect can be provided to provide more contact area between the third sub-chip and the fourth sub-chip, thereby providing more interconnection paths.

[0092] In an embodiment of the present application, the third sub-chip is placed on the fifth packaging layer, the third sub-chip is covered with the sixth packaging layer, a third through hole is opened in the sixth packaging layer on the side of the third sub-chip, and a third inter-chip interconnection is set in the third through hole to be electrically connected to the third sub-chip, and the fourth sub-chip is stacked vertically on the upper surface of the sixth packaging layer, wherein the bare chip included in the third sub-chip is opposite to the back metal layer included in the fourth sub-chip, the fourth sub-chip is covered with the seventh packaging layer, a fourth through hole is opened in the seventh packaging layer on the side of the fourth sub-chip, and a fourth inter-chip interconnection is set in the fourth through hole to be electrically connected to the fourth sub-chip, and the fourth sub-chip and the fourth inter-chip interconnection are covered with the eighth packaging layer, wherein the third through hole and the fourth through hole are connected in the vertical direction, and the third inter-chip interconnection is electrically connected to the fourth inter-chip interconnection, which can realize vertical stacking and interconnection between the two sub-chips face to back, providing a basis for vertical stacking of multiple sub-chips to form a MOS tube chip, thereby reducing the packaging cost of the MOS tube chip.

[0093] In one possible implementation, when the inter-chip interconnect is electrically connected to the first end of the pin and each inter-chip interconnect is electrically connected to at least one pin, when the fourth sub-chip is located on top of at least two sub-chips stacked vertically, a pin is set on the upper surface of the first metal trace of the fourth sub-chip, and the fourth inter-chip interconnect is electrically connected to the first end of the pin through the first metal trace.

[0094] like Figure 10As shown, when the fourth sub-chip is located on top of at least two sub-chips stacked vertically, a pin through-hole is opened in the eighth packaging layer from the top surface of the eighth packaging layer to the upper surface of the first metal trace, and a pin is set in the pin through-hole by pin electroplating, the first end of the pin is electrically connected to the first metal trace, and the fourth inter-chip interconnect is electrically connected to the first end of the pin through the first metal trace.

[0095] In an embodiment of the present application, when the fourth sub-chip is located on top of at least two vertically stacked sub-chips, a pin is set on the upper surface of the first metal trace of the fourth sub-chip, and the fourth inter-chip interconnect is electrically connected to the first end of the pin through the first metal trace. A connection path between the internal and external circuits of the vertically stacked chip can be established through the pin, thereby realizing communication and data transmission between the internal circuit of the MOS tube chip and the external circuit.

[0096] In one possible implementation, when at least two sub-chips and multiple inter-chip interconnects are encapsulated by a packaging layer, the fifth sub-chip and the sixth sub-chip can be vertically stacked and then encapsulated with a ninth packaging layer, wherein the bare chip included in the fifth sub-chip is opposite to the bare chip included in the sixth sub-chip, and a fifth through hole is opened in the ninth packaging layer on the side of the fifth sub-chip and the sixth sub-chip, and a fifth inter-chip interconnect is set in the fifth through hole to electrically connect the fifth sub-chip and the sixth sub-chip.

[0097] Figure 11 This is a schematic diagram of another MOS tube chip packaging method provided in an embodiment of the present application, such as Figure 11 As shown, the bare die included in the fifth sub-chip and the bare die included in the sixth sub-chip are stacked vertically relative to each other and then covered with a ninth packaging layer. A fifth through hole is opened in the ninth packaging layer on the side of the fifth sub-chip and the sixth sub-chip, and a fifth inter-chip interconnection is set in the fifth through hole. The fifth sub-chip is electrically connected to the fifth inter-chip interconnection through the first metal trace on the fifth sub-chip, and the sixth sub-chip is electrically connected to the fifth inter-chip interconnection through the first metal trace on the sixth sub-chip.

[0098] It should be noted that when the bare chip included in the fifth sub-chip and the bare chip included in the sixth sub-chip are stacked vertically relative to each other, the first metal trace on the fifth sub-chip and the first metal trace on the sixth sub-chip will also fit together. The electrical connection between the first metal trace on the fifth sub-chip and the first metal trace on the sixth sub-chip can be achieved by electrically connecting the first metal trace on the fifth sub-chip and the first metal trace on the sixth sub-chip, and at the same time, an insulating layer is set in the non-connected area to avoid short circuit between the sub-chips, thereby realizing the electrical connection between the fifth sub-chip and the sixth sub-chip, that is, the fifth sub-chip and the sixth sub-chip can be electrically connected through the fifth inter-chip interconnection component, and can also be electrically connected through the first metal trace at the same time.

[0099] In an embodiment of the present application, the fifth sub-chip and the sixth sub-chip are vertically stacked and then wrapped with a ninth packaging layer, wherein the bare die included in the fifth sub-chip is opposite to the bare die included in the sixth sub-chip, a fifth through hole is opened in the ninth packaging layer on the side of the fifth sub-chip and the sixth sub-chip, and a fifth inter-chip interconnection is set in the fifth through hole to electrically connect the fifth sub-chip and the sixth sub-chip, so that the two sub-chips can be vertically stacked and interconnected face to face, providing a basis for vertically stacking multiple sub-chips to form a MOS tube chip, thereby reducing the packaging cost of the MOS tube chip.

[0100] In one possible implementation, when the inter-chip interconnect is electrically connected to the first end of the pin and each inter-chip interconnect is electrically connected to at least one pin, the sixth sub-chip can be located on top of at least two sub-chips stacked vertically, and multiple second metal traces can be set on the upper surface of the ninth packaging layer to be electrically connected to the fifth inter-chip interconnect, the tenth packaging layer can be used to cover the multiple second metal traces, and pins can be set on the upper surface of the multiple second metal traces, and the fifth inter-chip interconnect can be electrically connected to the first end of the pin through the second metal traces.

[0101] like Figure 11 As shown, when the sixth sub-chip is located on top of at least two vertically stacked sub-chips, multiple second metal traces are provided on the upper surface of the ninth packaging layer to electrically connect to the fifth inter-chip interconnect, and the tenth packaging layer is used to cover the multiple second metal traces. Pin through-holes are provided in the tenth packaging layer, extending from the top surface of the tenth packaging layer to the upper surface of the second metal traces. Pins are provided in the pin through-holes by pin electroplating, and the first ends of the pins are electrically connected to the second metal traces. The fifth inter-chip interconnect is also electrically connected to the first ends of the pins via the second metal traces.

[0102] In an embodiment of the present application, when the sixth sub-chip is located on top of at least two sub-chips stacked vertically, a plurality of second metal traces are arranged on the upper surface of the ninth packaging layer to be electrically connected to the fifth inter-chip interconnection member, the tenth packaging layer is used to cover the plurality of second metal traces, and pins are arranged on the upper surface of the plurality of second metal traces. The fifth inter-chip interconnection member is electrically connected to the first end of the pin through the second metal trace, and a connection path between the internal and external circuits of the vertically stacked chip can be established through the pins, thereby realizing communication and data transmission between the internal circuit of the MOS tube chip and the external circuit.

[0103] It should be pointed out that, according to the needs of implementation, the various components / steps described in the embodiments of the present application can be split into more components / steps, or two or more components / steps or partial operations of components / steps can be combined into new components / steps to achieve the purpose of the embodiments of the present application.

[0104] Those skilled in the art will appreciate that the units and method steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of this application.

[0105] The above implementation methods are only used to illustrate the embodiments of the present application, and are not intended to limit the embodiments of the present application. Ordinary technicians in the relevant technical field can make various changes and modifications without departing from the spirit and scope of the embodiments of the present application. Therefore, all equivalent technical solutions also fall within the scope of the embodiments of the present application, and the scope of patent protection of the embodiments of the present application should be defined by the claims.

Claims

1. A MOS tube chip, characterized in that: include: at least two sub-chips, a plurality of inter-chip interconnects, a plurality of pins, and a packaging layer; The at least two sub-chips are stacked vertically, and each sub-chip includes at least one MOS transistor; The same poles of the MOS transistors in the at least two sub-chips are electrically connected via the inter-chip interconnection, and different poles of the MOS transistors are electrically connected to different inter-chip interconnections; The packaging layer covers the at least two sub-chips and the plurality of inter-chip interconnects; The first ends of the pins are electrically connected to the inter-chip interconnects, the second ends of the pins are exposed outside the packaging layer, and each of the inter-chip interconnects is electrically connected to at least one of the pins.

2. The MOS tube chip according to claim 1, characterized in that: The sub-chip comprises: a bare die, a back metal layer and a connection layer; The back surface of the die is bonded to the back metal layer, and the front surface of the die is bonded to the lower surface of the connection layer; The connection layer is provided with a plurality of electrical connection pillars, a first end of the electrical connection pillar is electrically connected to one electrode of the MOS tube in the bare chip, and a second end of the electrical connection pillar is electrically connected to the inter-chip interconnection member or the pin.

3. The MOS tube chip according to claim 2, characterized in that: The sub-chip further includes a first redistribution layer; The first redistribution layer is bonded to the upper surface of the connection layer; The first redistribution layer is provided with multiple first metal traces, the lower surface of the first metal trace is electrically connected to the second end of the electrical connection column, the first metal trace is electrically connected to the inter-chip interconnection, and the electrical connection columns connected to different poles of the MOS tube in the bare chip are electrically connected to different first metal traces.

4. The MOS tube chip according to claim 3, characterized in that: The at least two sub-chips include a first sub-chip and a second sub-chip; The back metal layer included in the first sub-chip and the back metal layer included in the second sub-chip are bonded together via an adhesive layer.

5. The MOS tube chip according to claim 4, characterized in that: When the first sub-chip is located at the bottom of the at least two sub-chips that are vertically stacked, the pin is electrically connected to the upper surface of the first metal trace in the first sub-chip.

6. The MOS tube chip according to claim 3, characterized in that: The at least two sub-chips include a third sub-chip and a fourth sub-chip; The third sub-chip and the fourth sub-chip are adjacent to each other, and the bare die included in the third sub-chip is opposite to the back metal layer included in the fourth sub-chip.

7. The MOS tube chip according to claim 6, characterized in that: When the third sub-chip is located at the bottom of the at least two sub-chips that are vertically stacked, the pin is electrically connected to the upper surface of the first metal trace in the fourth sub-chip.

8. The MOS tube chip according to claim 3, characterized in that: The at least two sub-chips include a fifth sub-chip and a sixth sub-chip; The fifth sub-chip and the sixth sub-chip are arranged adjacent to each other, the first redistribution layer included in the fifth sub-chip is adhered to the first redistribution layer included in the sixth sub-chip, and the fifth sub-chip and the sixth sub-chip are electrically connected through the first metal routing included in the fifth sub-chip and the first metal routing included in the sixth sub-chip.

9. The MOS tube chip according to claim 8, characterized in that: The MOS tube chip also includes a second redistribution layer; When the fifth sub-chip is located at the bottom of the at least two sub-chips vertically stacked, the second redistribution layer is arranged on the top of the sixth sub-chip, and the packaging layer covers the second redistribution layer; The second redistribution layer includes multiple second metal traces, the second metal traces are electrically connected to the inter-chip interconnects, the first ends of the pins are electrically connected to the second metal traces, and the inter-chip interconnects connected to different poles of the MOS tubes in the bare chip are electrically connected to different second metal traces.

10. A packaging method for a MOS tube chip, characterized in that: include: Vertically stacking at least two sub-chips, and electrically connecting the MOS transistors included in the at least two sub-chips through a plurality of inter-chip interconnects, wherein each sub-chip includes at least one MOS transistor, and different poles of the MOS transistor are electrically connected to different inter-chip interconnects; Electrically connecting the inter-chip interconnects to the first ends of the pins, each of the inter-chip interconnects being electrically connected to at least one of the pins; The MOS transistor chip is obtained by encapsulating the at least two sub-chips and the plurality of inter-chip interconnections with a packaging layer, and exposing the second ends of the pins outside the packaging layer.

11. The method according to claim 10, characterized in that The step of electrically connecting the MOS transistors included in the at least two sub-chips through a plurality of inter-chip interconnects comprises: A plurality of electrical connection pillars are provided on the front surface of the bare die of the sub-chip, wherein a first end of the electrical connection pillar is electrically connected to an electrode of at least one MOS transistor included in the bare die, wherein the sub-chip includes the bare die and a back metal layer; The second ends of the electrical connection pillars are electrically connected to the plurality of inter-chip interconnects or the pins through a plurality of first metal traces.

12. The method according to claim 11, characterized in that The step of encapsulating the at least two sub-chips and the plurality of inter-chip interconnects with a packaging layer comprises: Placing a first sub-chip on a temporary carrier, covering the first sub-chip with a first packaging layer, opening a first through-hole in the first packaging layer on a side of the first sub-chip, and providing a first inter-chip interconnect in the first through-hole to electrically connect the first sub-chip, and covering the first sub-chip and the first inter-chip interconnect with a second packaging layer; Peeling off the temporary carrier and flipping over the first sub-chip, providing an adhesive layer on the back metal layer of the first sub-chip, vertically stacking the second sub-chip on top of the first sub-chip, and adhering the back metal layer of the second sub-chip to the back metal layer of the first sub-chip via the adhesive layer, wherein the back metal layer of the first sub-chip is opposite to the back metal layer of the second sub-chip; A third packaging layer is used to cover the second sub-chip, a second through hole is opened in the third packaging layer on the side of the second sub-chip, and a second inter-chip interconnection is set in the second through hole to be electrically connected to the second sub-chip, and a fourth packaging layer is used to cover the second sub-chip and the second inter-chip interconnection, wherein the first through hole and the second through hole are connected in a vertical direction, and the first inter-chip interconnection and the second inter-chip interconnection are electrically connected.

13. The method according to claim 12, characterized in that The step of electrically connecting the inter-chip interconnects to the first ends of the pins, wherein each of the inter-chip interconnects is electrically connected to at least one of the pins, comprises: When the first sub-chip is located at the bottom of the at least two sub-chips stacked vertically, the pin is set on the upper surface of the first metal trace of the first sub-chip, and the first inter-chip interconnect is electrically connected to the first end of the pin through the first metal trace.

14. The method according to claim 11, characterized in that The step of encapsulating the at least two sub-chips and the plurality of inter-chip interconnects with a packaging layer comprises: Placing the third sub-chip on the fifth packaging layer, covering the third sub-chip with a sixth packaging layer, opening a third through hole in the sixth packaging layer on a side of the third sub-chip, and providing a third inter-chip interconnect in the third through hole to electrically connect with the third sub-chip; vertically stacking a fourth sub-chip on the upper surface of the sixth packaging layer, wherein the bare die included in the third sub-chip is opposite to the back metal layer included in the fourth sub-chip; The fourth sub-chip is covered with a seventh packaging layer, a fourth through hole is opened in the seventh packaging layer on the side of the fourth sub-chip, a fourth inter-chip interconnection is set in the fourth through hole to be electrically connected to the fourth sub-chip, and the fourth sub-chip and the fourth inter-chip interconnection are covered with an eighth packaging layer, wherein the third through hole and the fourth through hole are connected in a vertical direction, and the third inter-chip interconnection and the fourth inter-chip interconnection are electrically connected.

15. The method according to claim 14, characterized in that The step of electrically connecting the inter-chip interconnects to the first ends of the pins, wherein each of the inter-chip interconnects is electrically connected to at least one of the pins, comprises: When the fourth sub-chip is located on top of the at least two sub-chips stacked vertically, the pin is set on the upper surface of the first metal trace of the fourth sub-chip, and the fourth inter-chip interconnect is electrically connected to the first end of the pin through the first metal trace.

16. The method according to claim 11, characterized in that The step of encapsulating the at least two sub-chips and the plurality of inter-chip interconnects with a packaging layer comprises: vertically stacking a fifth sub-chip and a sixth sub-chip and encapsulating them with a ninth packaging layer, wherein the die included in the fifth sub-chip is opposite to the die included in the sixth sub-chip; A fifth through hole is opened in the ninth packaging layer on the side of the fifth sub-chip and the sixth sub-chip, and a fifth inter-chip interconnection is provided in the fifth through hole to electrically connect with the fifth sub-chip and the sixth sub-chip.

17. The method according to claim 16, characterized in that The step of electrically connecting the inter-chip interconnects to the first ends of the pins, wherein each of the inter-chip interconnects is electrically connected to at least one of the pins, comprises: When the sixth sub-chip is located on top of the at least two sub-chips stacked vertically, a plurality of second metal traces are arranged on the upper surface of the ninth packaging layer to be electrically connected to the fifth inter-chip interconnection component, the tenth packaging layer is used to cover the plurality of second metal traces, the pins are arranged on the upper surface of the plurality of second metal traces, and the fifth inter-chip interconnection component is electrically connected to the first end of the pins through the second metal traces.

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