High-voltage power supply selection circuit and control method thereof

Abstract

The application discloses a high-voltage power supply selection high circuit and a control method thereof, and comprises a floating power supply generation circuit, a high-voltage floating comparator circuit, inverters INV1 to INV4, a high-voltage PMOS tube PDM5 and a high-voltage PMOS tube PDM6. The floating power supply generation circuit generates a floating high voltage HVDD and a floating low voltage HVSS. Two inputs of the high-voltage floating comparator circuit are connected with input signals V1 and V2 respectively. The inverters INV1 to INV4 generate two inverted signals A and B from the output signal of the high-voltage floating comparator circuit. The high-voltage power supply end of the high-voltage floating comparator circuit, the source of the high-voltage PMOS tube PDM5 and the source of the high-voltage PMOS tube PDM6D are connected with the floating high voltage HVDD. The low-voltage power supply end of the high-voltage floating comparator circuit is connected with the floating low voltage HVSS. The application realizes the high-voltage power supply selection high circuit.

Description

Technical Field

[0001] This invention relates to a high-voltage power supply high-voltage selection circuit and its control method, particularly a high-voltage power supply high-voltage selection circuit and its control method, belonging to the field of semiconductor integrated circuit technology. Background Technology

[0002] In power management systems, load switches integrating ideal diode functions provide more efficient and reliable power to OR (orific power) systems due to their key advantages such as low forward conduction losses, low leakage, and simplified load distribution. However, when one power source in a dual-power system fails, the function of its internal ideal diode circuit cannot be maintained, causing reverse current from the high-voltage supply to the low-voltage supply, resulting in a decrease in output voltage and potentially leading to system malfunctions or even damage.

[0003] In existing technologies, power selection circuits are often low-voltage designs. They use a low-voltage comparator to determine the magnitude of the input and output voltages, and then use the result as an enable signal to turn on the high-voltage side switch to achieve the function of selecting high voltage. However, in high-voltage scenarios, the two voltages to be compared may differ by tens of volts, making this approach no longer applicable. Therefore, it is necessary to propose a high-voltage selection circuit for both input and output voltages, which powers an ideal diode circuit to ensure that the ideal diode circuit can still operate normally when the input voltage is lost, thereby protecting the input power supply and the load. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a high-voltage power supply high-voltage selection circuit and its control method, so as to realize the high-voltage power supply high-voltage selection circuit.

[0005] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0006] A high-voltage power supply selection circuit includes a floating power supply generation circuit, a high-voltage floating comparator circuit, inverters INV1 to INV4, a high-voltage PMOS transistor PDM5, and a high-voltage PMOS transistor PDM6. The floating power supply generation circuit generates a floating high voltage HVDD and a floating low voltage HVSS. The first input terminal of the high-voltage floating comparator circuit is connected to the drain of the high-voltage PMOS transistor PDM5 and is connected to the input signal V1. The second input terminal of the high-voltage floating comparator circuit is connected to the drain of the high-voltage PMOS transistor PDM6 and is connected to the input signal V2. The high-voltage power supply terminal of the high-voltage floating comparator circuit, the source of the high-voltage PMOS transistor PDM5, and the high voltage... The source of the high-voltage PMOS transistor PDM6D is connected to the floating high voltage HVDD. The low-voltage power supply of the high-voltage floating comparator circuit is connected to the floating low voltage HVSS. The output of the high-voltage floating comparator circuit is connected to the input of inverter INV1. The output of inverter INV1 is connected to the input of inverter INV2. The output of inverter INV2 is connected to the input of inverter INV3. The output of inverter INV3 is connected to the input of inverter INV4 and the gate of the high-voltage PMOS transistor PDM5 to generate signal A. The output of inverter INV4 is connected to the gate of the high-voltage PMOS transistor PDM6 to generate signal B.

[0007] Furthermore, the high-voltage floating comparator circuit includes NMOS transistors NM1-NM4, PMOS transistors PM1-PM2, high-voltage PMOS transistors PDM1-PDM4, and a current source I1. The drain of high-voltage PMOS transistor PDM1 is connected to the drain of high-voltage PMOS transistor PDM3 and serves as the first input terminal of the high-voltage floating comparator circuit. The drain of high-voltage PMOS transistor PDM2 is connected to the drain of high-voltage PMOS transistor PDM4 and serves as the second input terminal of the high-voltage floating comparator circuit. The gate of high-voltage PMOS transistor PDM1 is connected to the gates of high-voltage PMOS transistors PDM2, PDM3, and PDM4, the source of high-voltage PMOS transistor PDM1, the source of high-voltage PMOS transistor PDM2, and one end of the current source I1. The body terminal of high-voltage PMOS transistor PDM1 is connected to the body terminals of high-voltage PMOS transistors PDM3 and PDM2, and the body terminal of high-voltage PMOS transistor PDM4. The body terminal of PDM4, the source of PMOS transistor PM1, and the source of PMOS transistor PM2 are connected and serve as the high-voltage power supply terminal of the high-voltage floating comparator circuit. The source of high-voltage PMOS transistor PDM3 is connected to the drain and gate of NMOS transistor NM2, the gate of NMOS transistor NM1, and the gate of NMOS transistor NM3. The source of high-voltage PMOS transistor PDM4 is connected to the drain of NMOS transistor NM3 and the gate of NMOS transistor NM4. The gate of PMOS transistor PM1 is connected to the gate of PMOS transistor PM2, the drain of PMOS transistor PM1, and the drain of NMOS transistor NM1. The drain of PMOS transistor PM2 is connected to the drain of NMOS transistor NM4 and serves as the output terminal of the high-voltage floating comparator circuit. The sources of NMOS transistors NM1, NM2, NM3, and NM4 serve as the low-voltage power supply terminal of the high-voltage floating comparator circuit. The other end of current source I1 is grounded.

[0008] Furthermore, the NMOS transistors NM1 to NM4 have the same width-to-length ratio, the PMOS transistors PM1 to PM2 have the same width-to-length ratio, and the high-voltage PMOS transistors PDM1 to PDM4 have the same width-to-length ratio.

[0009] Further, the floating power supply generating circuit includes PMOS transistors PM3 to PM10, a high-voltage PMOS transistor PDM7, a high-voltage NMOS transistor NDM1, a resistor R3, and a current source I2. The source of PMOS transistor PM3 is connected to the source of PMOS transistor PM7 to generate a floating high voltage HVDD. The gate of PMOS transistor PM3 is connected to the drain of PMOS transistor PM3 and the source of PMOS transistor PM4. The gate of PMOS transistor PM7 is connected to the drain of PMOS transistor PM7 and the source of PMOS transistor PM8. The gate of PMOS transistor PM4 is connected to the drain of PMOS transistor PM4 and the source of PMOS transistor PM5. The gate of PMOS transistor PM8 is connected to the drain of PMOS transistor PM8 and the source of PMOS transistor PM10. The source of S-channel transistor PM9 is connected. The gate of PMOS transistor PM5 is connected to the drain of PMOS transistor PM5, the drain of high-voltage NMOS transistor NDM1, and the source of high-voltage PMOS transistor PDM7, generating a floating low voltage HVSS. The gate of PMOS transistor PM9 is connected to the drain of PMOS transistor PM9 and the source of PMOS transistor PM10. The gate of PMOS transistor PM10 is connected to the gate of high-voltage PMOS transistor PDM7, the drain of PMOS transistor PM10, and one end of current source I2. The drain of high-voltage PMOS transistor PDM7 is connected to the gate of high-voltage NMOS transistor NDM1 and one end of resistor R3. The source of high-voltage NMOS transistor NDM1, the other end of resistor R3, and the other end of current source I2 are grounded.

[0010] Furthermore, the floating power generation circuit also includes a capacitor C1, one end of which is connected to the floating high voltage HVDD, and the other end of which is connected to the floating low voltage HVSS.

[0011] Furthermore, the PMOS transistors PM3 to PM10 have the same width-to-length ratio.

[0012] Furthermore, it also includes resistors R1 and R2. One end of resistor R1 is connected to the input signal V1, and the other end of resistor R1 is connected to the first input terminal of the floating high voltage comparator circuit and the drain of the high voltage PMOS transistor PDM5. One end of resistor R2 is connected to the input signal V2, and the other end of resistor R2 is connected to the second input terminal of the floating high voltage comparator circuit and the drain of the high voltage PMOS transistor PDM6.

[0013] A control method for a high-voltage power supply high-voltage selection circuit includes the following steps:

[0014] PMOS transistors PM3-PM10, high-voltage PMOS transistor PDM7, high-voltage NMOS transistor NDM1, resistor R3, and current source I2 constitute a floating power supply generation circuit. PMOS transistors PM3-PM10 have the same width-to-length ratio. If the magnitude of the current from current source I2 is I, then

[0015]

[0016]

[0017] in, It refers to the electron mobility of a transistor. VTH is the gate oxide capacitance per unit area, and VTH is the threshold voltage.

[0018] The high-voltage NMOS transistor NDM1, resistor R3, and high-voltage PMOS transistor PDM7 form an enhancement-mode source follower structure, which enhances the current absorption capability of the floating low-voltage HVSS. When the floating low-voltage HVSS node needs to absorb a large current, the gate voltage of the high-voltage NMOS transistor NDM1 rises, turning on the high-voltage NMOS transistor NDM1 to assist the floating low-voltage HVSS node in absorbing current and prevent the floating low-voltage HVSS voltage from being raised.

[0019] This high-voltage floating comparator circuit consists of NMOS transistors NM1-NM4, PMOS transistors PM1-PM2, and high-voltage PMOS transistors PDM1-PDM4. NMOS transistors NM1-NM4 have the same width-to-length ratio, as do PMOS transistors PM1-PM2 and high-voltage PMOS transistors PDM1-PDM4. Current source I1 provides current bias for high-voltage transistors PDM1 and PDM2. High-voltage PMOS transistors PDM1-PDM4 have the same gate voltage. When the input signal V1 is greater than the input signal V2, the high-voltage PMOS transistor PDM1... As the current of transistor 3 increases, the current of high-voltage PMOS transistor PDM4 decreases, and the current of high-voltage PMOS transistor PDM3 is greater than the current of high-voltage PMOS transistor PDM4. The current of NMOS transistor NM2 is equal to the current of high-voltage PMOS transistor PDM3. NMOS transistor NM3 copies the current of NMOS transistor NM2. Therefore, the current of NMOS transistor NM3 is greater than the current of high-voltage PMOS transistor PDM4. The gate voltage of NMOS transistor NM4 is pulled down, and the drain voltage of NMOS transistor NM4 is pulled up by PMOS transistor PM2, resulting in a logic output of 1. Similarly, when the input signal V1 is less than the input signal V2, the logic output is 0.

[0020] Inverters INV1 to INV4 are inverters that float between the floating high voltage HVDD and the floating low voltage HVSS. After being driven by four inverters, the voltage of signal A is equal to the floating low voltage HVSS, and the voltage of signal B is equal to the floating high voltage HVDD. At this time, the high voltage PMOS transistor PDM5 is turned on, and HVDD = V1, thus realizing the high voltage selection function.

[0021] When input signals V1 and V2 are powered on, assuming V1 > V2, the floating high voltage HVDD will rise with the input signal V1, but the voltage drop of the body diode will decrease. When the floating high voltage HVDD is established to the point where the subsequent basic module can work, the bias current is generated, the high voltage floating comparator circuit can work normally, the high voltage PMOS transistor PDM5 turns on, and the voltage drop of the body diode is reduced to the voltage drop of the power transistor's drive current multiplied by the internal resistance, so that HVDD = V1.

[0022] Compared with the prior art, the present invention has the following advantages and effects: The present invention provides a high-voltage power supply selection circuit and its control method. A floating voltage domain is generated by a floating power supply generation circuit, a floating comparator is designed in the voltage domain, and then the magnitudes of two input voltages are compared, thereby selecting the corresponding power transistor to realize the high-voltage power supply selection circuit. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of a high-voltage power supply selection circuit according to the present invention. Detailed Implementation

[0024] To illustrate in detail the technical solutions adopted by the present invention to achieve the intended technical objectives, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Furthermore, the technical means or technical features in the embodiments of the present invention can be replaced without creative effort. The present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0025] like Figure 1As shown, a high-voltage power supply selection circuit of the present invention includes a floating power supply generation circuit, a high-voltage floating comparator circuit, inverters INV1 to INV4, a high-voltage PMOS transistor PDM5, and a high-voltage PMOS transistor PDM6. The floating power supply generation circuit generates a floating high voltage HVDD and a floating low voltage HVSS. The first input terminal of the high-voltage floating comparator circuit is connected to the drain of the high-voltage PMOS transistor PDM5 and is connected to the input signal V1. The second input terminal of the high-voltage floating comparator circuit is connected to the drain of the high-voltage PMOS transistor PDM6 and is connected to the input signal V2. The high-voltage power supply terminal of the high-voltage floating comparator circuit and the high-voltage PMOS transistor PDM5... The source of the high-voltage PMOS transistor PDM6D is connected to the floating high voltage HVDD. The low-voltage power supply of the high-voltage floating comparator circuit is connected to the floating low voltage HVSS. The output of the high-voltage floating comparator circuit is connected to the input of inverter INV1. The output of inverter INV1 is connected to the input of inverter INV2. The output of inverter INV2 is connected to the input of inverter INV3. The output of inverter INV3 is connected to the input of inverter INV4 and the gate of the high-voltage PMOS transistor PDM5 to generate signal A. The output of inverter INV4 is connected to the gate of the high-voltage PMOS transistor PDM6 to generate signal B.

[0026] The high-voltage floating comparator circuit includes NMOS transistors NM1-NM4, PMOS transistors PM1-PM2, high-voltage PMOS transistors PDM1-PDM4, and a current source I1. The drain of high-voltage PMOS transistor PDM1 is connected to the drain of high-voltage PMOS transistor PDM3 and serves as the first input terminal of the high-voltage floating comparator circuit. The drain of high-voltage PMOS transistor PDM2 is connected to the drain of high-voltage PMOS transistor PDM4 and serves as the second input terminal of the high-voltage floating comparator circuit. The gate of high-voltage PMOS transistor PDM1 is connected to the gates of high-voltage PMOS transistors PDM2, PDM3, and PDM4, the source of high-voltage PMOS transistors PDM1 and PDM2, and one end of the current source I1. The body terminal of high-voltage PMOS transistor PDM1 is connected to the body terminals of high-voltage PMOS transistors PDM3, PDM2, and PDM4. The body terminal, the source of PMOS transistor PM1, and the source of PMOS transistor PM2 are connected and serve as the high-voltage power supply terminal of the high-voltage floating comparator circuit. The source of high-voltage PMOS transistor PDM3 is connected to the drain of NMOS transistor NM2, the gate of NMOS transistor NM2, the gate of NMOS transistor NM1, and the gate of NMOS transistor NM3. The source of high-voltage PMOS transistor PDM4 is connected to the drain of NMOS transistor NM3 and the gate of NMOS transistor NM4. The gate of PMOS transistor PM1 is connected to the gate of PMOS transistor PM2, the drain of PMOS transistor PM1, and the drain of NMOS transistor NM1. The drain of PMOS transistor PM2 is connected to the drain of NMOS transistor NM4 and serves as the output terminal of the high-voltage floating comparator circuit. The sources of NMOS transistors NM1, NM2, NM3, and NM4 serve as the low-voltage power supply terminal of the high-voltage floating comparator circuit. The other end of current source I1 is grounded.

[0027] Among them, NMOS transistors NM1 to NM4 have the same width-to-length ratio, PMOS transistors PM1 to PM2 have the same width-to-length ratio, and high-voltage PMOS transistors PDM1 to PDM4 have the same width-to-length ratio.

[0028] The floating power supply generation circuit includes PMOS transistors PM3-PM10, a high-voltage PMOS transistor PDM7, a high-voltage NMOS transistor NDM1, a resistor R3, and a current source I2. The source of PMOS transistor PM3 is connected to the source of PMOS transistor PM7 to generate a floating high voltage HVDD. The gate of PMOS transistor PM3 is connected to the drain of PMOS transistor PM3 and the source of PMOS transistor PM4. The gate of PMOS transistor PM7 is connected to the drain of PMOS transistor PM7 and the source of PMOS transistor PM8. The gate of PMOS transistor PM4 is connected to the drain of PMOS transistor PM4 and the source of PMOS transistor PM5. The gate of PMOS transistor PM8 is connected to the drain of PMOS transistor PM8 and the source of PMOS transistor PM5. The source of PMOS transistor PM9 is connected to the drain of PMOS transistor PM5, the drain of high-voltage NMOS transistor NDM1, and the source of high-voltage PMOS transistor PDM7, generating a floating low voltage HVSS. The gate of PMOS transistor PM9 is connected to the drain of PMOS transistor PM9 and the source of PMOS transistor PM10. The gate of PMOS transistor PM10 is connected to the gate of high-voltage PMOS transistor PDM7, the drain of PMOS transistor PM10, and one end of current source I2. The drain of high-voltage PMOS transistor PDM7 is connected to the gate of high-voltage NMOS transistor NDM1 and one end of resistor R3. The source of high-voltage NMOS transistor NDM1, the other end of resistor R3, and the other end of current source I2 are grounded.

[0029] The floating power supply generating circuit also includes a capacitor C1, one end of which is connected to the floating high voltage HVDD, and the other end of which is connected to the floating low voltage HVSS.

[0030] PMOS transistors PM3 through PM10 have the same width-to-length ratio.

[0031] The high-voltage power supply selection circuit of the present invention further includes resistors R1 and R2. One end of resistor R1 is connected to the input signal V1, and the other end of resistor R1 is connected to the first input terminal of the floating high-voltage comparator circuit and the drain of the high-voltage PMOS transistor PDM5. One end of resistor R2 is connected to the input signal V2, and the other end of resistor R2 is connected to the second input terminal of the floating high-voltage comparator circuit and the drain of the high-voltage PMOS transistor PDM6. Resistors R1 and R2 are used to limit the instantaneous current when V1 and V2 are switched.

[0032] A control method for a high-voltage power supply high-voltage selection circuit includes the following steps:

[0033] PMOS transistors PM3-PM10, high-voltage PMOS transistor PDM7, high-voltage NMOS transistor NDM1, resistor R3, and current source I2 constitute a floating power supply generation circuit. PMOS transistors PM3-PM10 have the same width-to-length ratio. If the magnitude of the current from current source I2 is I, then

[0034]

[0035]

[0036] in, It refers to the electron mobility of a transistor. VTH is the gate oxide capacitance per unit area, and HVSS is the threshold voltage. HVSS is designed to be only three times lower than the VGS voltage of HVDD, approximately 4-5V. Therefore, HVDD to HVSS is a low-voltage power supply in a floating high-voltage domain. The comparator circuit can be designed using low-voltage transistors in the high-voltage domain, which greatly saves area costs.

[0037] The high-voltage NMOS transistor NDM1, resistor R3, and high-voltage PMOS transistor PDM7 form an enhancement-mode source follower structure, which enhances the current absorption capability of the floating low-voltage HVSS. When the floating low-voltage HVSS node needs to absorb a large current, the gate voltage of the high-voltage NMOS transistor NDM1 rises, turning on the high-voltage NMOS transistor NDM1 to assist the floating low-voltage HVSS node in absorbing current and prevent the floating low-voltage HVSS voltage from being raised.

[0038] A high-voltage floating comparator circuit composed of NMOS transistors NM1-NM4, PMOS transistors PM1-PM2, and high-voltage PMOS transistors PDM1-PDM4 is used to compare the magnitudes of input voltage V1 and input voltage V2, and output a logic 1 or logic 0 signal. NMOS transistors NM1 to NM4 have the same width-to-length ratio, PMOS transistors PM1 to PM2 have the same width-to-length ratio, and high-voltage PMOS transistors PDM1 to PDM4 have the same width-to-length ratio. Current source I1 provides current source bias for high-voltage transistors PDM1 and PDM2. High-voltage PMOS transistors PDM1 to PDM4 have the same gate voltage. When the input signal V1 is greater than the input signal V2, the current of high-voltage PMOS transistor PDM3 increases, and the current of high-voltage PMOS transistor PDM4 decreases. Moreover, the current of high-voltage PMOS transistor PDM3 is greater than the current of high-voltage PMOS transistor PDM4. The current of NMOS transistor NM2 is equal to the current of high-voltage PMOS transistor PDM3. NMOS transistor NM3 copies the current of NMOS transistor NM2. Therefore, the current of NMOS transistor NM3 is greater than the current of high-voltage PMOS transistor PDM4. The gate voltage of NMOS transistor NM4 is pulled down, and the drain voltage of NMOS transistor NM4 is pulled up by PMOS transistor PM2, resulting in output logic 1. NMOS transistor NM1 copies the current of NMOS transistor NM2, the current of PMOS transistor PM1 is equal to the current of NMOS transistor NM1, and PMOS transistor PM2 copies the current of PMOS transistor PM1. Therefore, the current of PMOS transistor PM2 is equal to the current of the high-voltage PMOS transistor PDM3. Similarly, when the input signal V1 is less than the input signal V2, the output logic is 0.

[0039] Inverters INV1 to INV4 are inverters that float between the floating high voltage HVDD and the floating low voltage HVSS. After being driven by four inverters, the voltage of signal A is equal to the floating low voltage HVSS, and the voltage of signal B is equal to the floating high voltage HVDD. At this time, the high voltage PMOS transistor PDM5 is turned on, and HVDD≈V1, thus realizing the high voltage selection function.

[0040] When the input signal V1 is much greater than the input signal V2, the current from the current source I1 flows entirely through the high-voltage PMOS transistor PDM1. Therefore, the drain and source voltages of the high-voltage PMOS transistor PDM1 are close to the high voltage of the input signal V1. The drain voltage of the high-voltage PMOS transistor PDM2 is low, and the gate voltage is high, so the high-voltage PMOS transistor PDM2 will not be damaged.

[0041] Since this circuit generates power for all modules, its operating mode is crucial before current sources I1 and I2 generate bias current. Because there is no bias current at this time, the output of the floating high-voltage comparator circuit cannot be determined, nor can the switching states of high-voltage PMOS transistors PDM5 and PDM6. However, there is a body diode connection between the drain of high-voltage PMOS transistors PDM5 and PDM6 and HVDD. When input signals V1 and V2 are powered on (assuming V1 > V2), the floating high voltage HVDD will rise with the input signal V1, only decreasing by the body diode voltage drop. When the floating high voltage HVDD is established to the point where the subsequent basic module can operate, the bias current is generated, the high-voltage floating comparator circuit can operate normally, and high-voltage PMOS transistor PDM5 turns on, reducing the body diode voltage drop to the voltage drop caused by the power transistor's drive current multiplied by its internal resistance, making HVDD ≈ V1.

[0042] This invention provides a high-voltage power supply selection circuit and its control method. A floating voltage domain is generated by a floating power supply generation circuit, and a floating comparator is designed in this voltage domain to compare the magnitudes of two input voltages and then select the corresponding power transistor, thereby realizing the high-voltage power supply selection circuit.

[0043] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent substitutions, and improvements made to the above embodiments without departing from the scope of the present invention, based on the technical essence of the present invention and within the spirit and principles of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A high-voltage power supply high-voltage selection circuit, characterized in that: It includes a floating power supply generation circuit, a high-voltage floating comparator circuit, inverters INV1 to INV4, high-voltage PMOS transistors PDM5 and PDM6. The floating power supply generation circuit generates a floating high voltage HVDD and a floating low voltage HVSS. The first input terminal of the high-voltage floating comparator circuit is connected to the drain of the high-voltage PMOS transistor PDM5 and is connected to the input signal V1. The second input terminal of the high-voltage floating comparator circuit is connected to the drain of the high-voltage PMOS transistor PDM6 and is connected to the input signal V2. The high-voltage power supply terminal of the high-voltage floating comparator circuit, the source of the high-voltage PMOS transistor PDM5, and the high-voltage PMOS transistor PDM6 are connected to the high-voltage PMOS transistor PDM6. The source of transistor PDM6D is connected to the floating high voltage HVDD. The low voltage power supply of the high voltage floating comparator circuit is connected to the floating low voltage HVSS. The output of the high voltage floating comparator circuit is connected to the input of inverter INV1. The output of inverter INV1 is connected to the input of inverter INV2. The output of inverter INV2 is connected to the input of inverter INV3. The output of inverter INV3 is connected to the input of inverter INV4 and the gate of high voltage PMOS transistor PDM5 to generate signal A. The output of inverter INV4 is connected to the gate of high voltage PMOS transistor PDM6 to generate signal B. The high-voltage floating comparator circuit includes NMOS transistors NM1-NM4, PMOS transistors PM1-PM2, high-voltage PMOS transistors PDM1-PDM4, and a current source I1. The drain of high-voltage PMOS transistor PDM1 is connected to the drain of high-voltage PMOS transistor PDM3 and serves as the first input terminal of the high-voltage floating comparator circuit. The drain of high-voltage PMOS transistor PDM2 is connected to the drain of high-voltage PMOS transistor PDM4 and serves as the second input terminal of the high-voltage floating comparator circuit. The gate of high-voltage PMOS transistor PDM1 is connected to the gates of high-voltage PMOS transistors PDM2, PDM3, and PDM4, the source of high-voltage PMOS transistor PDM1, the source of high-voltage PMOS transistor PDM2, and one end of the current source I1. The body terminal of high-voltage PMOS transistor PDM1 is connected to the body terminals of high-voltage PMOS transistors PDM3, PDM2, and PDM4. The body terminal of transistor 4, the source of PMOS transistor PM1, and the source of PMOS transistor PM2 are connected and serve as the high-voltage power supply terminal of the high-voltage floating comparator circuit. The source of high-voltage PMOS transistor PDM3 is connected to the drain, gate, gate of NMOS transistor NM2, gate of NMOS transistor NM1, and gate of NMOS transistor NM3. The source of high-voltage PMOS transistor PDM4 is connected to the drain of NMOS transistor NM3 and the gate of NMOS transistor NM4. The gate of PMOS transistor PM1 is connected to the gate, drain, and drain of PMOS transistor PM2. The drain of PMOS transistor PM2 is connected to the drain of NMOS transistor NM4 and serves as the output terminal of the high-voltage floating comparator circuit. The sources of NMOS transistors NM1, NM2, NM3, and NM4 serve as the low-voltage power supply terminal of the high-voltage floating comparator circuit. The other end of current source I1 is grounded.

2. The high-voltage power supply selection circuit according to claim 1, characterized in that: The NMOS transistors NM1 to NM4 have the same width-to-length ratio, the PMOS transistors PM1 to PM2 have the same width-to-length ratio, and the high-voltage PMOS transistors PDM1 to PDM4 have the same width-to-length ratio.

3. The high-voltage power supply selection circuit according to claim 1, characterized in that: The floating power supply generating circuit includes PMOS transistors PM3 to PM10, a high-voltage PMOS transistor PDM7, a high-voltage NMOS transistor NDM1, a resistor R3, and a current source I2. The source of PMOS transistor PM3 is connected to the source of PMOS transistor PM7 to generate a floating high voltage HVDD. The gate of PMOS transistor PM3 is connected to the drain of PMOS transistor PM3 and the source of PMOS transistor PM4. The gate of PMOS transistor PM7 is connected to the drain of PMOS transistor PM7 and the source of PMOS transistor PM8. The gate of PMOS transistor PM4 is connected to the drain of PMOS transistor PM4 and the source of PMOS transistor PM5. The gate of PMOS transistor PM8 is connected to the drain of PMOS transistor PM8 and the source of PMOS transistor PDM1. The source of M9 is connected. The gate of PMOS transistor PM5 is connected to the drain of PMOS transistor PM5, the drain of high-voltage NMOS transistor NDM1, and the source of high-voltage PMOS transistor PDM7 to generate a floating low voltage HVSS. The gate of PMOS transistor PM9 is connected to the drain of PMOS transistor PM9 and the source of PMOS transistor PM10. The gate of PMOS transistor PM10 is connected to the gate of high-voltage PMOS transistor PDM7, the drain of PMOS transistor PM10, and one end of current source I2. The drain of high-voltage PMOS transistor PDM7 is connected to the gate of high-voltage NMOS transistor NDM1 and one end of resistor R3. The source of high-voltage NMOS transistor NDM1, the other end of resistor R3, and the other end of current source I2 are grounded.

4. The high-voltage power supply selection circuit according to claim 3, characterized in that: The floating power generation circuit also includes a capacitor C1, one end of which is connected to the floating high voltage HVDD, and the other end of which is connected to the floating low voltage HVSS.

5. A high-voltage power supply selection circuit according to claim 3, characterized in that: The PMOS transistors PM3 to PM10 have the same width-to-length ratio.

6. The high-voltage power supply selection circuit according to claim 1, characterized in that: It also includes resistors R1 and R2. One end of resistor R1 is connected to the input signal V1, and the other end of resistor R1 is connected to the first input terminal of the floating high voltage comparator circuit and the drain of the high voltage PMOS transistor PDM5. One end of resistor R2 is connected to the input signal V2, and the other end of resistor R2 is connected to the second input terminal of the floating high voltage comparator circuit and the drain of the high voltage PMOS transistor PDM6.

7. A control method for a high-voltage power supply selection circuit according to any one of claims 1-6, characterized in that... Includes the following steps: PMOS transistors PM3-PM10, high-voltage PMOS transistor PDM7, high-voltage NMOS transistor NDM1, resistor R3, and current source I2 constitute a floating power supply generation circuit. PMOS transistors PM3-PM10 have the same width-to-length ratio. If the magnitude of the current from current source I2 is I, then in, It refers to the electron mobility of a transistor. VTH is the gate oxide capacitance per unit area, and VTH is the threshold voltage. The high-voltage NMOS transistor NDM1, resistor R3, and high-voltage PMOS transistor PDM7 form an enhancement-mode source follower structure, which enhances the current absorption capability of the floating low-voltage HVSS. When the floating low-voltage HVSS node needs to absorb a large current, the gate voltage of the high-voltage NMOS transistor NDM1 rises, turning on the high-voltage NMOS transistor NDM1 to assist the floating low-voltage HVSS node in absorbing current and prevent the floating low-voltage HVSS voltage from being raised. This high-voltage floating comparator circuit consists of NMOS transistors NM1-NM4, PMOS transistors PM1-PM2, and high-voltage PMOS transistors PDM1-PDM4. NMOS transistors NM1-NM4 have the same width-to-length ratio, as do PMOS transistors PM1-PM2 and high-voltage PMOS transistors PDM1-PDM4. Current source I1 provides current bias for high-voltage transistors PDM1 and PDM2. High-voltage PMOS transistors PDM1-PDM4 have the same gate voltage. When the input signal V1 is greater than the input signal V2, the high-voltage PMOS transistor PDM1... As the current of transistor 3 increases, the current of high-voltage PMOS transistor PDM4 decreases, and the current of high-voltage PMOS transistor PDM3 is greater than the current of high-voltage PMOS transistor PDM4. The current of NMOS transistor NM2 is equal to the current of high-voltage PMOS transistor PDM3. NMOS transistor NM3 copies the current of NMOS transistor NM2. Therefore, the current of NMOS transistor NM3 is greater than the current of high-voltage PMOS transistor PDM4. The gate voltage of NMOS transistor NM4 is pulled down, and the drain voltage of NMOS transistor NM4 is pulled up by PMOS transistor PM2, resulting in a logic output of 1. Similarly, when the input signal V1 is less than the input signal V2, the logic output is 0. Inverters INV1 to INV4 are inverters that float between the floating high voltage HVDD and the floating low voltage HVSS. After being driven by four inverters, the voltage of signal A is equal to the floating low voltage HVSS, and the voltage of signal B is equal to the floating high voltage HVDD. At this time, the high voltage PMOS transistor PDM5 is turned on, and HVDD = V1, thus realizing the high voltage selection function. When input signals V1 and V2 are powered on, assuming V1 > V2, the floating high voltage HVDD will rise with the input signal V1, but the voltage drop of the body diode will decrease. When the floating high voltage HVDD is established to the point where the subsequent basic module can work, the bias current is generated, the high voltage floating comparator circuit can work normally, the high voltage PMOS transistor PDM5 turns on, and the voltage drop of the body diode is reduced to the voltage drop of the power transistor's drive current multiplied by the internal resistance, so that HVDD = V1.

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