High-precision analog-domain gain error shaping analog-to-digital converter and implementation method thereof

Abstract

This invention discloses a high-precision analog-domain gain error shaping analog-to-digital converter (ADC) and its implementation method, relating to the field of integrated circuit design. The high-precision analog-domain gain error shaping ADC of this invention adopts a fully differential structure, comprising: a first-stage sub-ADC, a residual amplifier, and a second-stage sub-ADC connected sequentially. The first-stage sub-ADC is designed as a coarse-fine quantization architecture of an NS SAR ADC and a DAC. The coarse-quantized NS SAR ADC samples and quantizes the input signal to generate a first-stage digital code, which is then copied to the fine-quantized DAC. The fine-quantized DAC switches its DAC array based on the first-stage digital code, directly obtaining the shaped first-stage quantization noise to achieve gain error shaping. This invention eliminates the need to predict the first-stage quantization noise, solving the problems of truncation error and gain mismatch, and achieving a better gain error shaping effect.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design technology, specifically relating to a high-precision analog-domain gain error shaping analog-to-digital converter and its implementation method. Background Technology

[0002] Gain error shaping techniques can suppress in-band quantization noise leakage caused by gain error in pipelined SAR ADCs (Successive Approximation Register Analog-to-Digital Converters). By shaping the noise leakage out of the signal band, the dynamic performance of the ADC is effectively improved. Therefore, optimizing gain error shaping methods and improving the gain error shaping effect are of great significance to the design of pipelined SAR ADCs.

[0003] To address the gain error problem, the paper "A Pipeline SAR ADC With Second-Order Interstage Gain Error Shaping" first proposed a gain error shaping scheme, which uses a second-stage digital code to characterize the first-stage quantization noise. The method has two drawbacks: first, the finite number of bits in the second stage introduces truncation error; second, gain error affects the shaping effect. The paper "A 77.1-dB-SNDR 6.25-MHz-BW Pipeline SAR ADC With Enhanced Interstage Gain Error Shaping and Quantization Noise Shaping" proposes a digital error feedback technique to suppress in-band truncation error, but it does not completely eliminate it and does not solve the problem of interstage gain inaccuracy. The paper "A Second-Order NS Pipelined SAR ADC With Quantization-Prediction-Unrolled Gain Error Shaping and Fully Passive Integrator" uses digital codes from the SAR ADC to predict... This avoids the influence of gain error, but the problem of truncation error still exists.

[0004] In summary, all existing technologies are based on prediction in the digital domain. There is a problem with truncation error caused by finite-bit quantization. Additionally, the gain used for feedback before and after the residual amplifier is mismatched with the actual gain, resulting in a decrease in gain error shaping effectiveness. SUMMARY

[0005] In order to solve the above problems existing in the prior art, the application provides a high-precision analog domain gain error shaping analog-to-digital converter and an implementation method thereof. The technical problem to be solved by the application is solved through the following technical scheme:

[0006] The application provides a high-precision analog domain gain error shaping analog-to-digital converter, which adopts a fully differential structure and comprises a first-stage sub-analog-to-digital converter, a residual error amplifier and a second-stage sub-analog-to-digital converter connected in sequence, wherein,

[0007] The first-stage sub-analog-to-digital converter adopts a coarse-fine quantization architecture and comprises an NS SAR ADC and a DAC connected in sequence, wherein the quantization resolution of the NS SAR ADC is lower than that of the DAC, the NS SAR ADC samples and quantizes an input signal to obtain a first-stage digital code, and the DAC performs DAC array switching according to the first-stage digital code and the input signal to obtain a first-stage quantization noise after shaping, and a negative value of the first-stage quantization noise after shaping is taken as a residual error voltage of the first-stage sub-analog-to-digital converter.

[0008] The residual error amplifier is configured to amplify the residual error voltage to obtain an amplified residual error voltage.

[0009] The second-stage sub-analog-to-digital converter is configured to sample and quantize the amplified residual error voltage to obtain a second-stage digital code.

[0010] In an embodiment of the application, the quantization precision of the DAC is not lower than the quantization precision of the high-precision analog domain gain error shaping analog-to-digital converter.

[0011] In an embodiment of the application, the noise shaping circuit of the NS SAR ADC is a feedforward type, a feedback type or a feedforward-feedback hybrid type noise shaping circuit.

[0012] In an embodiment of the application, the transfer function of the NS SAR ADC is represented as:

[0013] ;

[0014] In the formula, is the first-stage digital code, is the input signal, is the noise transfer function of the NS SAR ADC, is the first-stage quantization noise.

[0015] In an embodiment of the application, the residual error voltage is represented as:

[0016] ,

[0017] wherein, is the first-stage quantization noise after shaping.

[0018] In an embodiment of the present application, the transfer function of the second-stage sub-ADC is represented as:

[0019] ;

[0020] wherein, is the second-stage digital code, is the amplified residue voltage, is the second-stage quantization noise, is the ideal gain of the residue amplifier, is the gain error.

[0021] In an embodiment of the present application, the transfer function of the high-precision analog-domain gain-error shaping ADC is represented as:

[0022] ;

[0023] wherein, is the output code of the high-precision analog-domain gain-error shaping ADC.

[0024] In an embodiment of the present application, the second-stage sub-ADC is a SAR ADC, a Sigma-Delta ADC, a VCO-based ADC or a MASH Sigma-Delta ADC.

[0025] The present application provides an implementation method of a high-precision analog-domain gain-error shaping ADC, which is applicable to the high-precision analog-domain gain-error shaping ADC of any of the above embodiments, and comprises:

[0026] sampling the input signal through the NS SAR ADC and the DAC in the first-stage sub-ADC, and quantizing the sampled signal through the NS SAR ADC to obtain a first-stage digital code;

[0027] copying the first-stage digital code to the DAC, and switching the DAC array according to the first-stage digital code and the input signal to generate an upper plate voltage, wherein the upper plate voltage is the residue voltage of the first-stage sub-ADC, and the value of the upper plate voltage is the negative value of the first-stage quantization noise after shaping;

[0028] amplifying the residue voltage through the residue amplifier to obtain an amplified residue voltage;

[0029] The second-stage sub-analog-to-digital converter is used for sampling and quantizing the amplified residual error voltage to obtain a second-stage digital code.

[0030] The first-stage digital code and the second-stage digital code are digitally encoded to obtain an output code of the high-precision analog-domain gain error shaping analog-to-digital converter.

[0031] Compared with the prior art, the high-precision analog-domain gain error shaping analog-to-digital converter has the following beneficial effects:

[0032] The high-precision analog-domain gain error shaping analog-to-digital converter of the present application is designed as a coarse-fine quantization architecture of a NS SAR ADC (Noise-Shaping Successive Approximation Register Analog-to-Digital Converter, a successive approximation register type analog-to-digital converter combined with noise shaping) and a DAC. The NS SAR ADC is used for sampling and quantizing an input signal to generate a first-stage digital code, and the first-stage digital code is copied to the DAC. The DAC is switched according to the first-stage digital code to directly obtain shaped first-stage quantization noise to realize gain error shaping. The present application does not need to predict the first-stage quantization noise , solves the problems of truncation error and gain mismatch, and realizes a better gain error shaping effect. The coarse-fine quantization architecture does not introduce additional errors, the errors and noise introduced by noise shaping can be corrected by redundant bits, and will not appear in the main signal path to affect the final quantization accuracy. At the same time, the noise shaping operation is realized in coarse quantization, which does not introduce additional time overhead and is suitable for high-speed high-precision applications.

[0033] The above description is only a summary of the technical solutions of the present application. In order to more clearly understand the technical means of the present application, the content of the specification can be implemented, and in order to make the above and other purposes, characteristics and advantages of the present application more obvious and easy to understand, the following preferred embodiments are described in detail below, and the accompanying drawings are described as follows. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 is a single-sided circuit structure diagram of a high-precision analog-domain gain error shaping analog-to-digital converter provided by an embodiment of the present application;

[0035] Figure 2 is a single-sided circuit structure diagram of a high-precision analog-domain gain error shaping analog-to-digital converter taking a pipeline-SAR ADC as an example;

[0036] Figure 3 is Figure 2 the overall circuit timing diagram of the analog-to-digital converter shown in

[0037] Figure 4 is a circuit structure diagram of a second-order EF NS SAR ADC provided by an embodiment of the present application;

[0038] Figure 5 is a signal flow diagram of a second-order EF NS SAR ADC provided by an embodiment of the present application;

[0039] Figure 6 is a working timing diagram of a simulation circuit provided by an embodiment of the present application;

[0040] Figure 7 is a comparison diagram of gain error shaping effects of the scheme provided by the present application and GES technology and two-stage pipeline-SAR ADC without GES technology. DETAILED DESCRIPTION

[0041] In order to further illustrate the technical means and effects taken by the present application to achieve the predetermined purposes, a high-precision analog domain gain error shaping analog-to-digital converter and an implementation method thereof according to the present application are described in detail below in combination with the accompanying drawings and specific embodiments.

[0042] The foregoing and other technical contents, features and effects of the present application can be clearly presented in the detailed description of the specific embodiments below in combination with the accompanying drawings. Through the description of the specific embodiments, the technical means and effects taken by the present application to achieve the predetermined purposes can be more deeply and specifically understood. However, the accompanying drawings are provided for reference and illustration only, and are not used to limit the technical scheme of the present application.

[0043] In a first aspect, an embodiment of the present application provides a high-precision analog domain gain error shaping analog-to-digital converter, please refer to Figure 1 , Figure 1 is a single-sided circuit structure diagram of a high-precision analog domain gain error shaping analog-to-digital converter provided by an embodiment of the present application. As shown in Figure 1 , the high-precision analog domain gain error shaping analog-to-digital converter of the embodiment of the present application adopts a fully differential structure, comprising: a first-stage sub-analog-to-digital converter, a residue error amplifier and a second-stage sub-analog-to-digital converter connected in sequence.

[0044] The first-stage sub-ADC adopts a coarse-fine quantization architecture, including a connected NS SAR ADC and a DAC, wherein the quantization resolution of the NS SAR ADC is lower than that of the DAC, the NS SAR ADC samples and quantizes an input signal to obtain a first-stage digital code, and the DAC performs DAC array switching according to the first-stage digital code and the input signal to obtain a first-stage quantization noise after shaping, and a negative value of the first-stage quantization noise after shaping is used as a residual voltage of the first-stage sub-ADC.

[0045] In the embodiment, the quantization accuracy of the DAC is not lower than that of the high-precision analog domain gain error shaping ADC. That is, the accuracy of the DAC at least reaches the overall accuracy of the high-precision analog domain gain error shaping ADC, so that the noise caused by the capacitor, such as sampling noise , is not allowed to affect the signal quality. is the Boltzmann constant, is the temperature, is the capacitor value. If the accuracy of the DAC is not high enough and does not reach the overall accuracy requirement of the high-precision analog domain gain error shaping ADC, subsequent quantization cannot reach the desired quantization accuracy. The larger the capacitor size is, the smaller the sampling noise is, and the higher the accuracy is.

[0046] Optionally, the noise shaping circuit of the NS SAR ADC is a feedforward type, a feedback type or a feedforward-feedback hybrid type noise shaping circuit.

[0047] It can be understood that the high-precision analog domain gain error shaping ADC of the embodiment further includes a sampling switch and an inter-stage amplification switch, the sampling switch is turned off and turned on according to a sampling clock signal to enable the first-stage sub-ADC to sample an input signal, and the inter-stage amplification switch is turned off and turned on according to an inter-stage amplification clock signal to enable the residual voltage amplifier to amplify the residual voltage.

[0048] The high-precision analog domain gain error shaping ADC of the embodiment designs the first-stage sub-ADC as a coarse-fine quantization architecture of the NS SAR ADC and the DAC, samples and quantizes an input signal through the coarse quantization NS SAR ADC to generate a first-stage digital code, and copies the first-stage digital code to the fine quantization DAC. The fine quantization DAC performs DAC array switching according to the first-stage digital code to directly obtain a first-stage quantization noise after shaping to realize gain error shaping. The present application no longer needs to predict the first-stage quantization noise , solve the problem of truncation error and gain mismatch, and achieve better gain error shaping effect. At the same time, the coarse-fine quantization architecture does not introduce additional error, and the error and noise introduced by noise shaping can be corrected by redundant bits and will not appear in the main signal path to affect the final quantization accuracy. At the same time, the noise shaping operation is realized in coarse quantization, which does not introduce additional time overhead and is suitable for high-speed high-precision applications.

[0049] It can be understood that if the first-stage sub-modular converter does not use the coarse-fine quantization structure, but only uses the fine quantization NS SAR ADC, the shaped first-stage quantization noise can also be directly generated on the plate of the fine quantization DAC However, the error introduced by the noise shaping operation will enter the main signal path, thereby reducing the final quantization accuracy.

[0050] In the present embodiment, the coarse-fine quantization architecture does not introduce additional error, and the error and noise introduced by noise shaping can be corrected by the specific formula derivation as follows:

[0051] The coarse quantization NS SAR ADC performs quantization operation on the input signal to obtain the first-stage digital code . Hereinafter all represent sampling thermal noise, all represent capacitor mismatch, the subscript "coarse" represents the noise in the quantization process of the coarse quantization NS SAR ADC, the subscript "fine" represents the noise in the code cutting process of the fine quantization DAC, and the subscript "2" represents the noise in the quantization of the second-stage sub-modular converter, is the noise transfer function, is the first-stage quantization noise, is the noise generated by the noise shaping operation of the coarse quantization NS SAR ADC. The transfer function can be expressed as

[0052]

[0053] The first-stage digital code is copied to the fine quantization DAC, and the fine quantization DAC cuts the code according to to obtain the residual voltage on the plate:

[0054]

[0055] The residual voltage enters the second-stage sub-modular converter for quantization after passing through the residual amplifier, and the second-stage digital code is obtained. The ideal gain of the residual amplifier is, and the transfer function can be expressed as:

[0056]

[0057] After the code is combined, the overall quantization result is , and the transfer function is represented as:

[0058]

[0059] As can be seen from the above formula, the noise of the coarse quantization stage of the high-precision analog domain gain error shaping analog-to-digital converter in the embodiment will not affect the accuracy of the final quantization result.

[0060] Optionally, the second-stage sub-analog-to-digital converter is an SAR ADC, a Sigma-Delta ADC, a VCO-based ADC, or a MASH Sigma-Delta ADC, etc. That is, the gain error shaping realized by the first-stage sub-analog-to-digital converter in the embodiment of the application can be applied to any form of multi-stage analog-to-digital converter, including but not limited to pipeline-SAR ADC, ZoomADC, SAR VCO, and MASH Sigma-Delta, etc. multi-stage ADC architecture.

[0061] Further, taking the ADC architecture of pipeline-SAR ADC as an example, the circuit working process of the high-precision analog domain gain error shaping analog-to-digital converter in the embodiment is described.

[0062] Please refer to Figure 2 , Figure 2 is a single-sided circuit structure diagram of the high-precision analog domain gain error shaping analog-to-digital converter taking the pipeline-SAR ADC as an example, as shown in Figure 2 , the circuit mainly includes a sampling switch, a coarse quantization NS SAR ADC in the first-stage sub-analog-to-digital converter, a fine quantization DAC in the first-stage sub-analog-to-digital converter, a residual error amplifier, and a second-stage SAR ADC as the second-stage sub-analog-to-digital converter. The ideal gain of the residual error amplifier is , but in the actual circuit, there is an error in the inter-stage gain, so the actual gain of the residual error amplifier is . is the first-stage digital code, is the second-stage digital code, is the digital code obtained by overall quantization using the high-precision analog domain gain error shaping analog-to-digital converter. is the input signal, is the input signal quantized by the second-stage SAR ADC, that is, the amplified residual error voltage output by the residual error amplifier.

[0063] Please refer to Figure 3 , Figure 3 is Figure 2The overall circuit timing diagram of the shown analog-to-digital converter, the working process of the high-precision analog domain gain error shaping analog-to-digital converter is as follows: when the sampling clock signal is high, the coarse quantization NS SAR ADC and the fine quantization DAC simultaneously sample the input signal . Then, the NS SAR ADC quantizes the sampling signal, and the transfer function of the NS SAR ADC is represented as:

[0064]

[0065] In the formula, is the first-stage digital code, is the input signal, is the noise transfer function of the NS SAR ADC, is the first-stage quantization noise.

[0066] After the coarse quantization NS SAR ADC completes quantization, the first-stage digital code obtained by quantization is copied to the fine quantization DAC, and the fine quantization DAC performs DAC array switching according to the first-stage digital code to generate the upper plate voltage represented as:

[0067]

[0068] In the formula, is the shaped first-stage quantization noise.

[0069] In the embodiment, the upper plate voltage is also the residue voltage of the first-stage sub-analog-to-digital converter.

[0070] After the DAC array switching is completed, the negative value of the shaped quantization noise, that is, can be obtained on the upper plate of the fine quantization DAC. When the inter-stage amplification clock signal is high, the residue voltage obtained by the first-stage sub-analog-to-digital converter is amplified by the residue amplifier to obtain the amplified residue voltage , and the second-stage SAR ADC samples the amplified residue voltage at the same time. At this time, the coarse quantization NS SAR ADC can perform noise shaping operation in parallel, take the information of the residue voltage and store it, so as to perform feedback in the next period, and the noise shaping operation does not introduce additional time overhead. When the second-stage SAR ADC starts to perform comparison quantization, the first-stage sub-analog-to-digital converter enters the sampling operation in the next period. The expression of the input signal of the second-stage SAR ADC, that is, the amplified residue voltage is: .

[0071] ​​The second-stage SAR ADC outputs the amplified residual voltage. Quantization yields a second-level digital code. Therefore, the transfer function of the second-stage sub-analog-to-digital converter is expressed as:

[0072] ;

[0073] In the formula, This is the second level of numeric code. This is the output signal of the residual amplifier. This is the second level of quantization noise. For the ideal gain of the residual amplifier, This represents the gain error.

[0074] Finally, the first-level numeric code Second-level digital code Digital encoding yields the output code of the high-precision analog-domain gain error shaping analog-to-digital converter. The encoding method is .

[0075] The transfer function of the high-precision analog-domain gain error shaping analog-to-digital converter can be obtained by simplification as follows:

[0076] .

[0077] The noise transfer function of the NS SAR ADC can be seen from the transfer function of the high-precision analog-domain gain error shaping analog-to-digital converter. Achieved control over quantization noise leakage The shaping process achieves the effect of gain error shaping, thereby improving quantization accuracy. In this embodiment, after the first-stage sub-analog-to-digital converter completes the coarse-fine quantization operation, the shaped first-stage quantization noise is obtained. The corresponding residual voltage The input residual amplifier passes the signal to the second-stage sub-analog-to-digital converter for quantization.

[0078] The core of this invention lies in proposing a first-level quantization noise after shaping. The generation method no longer requires prediction using digital codes. accomplish Instead, in the analog domain, through a coarse-fine quantization structure, the NS SAR ADC coarsely quantizes to obtain the result containing... Level 1 numeric code Then, the refined DAC uses the first-level digital code... The first-level quantization noise after array switching is obtained. This avoids the effects of truncation error and gain error.

[0079] Compared with the implementation mode of the traditional gain error shaping technology, the coarse-fine quantization architecture of the first-stage sub-ADC proposed by the application has stronger gain error suppression effect because the influence of the truncation error and the gain error is avoided; because the noise shaping operation does not introduce additional noise, error and time overhead, the circuit structure is simple, the hardware overhead is low, and the gain error shaping can be realized without affecting the whole ADC, which is an ideal architecture of the multi-mode (for example, oversampling / Nyquist) high-speed high-precision ADC.

[0080] Further, taking the second-order error feedback type NS SAR ADC, i.e., the second-order EF NS SAR ADC, as the coarse quantization NS SAR ADC in the first-stage sub-ADC as an example, the effect brought by the gain error shaping technology of the pipeline-SAR ADC shown in the application is introduced. Please refer to Figure 2 , Figure 4 , Figure 4 is the circuit structure diagram of the second-order EF NS SAR ADC provided by the embodiment of the application, as shown in Figure 4 , the second-order EF NS SAR ADC is formed by cascading two first-order EF loops, wherein, is an input signal, is connected to a reference voltage, is a common-mode voltage, generally 1 / 2 of the reference voltage, is connected to ground, is a positive output voltage of a unit gain buffer in the first loop, is a negative output voltage of the unit gain buffer in the first loop, is a positive output voltage of a unit gain buffer in the second loop, is a negative output voltage of the unit gain buffer in the second loop, is an integration capacitor in the first loop, is an integration capacitor in the second loop, is a feedback capacitor in the first loop, is a feedback capacitor in the second loop, is a sampling clock signal, is an inverted sampling clock signal, is an inter-stage amplification clock signal, is an integration clock signal, is a clock signal of a comparator in the second-order EF NS SAR ADC, is a clock signal of a comparator in the second-stage SAR ADC, is a feedback signal. The signal flow diagram of the second-order EF NS SAR ADC is shown in Figure 5 .

[0081] According to Mason formula, the transfer function of the second-order EF NS SAR ADC in z domain is expressed as:

[0082] ;

[0083] wherein, is the first-order digital code, is the input signal, is the transfer function of the loop filter, quantization noise, when , the second-order EF NS SAR ADC realizes standard second-order noise shaping.

[0084] Taking the first-order sub-modular converter's coarse quantization NS SAR ADC as a 6-bit second-order EF NS SAR ADC, the first-order sub-modular converter's fine quantization DAC as a 6-bit, the second-order sub-modular converter as an 8-bit SAR ADC, and the inter-stage redundancy as 3 bits as an example, the working timing of the simulation circuit is shown in Figure 6 . The working process of the simulation circuit is as follows: when the sampling clock signal is high, the first-order sub-modular converter's coarse quantization NS SAR ADC samples the input signal . Then, when the feedback signal is high, and feed back the information of the stored last-cycle residual voltage to and , and add it to the sampled input signal. Then, the quantization is performed on the feedback input signal, and when the clock signal of the comparator in the first-order sub-modular converter's NS SAR ADC is high, the sum of the last-cycle residual voltage and the sampling signal is quantized to generate a 6-bit first-order digital code . The 6-bit first-order digital code is copied to the fine quantization DAC synchronously. The DAC switches according to the first-order digital code to obtain the shaped first-order quantization noise, which is expressed as:

[0085] ;

[0086] When , the shaped first-order quantization noise is . After the quantization, the voltage before the comparator in the coarse quantization NS SAR ADC is . At this time, is high, and the information of the current-cycle residual voltage is stored in and The noise shaping is realized by feeding back the output of the first stage to the next cycle. Next, the inter-stage amplification clock signal is high, the residual amplifier amplifies the first stage quantization noise after shaping, and the second stage SAR ADC samples the amplified residual voltage. After sampling is completed, the comparator in the second stage SAR ADC quantizes. At this time, the coarse quantization NS SAR ADC of the first stage sub-ADC can sample in the next cycle.

[0087] Further, by changing the gain error of the residual amplifier for simulation, the SQNR (Signal to Quantization Noise Ratio) changes when the gain error increases from 0 to ±20% can be obtained to measure the effect of gain error shaping. Please refer to , Figure 7 , Figure 7 The figure is a comparison of the gain error shaping effects of the scheme of the present application and the GES technology and the two-stage pipeline-SAR ADC without GES technology. As shown in Figure 7 , When there is no gain error, i.e. , the SQNR of the three cases is the same, all 74.975 dB. The simulation results conform to the ADC transfer function formula, , so the quantization noise leakage term is not included in the output result, and therefore the SQNR of the three cases is consistent. When the absolute value increases, the SQNR of the two-stage pipeline-SAR ADC structure without using the GES technology decreases the most, the SQNR of the traditional GES technology decreases next, and the SQNR of the GES technology of the present application decreases very little. Taking , for example, the SQNR of the two-stage pipeline-SAR ADC structure without using the GES technology is 59.908 dB, which decreases by 15.067 dB compared to , the SQNR decreases by 10.01 dB when the traditional GES technology is used, which has a certain gain error shaping effect compared to the case without GES technology, but the effect is weak. When the improved GES technology of the present application is used, the SQNR decreases by only 1.289 dB. Compared to the GES technology without GES technology and the traditional GES technology, the GES technology of the present application has a better gain error shaping effect, and the SNDR decreases less and the quantization accuracy is higher under the same gain error. At the same time, the architecture of the present application is simpler than the circuit structure of the traditional GES technology, the circuit complexity is reduced, and the hardware overhead is reduced.

[0088] In a second aspect, the embodiments of the present application provide an implementation method of the high-precision analog domain gain error shaping ADC, which is suitable for the high-precision analog domain gain error shaping ADC provided in the first aspect and comprises the following steps.

[0089] The input signal is sampled by the NS SAR ADC and the DAC in the first-stage sub-ADC, and the first-stage digital code is obtained by quantizing the sampled signal by the NS SAR ADC;

[0090] The first-stage digital code is copied to the DAC, and the DAC performs DAC array switching according to the first-stage digital code and the input signal to generate an upper plate voltage, which is the residual voltage of the first-stage sub-ADC and has a value of the negative value of the first-stage quantization noise after shaping;

[0091] The residual voltage is amplified by the residual amplifier to obtain an amplified residual voltage;

[0092] The amplified residual voltage is sampled and quantized by the second-stage sub-ADC to obtain a second-stage digital code;

[0093] The first-stage digital code and the second-stage digital code are digitally encoded to obtain the output code of the high-precision analog domain gain error shaping ADC.

[0094] For the specific content and corresponding beneficial effects of the implementation method of the high-precision analog domain gain error shaping ADC, please refer to the related content of the high-precision analog domain gain error shaping ADC provided in the first aspect, which will not be repeated here.

[0095] It is to be understood that the terminology used herein such as first and second, and the like, is only intended to distinguish between one

[0096] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" and the like means that the specific features or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Also, the specific features or characteristics described can be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate different embodiments or examples described in the present specification.

[0097] The above is a further detailed description of the present application in conjunction with specific preferred embodiments, and it cannot be considered that the specific implementation of the present application is limited to these descriptions. For those skilled in the art, a number of simple deductions or replacements can be made without departing from the concept of the present application, which should be considered as falling within the scope of protection of the present application.

Claims

1. A high-precision analog-domain gain error shaping analog-to-digital converter, characterized in that, It adopts a fully differential structure, including: a first-stage sub-analog-to-digital converter, a residual amplifier, and a second-stage sub-analog-to-digital converter connected in sequence, wherein, The first-stage sub-analog-to-digital converter adopts a coarse-fine quantization architecture, including: a connected NS SAR ADC and a DAC, wherein the quantization resolution of the NS SAR ADC is lower than that of the DAC; the NS SAR ADC samples and quantizes the input signal to obtain a first-level digital code; the DAC switches the DAC array according to the first-level digital code and the input signal to obtain a shaped first-level quantization noise; the negative value of the shaped first-level quantization noise is used as the residual voltage of the first-stage sub-analog-to-digital converter. The residual voltage amplifier is used to amplify the residual voltage to obtain an amplified residual voltage. The second-stage sub-analog-to-digital converter is used to sample and quantize the amplified residual voltage to obtain the second-stage digital code.

2. The high-precision analog-domain gain error shaping analog-to-digital converter according to claim 1, characterized in that, The quantization accuracy of the DAC is no less than that of the high-precision analog-domain gain error shaping analog-to-digital converter.

3. The high-precision analog-domain gain error shaping analog-to-digital converter according to claim 1, characterized in that, The noise shaping circuit of the NS SAR ADC is a feedforward, feedback, or feedforward-feedback hybrid noise shaping circuit.

4. The high-precision analog-domain gain error shaping analog-to-digital converter according to claim 1, characterized in that, The transfer function of the NS SAR ADC is expressed as follows: ； In the formula, This is the first level of numeric code. For input signal, Let be the noise transfer function of the NS SAR ADC. This represents the first level of quantization noise.

5. The high-precision analog-domain gain error shaping analog-to-digital converter according to claim 4, characterized in that, The residual voltage is expressed as: ， In the formula, This represents the first level of quantization noise after shaping.

6. The high-precision analog-domain gain error shaping analog-to-digital converter according to claim 5, characterized in that, The transfer function of the second-stage sub-analog-to-digital converter is expressed as: ； In the formula, This is the second level of numeric code. This is the amplified residual voltage. This is the second level of quantization noise. For the ideal gain of the residual amplifier, This represents the gain error.

7. The high-precision analog-domain gain error shaping analog-to-digital converter according to claim 6, characterized in that, The transfer function of the high-precision analog-domain gain error shaping analog-to-digital converter is expressed as: ； In the formula, This is the output code of a high-precision analog-domain gain error shaping analog-to-digital converter.

8. The high-precision analog-domain gain error shaping analog-to-digital converter according to claim 1, characterized in that, The second-stage sub-analog-to-digital converter is a SAR ADC, Sigma-Delta ADC, VCO-based ADC, or MASH Sigma-Delta ADC.

9. A method for implementing a high-precision analog-domain gain error shaping analog-to-digital converter, characterized in that, The high-precision analog-domain gain error shaping analog-to-digital converter according to any one of claims 1-8 comprises: The input signal is sampled simultaneously by the NS SAR ADC and DAC in the first-stage sub-analog-to-digital converter, and the sampled signal is quantized by the NS SAR ADC to obtain the first-stage digital code. The first-level digital code is copied to the DAC. The DAC switches the DAC array according to the first-level digital code and the input signal to generate the upper plate voltage. The upper plate voltage is the residual voltage of the first-level sub-analog-to-digital converter, and its value is the negative value of the first-level quantization noise after shaping. The residual voltage is amplified by the residual amplifier to obtain the amplified residual voltage. The amplified residual voltage is sampled and quantized by the second-stage sub-analog-to-digital converter to obtain the second-stage digital code; The first-level digital code and the second-level digital code are digitally encoded to obtain the output code of the high-precision analog-domain gain error shaping analog-to-digital converter.

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