A method for manufacturing a tunneling field effect transistor and a tunneling field effect transistor

Abstract

The application provides a preparation method of a tunneling field effect transistor and the tunneling field effect transistor, and relates to the technical field of transistor preparation. The preparation method comprises the following steps: patterning and depositing a first low-dimensional semiconductor material film on a substrate; depositing a first hard mask film; spin-coating photoresist on the surface of the first hard mask film, removing the first hard mask film in a preset pattern area through exposure and development; depositing a second low-dimensional semiconductor material film and a second hard mask film, so that the second low-dimensional semiconductor material film outside the preset pattern area is covered by the second hard mask film and the first hard mask film to form a sandwich structure; and placing the device in a solution, only retaining the second low-dimensional semiconductor material film in the preset pattern area under the action of the solution and water bath ultrasonic waves, so as to obtain the tunneling field effect transistor. The above method can accurately control the appearance and size of the tunneling field effect transistor, ensure the pattern integrity and edge neatness, and improve the stability and repeatability of the electrical performance.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of transistor preparation, and particularly relate to a preparation method of a tunneling field effect transistor and the tunneling field effect transistor. BACKGROUND

[0002] Low-dimensional nanomaterials (such as carbon nanotubes, graphene, and transition metal chalcogenides) have great application potential in new semiconductor device technologies in the post-moore era due to their atomic thinness and excellent electronic properties. Two-dimensional heterostructures constructed by vertically stacking different layered materials have been widely used in various electronic and optoelectronic devices. Among them, heterostructure tunneling field effect transistors based on low-dimensional nanomaterials realize switching function by quantum tunneling effect, have lower power consumption and higher switching speed than traditional transistors, and have broad application prospects in the fields of computers, mobile terminals, and automotive electronics.

[0003] At present, the core of the preparation of low-dimensional material heterostructure tunneling field effect transistors lies in the preparation of overlapping hetero thin films, mainly relying on mechanical transfer method and vapor deposition method to construct overlapping structures. The mechanical transfer method forms a tunneling heterojunction by stacking different low-dimensional material thin films layer by layer; the vapor deposition method grows stacked thin films in situ on the substrate by physical or chemical vapor deposition means. At the same time, the existing low-dimensional material thin film patterning deposition mainly adopts etching and stripping two ways, the etching method realizes patterning by selectively removing specific areas, and the stripping method forms a pattern after exposing and developing a photoresist, then depositing a thin film and stripping.

[0004] However, the mechanical transfer method relies on the quality of the thin film morphology, has great randomness in preparation, and is easy to cause unstable electrical performance and poor repeatability of the device; the vapor deposition method is difficult to accurately control the morphology and size of the heterostructure. In terms of patterned deposition, the etching method will damage the first low-dimensional semiconductor material thin film when patterning the second low-dimensional semiconductor material; the stripping method is difficult to effectively tear due to the connection strength and toughness of the low-dimensional material thin film, and is easy to cause the thin film to wrinkle, curl or overlap, which cannot realize the required patterned preparation, and is difficult to ensure the pattern integrity and edge neatness. SUMMARY

[0005] To solve the above problems, the present application provides a preparation method of a tunneling field effect transistor and the tunneling field effect transistor, which can solve the technical problems of low pattern integrity, poor edge neatness, poor electrical performance stability, and poor repeatability of the tunneling field effect transistor.

[0006] To achieve the above object, the first aspect of the present application provides a preparation method of a tunneling field effect transistor, comprising: patterning and depositing a first low-dimensional semiconductor material film on a substrate; patterning and depositing a second low-dimensional semiconductor material film on the substrate, so that the second low-dimensional semiconductor material film partially overlaps the first low-dimensional semiconductor material film to form a heterostructure, wherein the patterning and depositing of the second low-dimensional semiconductor material film on the substrate comprises: completely depositing a first hard mask film on the substrate; spin-coating a photoresist on the surface of the first hard mask film, and removing the first hard mask film within a preset pattern region by exposure and development operations, while retaining the first hard mask film outside the preset pattern region; wherein the preset pattern region represents a region required for depositing the second low-dimensional semiconductor material film; completely depositing a second low-dimensional semiconductor material film on the substrate and performing annealing treatment; wherein the material of the second low-dimensional semiconductor material film is different from the material of the first low-dimensional semiconductor material film; completely depositing a second hard mask film on the second low-dimensional semiconductor material film, so that the second low-dimensional semiconductor material film outside the preset pattern region is covered by the second hard mask film and the first hard mask film to form a sandwich structure, thereby obtaining a first device; wherein the first hard mask film and the second hard mask film are amphoteric metal or oxide films that are easily dissolved in an acid or alkaline solution; placing the first device in an alkaline solution or an acidic solution, and performing auxiliary water bath ultrasonic treatment to remove the second hard mask film and the second low-dimensional semiconductor material film covered by the sandwich structure formed by the first hard mask film and the second hard mask film, while retaining the second low-dimensional semiconductor material film within the preset pattern region, thereby obtaining a second device; performing annealing treatment on the second device to obtain a tunneling field effect transistor.

[0007] In the above preparation method, after the patterning and deposition of the first low-dimensional semiconductor material film, the patterning and deposition of the second low-dimensional semiconductor material film are performed by a process combining the double-layer hard mask film and the acid or alkaline solution, thereby avoiding damage to the deposited first low-dimensional semiconductor material film caused by etching and problems such as film wrinkling, curling or overlapping caused by peeling. Since the sandwich structure formed by the double-layer hard mask film can peel off the second low-dimensional semiconductor material film outside the preset pattern region while retaining the second low-dimensional semiconductor material film within the preset pattern region. Therefore, the above preparation method can accurately control the morphology and size of the tunneling field effect transistor, ensure the integrity of the pattern and the neatness of the edge, and improve the stability and repeatability of the electrical performance of the tunneling field effect transistor.

[0008] In an implementation manner of the first aspect, the preparation method of the tunneling field effect transistor further comprises: preparing a source electrode and a drain electrode on the substrate, or preparing a source electrode and a drain electrode on the heterostructure formed by the first low-dimensional semiconductor material film and the second low-dimensional semiconductor material film; wherein the source electrode is in contact with the first low-dimensional semiconductor material film, and the drain electrode is in contact with the second low-dimensional semiconductor material film.

[0009] In the preparation method, the source electrode and the drain electrode are prepared on the substrate or the heterostructure, the source electrode is in contact with the first low-dimensional semiconductor material film, and the drain electrode is in contact with the second low-dimensional semiconductor material film, so that good contact is formed between each electrode and the corresponding low-dimensional semiconductor material film, and the electrical performance of the tunneling field effect transistor is improved.

[0010] In an implementation form of the first aspect, the substrate comprises silicon and silicon dioxide, and the silicon is heavily doped silicon; the heavily doped silicon is used as the gate electrode, and the silicon dioxide is used as the gate dielectric layer.

[0011] In an implementation form of the first aspect, the amphoteric metal comprises aluminum, zinc or titanium; and the oxide film comprises aluminum oxide, zinc oxide or titanium oxide.

[0012] In the preparation method, the amphoteric metal or the oxide film that is easily dissolved in an acidic or alkaline solution is used, so that the subsequent removal operation of the first hard mask film, the second hard mask film and the sandwich structure formed by the first hard mask film and the second hard mask film is facilitated, and the low-dimensional semiconductor material film that has been deposited is not damaged, and the preparation quality of the tunneling field effect transistor is improved.

[0013] In an implementation form of the first aspect, the deposition of the first hard mask film and the deposition of the second hard mask film comprise thermal evaporation, electron beam evaporation, magnetron sputtering, chemical vapor deposition, pulsed laser deposition or atomic layer deposition.

[0014] In the preparation method, a suitable deposition method can be selected according to specific requirements, so as to ensure the uniformity and compactness of the hard mask film, and provide a good basis for subsequent patterning and deposition of the second low-dimensional semiconductor material film.

[0015] In an implementation form of the first aspect, the pH value of the alkaline solution ranges from 8 to 11, and the pH value of the acidic solution ranges from 3 to 6.

[0016] In the preparation method, the alkaline solution or the acidic solution that meets the requirements can reduce damage to the first low-dimensional semiconductor material film that has been deposited and the second low-dimensional semiconductor material film in the preset pattern region when the second hard mask film and the sandwich structure formed by the first hard mask film and the second hard mask film are stripped, and the integrity and electrical performance of the edge of the tunneling field effect transistor are improved.

[0017] In an implementation form of the first aspect, the material of the first low-dimensional semiconductor material film and the material of the second low-dimensional semiconductor material film comprise: semiconducting single-walled carbon nanotubes, graphene nanoribbons, transition metal dichalcogenides, black phosphorus, and III-VI sulfides / selenides; and the material of the first low-dimensional semiconductor material film is different from the material of the second low-dimensional semiconductor material film.

[0018] In the preparation method, the material of the first low-dimensional semiconductor material film and the material of the second low-dimensional semiconductor material film can be selected according to actual needs. It should be understood that the material of the first low-dimensional semiconductor material film is different from the material of the second low-dimensional semiconductor material film. In this way, different types of heterostructures can be formed, so as to realize the preparation of the tunneling field effect transistor and improve the electrical performance of the tunneling field effect transistor. Moreover, the low-dimensional semiconductor material films of different materials have different energy band structures and electronic properties, and by selecting a suitable material combination, the preparation of a low-power tunneling field effect transistor can be realized.

[0019] In an implementation form of the first aspect, the thickness of the first hard mask film is 20 nm-50 nm; and the thickness of the second hard mask film is 20 nm-100 nm.

[0020] In the preparation method, the first hard mask film and the second hard mask film with suitable thicknesses are selected, so as to ensure the hardness and supportability of the sandwich structure formed by the first hard mask film and the second hard mask film on the second low-dimensional semiconductor material film, avoid the problems of incomplete and irregular peeling of the sandwich structure, and ensure the uniformity of the film formation of the second low-dimensional semiconductor material film.

[0021] In an implementation form of the first aspect, the power range of the water bath ultrasonic treatment is 50 W-100 W; and the time range of the water bath ultrasonic treatment is 10 s-100 s.

[0022] In the preparation method, in the process of peeling off the first hard mask film and the second hard mask film by using the alkaline solution or the acidic solution, the water bath ultrasonic treatment with a suitable power range and a suitable time range can accelerate the peeling speed of the second low-dimensional semiconductor material film outside the preset pattern area, and avoid damaging the first low-dimensional semiconductor material film that has been deposited in the peeling process, thereby improving the integrity of the tunneling field effect transistor and the stability of the electrical performance.

[0023] In a second aspect, the present application also provides a tunneling field effect transistor, which is prepared based on the preparation method of the tunneling field effect transistor according to the first aspect and any possible implementation manner thereof, and comprises: a substrate composed of silicon and silicon dioxide, wherein the silicon is heavily doped silicon, the heavily doped silicon is a gate electrode, and the silicon dioxide is a gate dielectric layer; a heterostructure composed of a first low-dimensional semiconductor material film and a second low-dimensional semiconductor material film partially overlapping; a source electrode and a drain electrode arranged on the substrate or on the heterostructure; the source electrode is in contact with the first low-dimensional semiconductor material film, and the drain electrode is in contact with the second low-dimensional semiconductor material film; and the material of the second low-dimensional semiconductor material film is different from that of the first low-dimensional semiconductor material film.

[0024] It can be understood that the beneficial effects achieved by the technical solution of the second aspect provided above can refer to the beneficial effects of the first aspect and any optional implementation manner thereof, which will not be described herein again.

[0025] According to the above technical solution, the present application provides a preparation method of a tunneling field effect transistor and the tunneling field effect transistor. The preparation method of the tunneling field effect transistor comprises: patterning and depositing a first low-dimensional semiconductor material film on a substrate; patterning and depositing a second low-dimensional semiconductor material film on the substrate, so that the second low-dimensional semiconductor material film partially overlaps with the first low-dimensional semiconductor material film to form a heterostructure, wherein patterning and depositing the second low-dimensional semiconductor material film on the substrate comprises: completely depositing a first hard mask film on the substrate; spin-coating photoresist on the surface of the first hard mask film, and removing the first hard mask film within a preset pattern area by exposure and development operations, while retaining the first hard mask film outside the preset pattern area; wherein the preset pattern area represents the area required for depositing the second low-dimensional semiconductor material film; completely depositing a second low-dimensional semiconductor material film on the substrate and performing annealing treatment; wherein the material of the second low-dimensional semiconductor material film is different from that of the first low-dimensional semiconductor material film; completely depositing a second hard mask film on the second low-dimensional semiconductor material film, so that the second low-dimensional semiconductor material film outside the preset pattern area is covered by the second hard mask film and the first hard mask film from both sides to form a sandwich structure, thereby obtaining a first device; wherein the first hard mask film and the second hard mask film are amphoteric metal or oxide films that are easily dissolved in an acid or alkaline solution; placing the first device in an alkaline solution or an acidic solution, and performing auxiliary water bath ultrasonic treatment to remove the second hard mask film and the second low-dimensional semiconductor material film covered by the sandwich structure formed by the first hard mask film and the second hard mask film, while retaining the second low-dimensional semiconductor material film within the preset pattern area, thereby obtaining a second device; and performing annealing treatment to obtain a tunneling field effect transistor.

[0026] In the above preparation method, after the patterned deposition of the first low-dimensional semiconductor material thin film, the patterned deposition of the second low-dimensional semiconductor material thin film is performed through the process of combining the double-layer hard mask thin film with the acid-base solution, so as to avoid the damage of the etching method to the deposited first low-dimensional semiconductor material thin film and the film folding, curling or overlapping problem caused by the peeling method. Since the interlayer structure formed by the double-layer hard mask thin film can peel off the second low-dimensional semiconductor material thin film outside the preset pattern area and retain the second low-dimensional semiconductor material thin film within the preset pattern area. Therefore, the above preparation method can accurately control the morphology and size of the tunneling field effect transistor, ensure the pattern integrity and edge neatness, and improve the stability and repeatability of the electrical performance of the tunneling field effect transistor. BRIEF DESCRIPTION OF DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the present application, the drawings needed in the embodiments will be briefly introduced below. Obviously, for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0028] Figure 1 A preparation method flow chart of a tunneling field effect transistor provided by the embodiment of the present application;

[0029] Figure 2 A flow chart of patterned deposition of a first low-dimensional semiconductor material thin film provided by the embodiment of the present application;

[0030] Figure 3 A flow chart of patterned deposition of a second low-dimensional semiconductor material thin film provided by the embodiment of the present application;

[0031] Figure 4 A flow chart of preparation of a source electrode and a drain electrode provided by the embodiment of the present application;

[0032] Figure 5 A schematic diagram of a tunneling field effect transistor structure provided by the embodiment of the present application;

[0033] Figure 6 Another schematic diagram of a tunneling field effect transistor structure provided by the embodiment of the present application.

[0034] Reference signs:

[0035] 1-silicon; 2-silicon dioxide; 3-source electrode; 4-drain electrode; 5-first low-dimensional semiconductor material thin film; 6-second low-dimensional semiconductor material thin film; 7-photolithography resist; 8-metal thin film; 9-first hard mask thin film; 10-second hard mask thin film. DETAILED DESCRIPTION

[0036] The embodiments will be described in detail below with reference to examples thereof as illustrated in the accompanying drawings. When the description below refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following embodiments are not meant to represent all implementations consistent with the present disclosure.

[0037] It should be noted that the brief description of the terms in the present application is only for the convenience of understanding the implementation described next, and is not intended to limit the implementation of the present application. Unless otherwise specified, these terms should be understood according to their ordinary and general meanings.

[0038] The terms "first", "second", "third" and the like in the specification and the above drawings are used to distinguish similar or similar objects or entities, and do not necessarily mean to limit the specific order or sequence, unless otherwise noted. It should be understood that the terms used in this way can be interchanged under appropriate circumstances.

[0039] For the convenience of understanding the scheme, the related terms are explained as follows:

[0040] Tunneling field effect transistor: a field effect transistor based on quantum tunneling effect, the working principle is that electrons pass through the barrier layer by tunneling effect, thereby realizing the switching function of the device.

[0041] Heterostructure: composed of a first low-dimensional semiconductor material film and a second low-dimensional semiconductor material film partially overlapping, which can improve the electrical performance of the tunneling field effect transistor.

[0042] Exposure and development: in the preparation process of the tunneling field effect transistor, exposure and development are used to remove the first hard mask film within the preset pattern area to provide a pattern template for subsequent deposition of the second low-dimensional semiconductor material film. By controlling the parameters of exposure and development, such as exposure time, developer concentration, etc., the accuracy of the pattern and the neatness of the edge can be ensured.

[0043] In the field of transistor preparation technology, low-dimensional nanomaterials (such as carbon nanotubes, graphene and transition metal chalcogenides, etc.) can be used as materials for preparing transistors due to their excellent electronic properties. The heterostructure tunneling field effect transistor based on low-dimensional nanomaterials can utilize quantum tunneling effect to realize switching function, which has lower power consumption and higher switching speed compared with traditional transistors.

[0044] The core of preparing a low-dimensional material heterostructure tunneling field effect transistor lies in the preparation of an overlapped hetero thin film. At present, the overlapped structure can be constructed by a mechanical transfer method and a vapor deposition method. The mechanical transfer method forms a tunneling heterojunction by stacking different low-dimensional material thin films layer by layer; the vapor deposition method in-situ grows the stacked thin films on a substrate by means of physical or chemical vapor deposition. However, the above two methods have certain defects: the mechanical transfer method has strong randomness in the preparation process, which easily leads to unstable electrical performance and poor repeatability of the device; the vapor deposition method is difficult to control the morphology and size of the heterostructure.

[0045] Meanwhile, the existing low-dimensional material thin film patterning deposition adopts two ways of etching and peeling. The etching method realizes patterning by selectively removing a specific area, and the peeling method forms a pattern after exposing and developing a photoresist, and then depositing a thin film and peeling. However, the etching method will damage the deposited first low-dimensional semiconductor material thin film 5 when patterning the second low-dimensional semiconductor material thin film 6; the peeling method is difficult to effectively tear due to the strength and toughness of the connection of the low-dimensional material thin film, and is easy to cause film wrinkles, curling or overlapping, which cannot meet the requirements of patterning preparation and cannot guarantee the pattern integrity and edge neatness.

[0046] To solve the above problems, the embodiment of the present application provides a preparation method of a tunneling field effect transistor, which can improve the pattern integrity, edge neatness, and stability and repeatability of the electrical performance of the tunneling field effect transistor.

[0047] Figure 1 A flow chart of a preparation method of a tunneling field effect transistor provided by the embodiment of the present application is shown in FIG. 1. Figure 1 As shown in FIG. 1, the preparation of the tunneling field effect transistor includes steps S1-S3.

[0048] Step S1: patterning and depositing a first low-dimensional semiconductor material thin film 5 on a substrate.

[0049] In some embodiments, the substrate includes silicon 1 and silicon dioxide 2, wherein the silicon 1 is heavily doped silicon. To improve the electrical performance of the prepared tunneling field effect transistor, the heavily doped silicon can be used as a gate electrode, and the silicon dioxide 2 can be used as a gate dielectric layer.

[0050] In some embodiments, the first low-dimensional semiconductor material thin film 5 needs to be prepared first, and the preparation method of the first low-dimensional semiconductor material thin film 5 includes a transfer method deposition, a solution spin coating deposition film forming or a solution immersion coating deposition film forming. The embodiment of the present application does not make specific limitation.

[0051] In some embodiments, the first low-dimensional semiconductor material film 5 can be patterned and deposited by etching. The etching method can achieve selective removal of specific areas by oxygen plasma, laser irradiation, high temperature treatment or chemical etching, so as to obtain a preset structure pattern of the first low-dimensional semiconductor material film 5. It should be understood that the etching method includes oxygen plasma etching, laser etching and chemical etching.

[0052] Figure 2 A flowchart for patterning and depositing the first low-dimensional semiconductor material film is provided for the embodiments of the present application. As shown in Figure 2 the first low-dimensional semiconductor material film 5 on the substrate includes steps S11-S16.

[0053] Step S11: providing a substrate composed of silicon 1 and silicon dioxide 2.

[0054] In some embodiments, a metal film 8 can be deposited on the substrate as the source electrode 3 and the drain electrode 4.

[0055] Step S12: completely depositing the first low-dimensional semiconductor material film 5 on the substrate composed of silicon 1 and silicon dioxide 2.

[0056] In some embodiments, the optional materials of the first low-dimensional semiconductor material film 5 include: semiconductor single-walled carbon nanotubes, graphene nanoribbons, transition metal dichalcogenides, black phosphorus and III-V sulfides / selenides. Among them, the semiconductor single-walled carbon nanotubes include mixed structure carbon nanotubes or single structure carbon nanotubes; the transition metal dichalcogenides include MoS2, WS2, WSe2, MoSe2, MoTe2.

[0057] It should be noted that in order to improve the bonding degree of the semiconductor material and the substrate, and optimize the contact between the electrodes and the semiconductor material in the tunneling field effect transistor after preparation, reduce the contact resistance, and thus improve the electrical performance of the tunneling field effect transistor, annealing treatment is needed after the first low-dimensional semiconductor material film 5 is deposited. The annealing treatment includes: placing the device after the first low-dimensional semiconductor material film 5 is completely deposited in a vacuum or inert gas protection environment, setting the temperature to 200-300°C, and processing for 10-120 minutes.

[0058] Step S13: uniformly spin-coating photoresist 7 on the first low-dimensional semiconductor material film 5 for subsequent formation of the required pattern of the first low-dimensional semiconductor material film 5.

[0059] Step S14: exposing the first low-dimensional semiconductor material film 5 according to the required pattern by using ultraviolet light or electron beam. After development, the photoresist 7 on the surface of the first low-dimensional semiconductor material film 5 forms the required pattern.

[0060] Step S15: etching away the first low-dimensional semiconductor material film 5 outside the area protected by the photoresist 7.

[0061] Step S16: immersing the device in a solution to remove the photoresist 7 covering the surface of the first low-dimensional semiconductor material film 5. The solution is a solution that can remove the photoresist 7, such as an acetone solution.

[0062] Step S2: patterning and depositing a second low-dimensional semiconductor material film 6 on the substrate, so that the second low-dimensional semiconductor material film 6 partially overlaps the first low-dimensional semiconductor material film 5, forming a heterostructure.

[0063] In some embodiments, to prepare a heterostructure composed of low-dimensional semiconductor material films of two different materials, it is necessary to pattern and deposit a second low-dimensional semiconductor material film 6 on the basis of patterning and depositing the first low-dimensional semiconductor material film 5. In order to avoid damaging the already patterned and deposited first low-dimensional semiconductor material film 5 when patterning and depositing the second low-dimensional semiconductor material film 6, etching cannot be used again. Therefore, a new preparation method is needed to pattern and deposit the second low-dimensional semiconductor material film 6.

[0064] Figure 3 A flowchart of patterning and depositing a second low-dimensional semiconductor material film according to an embodiment of the present application is shown in FIG. 3. As shown in FIG. 3, patterning and depositing the second low-dimensional semiconductor material film 6 includes steps S21-S27. Figure 3

[0065] Step S21: providing a device with a patterned and deposited first low-dimensional semiconductor material film 5.

[0066] In some embodiments, the device includes a substrate composed of silicon 1 and silicon dioxide 2, source and drain electrodes 3 and 4 deposited on the substrate by a metal film 8, and a first low-dimensional semiconductor material film 5 patterned and deposited by step S1.

[0067] Step S22: completely depositing a first hard mask film 9 on the substrate, and uniformly spin-coating a photoresist 7 on the first hard mask film 9.

[0068] In some embodiments, first, a layer of first hard mask film 9 is completely deposited on the substrate with the patterned and deposited first low-dimensional semiconductor material film 5 as a base, which is used for subsequent removal of the second low-dimensional semiconductor material film 6 outside the preset pattern area together with the second hard mask film 10.

[0069] ​It should be noted that, in order to ensure the hardness and supportability of the first hard mask film 9 and avoid the generation of non-uniform step structures, the deposition thickness of the first hard mask film 9 is set to 20 nm-50 nm.

[0070] Secondly, the photoresist 7 is uniformly spin-coated on the surface of the first hard mask film 9, so as to prepare for the subsequent exposure and development to form a preset pattern area required for depositing the second low-dimensional semiconductor material film 6.

[0071] Step S23: The first hard mask film 9 within the preset pattern area is removed by exposure and development, and the first hard mask film 9 outside the preset pattern area is reserved; wherein the preset pattern area represents the area required for depositing the second low-dimensional semiconductor material film 6.

[0072] For example, in order to obtain the preset pattern area of the patterned deposited second low-dimensional semiconductor material film 6 on the device, exposure is performed according to the preset pattern by means of ultraviolet light or an electron beam, and development is performed. It can be understood that, as shown in step S23, after the exposure and development, the area outside the preset pattern area of the patterned deposited second low-dimensional semiconductor material film 6 is covered by the first hard mask film 9. Figure 3

[0073] Step S24: The photoresist 7 covering the surface of the first hard mask film 9 is removed.

[0074] For example, the device after exposure and development is placed in an acetone solution to remove the photoresist 7.

[0075] Step S25: The second low-dimensional semiconductor material film 6 is completely deposited on the substrate, and annealing treatment is performed; wherein the material of the second low-dimensional semiconductor material film 6 is different from the material of the first low-dimensional semiconductor material film 5.

[0076] In some embodiments, in order to realize the preparation of the heterostructure, the material of the second low-dimensional semiconductor material film 6 should be different from the material of the first low-dimensional semiconductor material film 5.

[0077] For example, if the material of the first low-dimensional semiconductor material film 5 is MoS2, the material of the second low-dimensional semiconductor material film 6 can be WSe2 or other materials, which should be different from the material of the first low-dimensional semiconductor material film 5, and the present application embodiment does not make specific limitations.

[0078] ​First, a second low-dimensional semiconductor material film 6 is completely deposited on the device after step S24 is completed. Second, as in the patterning deposition of the first low-dimensional semiconductor material film 5 in step S1, in order to improve the bonding degree of the semiconductor material and the substrate, and optimize the contact between the electrode and the semiconductor material in the tunneling field effect transistor after preparation is completed, reduce the contact resistance, and thus improve the electrical performance of the tunneling field effect transistor, annealing treatment is needed after the second low-dimensional semiconductor material film 6 is deposited. The annealing treatment includes: placing the device after the second low-dimensional semiconductor material film 6 is completely deposited in a vacuum or inert gas protection environment, setting the temperature to 200-300°C, and processing for 10-120 minutes.

[0079] Step S26: A second hard mask film 10 is completely deposited on the second low-dimensional semiconductor material film 6, so that the second low-dimensional semiconductor material film 6 outside the preset pattern area is covered by the second hard mask film 10 and the first hard mask film 9 from both sides, forming a sandwich structure, and a first device is obtained.

[0080] In some embodiments, after the second low-dimensional semiconductor material film 6 is completely deposited, in order to realize the preparation of the heterostructure in which the first low-dimensional semiconductor material film 5 and the second low-dimensional semiconductor material film 6 partially overlap, the second low-dimensional semiconductor material film 6 needs to be removed outside the preset pattern area. Therefore, the second hard mask film 10 is completely deposited on the second low-dimensional semiconductor material film 6, so that the second hard mask film 10 forms a sandwich structure with the first hard mask film 9 originally outside the preset pattern area, and covers the upper and lower layers of the second low-dimensional semiconductor material film 6 outside the preset pattern area.

[0081] For example, the second hard mask film 10 is completely deposited on the second low-dimensional semiconductor material film 6, and the thickness of the second hard mask film 10 is set to 20-100 nm.

[0082] In some embodiments, in order to remove the sandwich structure and only keep the second low-dimensional semiconductor material film 6 inside the preset pattern area, an amphoteric metal or oxide film that is easily soluble in an acid or alkali solution is used as the first hard mask film 9 and the second hard mask film 10.

[0083] For example, an amphoteric metal such as aluminum, zinc, or titanium, or an oxide film such as aluminum oxide, zinc oxide, or titanium oxide is used as the first hard mask film 9 and the second hard mask film 10.

[0084] In some embodiments, the deposition of the first hard mask film 9 and the deposition of the second hard mask film 10 can be thermal evaporation, electron beam evaporation, magnetron sputtering, chemical vapor deposition, pulsed laser deposition, or atomic layer deposition, which is not specifically limited in the embodiments of the present application.

[0085] Step S27: The first device is placed in an alkaline solution or an acidic solution, and is subjected to auxiliary water bath ultrasonic treatment to remove the second hard mask film 10 and the second low-dimensional semiconductor material film 6 covered by the sandwich structure formed by the first hard mask film 9 and the second hard mask film 10, and to reserve the second low-dimensional semiconductor material film 6 within the preset pattern region.

[0086] In some embodiments, since the first hard mask film 9 and the second hard mask film 10 can be dissolved in an alkaline solution or an acidic solution, the first device after the deposition of the second hard mask film 10 in step S26 is immersed in an alkaline solution or an acidic solution, so that the sandwich structure formed by the first hard mask film 9 and the second hard mask film 10 and the second hard mask film 10 can be removed, and finally only the second low-dimensional semiconductor material film 6 within the preset pattern region is left. At the same time, in order to completely remove the sandwich structure, auxiliary water bath ultrasonic treatment can be performed to obtain the second device.

[0087] For example, the first device after the deposition of the second hard mask film 10 is immersed in a sodium hydroxide, potassium hydroxide or developing solution with a pH value ranging from 8 to 11, or a hydrochloric acid, sulfuric acid or nitric acid solution with a pH value ranging from 3 to 6. Auxiliary water bath ultrasonic treatment is performed. The power of the water bath ultrasonic treatment ranges from 50 W to 100 W, and the time ranges from 10 s to 100 s.

[0088] In this way, since the hard mask film has higher strength and toughness than the traditional photoresist film, and the upper and lower surfaces of the second low-dimensional semiconductor material film 6 outside the preset pattern region are covered by the sandwich structure formed by the second hard mask film 10 and the first hard mask film 9, the edge of the preset pattern region can be effectively torn and removed in the peeling process, while the edge wrinkles can be avoided, and the neatness of the edge of the preset pattern region is improved.

[0089] Step S3: Annealing treatment is performed on the second device to obtain a tunneling field effect transistor.

[0090] In some embodiments, after the preparation of the heterostructure with the first low-dimensional semiconductor material film 5 and the second low-dimensional semiconductor material film 6 partially overlapping each other is achieved through steps S1 and S2 to obtain the second device, in order to improve the electrical performance of the heterostructure, annealing treatment is performed on the second device to obtain the final tunneling field effect transistor.

[0091] For example, the second device is placed in a vacuum or an inert gas protection environment, the temperature is set to 200°C-300°C, and the annealing time is set to 30 min-120 min.

[0092] In some embodiments, in the process of preparing the tunneling field effect transistor, the source electrode 3 and the drain electrode 4 need to be prepared for the tunneling field effect transistor.

[0093] In an implementation, the metal film 8 can be deposited on the substrate as the source electrode 3 and the drain electrode 4 before the heterostructure composed of the first low-dimensional semiconductor material film 5 and the second low-dimensional semiconductor material film 6 is prepared.

[0094] Figure 4 A flowchart of preparing the source electrode and the drain electrode is provided for the embodiments of the present application.

[0095] As shown in Figure 4 , the process of preparing the source electrode 3 and the drain electrode 4 includes steps S41-S46.

[0096] Step S41: providing a substrate composed of silicon 1 and silicon dioxide 2.

[0097] In some embodiments, the substrate needs to be cleaned first to remove organic contamination, particles and ionic impurities on the surface of the substrate.

[0098] Step S42: uniformly spin-coating photoresist on the surface of the substrate.

[0099] For example, the photoresist 7 is uniformly spin-coated on the surface of the substrate composed of silicon 1 and silicon dioxide 2.

[0100] Step S43: forming an electrode pattern by exposure and development.

[0101] For example, as shown in step S43, Figure 4 , one electrode pattern is formed on the left side and the right side of the surface of the substrate.

[0102] Step S44: depositing a metal film.

[0103] In some embodiments, the way of depositing the metal film 8 includes thermal evaporation, electron beam evaporation or magnetron sputtering.

[0104] In some embodiments, the metal film 8 is a single-layer metal or a composite metal, wherein the single-layer metal includes Au, Pt, Pd or Ag; and the composite metal includes Ti / Au, Cr / Au or Ti / Pd. It should be noted that, in order to avoid that the metal film 8 is deposited too thick, resulting in too large internal stress of the metal or increasing the difficulty of peeling, if the single-layer metal is selected as the metal film 8, the thickness of the single-layer metal is set to be between 30 nm and 50 nm; if the composite metal is selected as the metal film 8, the thickness of the bottom metal (such as Ti or Cr) in the composite metal is set to be between 0.5 nm and 5 nm, and the thickness of the top metal (such as Au or Pd) in the composite metal is set to be between 30 nm and 50 nm.

[0105] For example, a composite metal Ti / Au is deposited as a metal thin film 8 on a substrate that has been exposed and developed by electron beam evaporation.

[0106] Step S45: Remove photoresist.

[0107] For example, the device after the metal thin film 8 is deposited in step S44 is immersed in a solvent for stripping, dissolving the photoresist 7 and removing the excess metal thin film 8 covering the photoresist 7. The solvent is one that can dissolve the photoresist 7, such as acetone.

[0108] Step S46: The source electrode and drain electrode are now fabricated.

[0109] At this point, the fabrication of the heterostructure tunneling field-effect transistor is complete. Figure 5 This is a schematic diagram of a tunneling field-effect transistor structure provided in an embodiment of this application.

[0110] like Figure 5 As shown, the tunneling field-effect transistor includes a substrate composed of silicon 1 and silicon dioxide 2, a source electrode 3 and a drain electrode 4 deposited on the substrate by a metal thin film 8, and a heterostructure formed by a patterned deposition of a first low-dimensional semiconductor material thin film 5 and a second low-dimensional semiconductor material thin film 6. The first low-dimensional semiconductor material thin film 5 is in contact with the source electrode 3, and the second low-dimensional semiconductor material thin film 6 is in contact with the drain electrode 4.

[0111] In another implementation, after the heterostructure composed of the first low-dimensional semiconductor material thin film 5 and the second low-dimensional semiconductor material thin film 6 is prepared, a metal thin film 8 can be deposited on the heterostructure formed by the first low-dimensional semiconductor material thin film 5 and the second low-dimensional semiconductor material thin film 6 to serve as the source electrode 3 and the drain electrode 4.

[0112] The following describes a complete process for fabricating a tunneling field-effect transistor by preparing a source electrode 3 and a drain electrode 4 after preparing a heterostructure composed of a first low-dimensional semiconductor material thin film 5 and a second low-dimensional semiconductor material thin film 6, including steps S101-S111.

[0113] Step S101: Clean the substrate composed of silicon 1 and silicon dioxide 2.

[0114] The silicon dioxide was ultrasonically cleaned sequentially with deionized water, acetone, and alcohol for 15 minutes each, and then dried with high-purity nitrogen. Silicon 1 was p-type heavily doped silicon, and silicon dioxide 2 had a thickness of 300 nm.

[0115] Step S102: Deposit the first low-dimensional semiconductor material thin film 5 using the solution immersion method.

[0116] After the substrate composed of silicon 1 and silicon dioxide 2 is pretreated in a polylysine aqueous solution for 15 min, it is immersed in a semiconductor carbon nanotube solution dispersed by a surfactant at a concentration of 3 μg / mL, and the immersion is continued at a temperature of 30°C for 30 min.

[0117] Step S103: annealing treatment is performed.

[0118] The substrate on which the first low-dimensional semiconductor material film 5 is deposited is placed in a vacuum annealing furnace and annealed at 300°C for 60 min.

[0119] Step S104: the first low-dimensional semiconductor material film 5 is subjected to a patterning treatment.

[0120] Photoresist 7 is spin-coated on the surface of the first low-dimensional semiconductor material film 5; by ultraviolet light exposure and development, a preset pattern region is formed. At this time, the photoresist 7 in the exposed region is removed, the first low-dimensional semiconductor material film 5 in the unexposed region is still covered by the photoresist 7, and the remaining region is exposed; the oxygen plasma etching process is used to remove the first low-dimensional semiconductor material film 5 in the exposed region. The etching conditions are: power 50 W, oxygen flow rate 50 sccm, working pressure 100 mTorr, and time 60 s.

[0121] Step S105: a 30 nm thick metal aluminum film is deposited on the surface of the patterned first low-dimensional semiconductor material film 5 by thermal evaporation; photoresist 7 is spin-coated on the surface of the metal aluminum film; by ultraviolet light exposure and development, a preset pattern region of the second low-dimensional semiconductor material film 6 is formed. The development process includes: developing for 60 s to remove the exposed photoresist; and developing for 50 s to etch the metal aluminum film in the exposed region; the device is immersed in an acetone solution for 5 min to remove the unexposed photoresist 7 in the remaining region.

[0122] Step S106: the second low-dimensional semiconductor material film 6 is deposited by spin coating.

[0123] A 0.1 mg / mL isopropyl alcohol dispersed MoS2 solution is selected to spin-coat the device obtained in step S105, and the spin-coating method is as follows: first spin-coating at 500 rpm for 5 s, and then spin-coating at 4000 rpm for 30 s, so as to realize the preparation of the second low-dimensional semiconductor material film 6.

[0124] Step S107: annealing treatment is performed.

[0125] The device obtained in step S106 is placed in a vacuum annealing furnace and annealed at 300°C for 60 min.

[0126] Step S108: A 30nm thick aluminum film is deposited again on the device surface obtained in step S107 using thermal evaporation. At this point, both the upper and lower surfaces of the second low-dimensional semiconductor material film 6, outside the preset pattern area, are covered with an aluminum film, forming a sandwich structure.

[0127] Step S109: Place the device obtained in step S108 in a beaker containing developing solution and place it in a 70W water bath ultrasonic tank. Process it using pulsed ultrasonic treatment for 60s, wherein the pulse start time is 3s and the interval time is 3s.

[0128] Step S110: Prepare the source electrode and drain electrode.

[0129] Photoresist 7 is spin-coated onto the surface of a heterostructure formed by a first low-dimensional semiconductor material thin film 5 and a second low-dimensional semiconductor material thin film 6, and then exposed and developed under ultraviolet light to form patterns of source electrode 3 and drain electrode 4. A Ti / Au composite metal thin film is deposited by thermal evaporation, wherein the thickness of Ti is 0.5 nm and the thickness of Au is 40 nm. The sample is placed in an acetone solution for peeling to remove excess metal film, leaving only the Ti / Au metal in the preset area, thereby completing the fabrication of transistor source electrode 3 and drain electrode 4.

[0130] Step S111: Place the device obtained in step 110 in a vacuum annealing furnace and anneal it at 300°C for 60 minutes.

[0131] This completes the fabrication of the heterostructure tunneling field-effect transistor. Figure 6 This is a schematic diagram of another tunneling field-effect transistor structure provided in an embodiment of this application.

[0132] like Figure 6 As shown, in the tunneling field-effect transistor prepared by the above method, the source electrode 3 and the drain electrode 4 are disposed on a heterostructure composed of a first low-dimensional semiconductor material thin film 5 and a second low-dimensional semiconductor material thin film 6 partially overlapping.

[0133] It should be understood that, in order to ensure good contact between each electrode and the corresponding low-dimensional semiconductor material film, thereby improving the electrical performance of the tunneling field-effect transistor, whether the metal film 8 is deposited before or after the heterostructure is fabricated, the source electrode 3 should be in contact with the first low-dimensional semiconductor material film 5, and the drain electrode 4 should be in contact with the second low-dimensional semiconductor material film 6.

[0134] The embodiment of the present application also provides a tunneling field effect transistor, which is manufactured based on the preparation method of the tunneling field effect transistor, and comprises: a substrate composed of silicon 1 and silicon dioxide 2, wherein the silicon 1 is heavily doped silicon, the heavily doped silicon is a gate electrode, and the silicon dioxide 2 is a gate dielectric layer; a heterostructure composed of a first low-dimensional semiconductor material film 5 and a second low-dimensional semiconductor material film 6 partially overlapping; a source electrode 3 and a drain electrode 4 arranged on the substrate or on the heterostructure; the source electrode 3 is in contact with the first low-dimensional semiconductor material film 5, and the drain electrode 4 is in contact with the second low-dimensional semiconductor material film 6; and the material of the second low-dimensional semiconductor material film 6 is different from that of the first low-dimensional semiconductor material film 5.

[0135] According to the above technical solution, the present application provides a preparation method of a tunneling field effect transistor and the tunneling field effect transistor. The preparation method of the tunneling field effect transistor comprises: patterning and depositing a first low-dimensional semiconductor material film 5 on a substrate; patterning and depositing a second low-dimensional semiconductor material film 6 on the substrate, so that the second low-dimensional semiconductor material film 6 partially overlaps with the first low-dimensional semiconductor material film 5 to form a heterostructure, and the patterning and depositing of the second low-dimensional semiconductor material film 6 on the substrate comprises: completely depositing a first hard mask film 9 on the substrate; spin-coating photoresist 7 on the surface of the first hard mask film 9, removing the first hard mask film 9 within a preset pattern area by exposure and development operations, and retaining the first hard mask film 9 outside the preset pattern area; wherein the preset pattern area represents a required area for depositing the second low-dimensional semiconductor material film 6; completely depositing the second low-dimensional semiconductor material film 6 on the substrate and performing annealing treatment; wherein the material of the second low-dimensional semiconductor material film 6 is different from that of the first low-dimensional semiconductor material film 5; completely depositing a second hard mask film 10 on the second low-dimensional semiconductor material film 6, so that the second low-dimensional semiconductor material film 6 outside the preset pattern area is covered by the second hard mask film 10 and the first hard mask film 9 from the top and bottom to form a sandwich structure, and a first device is obtained; wherein the first hard mask film 9 and the second hard mask film 10 are amphoteric metal or oxide films which are easily dissolved in acid or alkali solution; placing the first device in an alkaline solution or an acidic solution, performing auxiliary water bath ultrasonic treatment, removing the second hard mask film 10 and the second low-dimensional semiconductor material film 6 covered by the sandwich structure formed by the first hard mask film 9 and the second hard mask film 10, retaining the second low-dimensional semiconductor material film 6 within the preset pattern area, and obtaining a second device; and performing annealing treatment on the second device to obtain a tunneling field effect transistor.

[0136] In the preparation method, after the patterning deposition of the first low-dimensional semiconductor material film 5, the patterning deposition of the second low-dimensional semiconductor material film 6 is performed through the process of combining the double-layer hard mask film with an acid or alkali solution, so as to avoid the damage of the etching method to the deposited first low-dimensional semiconductor material film 5 and the film folding, curling or overlapping problem caused by the peeling method. The interlayer structure formed by the double-layer hard mask film can peel off the second low-dimensional semiconductor material film 6 outside the preset pattern area and retain the second low-dimensional semiconductor material film 6 within the preset pattern area. Therefore, the above preparation method can accurately control the morphology and size of the tunneling field effect transistor, ensure the pattern integrity and edge neatness, and improve the stability and repeatability of the electrical performance of the tunneling field effect transistor.

[0137] The similar parts among the embodiments provided in the present application can be referred to each other, the specific embodiments provided above are only a few examples under the general concept of the present application, and do not constitute the limitation of the protection scope of the present application. Any other embodiments extended according to the present application scheme without creative labor belong to the protection scope of the present application for those skilled in the art.

Claims

1. A method for manufacturing a tunneling field effect transistor, the method comprising: patterning a first low-dimensional semiconductor material film (5) on a substrate; patterning a second low-dimensional semiconductor material film (6) on the substrate, such that the second low-dimensional semiconductor material film (6) partially overlaps the first low-dimensional semiconductor material film (5), forming a heterostructure, the patterning a second low-dimensional semiconductor material film (6) on the substrate comprising: completely depositing a first hard mask film (9) on the substrate; spin-coating a photoresist (7) on the first hard mask film (9), removing the first hard mask film (9) within a preset pattern region by exposure and development, and retaining the first hard mask film (9) outside the preset pattern region; wherein the preset pattern region represents a region required for depositing the second low-dimensional semiconductor material film (6); completely depositing the second low-dimensional semiconductor material film (6) on the substrate, and performing annealing treatment; wherein the material of the second low-dimensional semiconductor material film (6) is different from the material of the first low-dimensional semiconductor material film (5); completely depositing a second hard mask film (10) on the second low-dimensional semiconductor material film (6), such that the second low-dimensional semiconductor material film (6) outside the preset pattern region is covered by the second hard mask film (10) and the first hard mask film (9) from both sides, forming a sandwich structure, to obtain a first device; wherein the first hard mask film (9) and the second hard mask film (10) are amphoteric metal or oxide films which are easily dissolved in an acid or alkaline solution; placing the first device in an alkaline solution or an acidic solution, and performing auxiliary water bath ultrasonic treatment, to remove the second hard mask film (10), and the second low-dimensional semiconductor material film (6) covered by the sandwich structure formed by the first hard mask film (9) and the second hard mask film (10), and to retain the second low-dimensional semiconductor material film (6) within the preset pattern region, to obtain a second device; performing annealing treatment on the second device, to obtain a tunneling field effect transistor.

2. The method of claim 1, wherein the method further comprises: The method further comprises: depositing a metal film (8) on the substrate as a source electrode (3) and a drain electrode (4), or depositing the metal film (8) on the heterostructure formed by the first low-dimensional semiconductor material film (5) and the second low-dimensional semiconductor material film (6) as the source electrode (3) and the drain electrode (4); wherein the source electrode (3) is in contact with the first low-dimensional semiconductor material film (5), and the drain electrode (4) is in contact with the second low-dimensional semiconductor material film (6).

3. The method for manufacturing a tunneling field effect transistor according to claim 2, wherein: the substrate comprises silicon (1) and silicon dioxide (2), and the silicon (1) is heavily doped silicon; the heavily doped silicon is used as a gate electrode, and the silicon dioxide (2) is used as a gate dielectric layer.

4. The method for manufacturing a tunneling field effect transistor according to claim 2, wherein: The amphoteric metal comprises aluminum, zinc or titanium; The oxide film comprises aluminum oxide, zinc oxide or titanium oxide.

5. The method for fabricating a tunneling field-effect transistor according to claim 2, characterized in that, The manner of depositing the first hard mask film (9) and the manner of depositing the second hard mask film (10) comprise: thermal evaporation, electron beam evaporation, magnetron sputtering, chemical vapor deposition, pulsed laser deposition or atomic layer deposition.

6. The method of claim 2, wherein the pH of the alkaline solution is in the range of 8-11. The pH of the acidic solution is in the range of 3-6. The material of the first low-dimensional semiconductor material film (5) and the material of the second low-dimensional semiconductor material film (6) comprise:

7. The method for fabricating a tunneling field-effect transistor according to claim 2, characterized in that, semiconductor single-walled carbon nanotubes, graphene nanoribbons, transition metal dichalcogenides, black phosphorus and III-VI sulfides / selenides; The material of the first low-dimensional semiconductor material film (5) is different from the material of the second low-dimensional semiconductor material film (6).

8. The method of claim 2, wherein the thickness of the first hard mask film (9) is in the range of 20-50 nm. The thickness of the second hard mask film (10) is in the range of 20-100 nm.

9. The method of claim 2, wherein the power of the water bath ultrasonic treatment is in the range of 50-100 W. The time of the water bath ultrasonic treatment is in the range of 10-100 s. comprise: a substrate composed of silicon (1) and silicon dioxide (2), wherein the silicon (1) is heavily doped silicon, the heavily doped silicon is a gate electrode, and the silicon dioxide (2) is a gate dielectric layer; a heterostructure composed of the first low-dimensional semiconductor material film (5) and the second low-dimensional semiconductor material film (6) partially overlapping; 10. A tunneling field effect transistor fabricated based on the method of fabricating a tunneling field effect transistor according to any one of claims 1-9, characterized in that, a source electrode (3) and a drain electrode (4) disposed on the substrate or on the heterostructure; the source electrode (3) is in contact with the first low-dimensional semiconductor material film (5), and the drain electrode (4) is in contact with the second low-dimensional semiconductor material film (6); wherein the material of the second low-dimensional semiconductor material film (6) is different from the material of the first low-dimensional semiconductor material film (5). ​ ​ ​

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