An anti-radiation SiC MOSFET device and a manufacturing method thereof

Abstract

The application relates to an anti-radiation SiC MOSFET device and a manufacturing method thereof. A gate region of the anti-radiation SiC MOSFET device comprises: a gate dielectric layer located on a surface of a first-conductivity-type drift region; an electron-rich defect gate oxide layer located on a surface of the gate dielectric layer; and a gate electrode located on a surface of the electron-rich defect gate oxide layer. The electron-rich defect gate oxide layer contains a large number of electron defects, and can capture electrons excited by high-energy space rays to form negative electron defect charges when the anti-radiation SiC MOSFET device is subjected to ionizing total dose radiation effects. That is, the positive trap charge accumulation generated at the SiC / SiO2 interface can be balanced, and the threshold voltage V TH of the anti-radiation SiC MOSFET device can be prevented from negatively drifting, so that the anti-total dose effect capability is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and more particularly to an anti-radiation SiC MOSFET device and a manufacturing method thereof. BACKGROUND

[0002] MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is a kind of semiconductor device, which is widely used for switching purposes and amplification of electronic signals in electronic devices.

[0003] Early MOSFET device substrates are mainly based on silicon, but due to the limitations of material properties (such as narrow band gap), they have high limitations. With the rise of wide band gap materials, silicon carbide (SiC) and gallium nitride (GaN) are gradually commercialized, breaking through the performance limits of silicon-based materials and being more widely used.

[0004] Among them, SiC MOSFET is a high-performance power device based on wide band gap semiconductor materials, which has high voltage resistance (breakdown field strength up to 3 MV / cm), high temperature stability (> 200℃), and radiation resistance, which is very suitable for application requirements in space field.

[0005] A commonly used SiC MOSFET structure is shown in Figure 1 , which includes a substrate 1, a first conductive type drift region 2, a second conductive type body region 3, a second conductive type ohmic contact region 4, a first conductive type heavily doped region 5, a gate region 6, a field oxide passivation layer 7, and a metal electrode 8 for realizing electrical contact. Among them, the first conductive type drift region 2 is located in the epitaxial layer of the substrate 1, which is lightly doped; the first conductive type heavily doped region 5 can be used as the source region of the device, or as the drain region; the second conductive type ohmic contact region 4 is a second conductive type heavily doped region, which is used to provide a good ohmic contact for the first conductive type heavily doped region 5; the structure of the gate region 6 is shown in Figure 2 , which includes a gate dielectric layer 61 and a gate electrode 62, the gate dielectric layer 61 is generally a silicon dioxide layer, and the gate electrode 62 is generally polycrystalline silicon.

[0006] However, in the process of applying the existing SiC MOSFET device in the space field, the high-energy rays in space will produce the effect of total ionizing dose radiation, which will cause charge accumulation in the power device, resulting in degradation of parameters such as threshold voltage, on-resistance, and breakdown voltage. Especially for the gate dielectric layer (SiO2 layer) of SiC MOSFET, which undergoes long-term high-temperature growth, the oxidation quality is poor, the interface state density is high, the total dose effect is significant, and the positively charged trap charges captured at the SiC / SiO2 interface will cause the threshold voltage V THNegative drift, resulting in the device channel losing control ability, the device mis-opening, and finally the device failure. SUMMARY

[0007] Therefore, it is necessary to provide an anti-radiation SiC MOSFET device and a manufacturing method thereof to solve the above problems, reinforce the anti-radiation capability of the existing SiC MOSFET device, improve the anti-radiation capability, and avoid the mis-opening of the device.

[0008] To achieve the above object, the technical scheme adopted by the present application is as follows:

[0009] An anti-radiation SiC MOSFET device, a cell of the anti-radiation SiC MOSFET device comprising: a substrate and a first-conductivity-type drift region, a second-conductivity-type body region, a first-conductivity-type heavily doped region and a second-conductivity-type ohmic contact region arranged on the substrate, the drift region being provided with a gate region on the surface, the gate region comprising:

[0010] a gate dielectric layer on the surface of the first-conductivity-type drift region;

[0011] an electron-rich defect gate oxide layer on the surface of the gate dielectric layer;

[0012] a gate electrode on the surface of the electron-rich defect gate oxide layer.

[0013] In one embodiment, the electron-rich defect gate oxide layer is a silicon dioxide layer treated by hydrogen-containing plasma.

[0014] In one embodiment, the electron-rich defect gate oxide layer is a P-doped silicon dioxide layer.

[0015] In one embodiment, the electron-rich defect gate oxide layer is a hafnium oxide layer or a hafnium-zirconium oxide layer.

[0016] In one embodiment, the anti-radiation SiC MOSFET device further comprises:

[0017] a second-conductivity-type medium-doped channel region above the second-conductivity-type body region and on the inner side of the first-conductivity-type heavily doped region, and protruding 0.1-0.4 μm towards the center from the second-conductivity-type body region.

[0018] In one embodiment, the second-conductivity-type medium-doped channel region has a lateral width of 0.8-1.8 μm, a doping depth less than that of the first-conductivity-type heavily doped region, and a doping concentration of 1×10 17 cm -3 ~8×10 17cm -3 .

[0019] Another embodiment discloses a method for manufacturing an anti-radiation SiC MOSFET device, comprising: providing a substrate, forming a first-conductivity-type drift region, a second-conductivity-type body region, a first-conductivity-type heavily doped region and a second-conductivity-type ohmic contact region on the substrate, and further comprising:

[0020] forming a gate dielectric layer on the surface of the first-conductivity-type drift region;

[0021] forming an electron-rich defect gate oxide layer on the surface of the gate dielectric layer;

[0022] forming a gate on the surface of the electron-rich defect gate oxide layer.

[0023] In one embodiment, the process of forming an electron-rich defect gate oxide layer on the surface of the gate dielectric layer comprises:

[0024] using an LPCVD process, introducing tetraethyl orthosilicate and oxygen into a reaction chamber, and forming a silicon dioxide layer on the surface of the gate dielectric layer at 600-850°C;

[0025] using a hydrogen-containing plasma to perform surface treatment on the silicon dioxide layer to form an electron-rich defect gate oxide layer.

[0026] In one embodiment, the process of forming an electron-rich defect gate oxide layer on the surface of the gate dielectric layer comprises:

[0027] performing P-doping on the surface of the gate dielectric layer to form an electron-rich defect gate oxide layer.

[0028] In one embodiment, the process of forming an electron-rich defect gate oxide layer on the surface of the gate dielectric layer comprises:

[0029] using an atomic vapor deposition process to deposit a hafnium oxide layer or a hafnium-zirconium oxide layer on the surface of the gate dielectric layer to form an electron-rich defect gate oxide layer.

[0030] The anti-radiation SiC MOSFET device and the method for manufacturing the same disclosed in the present application introduce an electron-rich defect gate oxide layer between the gate dielectric layer and the gate. The electron-rich defect gate oxide layer contains a large number of electron-type defects, which can capture electrons excited by high-energy rays in space when the anti-radiation SiC MOSFET device is subjected to ionizing total dose radiation effects, and form negative electron defect charges. That is, the accumulation of positive trap charges generated at the SiC / SiO2 interface can be balanced, and the trend of negative drift of the threshold voltage V TH can be inhibited, thereby improving the anti-total dose effect capability.

[0031] In addition, the anti-radiation SiC MOSFET device disclosed in the present application adopts the design of middle-doped and long-channel second-conductivity-type channel region, which can make the threshold voltage V TH larger than that of conventional SiC MOSFET. After the same dose of radiation, the threshold voltage V TH can be maintained at 1V or above, so that the device can always be kept in the controllable range of channel and will not produce large leakage, thereby improving the total dose effect. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 Fig. 1 is a schematic diagram of a SiC MOSFET device structure in the prior art;

[0033] Figure 2 Fig. 3 is a schematic diagram of a gate region structure of a SiC MOSFET device in the prior art;

[0034] Figure 3 Fig. 6 is a schematic diagram of a gate region structure of an anti-radiation SiC MOSFET device provided in an embodiment of the present application;

[0035] Figure 4 Fig. 7 is a schematic diagram of a structure of an anti-radiation SiC MOSFET device provided in another embodiment of the present application;

[0036] Figure 5 Fig. 8 is a schematic diagram of another structure of an anti-radiation SiC MOSFET device provided in another embodiment of the present application;

[0037] Figure 6 Fig. 9 is a schematic diagram of a three-dimensional structure of another anti-radiation SiC MOSFET device provided in another embodiment of the present application;

[0038] Figure 7 Fig. 10 is a schematic diagram of a manufacturing step of an anti-radiation SiC MOSFET device provided in an embodiment of the present application;

[0039] Figure 8 Fig. 11 is a schematic diagram of another manufacturing step of an anti-radiation SiC MOSFET device provided in another embodiment of the present application.

[0040] In the figure, 1 is a substrate; 2 is a first-conductivity-type drift region; 3 is a second-conductivity-type body region; 4 is a second-conductivity-type ohmic contact region; 5 is a first-conductivity-type heavily doped region; 6 is a gate region; 7 is a field oxide passivation layer; 8 is a metal electrode; 9 is a second-conductivity-type middle-doped channel region; 61 is a gate dielectric layer; 62 is a gate electrode; and 63 is a gate oxide layer with electron-rich defects. DETAILED DESCRIPTION

[0041] For the purpose of facilitating the understanding of the present application, the present application will be described in more detail below. However, it should be understood that the present application can be realized in many different forms and is not limited to the embodiments or examples described herein. Rather, the purpose of the embodiments or examples is to make the disclosure of the present application more thorough and comprehensive.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments or examples only and is not intended to be limiting of the application. As used herein, the term "and / or", alone or in combination, means that there is at least one of the items in the combination and includes many combinations of the items, including individual items.

[0043] One embodiment of the present application discloses an anti-radiation SiC MOSFET device, the anti-radiation SiC MOSFET device cell comprising: a substrate and a first-conductivity-type drift region, a second-conductivity-type body region, a first-conductivity-type heavily doped region and a second-conductivity-type ohmic contact region disposed on the substrate, and a gate region disposed on the surface of the drift region. As shown in the figure, the gate region comprises: Figure 3 A gate dielectric layer 61 is disposed on the surface of the first-conductivity-type drift region 2.

[0044] A gate dielectric layer 61 is disposed on the surface of the first-conductivity-type drift region 2.

[0045] An electron-rich defect gate oxide layer 63 is disposed on the surface of the gate dielectric layer 61, wherein the electron-rich defect gate oxide layer 63 contains a large number of electron-type defects, and the electron-type defects can capture electrons to form negative electron defect charges.

[0046] A gate electrode 62 is disposed on the surface of the electron-rich defect gate oxide layer 63.

[0047] The anti-radiation SiC MOSFET device disclosed in the embodiments of the present application introduces an electron-rich defect gate oxide layer between the gate dielectric layer and the gate electrode. The electron-rich defect gate oxide layer contains a large number of electron-type defects, which can capture electrons excited by high-energy space rays to form negative electron defect charges when the anti-radiation SiC MOSFET device produces ionizing total dose radiation effects. That is, the accumulation of positive trap charges at the SiC / SiO2 interface can be balanced, and the threshold voltage V TH The negative drift trend is suppressed, thereby improving the total dose effect resistance.

[0048] Another embodiment of the present application discloses another anti-radiation SiC MOSFET device, as shown in the figure. Figure 4 The anti-radiation SiC MOSFET device cell comprises: a substrate 1, a first-conductivity-type drift region 2, a second-conductivity-type body region 3, a second-conductivity-type ohmic contact region 4, a first-conductivity-type heavily doped region 5, a gate dielectric layer 61, an electron-rich defect gate oxide layer 63, a gate 62, a field oxide passivation layer 7, and a metal electrode 8 for realizing electrical contact.

[0049] The substrate 1 is a SiC substrate with a first-conductivity-type epitaxial layer. The first-conductivity-type drift region 2 is a first-conductivity-type lightly doped region in the epitaxial layer of the substrate 1, with a specific doping concentration of 9×10 15 cm -3 , and a thickness of 11 μm.

[0050] In this embodiment, the first-conductivity-type heavily doped region 5 is a first-conductivity-type heavily doped source region with a doping concentration of 1×10 19 cm -3 . The second-conductivity-type ohmic contact region 4 is a second-conductivity-type heavily doped region on both sides of the surface of the first-conductivity-type drift region 2 and adjacent to the first-conductivity-type heavily doped region 5, for providing a good ohmic contact for the source region. The second-conductivity-type body region 3 is symmetrically distributed on the inner side of the second-conductivity-type ohmic contact region 4 and surrounds the first-conductivity-type heavily doped region 5.

[0051] In this embodiment, the gate dielectric layer 61 is a silicon dioxide layer, the electron-rich defect gate oxide layer 63 is a silicon dioxide layer treated by hydrogen-containing plasma, and the gate 62 is a polysilicon layer.

[0052] The hydrogen-containing plasma treatment process of the electron-rich defect gate oxide layer 63 is as follows:

[0053] A silicon dioxide layer is formed on the surface of the gate dielectric layer 61 by using an LPCVD process, hydrogen-containing plasma is used to bombard the interface, activate dangling bonds and inject hydrogen atoms, and finally hydrogen ions are doped into the SiO2 / poly-Si interface and the silicon oxide near the interface, so as to introduce electron-type defects at the interface and near the interface, and form the electron-rich defect gate oxide layer 63.

[0054] The electron-rich defect gate oxide layer 63 treated by the above process contains a large number of electron-type defects, which can capture electrons excited by high-energy space rays when the anti-radiation SiC MOSFET device is subjected to ionizing total dose radiation effects, and form negative electron defect charges. That is, the positive trap charge accumulation at the SiC / SiO2 interface can be balanced, and the threshold voltage VTH a negative shift trend, thereby improving the ability to resist total dose effects.

[0055] Another embodiment discloses another anti-radiation SiC MOSFET device, which is different from the above-mentioned embodiment in that the electron-rich defect gate oxide layer is a P-doped silicon dioxide layer. The process is as follows:

[0056] First, a silicon dioxide layer is grown on the surface of the first-conductivity-type drift region by a thermal oxidation method, and then the surface of the silicon dioxide layer is P-doped to obtain a phosphorus-silicon dioxide / poly-silicon interface and a silicon dioxide doping near the interface, thereby forming an electron-rich defect gate region. The P-doped region is an electron-rich defect gate oxide layer, and the region outside the P-doped silicon dioxide layer is a gate dielectric layer.

[0057] Another embodiment discloses another anti-radiation SiC MOSFET device, which is different from the above-mentioned embodiment in that the electron-rich defect gate oxide layer is a hafnium oxide layer or a hafnium-zirconium oxide layer. The hafnium oxide layer or the hafnium-zirconium oxide layer can be prepared by an atomic vapor deposition process.

[0058] As can be seen from the above embodiments, there are many methods for preparing the electron-rich defect gate oxide layer, but the basic idea of the present application is to introduce an electron-rich defect gate oxide layer containing a large number of electron-type defects between the gate dielectric layer and the gate. That is, the electron-rich defect gate oxide layer can capture electrons excited by high-energy space rays when the anti-radiation SiC MOSFET device produces ionizing total dose radiation effects, thereby forming a negative electron defect charge. That is, it can balance the positive trap charge accumulation at the SiC / SiO2 interface and suppress the threshold voltage V TH a negative shift trend, thereby improving the ability to resist total dose effects.

[0059] It should be noted that as long as the idea of introducing an electron-rich defect gate oxide layer containing a large number of electron-type defects between the gate dielectric layer and the gate is within the protection and disclosure range of the present application. In specific applications, the gate region structure disclosed in the present application can be applied to planar gate MOSFETs, trench gate MOSFETs, FinFETs and other types of MOS devices, and is also applicable to silicon-based substrates, silicon carbide substrates and gallium nitride substrates, and thus will not be described one by one here.

[0060] Another embodiment of the present application discloses another anti-radiation SiC MOSFET device, as shown in Figure 5 and Figure 6As shown, the anti-radiation SiC MOSFET device cell comprises: a substrate 1, a first-conductivity-type drift region 2, a second-conductivity-type body region 3, a second-conductivity-type ohmic contact region 4, a first-conductivity-type heavily doped region 5, a gate dielectric layer 61, an electron-rich defect gate oxide layer 63, a gate 62, a field oxide passivation layer 7, and a metal electrode 8 for realizing electrical contact.

[0061] The difference between the above embodiment and the anti-radiation SiC MOSFET device further comprises:

[0062] A second-conductivity-type medium-doped channel region 9 is located above the second-conductivity-type body region 3 and inside the first-conductivity-type heavily doped region 5, and protrudes from the second-conductivity-type body region 3 by a distance w of 0.1 μm to 0.4 μm in the central direction. Specifically, w can be 0.1 μm, 0.2 μm, 0.3 μm, or 0.4 μm.

[0063] In another embodiment, the second-conductivity-type medium-doped channel region 9 has a lateral width of 0.8 μm to 1.8 μm, a doping depth less than that of the first-conductivity-type heavily doped region 5, and a doping concentration of 1×10 17 cm -3 ~8×10 17 cm -3 . Specifically, the second-conductivity-type medium-doped channel region 9 has a lateral width of 0.8 μm and a doping concentration of 5×10 17 cm -3 .

[0064] The anti-radiation SiC MOSFET device disclosed in the embodiment adopts a second-conductivity-type medium-doped channel region design with medium doping and long channel, which can make the threshold voltage V TH of the device larger than that of a conventional SiC MOSFET. After the same dose of radiation, the threshold voltage V TH can be maintained at 1 V or more, so that the device always remains in a channel-controllable range and does not produce large leakage, thereby improving the total dose effect.

[0065] It should be noted that the heavy doping in each embodiment of the present application is a doping concentration greater than or equal to 1×10 19 cm -3 .

[0066] Another embodiment discloses a method for manufacturing an anti-radiation SiC MOSFET device, comprising: providing a substrate, forming a first-conductivity-type drift region, a second-conductivity-type body region, a first-conductivity-type heavily doped region, and a second-conductivity-type ohmic contact region on the substrate, and further comprising:

[0067] forming a gate dielectric layer on the surface of the first-conductivity-type drift region;

[0068] An electron-rich defect gate oxide layer is formed on the surface of the gate dielectric layer;

[0069] A gate is formed on the surface of the electron-rich defect gate oxide layer.

[0070] The electron-rich defect gate oxide layer contains a large number of electronic defects. When the radiation-resistant SiC MOSFET device generates ionizing total dose radiation, the electron-rich defect gate oxide layer traps electrons excited by high-energy space radiation, forming negative electronic defect charges. This balances the accumulation of positive trapped charges at the SiC / SiO2 interface, suppressing the threshold voltage V. TH The tendency of negative drift improves the ability to resist total dose effect.

[0071] Another embodiment discloses a different method for fabricating a radiation-resistant SiC MOSFET device, such as... Figure 7 As shown, it includes:

[0072] Prepare a silicon carbide substrate.

[0073] A first conductive epitaxial layer (e.g., ...) is grown on the surface of the silicon carbide substrate. Figure 7 (7a) The doping concentration of the epitaxial layer is 9 × 10⁻⁶. 15 cm -3 The thickness is 11μm.

[0074] Perform RCA cleaning to remove contaminants and particles from the wafer surface.

[0075] The first mask growth is performed with a mask thickness of 2 μm, followed by photolithography, and then implantation of the second conductivity type bulk region (e.g., Figure 7 (7b) The implantation type is the second conductivity type, and the doping concentration is 1×10⁻⁶. 18 cm -3 .

[0076] Cleaning, followed by a second mask growth process with a mask thickness of 1 μm, photolithography, and implantation of the first conductivity-type heavily doped region (e.g., Figure 7 (7c), implantation type is first conductivity type, doping concentration is 1×10 19 cm -3 .

[0077] Cleaning, third mask growth with a mask thickness of 2μm, photolithography, and implantation of the second conductive ohmic contact region (e.g.) Figure 7 (7d), implantation type is second conductivity type, doping concentration is 1×10 20 cm -3 .

[0078] Activation annealing is performed for all implants, with an activation anneal temperature of 1500-1850°C and an anneal time of 30-60 minutes.

[0079] After activation, the wafers are cleaned.

[0080] After cleaning, the wafers are subjected to thermal oxidation to grow gate dielectric layers.

[0081] An electron-rich defect gate oxide layer is formed on the surface of the gate dielectric layer. Specifically, an LPCVD process can be used to introduce tetraethyl orthosilicate and oxygen into the reaction chamber, and a silicon dioxide layer is formed on the surface of the gate dielectric layer at a temperature of 600-850°C. A hydrogen-containing plasma is used to treat the surface of the silicon dioxide layer to form an electron-rich defect gate oxide layer. Alternatively, the surface of the gate dielectric layer is doped with phosphorus to form an electron-rich defect gate oxide layer. Alternatively, an atomic vapor deposition process is used to deposit a hafnium oxide layer or hafnium-zirconium oxide layer on the surface of the gate dielectric layer to form an electron-rich defect gate oxide layer.

[0082] Polysilicon is deposited and subjected to POCL3 annealing to incorporate P elements in the polysilicon to form a gate (e.g. Figure 7 7e in FIG. 1).

[0083] A low-pressure chemical vapor deposition process is used to deposit a field oxide passivation layer for the gate and the first-conductivity-type heavily doped region.

[0084] Photolithography and etching are performed to open an orifice for an ohmic contact.

[0085] A magnetron sputtering process is used to sputter metal nickel, and annealing is performed in a rapid annealing device to form an ohmic contact for the source.

[0086] Photolithography is performed, and the field oxide passivation layer on the surface of the gate is etched away (e.g. Figure 7 7f in FIG. 1).

[0087] Photolithography is performed, and a front-side thick AL deposition is performed (e.g. Figure 7 7g in FIG. 1).

[0088] A magnetron sputtering process is used to sputter metal nickel on the back side, and laser annealing is performed, followed by a back-side thick metal TiNiAg deposition (e.g. Figure 8 7h in FIG. 1).

[0089] Another embodiment discloses a method for manufacturing an anti-radiation SiC MOSFET device, comprising:

[0090] A silicon carbide substrate is prepared.

[0091] A first-conductivity-type epitaxial layer is grown on the surface of the silicon carbide substrate, with a doping concentration of 9x1018-2x1020cm 15 cm -3The thickness is 11μm.

[0092] Perform RCA cleaning to remove contaminants and particles from the wafer surface.

[0093] The first mask growth was performed with a mask thickness of 2 μm, followed by photolithography. Then, second conductivity type bulk region implantation was performed with a doping concentration of 1 × 10⁻⁶. 18 cm -3 .

[0094] After cleaning, a second mask growth was performed with a mask thickness of 1 μm. Photolithography was then performed, followed by implantation of heavily doped regions of the first conductivity type at a doping concentration of 1 × 10⁻⁶. 19 cm -3 .

[0095] Cleaning, third mask growth (mask thickness 2 μm), photolithography, ohmic contact region implantation (second conductivity type, doping concentration 1 × 10⁻⁶) 20 cm -3 .

[0096] All injections were activated and annealed at a temperature of 1500℃ to 1850℃ for 30 to 60 minutes.

[0097] The activated wafers are then cleaned after sacrificial oxidation.

[0098] The cleaned wafer is then subjected to thermal oxidation to grow a gate dielectric layer. Specifically, the temperature is raised from room temperature to the target temperature (1000℃~1450℃, preferably 1200±5℃) at an initial heating rate of 30±2K / min. During the heating process, high-purity N2 (purity ≥99.999%, flow rate 3SLM) is introduced to avoid lattice defects caused by thermal stress. Oxidation is carried out in a dry oxygen atmosphere at 1000℃~1450℃ (preferably 1200℃), with a gas atmosphere of O2:N2=1:10. The oxidation time is between 10min and 50min, forming 25±2nm SiO2. The SiO2 growth rate is monitored using an in-situ ellipsometry. During the cooling process, high-purity argon (Ar) is introduced at a cooling rate of 40K / min. After the temperature drops to 800℃, a rapid cooling mode (>50K / min) is switched on. The wafer is then removed at 50℃, completing the fabrication of the gate dielectric layer.

[0099] An electron-rich defect gate oxide layer is formed on the surface of the gate dielectric layer. Specifically, a silicon dioxide layer is prepared by using an LPCVD process, TEOS (tetraethyl orthosilicate) and oxygen are introduced into a reaction chamber, and low pressure chemical vapor deposition (LPCVD) is performed at 600-850°C. The film density is optimized by a three-stage temperature-gas coordination strategy. The initial temperature is 800-850°C, and the O2 flow rate is 80-90%. The purpose is to fully decompose and promote dense nucleation. The temperature is reduced to 600-650°C in the middle stage, and the O2 flow rate is 50%. The purpose is to inhibit grain coarsening and reduce surface roughness. The final temperature is 800-850°C, and the O2 flow rate is 70%. The purpose is to stabilize the film density and oxidize the layer. The deposition time is 10-30 min, and the final thickness of the silicon dioxide layer is 15-25 nm. The cooling rate is 20K / min, and the wafer is taken out at 25°C. After the deposition of the SiO2 layer, the wafer is transferred to an RF plasma enhanced processing chamber (RF-PECVD). The chamber pressure is maintained at 5Torr, and the RF power is set to 100W. The interface is bombarded with H2:N2=1:2 hydrogen-containing plasma for 10-30s to activate the dangling bonds and inject hydrogen atoms. Then, the H2:N2 ratio is adjusted to 1:5 for 30-100s. Hydrogen ions are incorporated into the SiO2 / poly-Si interface and the SiO2 near the interface. Electron-type defects are introduced in the interface and the oxide near the interface to form an electron-rich defect gate oxide layer.

[0100] Polycrystalline silicon is deposited and then POCL3 annealing is performed to introduce P elements into the polycrystalline silicon to form a gate.

[0101] Low pressure chemical vapor deposition is used to deposit a field oxide passivation layer for the gate and the first conductivity type heavily doped region.

[0102] Photolithography and etching are performed to open an ohmic contact hole.

[0103] Metallic nickel is sputtered by using a magnetron sputtering method, and annealing is performed in a rapid annealing device to form an ohmic contact of a source electrode.

[0104] Photolithography is performed to etch away the field oxide passivation layer on the surface of the gate.

[0105] Photolithography is performed to deposit a thick AL on the front surface.

[0106] Metallic nickel is sputtered on the back surface by using a magnetron sputtering method, and laser annealing is performed. Then, a thick TiNiAg metal layer is deposited on the back surface.

[0107] Another embodiment discloses a method for manufacturing an anti-radiation SiC MOSFET device, comprising:

[0108] Prepare a silicon carbide substrate.

[0109] Growth of a first conductive type epitaxial layer on the surface of the silicon carbide substrate, the doping concentration of the epitaxial layer being 9×10 15 cm -3 , and the thickness being 11 μm.

[0110] RCA cleaning is performed to remove contaminants and particles on the surface of the wafer.

[0111] First mask growth is performed, the mask thickness being 2 μm, photolithography is performed, and second conductive type body region implantation is performed, the implantation type being the second conductive type, and the doping concentration being 1×10 18 cm -3 .

[0112] Cleaning is performed, second mask growth is performed, the mask thickness being 1 μm, photolithography is performed, and first conductive type heavily doped region implantation is performed, the implantation type being the first conductive type, and the doping concentration being 1×10 19 cm -3 .

[0113] Cleaning is performed, third mask growth is performed, the mask thickness being 2 μm, photolithography is performed, and ohmic contact region implantation is performed, the implantation type being the second conductive type, and the doping concentration being 1×10 20 cm -3 .

[0114] Activation annealing is performed on all implantations, the activation annealing temperature being 1500℃-1850℃, and the annealing time being 30 min-60 min.

[0115] The activated wafer is cleaned after sacrificial oxidation.

[0116] The cleaned wafer is subjected to thermal oxidation to grow a gate dielectric layer. Specifically, silicon oxide with a thickness of about 48 nm-52 nm is grown by thermal oxidation, the oxidation temperature being in the range of 1000℃-1450℃, the gas atmosphere being O2:N2=1:10, the oxidation time being 10 min-100 min, high-purity N2 being introduced during the temperature rising process, and the temperature rising rate being 30 K / min. High-purity argon Ar is introduced during the temperature falling process, the temperature falling rate being 40 K / min, the temperature is reduced to 800℃, and then a rapid cooling mode (>50 K / min) is switched to, the temperature is reduced to 50℃, and the wafer is taken out, thereby completing the preparation of the gate dielectric layer.

[0117] An electron-rich defect gate oxide layer is formed on the surface of the gate dielectric layer. Specifically, P doping is performed on the surface of the gate dielectric layer (silicon dioxide) by using POCL3, and the specific steps are as follows:

[0118] In a quartz diffusion furnace, a POCl3 / O2 / N2 ternary mixed gas (volume ratio 1:3:15) is introduced, and the wafer is treated at 750-850°C (preferably 800°C) for 80-300s, and at the end of the treatment, the wafer is cooled down in pure N2. A phosphorus-doped SiO2 / poly-Si interface and a SiO2 doped region near the interface are formed, i.e. a defect gate oxide layer with an electron-rich type is formed.

[0119] Polysilicon is deposited and then POCL3 annealing is performed to dope P elements in the polysilicon, thereby forming a gate.

[0120] A field oxide passivation layer is formed for the gate and the first conductive type heavily doped region by low pressure chemical vapor deposition.

[0121] Photoetching and etching are performed to open an ohmic contact hole.

[0122] Metallic nickel is sputtered by magnetron sputtering and annealing is performed in a rapid annealing device, thereby forming an ohmic contact of a source.

[0123] Photoetching is performed and the field oxide passivation layer on the surface of the gate is etched off.

[0124] Photoetching is performed and thick AL deposition is performed on the front surface.

[0125] Metallic nickel is sputtered on the back surface by magnetron sputtering and laser annealing is performed, and then thick metallic TiNiAg deposition is performed on the back surface.

[0126] Another embodiment discloses a method for manufacturing an anti-radiation SiC MOSFET device, comprising:

[0127] A silicon carbide substrate is prepared.

[0128] A first conductive type epitaxial layer is grown on the surface of the silicon carbide substrate, the doping concentration of the epitaxial layer is 9×10 15 cm -3 , and the thickness is 11 μm.

[0129] RCA cleaning is performed to remove contamination and particles on the surface of the wafer.

[0130] First mask growth is performed, the mask thickness is 2 μm, photoetching is performed, and second conductive type body region implantation is performed, the implantation type is the second conductive type, and the doping concentration is 1×10 18 cm -3 .

[0131] Cleaning is performed, second mask growth is performed, the mask thickness is 1 μm, photoetching is performed, and first conductive type heavily doped region implantation is performed, the implantation type is the first conductive type, and the doping concentration is 1×10 19 cm -3 .

[0132] Cleaning, third mask growth, mask thickness 2 μm, lithography, ohmic contact region implant, implant type second conductivity type, doping concentration 1 x 1019cm-3 20 cm -3 .

[0133] Activation annealing for all implants, activation annealing temperature 1500-1850 °C, annealing time 30-60 min.

[0134] Cleaning after sacrificial oxidation of the activated wafer.

[0135] After cleaning the wafer, thermal oxidation is performed to grow a gate dielectric layer. Specifically, a thickness of 48-52 nm of silicon oxide is grown by thermal oxidation, the oxidation temperature is in the range of 1000-1450 °C, the gas atmosphere is O2:N2=1:10, the oxidation time is between 10-50 min, N2O annealing is performed after oxidation, the gas atmosphere is a mixture of N2O and N2, the gas ratio can be 1:5, the annealing time is 30 min, and the preparation of the gate dielectric layer is completed.

[0136] An electron-rich defect gate oxide layer is formed on the surface of the gate dielectric layer. Specifically, atomic vapor deposition ALD (Atomic Layer Deposition) is performed on the wafer after thermal oxidation to deposit a layer of 10-20 nm of hafnium oxide HfO2 or HfZrO2, forming an electron-rich defect gate oxide layer.

[0137] Deposition of polysilicon and subsequent POCL3 annealing to incorporate P elements in the polysilicon to form a gate.

[0138] Low-pressure chemical vapor deposition is used to deposit a field oxide passivation layer for the gate and the first conductivity type heavily doped region.

[0139] Lithography, etching of ohmic contact openings.

[0140] Metallic nickel is sputtered using a magnetron sputtering and annealed in a rapid annealing device to form an ohmic contact for the source.

[0141] Lithography, etching of the field oxide passivation layer on the surface of the gate.

[0142] Lithography, front side thick AL deposition.

[0143] Metallic nickel is sputtered on the back side using a magnetron sputtering and laser annealing is performed, followed by deposition of a thick metal TiNiAg on the back side.

[0144] Another embodiment discloses a method for manufacturing an anti-radiation SiC MOSFET device, as shown in Figure 8 Fig. 1.

[0145] Prepare a silicon carbide substrate.

[0146] Growth of a first conductivity type epitaxial layer (e.g. 8a in Figure 8 15 cm -3 -9x1018cm-3, 11μm thick.

[0147] RCA clean to remove contamination and particles from the wafer surface.

[0148] First mask growth, 1μm thick, lithography, second conductivity type channel implant (e.g. 8b in Figure 8 17 cm -3 -4x1018cm-3.

[0149] Clean, second mask growth, 2μm thick, lithography, second conductivity type body implant (e.g. 8c in Figure 8 18 cm -3 -1x1018cm-3.

[0150] Clean, third mask growth, 1μm thick, lithography, first conductivity type heavily doped region implant (e.g. 8d in Figure 8 19 cm -3 -1x1018cm-3, deeper than the second conductivity type channel implant.

[0151] Clean, fourth mask growth, 2μm thick, lithography, second conductivity type ohmic contact implant (e.g. 8e in Figure 8 20 cm -3 -1x1018cm-3.

[0152] Activation anneal for all implants, 1500-1850C, 30-60min.

[0153] Sacrificial oxidation and clean of the activated wafer.

[0154] Thermal oxidation of the cleaned wafer to grow gate dielectric.

[0155] Formation of an electron rich defect gate oxide on the gate dielectric.

[0156] ​​​​​Depositing polysilicon and performing POCL3 annealing to dope P element in the polysilicon to form a gate (e.g. Figure 8 8f in FIG. 1).

[0157] A field oxide passivation layer of the gate and the first conductive type heavily doped region is deposited by low pressure chemical vapor deposition.

[0158] Photoetching and etching an ohmic contact opening.

[0159] Sputtering metal nickel by magnetron sputtering and annealing in a rapid annealing device to form an ohmic contact of the source.

[0160] Photoetching and etching the passivation layer above the gate on the surface (e.g. Figure 8 8g in FIG. 1).

[0161] Photoetching and performing front thick AL deposition (e.g. Figure 8 8h in FIG. 1).

[0162] Sputtering metal nickel on the back by magnetron sputtering and performing laser annealing, and then performing back thick metal TiNiAg deposition (e.g. ​ 8i in FIG. 1).

[0163] The anti-radiation SiC MOSFET device prepared by the method disclosed in the embodiment adopts a middle-doped and long-channel second conductive type middle-doped channel region design, which can make the threshold voltage V TH of the device larger than that of a conventional SiC MOSFET. After the same dose of irradiation, the threshold voltage V TH can be maintained at 1V or above, so that the device always remains in a controllable channel range and does not produce large leakage, thereby improving the total dose effect.

[0164] It should be noted that the first conductive type in the present application can be N type, and the corresponding second conductive type can be P type. Conversely, the first conductive type can be P type, and the corresponding second conductive type can be N type.

[0165] The technical features of the above-described embodiments can be combined in any manner. To make the description concise, all possible combinations of the technical features in the above-described embodiments are not described, but as long as the combinations of the technical features do not contradict, they should be considered as within the scope of the present application. The terms "first" and "second" are used only for distinction and do not limit the content of the present application.

[0166] The above embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent. It should be noted that for ordinary skilled persons in the art, without departing from the concept of the present application, several modifications and improvements can be made, which are within the scope of protection of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A radiation-hardened SiC MOSFET device, a cell of the radiation-hardened SiC MOSFET device comprising: A substrate and a first-conductivity-type drift region, a second-conductivity-type body region, a first-conductivity-type heavily doped region and a second-conductivity-type ohmic contact region disposed on the substrate, the drift region is disposed with a gate region on the surface, characterized in that the gate region comprises: a gate dielectric layer disposed on the surface of the first-conductivity-type drift region; an electron-rich defect gate oxide layer disposed on the surface of the gate dielectric layer; the electron-rich defect gate oxide layer can capture electrons excited by spatial high-energy rays to form negative electron defect charges to inhibit the tendency of threshold voltage negative shift; a gate electrode disposed on the surface of the electron-rich defect gate oxide layer.

2. The radiation tolerant SiC MOSFET device of claim 1, wherein, The electron-rich defect gate oxide layer is a silicon dioxide layer treated by hydrogen-containing plasma.

3. The radiation tolerant SiC MOSFET device of claim 1, wherein, The electron-rich defect gate oxide layer is a P-doped silicon dioxide layer.

4. The radiation tolerant SiC MOSFET device of claim 1, wherein, The electron-rich defect gate oxide layer is a hafnium oxide layer or a hafnium zirconium oxide layer.

5. The radiation tolerant SiC MOSFET device of any of claims 2-4, wherein, Further comprising: a second-conductivity-type medium-doped channel region disposed above the second-conductivity-type body region and on the inner side of the first-conductivity-type heavily doped region, and protruding 0.1 μm to 0.4 μm towards the center of the second-conductivity-type body region.

6. The radiation tolerant SiC MOSFET device of claim 5, wherein, The lateral width of the channel region of the second conductivity type is 0.8-1.8 μm, the doping depth is less than that of the first conductivity type heavily doped region, and the doping concentration is 1×10 17 cm -3 ~8×10 17 cm -3 .

7. A method of fabricating a radiation-hardened SiC MOSFET device, comprising: A substrate is provided, and a first-conductivity-type drift region, a second-conductivity-type body region, a first-conductivity-type heavily doped region and a second-conductivity-type ohmic contact region are formed on the substrate, characterized in that further comprising: forming a gate dielectric layer on the surface of the first-conductivity-type drift region; forming an electron-rich defect gate oxide layer on the surface of the gate dielectric layer; forming a gate electrode on the surface of the electron-rich defect gate oxide layer; the electron-rich defect gate oxide layer can capture electrons excited by spatial high-energy rays to form negative electron defect charges to inhibit the tendency of threshold voltage negative shift.

8. The method of fabricating a radiation-hardened SiC MOSFET device according to claim 7, wherein, The process of forming an electron-rich defect gate oxide layer on the surface of the gate dielectric layer comprises: using an LPCVD process, introducing tetraethyl orthosilicate and oxygen into the reaction chamber, and forming a silicon dioxide layer on the surface of the gate dielectric layer at 600°C to 850°C; using hydrogen-containing plasma to perform surface treatment on the silicon dioxide layer to form an electron-rich defect gate oxide layer.

9. The method of fabricating a radiation-hardened SiC MOSFET device of claim 7, wherein, The process of forming an electron-rich defect gate oxide layer on the surface of the gate dielectric layer comprises: P-doping the surface of the gate dielectric layer to form an electron-rich defect gate oxide layer.

10. The method of fabricating a radiation-hardened SiC MOSFET device of claim 7, wherein, The process of forming an electron-rich defect gate oxide layer on the surface of the gate dielectric layer comprises: using atomic vapor deposition process to deposit a hafnium oxide layer or a hafnium zirconium oxide layer on the surface of the gate dielectric layer to form an electron-rich defect gate oxide layer.

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