Light detection device

Abstract

According to the invention, the power consumption of the light detection device is reduced, and the light detection device can detect incidence of photons based on avalanche amplification. The light detection device includes: a photoelectric conversion section in which a first electrode is connected to a first potential, and which multiplies charges generated from photons; a resistance portion connected in series to the photoelectric conversion portion at a second electrode opposite the first electrode; a recharging unit that recharges the photoelectric conversion unit through the resistance unit; and a discharge portion in which a potential difference from a side opposite to the resistance portion and the recharging portion to which the resistance portion is connected is connected to a second potential lower than the first potential. The light detection device may include a detection section that detects a potential of the resistance section.

Description

Technical Field

[0001] The present technology relates to a light detection device, and more particularly to a light detection device capable of detecting incident photons based on avalanche amplification. Background Art

[0002] Some light detection devices output pulses in response to the incidence of photons. For example, a light receiving element including a photon response multiplier has been proposed, which is capable of multiplying the charge generated in response to the incidence of photons, and the light receiving element is configured to read out the output from the photon response multiplier via a resistor portion (for example, see patent document 1). At this time, avalanche amplification is used to multiply the charge generated in response to the incidence of photons. During avalanche amplification, a reverse bias of approximately tens of volts can be applied to the photon response multiplier, that is, a high voltage is applied to the photon response multiplier. Power consumption is reduced by electrically shielding the capacitance connected to the output of the multiplier by the above-mentioned resistor portion to reduce the charge consumed when current flows through the photon response multiplier.

[0003] Reference List

[0004] Patent Literature

[0005] Patent Document 1: WO 2021 / 172216 A Summary of the Invention

[0006] Problems to be solved by the present invention

[0007] In environments with a high frequency of incident photons, such as sunlight, multiple photon generation rates occur during the period between charge shielding by the resistor and the start of recharging. As a result, the shielded charge due to the high photon generation rate is discharged to the high-potential power supply, which can lead to increased power consumption.

[0008] The present technology has been made in view of such circumstances, and therefore an object of the present technology is to reduce power consumption of a light detection device capable of detecting incidence of photons based on avalanche amplification.

[0009] Solution to the problem

[0010] The present technology has been developed to address the above-mentioned issues, and in its first aspect, a light detecting device includes: a photoelectric converter having a first electrode connected to a first potential, the photoelectric converter configured to multiply charge generated from photons; a resistor connected in series to a second electrode opposite the first electrode of the photoelectric converter; a recharging section that recharges the photoelectric converter via the resistor; and a drain section connected to the resistor and a second potential, the second potential having a smaller potential difference than the first potential relative to the side of the charging section connected to the resistor. This has the effect of lowering the potential of a drain destination of at least some of the charge flowing out of the photoelectric converter.

[0011] Furthermore, in the first aspect, the resistance portion may have a higher resistance than the photoelectric conversion portion. This has the effect of suppressing the outflow of charge from the parasitic capacitance added to the photoelectric conversion portion to the photoelectric conversion portion.

[0012] Furthermore, in the first aspect, the charging portion can charge the photoelectric conversion portion based on the detection result of the potential of the resistance portion. Therefore, there is an effect that the charging time can be set according to the detection result of the detection portion.

[0013] Furthermore, in the first aspect, the charging portion may charge the photoelectric conversion portion based on a control signal received from the outside, thereby producing an effect of controlling the charging time from the outside.

[0014] Furthermore, in the first aspect, the control signal may be used as a periodic signal, thereby producing an effect of externally and periodically controlling the recharging period.

[0015] Furthermore, in the first aspect, the control signal may include a plurality of control signals having different cycles, and whether to discharge the charge from the discharge portion may be determined for each cycle. This has the effect of shortening the duration of charge discharge from the discharge portion according to the length of the recharge cycle.

[0016] Furthermore, in the first aspect, a detection unit for detecting the potential of the resistor unit may be further included. This provides an effect of controlling the discharge unit based on the detection result of the potential of the resistor unit.

[0017] Furthermore, in the first aspect, a readout circuit may be further included that reads out the result of photon detection by the photoelectric conversion unit from the input side of the detection unit. This brings about an effect of reading out the result of photon detection based on the input of the detection unit.

[0018] Furthermore, in the first aspect, a readout circuit may be further included that reads out the result of photon detection by the photoelectric conversion unit from the output side of the detection unit. This brings about an effect of reading out the result of photon detection based on the output of the detection unit.

[0019] Furthermore, in the first aspect, an amplitude limiting transistor connected between the detection unit and the discharge unit may be further included, the amplitude limiting transistor being configured to limit the output amplitude of the detection unit. This reduces the power required to drive the discharge unit.

[0020] In addition, in the first aspect, an initialization transistor connected in series to the output side of the detection section may be further included, the initialization transistor being configured to initialize the output of the detection section. This has the effect of stabilizing the charge discharge operation from the discharge section.

[0021] Furthermore, in the first aspect, an anti-punch-through transistor for preventing a punch-through current from flowing through the detection portion may be further included. This results in an effect of reducing power consumption during operation of the detection portion.

[0022] Furthermore, in the first aspect, a clamp transistor may be further included to prevent the potential of the resistor from being input to a readout circuit for reading out the result of photon detection. This allows the result of photon detection to be read out after the photon is detected by the photoelectric conversion unit.

[0023] Furthermore, in the first aspect, an anti-punch-through transistor is provided to prevent a breakdown current from flowing through the detection portion, an initialization transistor is connected in series to the output side of the detection portion, the initialization transistor is configured to initialize the output of the detection portion, and a clamping transistor is further provided to prevent the potential of the resistor portion from being input to a readout circuit for reading out the detection result of the photon. At least one of the anti-punch-through transistor, the initialization transistor, or the clamping transistor can be shared among multiple pixels. This reduces the number of transistors per pixel.

[0024] Furthermore, in the first aspect, the device may further include an anti-punch-through transistor for preventing a punch-through current from flowing through the detection portion, and an initialization transistor connected in series to the output side of the detection portion. The initialization transistor is configured to initialize the output of the detection portion, and at least one of the anti-punch-through transistor or the initialization transistor may include a driver for limiting input amplitude. This reduces the power required to drive the amplitude-limiting transistor or the initialization transistor.

[0025] Furthermore, in the first aspect, a resistor connected between the charging unit and the resistance unit may be further included. This has the effect of reducing the power required to drive the detection unit.

[0026] Furthermore, in the first aspect, the device may further include a first substrate and a second substrate. The first substrate may include at least one of a recharging unit, a readout circuit for reading out the result of photon detection, or a counter for counting based on the result read out by the readout circuit. The second substrate may include a photoelectric conversion unit, a resistor unit, a detection unit, and a discharge unit. The second substrate may be stacked on the first substrate. This allows transistors with different breakdown voltages to be formed on different substrates.

[0027] Furthermore, in the first aspect, the device may further include a first substrate having at least one of a recharge unit, a readout circuit for reading out the result of photon detection, or a counter for counting based on the result read out by the readout circuit; a second substrate having a resistor unit, a detection unit, and a discharge unit, the second substrate being stacked on the first substrate; and a third substrate having a photoelectric conversion unit, the third substrate being stacked on the second substrate. This increases the light-receiving area of ​​the photoelectric conversion unit while allowing transistors with different breakdown voltages to be formed on different substrates.

[0028] Furthermore, in the first aspect, a low breakdown voltage region in which low breakdown voltage transistors are formed and a high breakdown voltage region in which high breakdown voltage transistors are formed may be included, the high breakdown voltage regions being arranged adjacent to each other across a plurality of pixels, and the detection unit and the drain unit being formed in the high breakdown voltage region. This has the effect of reducing the area of ​​the isolation region for each pixel that isolates the detection unit and the drain unit.

[0029] Furthermore, in the first aspect, a readout circuit for reading out the result of photon detection may be further included, and the discharge unit may discharge at least a portion of the charge that can flow out to the photoelectric conversion unit to a second potential lower than the first potential based on the output of the readout circuit. This provides the effect of driving the discharge unit based on the output of the readout circuit.

[0030] Furthermore, in the first aspect, a latch circuit for latching the result of photon detection may be further included. This has the effect of stabilizing the result of photon detection.

[0031] Furthermore, in the first aspect, the latch circuit may include a switching transistor that connects the detection node where the photon is detected to a constant potential based on the result of detecting the photon. This has the effect of preventing potential fluctuations at the detection node where the photon is detected.

[0032] Furthermore, in the first aspect, the result of detecting the photon can be input to the gate of the switching transistor for retention, which results in the effect of retaining the detection result when the photon is detected.

[0033] Furthermore, in the first aspect, a blocking transistor may be further included that disconnects the switching transistor and the charging portion based on the potential of the detection node. This has the effect of preventing recharging during the photon detection standby period.

[0034] Furthermore, in the first aspect, the charging portion can charge the photoelectric conversion portion based on the potential of the detection node. This brings about an effect of controlling recharging based on the result of detecting photons.

[0035] Furthermore, in the first aspect, the device may further include: a first amplitude limiting transistor that limits the output amplitude of the photon detection result; and a reset transistor that resets the photon detection result. The reset transistor may be placed in a region where the amplitude is limited by the first amplitude limiting transistor, thereby operating at a lower voltage than the latch circuit. This results in a faster reset operation.

[0036] Furthermore, in the first aspect, a recharge control transistor for controlling recharging of the photoelectric conversion portion based on the result of photon detection may be further included. This has the effect of stopping recharging during photon detection.

[0037] Furthermore, in the first aspect, a second amplitude limiting transistor for limiting the input amplitude of the recharge section may be further included. The recharge section may be placed in a region where the amplitude is limited by the second amplitude limiting transistor, thereby operating at a lower voltage than the latch circuit. This results in a faster recharge operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 is a block diagram showing a configuration example of an imaging device to which the light detection device according to the first embodiment is applied.

[0039] Figure 2 is a block diagram showing a configuration example of a solid-state imaging device to which the light detection device according to the first embodiment is applied.

[0040] Figure 3 is a block diagram showing a configuration example of a pixel to which the light detection device according to the first embodiment is applied.

[0041] Figure 4 is a block diagram showing a first example of the optical pulse response unit according to the first embodiment.

[0042] Figure 5 is a timing chart showing the operation of the optical pulse response unit according to the first embodiment.

[0043] Figure 6 is a block diagram showing a second example of the optical pulse response unit according to the first embodiment.

[0044] Figure 7 is a block diagram showing a third example of the optical pulse response unit according to the first embodiment.

[0045] Figure 8 is a block diagram showing a configuration example of a pixel to which the light detection device according to the second embodiment is applied.

[0046] Figure 9 is a block diagram showing a configuration example of a solid-state imaging device to which the light detection device according to the third embodiment is applied.

[0047] Figure 10 is a block diagram showing a configuration example of an optical pulse response unit according to a third embodiment.

[0048] Figure 11 is a block diagram showing a first example of the optical pulse response unit according to the fourth embodiment.

[0049] Figure 12 is a block diagram showing a configuration example of an optical pulse response unit according to a fourth embodiment.

[0050] Figure 13is a block diagram showing a second example of the optical pulse response unit according to the fourth embodiment.

[0051] Figure 14 is a timing chart showing the operation of the optical pulse response unit according to the fourth embodiment.

[0052] Figure 15 is a timing chart showing a first example of the operation of the optical pulse response unit according to the fifth embodiment.

[0053] Figure 16 is a timing chart showing a second example of the operation of the optical pulse response unit according to the fifth embodiment.

[0054] Figure 17 is a block diagram showing a first example of a pixel to which the light detection device according to the sixth embodiment is applied.

[0055] Figure 18 is a block diagram showing a second example of a pixel to which the light detection device according to the sixth embodiment is applied.

[0056] Figure 19 is a block diagram showing a third example of a pixel to which the light detection device according to the sixth embodiment is applied.

[0057] Figure 20 is a block diagram showing a fourth example of a pixel to which the light detection device according to the sixth embodiment is applied.

[0058] Figure 21 is a block diagram showing a configuration example of an optical pulse response unit according to a seventh embodiment.

[0059] Figure 22 is a timing chart showing the operation of the optical pulse response unit according to the seventh embodiment.

[0060] Figure 23 is a block diagram showing a configuration example of an optical pulse response unit according to an eighth embodiment.

[0061] Figure 24 is a block diagram showing a configuration example of an optical pulse response unit according to a ninth embodiment.

[0062] Figure 25 is a block diagram showing a first example of a pixel to which the light detection device according to the tenth embodiment is applied.

[0063] Figure 26 is a block diagram showing a second example of a pixel to which the light detection device according to the tenth embodiment is applied.

[0064] Figure 27 is a block diagram showing a first example of the optical pulse response unit according to the eleventh embodiment.

[0065] Figure 28 is a block diagram showing a second example of the optical pulse response unit according to the eleventh embodiment.

[0066] Figure 29 is a block diagram showing a configuration example of an optical pulse response unit according to a twelfth embodiment.

[0067] Figure 30 is a block diagram showing a configuration example of an optical pulse response unit according to a thirteenth embodiment.

[0068] Figure 31 is a timing chart showing the operation of the optical pulse response unit according to the thirteenth embodiment.

[0069] Figure 32 is a block diagram showing a first example of an optical pulse response unit according to a fourteenth embodiment.

[0070] Figure 33 is a block diagram showing a second example of the optical pulse response unit according to the fourteenth embodiment.

[0071] Figure 34 is a block diagram showing a first example of a pixel to which the light detection device according to the fifteenth embodiment is applied.

[0072] Figure 35 is a block diagram showing a second example of a pixel to which the light detection device according to the fifteenth embodiment is applied.

[0073] Figure 36 is a block diagram showing a configuration example of an optical pulse response unit according to a sixteenth embodiment.

[0074] Figure 37 is a plan view showing a layout example of an optical pulse response unit according to a sixteenth embodiment.

[0075] Figure 38 17 is a block diagram showing a configuration example of a solid-state imaging device to which a light detection device according to the seventeenth embodiment is applied.

[0076] Figure 39 is a block diagram showing a configuration example of an optical pulse response unit according to an eighteenth embodiment.

[0077] Figure 40 is a perspective view showing an example of stacking of a pixel array unit according to a nineteenth embodiment.

[0078] Figure 41 is a perspective view showing an example of stacking of a pixel array unit according to a twentieth embodiment.

[0079] Figure 42 is a block diagram showing a configuration example of a distance measuring device according to a twenty-first embodiment.

[0080] Figure 43 is a block diagram showing a configuration example of an optical pulse response unit according to a twenty-second embodiment.

[0081] Figure 44 is a timing chart showing the operation of the optical pulse response unit according to the twenty-second embodiment.

[0082] Figure 45 is a timing chart showing a comparative example of the operation of the optical pulse response unit according to the twenty-second embodiment.

[0083] Figure 46 is a block diagram showing a configuration example of a pixel to which the light impulse response unit according to the twenty-third embodiment is applied.

[0084] Figure 47 is a block diagram showing a configuration example of an optical pulse response unit according to a twenty-fourth embodiment.

[0085] Figure 48 is a block diagram showing a configuration example of an optical pulse response unit according to a twenty-fifth embodiment.

[0086] Figure 49 is a block diagram showing a configuration example of a pixel to which a light impulse response unit according to a twenty-sixth embodiment is applied.

[0087] Figure 50 : is a block diagram showing a configuration example of a pixel to which the light impulse response unit according to the twenty-seventh embodiment is applied.

[0088] Figure 51 is a block diagram showing a configuration example of a pixel to which the light impulse response unit according to the twenty-eighth embodiment is applied.

[0089] Figure 52 is a block diagram showing a configuration example of a pixel to which the light impulse response unit according to the twenty-ninth embodiment is applied.

[0090] Figure 53 is a block diagram showing a schematic configuration example of a vehicle control system.

[0091] Figure 54 It is an explanatory diagram showing an example of the installation position of the imaging section. DETAILED DESCRIPTION

[0092] Modes for carrying out the present technology (hereinafter, referred to as embodiments) will be described below. The description will be given in the following order.

[0093] 1. First Embodiment (Example in which charge is discharged to a potential lower than the potential at which charge is discharged from the photoelectric conversion portion in the potential difference from the power supply potential of the charging portion based on the result of detecting the potential of the resistance portion connected in series to the photoelectric conversion portion)

[0094] 2. Second Embodiment (Example in which a pixel is equipped with a plurality of light impulse response units)

[0095] 3. Third Embodiment (Example in which, based on the result of detecting the potential of the connection point between the resistance section and the recharging section, charges are discharged to a potential whose potential difference from the power supply potential of the recharging section is smaller than the potential at which charges are discharged from the photoelectric conversion section, and the recharging section is controlled)

[0096] 4. Fourth Embodiment (Example in which, based on the result of detecting the potential of the connection point between the resistance section and the recharging section, charge is discharged to a potential lower than the potential at which charge is discharged from the photoelectric conversion section at a potential difference from the power supply potential of the recharging section, and the recharging section is controlled)

[0097] 5. Fifth Embodiment (Example of Externally Controlling Charging Member Based on Multiple Control Signals Having Different Cycles)

[0098] 6. Sixth Embodiment (Example of Reading Photon Detection Results Based on Detection of the Potential at the Connection Point Between the Resistance Section and the Recharge Section)

[0099] 7. Seventh Embodiment (Example in which an amplitude limiting transistor for limiting the driving potential of the discharge portion is provided)

[0100] 8. Eighth Embodiment (Example in which a resistor portion connected in series to a photoelectric conversion portion and a detection portion for detecting the potential of the resistor portion are isolated by a capacitor)

[0101] 9. Ninth Embodiment (Example of Discharging Charge from a Connection Point Between a Photoelectric Conversion Section and a Resistance Section Connected in Series Based on a Result of Detecting the Potential of a Resistance Section)

[0102] 10. Tenth Embodiment (Example of Discharging Charges to a Potential Lower than the Potential at Which Charges Are Discharged from the Photoelectric Conversion Portion Based on the Output of the Readout Circuit)

[0103] 11. Eleventh Embodiment (Example of Reading the Result of Photon Detection from the Output of a Detection Section Detecting the Potential of a Resistor Section Connected in Series with a Photoelectric Converter Section)

[0104] 12. Twelfth Embodiment (Example of Providing a Driver for Limiting the Input Amplitude of the Anti-Punch-Through Transistor and the Input Amplitude of the Initialization Transistor)

[0105] 13. Thirteenth Embodiment (Example in which a Resistor is Provided Between a Resistance Section Connected in Series to a Photoelectric Converter and a Clamp Transistor)

[0106] 14. Fourteenth Embodiment (Example in which a second substrate in which a photoelectric conversion portion, a resistance portion, a detection portion, and a discharge portion are formed is stacked on a first substrate in which a charging portion is formed)

[0107] 15. Fifteenth Embodiment (Example in which a second substrate in which a photoelectric conversion portion, a resistance portion, a detection portion, and a discharge portion are formed is stacked on a first substrate in which a recharging portion, a readout circuit, and a counter are formed)

[0108] 16. Sixteenth Embodiment (Example where High Breakdown Voltage Regions Forming High Breakdown Voltage Transistors Are Arranged Adjacent to Each Other Across Multiple Pixels)

[0109] 17. Seventeenth Embodiment (Example in which a counter output and the most significant bit (MSB) of the counter output can be output in a switchable manner)

[0110] 18. Eighteenth Embodiment (Example in which a resistor portion is connected to the anode side of a photoelectric conversion portion)

[0111] 19. Nineteenth Embodiment (Example in which the Light Receiving Array Unit is Provided on an Upper Chip, and the Circuit Array Unit is Provided on a Lower Chip)

[0112] 20. Twenty-fifth Embodiment (Example in which a light-receiving array unit in which pixels are arranged to be equipped with a plurality of light-receiving sections is provided on an upper chip, and a circuit array unit is provided on a lower chip)

[0113] 21. Embodiment 21 (Example in which a pixel equipped with a discharge portion that discharges charge to a potential smaller than the power supply potential of a charging portion than the potential at which charge is discharged from a photoelectric conversion portion is applied to a distance measuring device)

[0114] 22. Twenty-Second Embodiment (Example of Connecting a Detection Node for Photon Detection to Ground Potential Based on a Result of Photon Detection)

[0115] 23. Twenty-third Embodiment (Example of Connecting a Detection Node for Detecting Photons to a Power Supply Potential Based on a Result of Detecting Photons)

[0116] 24. Twenty-fourth Embodiment (Based on the result of detecting photons, an example in which the detection node for detecting photons is connected to the ground potential and recharging is stopped)

[0117] 25. Twenty-fifth Embodiment (Based on the result of detecting photons, an example in which the detection node for detecting photons is connected to the ground potential, and the readout circuit and the recharging section are disconnected)

[0118] 26. Twenty-sixth embodiment (Example in which the output amplitude as a result of detecting photons is limited so as to enable the reset transistor to operate at a low voltage)

[0119] 27. Twenty-seventh Embodiment (Example of Interrupting Recharging Based on Result of Photon Detection)

[0120] 28. Twenty-eighth Embodiment (Example in which the input amplitude of the charging member is limited to enable the charging member to operate at a low voltage)

[0121] 29. Twenty-ninth Embodiment (Example in which the output amplitude of the result of photon detection is limited so that the reset transistor can operate at a low voltage, and the input amplitude of the recharging unit is limited so that the recharging unit can operate at a low voltage)

[0122] 30. Application Examples of Mobile Entities

[0123] <1. First embodiment>

[0124] Figure 1 is a block diagram showing a configuration example of an imaging device according to the first embodiment.

[0125] In the drawing, the imaging device 100 includes an optical system 101, a solid-state imaging device 102, an imaging control unit 103, an image processing unit 104, a storage unit 105, a display unit 106, and an operation unit 107. The imaging control unit 103, the image processing unit 104, the storage unit 105, the display unit 106, and the operation unit 107 are interconnected via a bus 108. It should be noted that the imaging device 100 can be used alone, can be incorporated into a mobile terminal such as a smartphone, or can be incorporated into an authentication device or a monitoring device.

[0126] The optical system 101 allows light from a subject to enter the solid-state imaging device 102 to form an image of the subject on a light receiving surface of the solid-state imaging device 102. The optical system 101 may include, for example, a focusing lens, a zoom lens, a stop, etc. The optical system 101 may include a plurality of lenses such as a wide-angle lens, a standard lens, and a telephoto lens.

[0127] The solid-state imaging device 102 converts light from an object into an electrical signal for each pixel, digitizes the electrical signal, and outputs it. The solid-state imaging device 102 may be, for example, an event-based visual sensor. The light received by the solid-state imaging device 102 may be visible light, near-infrared light (NIR), short-wavelength infrared light (SWIR), ultraviolet light, X-rays, or the like.

[0128] The imaging control unit 103 controls imaging of the solid-state imaging device 102 based on a command from the operation unit 107. At this time, the imaging control unit 103 can control exposure conditions, imaging timing, and the like of the solid-state imaging device 102.

[0129] The image processing unit 104 performs image processing based on the output from the solid-state imaging device 102. The image processing unit 104 may include an application processor that performs processing based on software.

[0130] The storage unit 105 stores captured images captured by the solid-state imaging device 102, and stores imaging parameters and the like of the solid-state imaging device 102. In addition, the storage unit 105 may store a program for operating the imaging device 100 based on software. The storage unit 105 may include a read-only memory (ROM), a random access memory (RAM), and a memory card.

[0131] The display unit 106 displays a captured image and displays various types of information supporting imaging operations. The display unit 106 may be a liquid crystal display or an organic electroluminescence (EL) display.

[0132] The operation unit 107 provides a user interface for operating the imaging apparatus 100. The operation unit 107 may include, for example, buttons, dials, and switches provided in the imaging apparatus 100. The operation unit 107 may be implemented as a touch panel integrated with the display unit 106.

[0133] Figure 2 is a block diagram showing a configuration example of a solid-state imaging device to which the light detection device according to the first embodiment is applied.

[0134] In the drawing, the solid-state imaging device 102 includes a pixel array unit 111, a row scanning circuit 112, a column processing circuit 113, a control signal generating circuit 114, and a frame memory 115. These circuits may be arranged on a single semiconductor substrate or may be arranged on a multilayer substrate.

[0135] The pixel array unit 111 includes pixels 121 arranged in a matrix in the row direction and the column direction. Each pixel 121 is connected to a signal line SVL via a switch 122 of each column and is connected to a horizontal control line CHL of each row. In addition, each pixel 121 is connected to a vertical control line CVL for each column. Each pixel 121 outputs a count value of a pulse generated in response to the incidence of a photon as pixel data. The light receiving portion into which the photon enters may include a single photon avalanche diode (SPAD) or may include an avalanche photodiode.

[0136] The row scanning circuit 112 selects rows in sequence in synchronization with the vertical synchronization signal. At this time, the row scanning circuit 112 can select the pixel 121 via the horizontal control line CHL. The row scanning circuit 112 selects the pixel 121 via the horizontal control line CHL. <1> - <n>The row scanning circuit 112 supplies a count reset signal RST to the switch 122 of each row to select the pixel 121 of each row. <1> - <n>To reset the count value of each row of pixels 121. RST <1> - <n>It can be used for resetting by row-by-row scanning or for resetting all rows simultaneously. Resetting all rows simultaneously can shorten the time until CVL starts. The row scanning circuit 112 can include a vertical arbiter that arbitrates the selection of the row containing the pixels 121 that have detected photons.

[0137] The column processing circuit 113 performs various types of signal processing on the pixel data transmitted via the signal line SVL. The column processing circuit 113 may include a row scanner that scans the columns. The column processing circuit 113 may include a horizontal arbiter that arbitrates the selection of the column containing the pixel 121 that has detected the photon.

[0138] The control signal generation circuit 114 controls the exposure and recharging of the photoelectric converter of each pixel 121 via the vertical control line CVL. The control signal generation circuit 114 provides a recharge control signal RCG, a breakdown current control signal QEN, an initialization signal INT, and a clamp signal CRP to each column of pixels 121. The frame memory 115 stores pixel data for one frame.

[0139] Figure 3 is a block diagram showing a configuration example of a pixel to which the light detection device according to the first embodiment is applied.

[0140] In the drawing, each pixel 121 includes a light pulse response unit 131 , a readout circuit 132 , and a counter 133 .

[0141] The optical pulse response unit 131 outputs a pulse in response to the incidence of a photon. At this time, in order to detect the photon, the optical pulse response unit 131 may multiply the charge generated from the photon.

[0142] The readout circuit 132 reads out the pulse output from the optical pulse response unit 131 in response to the incidence of photons. The readout circuit 132 is connected downstream of the optical pulse response unit 131.

[0143] The counter 133 performs a counting operation based on the pulse read out by the readout circuit 132. The counter 133 is connected downstream of the readout circuit 132. The counter 133 is connected to the signal line SVL via the switch 122. The switch 122 is turned on / off based on the selection signal SEL. In addition, the count reset signal RST is provided to the counter 133 via the horizontal control line CHL.

[0144] Figure 4 is a block diagram showing a first example of the optical pulse response unit according to the first embodiment.

[0145] In the drawing, the light pulse response unit 131 includes a photoelectric conversion section 141 , a resistance section 142 , a recharging section 143 , a detection section 144 , and a discharge section 145 .

[0146] The photoelectric conversion unit 141 has a first electrode connected to a potential VRH. At this time, the photoelectric conversion unit 141 multiplies the charge generated from the photons and discharges the charge to the potential VRH. The photoelectric conversion unit 141 includes a SPAD 151. The SPAD 151 has its anode and cathode connected to the potential VRH and the resistor 142, respectively. Here, the potential VRH can be set to ensure that a reverse bias of approximately tens of volts is applied, thereby enabling the SPAD 151 to operate in Geiger mode. At this time, the gain of the avalanche amplification in the SPAD 151 becomes theoretically infinite. This enables the SPAD 151 to generate a saturated output current regardless of the number of photons incident per unit time, and to detect photons one by one.

[0147] Resistive section 142 is connected in series to the second electrode of photoelectric conversion section 141, which is opposite to the first electrode of photoelectric conversion section 141. At this time, parasitic resistance C1 is added to the connection point between photoelectric conversion section 141 and resistive section 142. Resistive section 142 includes resistor 152. At this time, resistor 152 can have a higher resistance than SPAD 151. The resistance of resistive section 142 can be the on-resistance of a transistor or the resistance of a current source.

[0148] The recharging section 143 recharges the photoelectric conversion section 141 via the resistance section 142. The recharging section 143 can be directly connected to the resistance section 142. At this time, a parasitic resistance C2 is added to the connection point between the resistance section 142 and the recharging section 143. The power supply voltage VDD is provided to the recharging section 143. In addition, the charging control signal RCG is input to the recharging section 143. At this time, during the activation exposure period of the photon detection activation, the recharging section 143 disconnects the resistance section 142 from the power supply voltage VDD. In addition, the recharging section 143 connects the power supply voltage VDD to the resistance section 142 for recharging so that the SPAD 151 can operate in the Geiger mode.

[0149] The detection section 144 detects the potential VK2 of the resistance section 142 and outputs a detection signal AQ to the discharge section 145 . At this time, the potential VK2 of the resistance section 142 is input to the detection section 144 .

[0150] Drain section 145 is connected to resistor section 142 and to a potential VRL that is lower than a potential VRH representing a potential difference from the opposite potential on the side of resistor section 142 connected to recharge section 143. Based on detection signal AQ of potential VK2 of resistor section 142, drain section 145 drains at least some of the charge that can flow out to photoelectric converter 141 to a potential VRL that is lower than a potential VRH representing a potential difference from power supply potential VDD of recharge section 143. The at least some of the charge that can flow out to photoelectric converter 141 includes charge remaining in each of parasitic resistors C1 and C2 after quenching of SPAD 151. Quenching of SPAD 151 is a phenomenon in which avalanche amplification in SPAD 151 ceases.

[0151] Drain section 145 includes switch 155. Switch 155 may be a field-effect transistor. Switch 155 may be turned on based on detection signal AQ of potential VK2 of resistor section 142 to drain the remaining charge in each of parasitic resistors C1 and C2 to potential VRL after quenching by SPAD 151. Draining the remaining charge in parasitic resistor C2 to potential VRH via drain section 145 allows for reduced power consumption, compared to draining the charge to potential VRH via SPAD 151.

[0152] Figure 5 is a timing chart showing the operation of the optical pulse response unit according to the first embodiment.

[0153] In the figure, when a photon enters SPAD 151 while SPAD 151 is in Geiger mode (t11), avalanche amplification occurs in SPAD 151. At this time, current flows through SPAD 151 to potential VRH, causing a voltage drop across resistor 152, which reduces the cathode potential VK1 of SPAD 151. Here, resistor 152 is connected in series to the cathode side of SPAD 151. This causes the current flowing from parasitic resistance C1 to SPAD 151 to be greater than the current flowing from parasitic resistance C2 to SPAD 151.

[0154] Then, when the cathode potential VK1 of the SPAD 151 decreases, avalanche amplification in the SPAD 151 stops, and quenching occurs accordingly (t12). At this time, the cathode potential VK1 of the SPAD 151 becomes equal to the quenching voltage Vqe at which avalanche amplification in the SPAD 151 stops, and the potential VK2 at the connection point between the resistor section 142 and the recharge section 143 becomes higher than the quenching voltage Vqe.

[0155] When quenching occurs in the SPAD 151, charge begins to be redistributed from the parasitic capacitance C2 to the parasitic capacitance C1, again causing an increase in the cathode potential VK1 of the SPAD 151. At this time, the cathode potential VK1 of the SPAD 151 changes in a negative pulse-like manner.

[0156] On the other hand, the potential VK2 at the connection point between the resistance section 142 and the recharging section 143 decreases during the avalanche amplification period and the redistribution period between the parasitic capacitances C1 and C2 in the SPAD 151. At this time, when the detection section 144 detects the potential VK2 of the resistance section 142 and the potential VK2 of the resistance section 142 reaches the threshold value Vth (t13), the detection section 144 raises the detection signal AQ (E11).

[0157] When the detection signal AQ rises, the drain section 145 turns on the switch 155. At this time, the connection point between the resistance section 142 and the recharge section 143 is connected to the potential VRL, and the charge accumulated in the parasitic capacitance C2 is then mainly drained to the potential VRL, causing a decrease in both the cathode potential VK1 of the SPAD 151 and the potential VK2 of the resistance section 142 (E12).

[0158] After the charge accumulated in the parasitic capacitance C2 is discharged to the potential VRL, the detection unit 144 lowers the detection signal AQ (t14). At this time, the switch 155 is opened, and the connection point between the resistance unit 142 and the recharge unit 143 is disconnected from the potential VRL. In addition, the charge control signal RCG drops, and the recharge unit 143 then charges the photoelectric conversion unit 141 via the resistance unit 142, returning the SPAD 151 to the Geiger mode (E13).

[0159] Figure 6 is a block diagram showing a second example of the optical pulse response unit according to the first embodiment.

[0160] In the figure, the optical pulse response unit 161 includes a photoelectric conversion unit 171 instead of Figure 4 The other components of the optical pulse response unit 161 are similar to those of the photoelectric conversion unit 141 shown in FIG. Figure 4 Components of the optical pulse response unit 131 are shown. The photoelectric conversion section 171 includes a plurality of SPADs 151. The SPADs 151 are connected in parallel, and the anodes and cathodes of the SPADs 151 are connected to the potential VRH and the resistor 142, respectively. Photons detected by the plurality of SPADs 151 are added together and output from the photoelectric conversion section 171.

[0161] Here, the configuration in which the photoelectric conversion portion 171 is equipped with a plurality of SPADs 151 allows the number of photons detected per pixel to be increased, resulting in an increase in the S / N ratio.

[0162] Figure 7 is a block diagram showing a third example of the optical pulse response unit according to the first embodiment.

[0163] In the figure, the optical pulse response unit 181 includes a photoelectric conversion unit 191 and a resistor unit 192. Figure 6 The photoelectric conversion unit 171 and the resistance unit 142 are shown in FIG. The other components of the light pulse response unit 181 are similar to those of FIG. Figure 6 Components of the optical pulse response unit 161 are shown in FIG. Photoelectric conversion section 191 includes multiple SPADs 151. Resistance section 192 includes multiple resistors 152. Each SPAD 151 is connected in series to a corresponding resistor 152, and each series circuit including a SPAD 151 and a resistor 152 is connected in parallel. Multiple SPADs 151 have their anodes connected to a potential VRH, and the connection point between resistors 152 is connected to recharging section 143. Photons detected by multiple SPADs 151 are added together and output from photoelectric conversion section 191.

[0164] Here, the configuration in which the photoelectric conversion portion 191 is equipped with a plurality of SPADs 151 allows the number of photons detected per pixel to be increased, resulting in an increase in the S / N ratio.

[0165] In the first embodiment described above, based on the detection result of the potential VK2 of the resistor section 192 connected in series to the photoelectric conversion section 191, charge is discharged to a potential VRL that is lower than the potential VRH of the power supply potential VDD. Therefore, compared to the case where the charge remaining after quenching of the SPAD 151 is discharged to the potential VRH via the SPAD 151, power consumption can be reduced.

[0166] <2. Second embodiment>

[0167] In the first embodiment described above, the pixel 121 is provided with the light pulse response unit 131 and the readout circuit 132. In this second embodiment, each pixel is provided with a plurality of light pulse response units 131 and a plurality of readout circuits 132.

[0168] Figure 8 is a block diagram showing a configuration example of a pixel to which the light detection device according to the second embodiment is applied.

[0169] In the drawing, the pixel 221 includes a plurality of light pulse response units 131 , a plurality of readout circuits 132 , an OR circuit 233 , and a counter 133 .

[0170] Each optical pulse response unit 131 is connected in series to a corresponding readout circuit 132. Each series circuit of the optical pulse response unit 131 and the readout circuit 132 is connected to an OR circuit 233, and a counter 133 is connected downstream of the OR circuit 233. The results of detecting photons read by each readout circuit 132 are added by the OR circuit 233 and counted by the counter 133.

[0171] In the second embodiment described above, each pixel 221 is equipped with a plurality of light pulse response units 131 and a plurality of readout circuits 132. This configuration allows the number of photons detected per pixel to be increased, resulting in an increase in the S / N ratio.

[0172] <3. Third embodiment>

[0173] In the first embodiment described above, charge is discharged to a potential VRL that is lower than the potential VRH that is the potential difference from the power supply potential VDD based on the detection signal AQ from the detection unit 144. In this third embodiment, charge is discharged to a potential VRL that is lower than the potential VRH that is the potential difference from the power supply potential VDD based on the detection signal AQ from the detection unit 144, and the recharge unit 143 is controlled.

[0174] Figure 9 is a block diagram showing a configuration example of a solid-state imaging device to which the light detection device according to the third embodiment is applied.

[0175] In the drawings, this solid-state imaging device includes a pixel array unit 116 instead of the pixel array unit 111 of the first embodiment described above. In addition, compared with the solid-state imaging device of the first embodiment described above, this solid-state imaging device does not include a control signal generating circuit 114. Other components of the solid-state imaging device of the third embodiment are similar to those of the solid-state imaging device of the first embodiment described above.

[0176] The pixel array unit 116 includes pixels 123 arranged in a matrix in the row and column directions. Each pixel 123 is connected to a signal line SVL via a switch 122 for each column and to a horizontal control line CHL for each row. Each pixel 123 outputs a count value of pulses generated in response to the incidence of photons as pixel data.

[0177] Figure 10 is a block diagram showing a configuration example of an optical pulse response unit according to a third embodiment.

[0178] In the drawing, compared to the optical pulse response unit 131 of the first embodiment, this optical pulse response unit 331 further includes a pulse generating unit 341. Furthermore, the input terminal of the readout circuit 132 is connected to the connection point between the resistor 142 and the recharging unit 143. The remaining components of the optical pulse response unit 331 of the third embodiment are similar to those of the optical pulse response unit 131 of the first embodiment.

[0179] The pulse generating section 341 controls the discharge section 145 and generates a recharge control signal RCG for the recharge section 143 based on the detection signal AQ from the detection section 144. To control the discharge section 145, the pulse generating section 341 may output the detection signal AQ from the detection section 144 to the discharge section 145. Furthermore, the pulse generating section 341 may set the falling edge timing of the charge control signal RCG based on the falling edge timing of the detection signal AQ.

[0180] In the third embodiment described above, based on the detection signal AQ from the detection section 144, charge is discharged to a potential VRL that is less than the potential difference VRH from the power supply potential VDD, and a recharge control signal RCG is generated for the recharge section 143. This configuration allows the recharge section 143 to be controlled based on the output timing of the detection signal AQ from the detection section 144. Therefore, the time delay from when the charge remaining after quenching of the SPAD 151 is discharged to the potential VRL until the SPAD 151 returns to Geiger mode can be reduced.

[0181] <4. Fourth embodiment>

[0182] In the first embodiment, the recharge control signal RCG for the recharge section 143 is generated based on the detection signal AQ of the detector 144. In the fourth embodiment, the recharge section 143 is externally controlled based on the charge control signal RCG input from outside the optical pulse response unit.

[0183] Figure 11 is a block diagram showing a first example of the optical pulse response unit according to the fourth embodiment.

[0184] In the drawing, the pixel 421 includes a light pulse response unit 431 in place of the light pulse response unit 131 of the first embodiment. Furthermore, the input terminal of the readout circuit 132 is connected to the connection point between the resistor 142 and the recharge unit 143. The other components of the pixel 421 of the fourth embodiment are similar to those of the pixel 121 of the first embodiment.

[0185] In the optical pulse response unit 431, the recharging section 143 is externally controlled based on the charge control signal RCG inputted from the outside. Other components of the optical pulse response unit 431 of the fourth embodiment are similar to those of the optical pulse response unit 131 of the first embodiment described above.

[0186] Figure 12 is a block diagram showing a configuration example of an optical pulse response unit according to a fourth embodiment.

[0187] In the drawing, compared with the optical pulse response unit 131 of the first embodiment, the optical pulse response unit 431 further includes an initialization transistor 436 and an anti-punch-through transistor 437 .

[0188] The initialization transistor 436 initializes the output of the detection unit 144. An N-channel field effect transistor can be used as the initialization transistor 436. The initialization transistor 436 is connected between the detection unit 144 and the potential VRL. The initialization signal INQ is input to the gate of the initialization transistor 436.

[0189] The anti-punch-through transistor 437 prevents a punch-through current from flowing through the detection unit 144. A P-channel field effect transistor can be used as the anti-punch-through transistor 437. The anti-punch-through transistor 437 is connected between the power supply potential VDD and the detection unit 144. An initialization signal INQ is input to the gate of the anti-punch-through transistor 437.

[0190] The recharging section 143 includes a recharging transistor 433. A P-channel field effect transistor can be used as the recharging transistor 433. The recharging transistor 433 is connected between the power supply potential VDD and the resistor 152. A charging control signal RCG is input to the gate of the recharging transistor 433.

[0191] The detection unit 144 includes a detection transistor 434. A P-channel field effect transistor can be used as the detection transistor 434. The detection transistor 434 is connected between the initialization transistor 436 and the anti-punch-through transistor 437. The potential VK2 of the resistor unit 142 is input to the gate of the detection transistor 434.

[0192] The drain unit 145 includes a drain transistor 435. An N-channel field-effect transistor can be used as the drain transistor 435. The drain transistor 435 is connected between the connection point between the resistor 152 and the recharge transistor 433 and the potential VRL. The detection signal AQ from the detection unit 144 is input to the gate of the drain transistor 435.

[0193] Readout circuit 132 includes a readout transistor 442 and active transistors 441 and 443. Active transistors 441 and 442 can be P-channel field-effect transistors. Active transistor 443 can be N-channel field-effect transistors. Readout transistor 442 is connected between active transistors 441 and 443. Readout transistor 442 is connected between power supply potential VDD2 and ground potential via active transistors 441 and 443. Active signal INT is input to the gates of active transistors 441 and 443. The potential VK2 of resistor section 142 is input to the gate of readout transistor 442.

[0194] Note that the combination of the power supply voltages VDD and VDD2, the potential VRH, and the potential VRL may be, for example, power supply voltage VDD = 3 V, power supply voltage VDD2 = 0.8 V, potential VRH = -18 V, and potential VRL = 0 V. Alternatively, the combination may be power supply voltage VDD = power supply voltage VDD2 = 0.8 V, potential VRH = -20.2 V, and potential VRL = -2.2 V.

[0195] Figure 13 is a block diagram showing a second example of the optical pulse response unit according to the fourth embodiment.

[0196] In the accompanying drawings, Figure 12 Compared to the light pulse response unit 431 shown in FIG, the light pulse response unit 441 further includes a clamp transistor 432. In addition, the readout circuit 132 has its input terminal connected to the connection point between the clamp transistor 432 and the recharge section 143. The other components of the light pulse response unit 441 are the same as those of FIG. Figure 12 The components of the optical pulse response unit 431 shown in FIG. 4 are similar.

[0197] The clamp transistor 432 prevents the potential VK2 of the resistor 142 from being input to the readout circuit 132. A P-channel field effect transistor can be used as the clamp transistor 432. The clamp transistor 432 is connected between the recharge transistor 433 and the resistor 152. A clamp signal CLP is input to the gate of the clamp transistor 432.

[0198] Note that a combination of the power supply voltages VDD and VDD2 , the potential VRH, and the potential VRL may be, for example, power supply voltage VDD=power supply voltage VDD2=0.8V, potential VRH=−20.2V, and potential VRL=−2.2V.

[0199] Figure 14 is a timing chart showing the operation of the optical pulse response unit according to the fourth embodiment.

[0200] In the accompanying drawings, when the SPAD 151 is in Geiger mode, the clamp signal CLP is set to a high level. At this time, the readout circuit 132 is disconnected from the potential VK2 of the resistor section 142 via the clamp transistor 432. Furthermore, the initialization signal INQ is set to a low level. At this time, the detection transistor 434 is connected to the power supply potential VDD via the anti-punch-through transistor 437, and the gate of the drain transistor 435 is disconnected from the potential VRL via the initialization transistor 436. Furthermore, the valid signal INT is set to a high level. At this time, the readout transistor 442 is disconnected from the power supply potential VDD2 and the ground potential via the active transistors 441 and 443.

[0201] Furthermore, the charge control signal RCG is set to a high level. At this point, the SPAD 151 is disconnected from the power supply potential VDD via the recharge transistor 433. Setting the charge control signal RCG to a high level enables the active exposure period P2. Furthermore, setting the charge control signal RCG to a low level enables the active recharge period P1.

[0202] Then, when a photon enters the SPAD 151 while the SPAD 151 is in Geiger mode (t21), avalanche amplification occurs in the SPAD 151. At this time, current flows through the SPAD 151 to the potential VRH, causing a voltage drop across the resistor 152 by the cathode potential VK1 of the SPAD 151 (E21).

[0203] Then, when the cathode potential VK1 of the SPAD 151 decreases, avalanche amplification in the SPAD 151 stops and the potential VK2 of the resistor 142 decreases. At this time, when the potential VK2 of the resistor 142 reaches the threshold Vth, the detection transistor 434 turns on and the detection signal AQ rises (E22).

[0204] When the detection signal AQ rises, the drain transistor 435 is turned on. At this time, the resistor 152 is connected to the potential VRL, and the charge accumulated in the parasitic capacitance C2 is mainly drained to the potential VRL.

[0205] After the charge accumulated in the parasitic capacitor C2 is discharged to the potential VRL, the initialization signal INQ rises (t22). At this time, the detection transistor 434 is disconnected from the power supply potential VDD via the anti-punch-through transistor 437 and connected to the potential VRL via the initialization transistor 436, and the detection signal AQ falls (E23). When the detection signal AQ falls, the discharge transistor 435 is turned off, and the resistor 152 is disconnected from the potential VRL.

[0206] Next, after the initialization signal INQ falls, the clamp signal CLP and the valid signal INT fall (t23). At this time, the clamp transistor 432 and the active transistors 441 and 443 are turned on, the gate potential VK3 of the read transistor 442 decreases and becomes equal to the potential VK2 of the resistor 142 (E24), and the power supply potential VDD2 is supplied to the read transistor 442. As a result, the output PLS of the read circuit 132 rises (E25).

[0207] Next, the charge control signal RCG falls (t24). At this time, the recharge transistor 433 is turned on, and then the SPAD 151 is charged via the recharge transistor 433 and the resistor 152, thereby restoring the SPAD 151 to the Geiger mode.

[0208] After the recharge control signal RCG rises, the clamp signal CLP and the active signal INT rise (t25), and the clamp transistor 432 and the active transistors 441 and 443 are turned off. At this time, the readout circuit 132 is disconnected from the potential VK2 of the resistor 142 via the clamp transistor 432, and the readout transistor 442 is disconnected from the power supply potential VDD2 and the ground potential via the active transistors 441 and 443. Therefore, the output PLS of the readout circuit 132 falls (E26), and the count value CNT of the counter 133 is incremented based on the output PLS of the readout circuit 132 (E27).

[0209] In the fourth embodiment described above, the recharging section 143 is externally controlled based on the charge control signal RCG input from outside the optical pulse response unit 441. This eliminates the need for the optical pulse response unit 441 to include the pulse generating section 341 that generates the recharge control signal RCG, thereby allowing the number of elements in the optical pulse response unit 441 to be reduced.

[0210] <5. Fifth embodiment>

[0211] In the fourth embodiment, the recharge section 143 is externally controlled based on the charge control signal RCG input from outside the optical pulse response unit 441. In the fifth embodiment, a plurality of different cycles are set for the recharge control signal RCG input from outside the optical pulse response unit 441.

[0212] Figure 15 1 is a timing chart illustrating a first example of the operation of the optical pulse response unit according to the fifth embodiment. Note that diagram a shows a case where the solid-state imaging device is used in a low-light environment, and diagram b shows a case where the solid-state imaging device is used in a high-light environment.

[0213] In the drawing, the charge control signal RCG alternately switches between a short period and a long period to define a recharge period. At this time, during the short period and the long period, the function of discharging charge to the potential VRH via the discharge portion 145 is enabled.

[0214] Figure 16 1 is a timing chart illustrating a second example of the operation of the optical pulse response unit according to the fifth embodiment. Note that a in the figure illustrates a case where the solid-state imaging device is used in a low-lighting environment, and b in the figure illustrates a case where the solid-state imaging device is used in a high-lighting environment.

[0215] In the figure, the charge control signal RCG alternately switches between short and long cycles to define a recharge cycle. At this time, during the short period, the function of discharging the charge to the potential VRH via the discharge unit 145 is disabled, and during the long period, the function of discharging the charge to the potential VRH via the discharge unit 145 is enabled.

[0216] In the fifth embodiment described above, the charge control signal RCG alternately switches between short and long cycles to define a recharge cycle. In this case, by disabling the function of discharging charge to the potential VRH via the discharge unit 145 during short periods, a sufficient operating time can be ensured. Furthermore, by enabling the function of discharging charge to the potential VRH via the discharge unit 145 during long periods, power consumption can be reduced.

[0217] <6. Sixth embodiment>

[0218] In the third embodiment, the readout circuit 132 generates the output PLS based on the potential VK2 of the resistor 142. In the sixth embodiment, the readout circuit 132 generates the output PLS based on the detection signal AQ of the detector 144.

[0219] Figure 17 is a block diagram showing a first example of a pixel to which the light detection device according to the sixth embodiment is applied.

[0220] In the drawing, a pixel 521 includes an optical pulse response unit 531 instead of the optical pulse response unit 331 of the third embodiment. Other components of the pixel 521 of the sixth embodiment are similar to those of the pixel 321 of the third embodiment.

[0221] In the optical pulse response section 531, the detection signal AQ output from the pulse generation section 341 is input to the readout circuit 132. At this time, the readout circuit 132 generates an output PLS based on the detection signal AQ output from the pulse generation section 341.

[0222] Figure 18 is a block diagram showing a second example of a pixel to which the light detection device according to the sixth embodiment is applied.

[0223] In the drawing, a pixel 522 includes an optical pulse response unit 532 instead of the optical pulse response unit 431 of the fourth embodiment. Other components of the pixel 522 of the sixth embodiment are similar to those of the pixel 421 of the fourth embodiment.

[0224] In the optical pulse response unit 532, the detection signal AQ output from the detection section 144 is input to the readout circuit 132. At this time, the readout circuit 132 generates an output PLS based on the detection signal AQ output from the detection section 144.

[0225] Figure 19 is a block diagram showing a third example of a pixel to which the light detection device according to the sixth embodiment is applied.

[0226] In the accompanying drawings, the pixel includes the optical pulse response unit 431 of the fourth embodiment described above as Figure 18 4. Thus, the detection signal AQ output from the detection transistor 434 is input to the gate of the readout transistor 442. The readout circuit 132 generates an output PLS based on the detection signal AQ output from the detection transistor 434.

[0227] Note that the combination of the power supply voltages VDD and VDD2, the potential VRH, and the potential VRL may be, for example, power supply voltage VDD = power supply voltage VDD2 = 3 V, potential VRH = -20.2 V, and potential VRL = 0 V. Alternatively, the combination may be power supply voltage VDD == 3 V, power supply voltage VDD2 = 0.8 V, potential VRH = -20.2 V, and potential VRL = 0 V.

[0228] Figure 20 is a block diagram showing a fourth example of a pixel to which the light detection device according to the sixth embodiment is applied.

[0229] In the drawings, the pixel includes Figure 18 The optical pulse response unit 532 shown in FIG. 4 is an optical pulse response unit 451.

[0230] In the accompanying drawings, compared to the optical pulse response unit 441 of the fourth embodiment, the optical pulse response unit 451 further includes a clamp transistor 452. The clamp transistor 452 prevents the readout circuit 132 from reading the detection signal AQ. A P-channel field-effect transistor can be used as the clamp transistor 452. The clamp transistor 452 is connected between the connection point between the detection transistor 434 and the initialization transistor 436 and the gate of the readout transistor 442. The clamp signal CLP is input to the gate of the clamp transistor 452.

[0231] At this time, the detection signal AQ output from the detection transistor 434 is input to the gate of the readout transistor 442 via the clamp transistor 452. The readout circuit 132 generates the output PLS based on the detection signal AQ output from the detection transistor 434. At this time, the clamp signal CLP can be fixed at a low level. Therefore, the timing of the charge control signal RCG can be set regardless of the timing of the clamp signal CLP, and the input amplitude of the readout circuit 132 can be limited.

[0232] Note that a combination of the power supply voltages VDD and VDD2 , the potential VRH, and the potential VRL may be, for example, the power supply voltage VDD==3V, the power supply voltage VDD2=0.8V, the potential VRH=−20.2V, and the potential VRL=−2.2V.

[0233] In the sixth embodiment described above, the readout circuit 132 generates the output PLS based on the detection signal AQ of the detection section 144. This configuration allows the readout circuit 132 to generate the output PLS without detecting the potential VK2 of the resistance section 142. In this case, the detection signal AQ of the detection section 144 is a digitized signal, which facilitates easier readout.

[0234] <7. Seventh embodiment>

[0235] In the fourth embodiment, the anti-punch-through transistor 437 is connected between the power supply potential VDD and the detection unit 144. In the seventh embodiment, an amplitude limiting transistor for limiting the drive potential of the discharge unit 145 is provided.

[0236] Figure 21 is a block diagram showing a configuration example of an optical pulse response unit according to a seventh embodiment, Figure 22 is a timing chart showing the operation of the optical pulse response unit according to the seventh embodiment.

[0237] exist Figure 21 , compared to the optical pulse response unit 441 of the fourth embodiment described above, the optical pulse response unit 621 further includes an amplitude limiting transistor 622. Furthermore, compared to the optical pulse response unit 441 of the fourth embodiment described above, the optical pulse response unit 621 does not include the anti-punch-through transistor 437. Other components of the optical pulse response unit 621 of the seventh embodiment are similar to those of the optical pulse response unit 441 of the fourth embodiment described above.

[0238] The amplitude limiting transistor 622 limits the amplitude of the driving potential of the discharge portion 145. At this time, the amplitude limiting transistor 622 can also be used to prevent a breakdown current from flowing through the detection portion 144. As the amplitude limiting transistor 622, an N-channel field effect transistor can be used. The amplitude limiting transistor 622 is connected between the detection transistor 434 and the initialization transistor 436. The amplitude limiting signal AQE is input to the gate of the amplitude limiting transistor 622. At this time, the amplitude limiting transistor 622 can limit the amplitude of the detection signal AQ1 of the detection portion 144, and input the resulting signal to the gate of the discharge transistor 435. For example, when the amplitude of the detection signal AQ1 of the detection portion 144 is within the range from 0V to -2.2V, as shown in FIG. Figure 22 As shown, the potential of the detection signal AQ2 input to the gate of the drain transistor 435 can be limited to a range from -0.5V to -2.2V.

[0239] In the seventh embodiment described above, the optical pulse response unit 621 is equipped with an amplitude limiting transistor 622 that limits the drive potential of the discharge section 145. With this configuration, the charging and discharging power of the discharge section 145 can be reduced, and the coupling between the potential VK2 of the resistor section 142 and the detection signal AQ2 can be suppressed.

[0240] <8. Eighth embodiment>

[0241] In the fourth embodiment, the detector 144 controls the discharge operation of the discharge unit 145 based on the potential VK2 of the resistor 142. In the eighth embodiment, the resistor 142 connected in series to the photoelectric converter 141 and the detector 144 detecting the potential VK2 of the resistor 142 are isolated by capacitance.

[0242] Figure 23 is a block diagram showing a configuration example of an optical pulse response unit according to an eighth embodiment.

[0243] In the figure, compared with the optical pulse response unit 431 of the fourth embodiment, the optical pulse response unit 721 further includes a capacitor 722 and a charging transistor 723. Other components of the optical pulse response unit 721 of the eighth embodiment are similar to those of the optical pulse response unit 431 of the fourth embodiment.

[0244] A P-channel field effect transistor can be used as the recharge transistor 723. The recharge transistor 723 is connected between the power supply potential VDD and the gate of the detection transistor 434. The gate of the recharge transistor 723 receives a charge control signal RCG.

[0245] The capacitor 722 is connected between the resistor 142 and the detection unit 144. The capacitor 722 can isolate the resistor 142 from the detection unit 144 and the discharge unit 145 and reduce the parasitic capacitance C2 added to the potential VK2 of the resistor 142.

[0246] In the eighth embodiment described above, the resistance section 142 connected in series to the photoelectric conversion section 141 and the detection section 144 that detects the potential VK2 of the resistance section 142 are capacitively isolated via the capacitor 722. With this configuration, the parasitic capacitance C2 added to the potential VK2 of the resistance section 142 can be reduced, and the current flowing from the parasitic capacitance C2 to the SPAD 151 can be reduced.

[0247] <9. Ninth embodiment>

[0248] In the fourth embodiment, the drain section 145 extracts charge from the connection point between the resistor section 142 and the recharge section 143. In the ninth embodiment, the drain section 145 extracts charge from the connection point between the photoelectric converter 141 and the resistor section 142.

[0249] Figure 24 is a block diagram showing a configuration example of an optical pulse response unit according to a ninth embodiment.

[0250] In the drawing, in the optical pulse response unit 821, the drain transistor 435 is connected between the connection point between the photoelectric converter 141 and the resistor 142 and the potential VRL. The detection signal AQ from the detector 144 is input to the gate of the drain transistor 435. At this time, when the drain transistor 435 is turned on, the charge accumulated in the parasitic capacitances C1 and C2 is extracted via the connection point between the photoelectric converter 141 and the resistor 142.

[0251] In the ninth embodiment described above, the drain section 145 extracts charge from the connection point between the photoelectric converter 141 and the resistor 142. With this configuration, charge can be extracted from the parasitic capacitances C1 and C2 without connecting the drain transistor 435 to the gate of the detection transistor 434.

[0252] <10. Tenth embodiment>

[0253] In the fourth embodiment described above, charge is discharged to a potential VRL having a potential difference from the power supply potential VDD smaller than the potential VRH based on the detection signal AQ output from the detection unit 144. In the tenth embodiment, charge is discharged to a potential VRL having a potential difference from the power supply potential VDD smaller than the potential VRH based on the output PLS of the readout circuit 132.

[0254] Figure 25 is a block diagram showing a first example of a pixel to which the light detection device according to the tenth embodiment is applied.

[0255] In the drawing, compared with the optical pulse response unit 441 of the fourth embodiment described above, the optical pulse response unit 921 does not include the detection section 144 , the initialization transistor 436 , and the anti-punch-through transistor 437 .

[0256] Furthermore, in the optical pulse response unit 921, the discharge section 145 discharges the charge to a potential VRL lower than the potential VRH at which the charge is discharged from the photoelectric conversion unit 141 based on the output PLS of the readout circuit 132. In this case, a buffer 922 may be provided downstream of the readout circuit 132. The output PLS of the readout circuit 132 may be input to the counter 133 via the buffer 922. The other components of the optical pulse response unit 921 of the tenth embodiment are similar to those of the optical pulse response unit 441 of the fourth embodiment described above.

[0257] Figure 26 is a block diagram showing a second example of a pixel to which the light detection device according to the tenth embodiment is applied.

[0258] In the accompanying drawings, Figure 25 Compared to the pixel shown in FIG, this pixel further includes a buffer 923. The output PLS of the readout circuit 132 is input to the drain portion 145 via the buffer 923. The output terminal of the buffer 923 is connected to the gate of the drain transistor 435. The buffer 923 can level-shift the output PLS of the readout circuit 132 and apply the level-shifted output PLS to the gate of the drain transistor 435. At this time, for example, the high power supply potential VDH of the buffer 923 can be set to 0.8V, and the low power supply potential VDL of the buffer 923 can be set to -2.2V.

[0259] In the tenth embodiment described above, the drain section 145 drains charge based on the output PLS of the readout circuit 132. This eliminates the need for the detection section 144, the initialization transistor 436, and the anti-punch-through transistor 437, thereby reducing the number of components in the light pulse response unit 921. In this case, by routing the output PLS of the readout circuit 132 to the drain section 145 via the buffer 923, the input amplitude of the drain section 145 can be limited, reducing power requirements.

[0260] <11. Eleventh embodiment>

[0261] In the fourth embodiment, the readout circuit 132 generates the output PLS based on the potential VK2 of the resistor 142. In the eleventh embodiment, the readout circuit 132 generates the output PLS based on the detection signal AQ of the detector 144.

[0262] Figure 27 is a block diagram showing a first example of the optical pulse response unit according to the eleventh embodiment.

[0263] In the drawing, in the optical pulse response unit 931, the detection signal AQ of the detection section 144 is input to the readout circuit 132. Other components of the optical pulse response unit 931 of the eleventh embodiment are similar to those of the optical pulse response unit 431 of the fourth embodiment described above.

[0264] The readout circuit 132 generates an output PLS based on the detection signal AQ of the detection unit 144. At this time, the gate of the readout transistor 442 is connected to the connection point between the detection transistor 434 and the initialization transistor 436.

[0265] Figure 28 is a block diagram showing a second example of the optical pulse response unit according to the eleventh embodiment.

[0266] In the accompanying drawings, Figure 27 Compared to the pixel shown in FIG, this pixel further includes an amplitude limiting transistor 932. A P-channel field-effect transistor can be used as the amplitude limiting transistor 932. The amplitude limiting transistor 932 is connected between the gate of the readout transistor 442 and the connection point between the detection transistor 434 and the initialization transistor 436. A bias voltage VB is applied to the gate of the amplitude limiting transistor 932. The bias voltage VB can be fixed at -0.5V, for example.

[0267] In the eleventh embodiment described above, the readout circuit 132 can generate the output PLS based on the detection signal AQ of the detection section 144, thereby allowing a reduction in the number of elements in the optical pulse response unit 931. In this case, the input amplitude of the readout circuit 132 can be limited by routing the detection signal AQ of the detection section 144 to the readout circuit 132 via the amplitude limiting transistor 932, thereby allowing a reduction in power requirements.

[0268] <12. Twelfth Implementation>

[0269] In the fourth embodiment, the optical pulse response unit 441 includes the initialization transistor 436, the anti-punch-through transistor 437, and the clamp transistor 432. In the twelfth embodiment, a driver is provided that limits the input amplitudes of the initialization transistor 436 and the anti-punch-through transistor 437.

[0270] Figure 29 is a block diagram showing a configuration example of an optical pulse response unit according to a twelfth embodiment.

[0271] Compared with the optical pulse response unit 441 of the fourth embodiment, the optical pulse response unit 951 further includes drivers 348 and 349. Other components of the optical pulse response unit 951 of the twelfth embodiment are similar to those of the optical pulse response unit 441 of the fourth embodiment.

[0272] The driver 348 limits the amplitude of the initialization signal INQ and inputs the resulting signal to the gate of the initialization transistor 436. At this time, the power supply of the driver 348 is connected between the intermediate potential VDM and the potential VRL. The intermediate potential VDM can be set to, for example, -0.7V.

[0273] The driver 349 limits the amplitude of the anti-punch-through signal ENQ and inputs the resulting signal to the gate of the anti-punch-through transistor 437. At this time, the power supply of the driver 349 is connected between the power supply potential VDD and the intermediate potential VDM.

[0274] In the twelfth embodiment described above, the driver 348 that limits the amplitude of the initialization signal INQ and the driver 349 that limits the amplitude of the anti-punchthrough signal ENQ are provided. With this configuration, the charging and discharging power of the initialization transistor 436 and the anti-punchthrough transistor 437 can be reduced, thereby allowing the power requirement to be reduced.

[0275] Note that, in the above embodiment, an example has been described in which the initialization transistor 436 , the anti-punch-through transistor 437 , and the clamp transistor 432 are provided for each pixel, but those transistors may be shared among a plurality of pixels.

[0276] <13. Thirteenth Implementation Method>

[0277] In the fourth embodiment described above, the clamp transistor 432 is connected between the resistor 152 and the recharge transistor 433. In this thirteenth embodiment, a resistor that reduces the potential VK2 of the resistance section 142 is provided between the resistance section 142 and the clamp transistor 432.

[0278] Figure 30 is a block diagram showing a configuration example of an optical pulse response unit according to a thirteenth embodiment, Figure 31 is a timing chart showing the operation of the optical pulse response unit according to the thirteenth embodiment.

[0279] exist Figure 30 Compared with the optical pulse response unit 441 of the fourth embodiment, the optical pulse response unit 961 further includes a resistor 962. Other components of the optical pulse response unit 961 of the thirteenth embodiment are similar to those of the optical pulse response unit 441 of the fourth embodiment.

[0280] The resistor 962 reduces the potential VK2 of the resistor section 142. The resistor 962 is connected between the resistor section 142 and the clamp transistor 432. Figure 31 As shown, the resistor 962 can reduce the potential VK2 of the resistance portion 142 based on its voltage effect.

[0281] In the thirteenth embodiment described above, the resistor 962 that lowers the potential VK2 of the resistance section 142 is provided between the resistance section 142 and the clamp transistor 432. With this configuration, the potential VK2 of the resistance section 142 can be lowered, allowing reduction in power requirements.

[0282] <14. Fourteenth Implementation>

[0283] In the fourth embodiment described above, charge is discharged to a potential VRL that is lower than the potential VRH of the power supply potential VDD based on detection signal AQ from detection unit 144. In this embodiment, a second substrate having detection unit 144 and discharge unit 145 formed thereon is stacked on a first substrate having recharge unit 143 formed thereon.

[0284] Figure 32 is a block diagram showing a first example of an optical pulse response unit according to a fourteenth embodiment.

[0285] In the drawings, the solid-state imaging device includes a first substrate 1001 and a second substrate 1002. The second substrate 1002 is stacked on the first substrate 1001. The first substrate 1001 and the second substrate 1002 may be semiconductor substrates such as Si, InGaAs, or InP.

[0286] The recharging portion 143 is formed on the first substrate 1001. The photoelectric conversion portion 141, the resistance portion 142, the detection portion 144, and the discharge portion 145 are formed on the second substrate 1002.

[0287] Figure 33 is a block diagram showing a second example of the optical pulse response unit according to the fourteenth embodiment.

[0288] In the accompanying drawings, the solid-state imaging device includes a first substrate 1001, a second substrate 1012, and a third substrate 1003. The second substrate 1002 is stacked on the first substrate 1001. The third substrate 1003 is stacked on the second substrate 1012. The first substrate 1001, the second substrate 1012, and the third substrate 1003 can be semiconductor substrates such as Si, InGaAs, or InP. Note that the semiconductor material of the first and second substrates 1001 and 1012 can be different from the semiconductor material of the third substrate 1003. For example, if InGaAs is used for the third substrate 1003 to ensure sensitivity in the infrared region, Si can be used for the first and second substrates 1001 and 1012.

[0289] The recharging portion 143 is formed on the first substrate 1001 . The resistance portion 142 , the detection portion 144 , and the discharge portion 145 are formed on the second substrate 1012 . The photoelectric conversion portion 141 is formed on the third substrate 1003 .

[0290] In the fourteenth embodiment described above, the second substrate 1002 having the detection section 144 and the discharge section 145 formed thereon is stacked on the first substrate 1001 having the recharge section 143 formed thereon. This allows the detection section 144 and the discharge section 145, each having a higher breakdown voltage than the recharge section 143, to be formed on separate substrates, enabling the circuitry downstream of the recharge section 143 to be miniaturized.

[0291] <15. Fifteenth Implementation>

[0292] In the fourteenth embodiment described above, the second substrate 1002 on which the detection section 144 and the discharge section 145 are formed is stacked on the first substrate 1001 on which the recharge section 143 is formed. In this fifteenth embodiment, the second substrate on which the detection section 144 and the discharge section 145 are formed is stacked on the first substrate on which the recharge section 143, the readout circuit 132, and the counter 133 are formed.

[0293] Figure 34 is a block diagram showing a first example of a pixel to which the light detection device according to the fifteenth embodiment is applied.

[0294] In the drawing, the solid-state imaging device includes a first substrate 2001 and a second substrate 2002. The second substrate 2002 is stacked on the first substrate 2001.

[0295] The recharging portion 143, the readout circuit 132, and the counter 133 are formed on the first substrate 2001. The photoelectric conversion portion 141, the resistance portion 142, the detection portion 144, and the discharge portion 145 are formed on the second substrate 2002.

[0296] Figure 35 is a block diagram showing a second example of a pixel to which the light detection device according to the fifteenth embodiment is applied.

[0297] In the drawing, the solid-state imaging device includes a first substrate 2001, a second substrate 2012, and a third substrate 2003. The second substrate 2002 is stacked on the first substrate 2001. The third substrate 2003 is stacked on the second substrate 2012.

[0298] The recharging section 143, the readout circuit 132, and the counter 133 are formed on the first substrate 2001. The resistance section 142, the detection section 144, and the discharge section 145 are formed on the second substrate 2012. The photoelectric conversion section 141 is formed on the third substrate 2003.

[0299] In the fifteenth embodiment described above, the second substrate 2002 on which the detection section 144 and the discharge section 145 are formed is stacked on the first substrate 2001 on which the recharge section 143, the readout circuit 132, and the counter 133 are formed. With this configuration, the detection section 144 and the discharge section 145 having a higher breakdown voltage than the recharge section 143 can be formed on different substrates, which makes it possible to miniaturize the recharge section 143, the readout circuit 132, and the counter 133.

[0300] <16. Sixteenth embodiment>

[0301] In the first embodiment described above, charge is discharged to a potential VRL smaller than the potential VRH of the power supply potential VDD based on the detection signal AQ of the detection unit 144. In this sixteenth embodiment, high breakdown voltage regions forming high breakdown voltage transistors are arranged adjacent to each other in a plurality of pixels.

[0302] Figure 36 is a block diagram showing a configuration example of an optical pulse response unit according to a sixteenth embodiment.

[0303] In the drawing, a low breakdown voltage region 3001 and a high breakdown voltage region 3002 are provided in a semiconductor substrate forming the optical pulse response unit 131. A low breakdown voltage transistor is formed in the low breakdown voltage region 3001. A high breakdown voltage transistor is formed in the high breakdown voltage region 3002.

[0304] For example, when the cathode voltage of the SPAD 151 ranges from 2V to 3V, the detection section 144 and the discharge section 145 are formed in the high breakdown voltage region 3002. The recharge section 143, the photoelectric conversion section 141, and the resistance section 142 are formed in the low breakdown voltage region 3001. In this case, the high breakdown voltage regions 3002 can be arranged adjacent to each other on a plurality of pixels.

[0305] Figure 37 is a plan view showing a layout example of an optical pulse response unit according to a sixteenth embodiment.

[0306] In the accompanying drawings, pixels 4001 are arranged in a matrix along row and column directions on a semiconductor substrate 4000. Each pixel 4001 is provided with a low breakdown voltage region 4002 and a high breakdown voltage region 4004. The low breakdown voltage region 4002 is provided around the high breakdown voltage region 4004. A boundary region 4003 is provided between the low breakdown voltage region 4002 and the high breakdown voltage region 4004. In the boundary region 4003, an element isolation region such as shallow trench isolation (STI) can be formed.

[0307] The recharge portion 143, the photoelectric conversion portion 141, and the resistance portion 142 are formed in the low breakdown voltage region 4002 for each pixel 4001. The detection portion 144 and the discharge portion 145 are formed in the high breakdown voltage region 4004 of each pixel 4001.

[0308] In b of the accompanying drawings, pixels 4011 are arranged in a matrix in row and column directions on a semiconductor substrate 4010. Each pixel 4011 is provided with a low breakdown voltage region 4012 and a high breakdown voltage region 4014. Each pixel 4011 is provided with a boundary region 4013 between the low breakdown voltage region 4012 and the high breakdown voltage region 4014.

[0309] At this time, the four pixels 4011 are grouped to ensure that the high breakdown voltage regions 4014 are arranged adjacent to each other. At this time, the boundary region 4013 may be arranged to surround the high breakdown voltage regions 4014 arranged adjacent to each other across the four pixels 4011.

[0310] In the sixteenth embodiment described above, high breakdown voltage regions 4014 forming high breakdown voltage transistors are arranged adjacent to each other across a plurality of pixels 4011. This configuration eliminates the need for boundary regions 4013 between adjacent high breakdown voltage regions 4014, allowing the area of ​​the element region to be reduced.

[0311] Note that in the above fourteenth to sixteenth embodiments, an example has been described in which each embodiment is applied to the optical pulse response unit 431 of the above fourth embodiment, but the embodiment can be applied to the optical pulse response unit 331 of the above third embodiment.

[0312] <17. Seventeenth Implementation>

[0313] In the first embodiment described above, the counter 133 is provided to perform a counting operation based on the pulse read out by the readout circuit 132. In this seventeenth embodiment, the solid-state imaging device can output the counter output and the MSB of the counter output in a switchable manner.

[0314] Figure 38 17 is a block diagram showing a configuration example of a solid-state imaging device to which a light detection device according to the seventeenth embodiment is applied.

[0315] In the drawing, the solid-state imaging device includes a pixel array unit 117 , a row scanning circuit 118 , a column processing circuit 119 , a control signal generating circuit 114 , and a frame memory 115 .

[0316] The pixel array unit 117 includes pixels 124 arranged in a matrix in the row direction and the column direction. Each pixel 124 is connected to the column processing circuit 119 via switches 122 and 125 of each column, and is connected to the row scanning circuit 118 of each row. Here, the switch 122 is connected to the counter output of the counter 133. The switch 125 is connected to the MSB output of the counter 133. In addition, each pixel 124 is connected to the control signal generating circuit 114 of each column. Each pixel 124 outputs a count value of a pulse generated in response to the incidence of a photon as pixel data. The light receiving portion into which the photon enters may include a SPAD or may include an avalanche photodiode.

[0317] The row scanning circuit 118 selects rows in sequence in synchronization with the vertical synchronization signal. <1> - <n>Supplied to the switch 122 of each row to select the pixel 124 of each row. In addition, the row scanning circuit 118 counts the reset signal RST <1> - <n>Supplied to the pixels 124 of each row to reset the count value of the pixels 124 of each row. In addition, the row scanning circuit 118 selects the MSB signal MEL <1> - <n>The switch 125 supplied to each row reads out the MSB of the count value of each pixel 124 .

[0318] The column processing circuit 119 performs various types of signal processing on the pixel data read out from each pixel 124. In addition, the column processing circuit 119 performs processing to extend the count range of the counter 133 based on the counter output read out from each pixel 124 and the MSB of the counter output. At this time, the column processing circuit 119 determines the overflow number of the counter 133 based on the MSB of the counter output read out from each pixel 124. Then, the column processing circuit 119 adds a value shifted by the same shift amount as the overflow amount to the bit sequence indicating the count value, thereby generating an extended count value with the count value of the counter 133 shifted to the higher-order bits. The count value is stored in the frame memory 115.

[0319] In the seventeenth embodiment described above, the counter output of the counter 133 and the MSB of the counter output can be output in a switchable manner. With this configuration, the counting range of the counter 133 can be extended without increasing the bit width of the counter 133.

[0320] <18. Eighteenth Implementation>

[0321] In the first embodiment described above, the resistor section 142 is connected to the cathode side of the photoelectric conversion section 141. In the eighteenth embodiment, the resistor section 142 is connected to the anode side of the photoelectric conversion section 141.

[0322] Figure 39 is a block diagram showing a configuration example of an optical pulse response unit according to an eighteenth embodiment.

[0323] In the drawing, the optical pulse response unit 131 ′ includes a photoelectric conversion section 141 , a resistance section 142 , a recharging section 143 , a detection section 144 , and a discharge section 145 . The photoelectric conversion section 141 includes a SPAD 151 . The resistance section 142 includes a resistor 152 .

[0324] Here, the anode and cathode of the SPAD 151 are connected to the resistor 142 and the potential VRH, respectively. That is, the SPAD 151 of the eighteenth embodiment is connected with reverse polarity to the SPAD 151 of the first embodiment.

[0325] Furthermore, in the optical pulse response unit 131′, the recharging section 143 is connected to the ground potential GND instead of the power supply voltage VDD, and the charging control signal XRCG is input to the recharging section 143 instead of the charging control signal RCG. The charging control signal XRCG has the opposite polarity to the charging control signal RCG. The other connections of the optical pulse response unit 131′ are similar to those of the optical pulse response unit 131 of the first embodiment described above.

[0326] At this time, the anode potential VA1 of the SPAD 151 and the potential VA2 of the resistor section 142 change in response to the incidence of photons on the SPAD 151. Then, based on the detection signal AQ of the potential VA2 of the resistor section 142, the discharge section 145 discharges at least some of the charges that can flow out to the photoelectric conversion section 141 to a potential VRL that is smaller than the potential difference VRH from the ground potential GND of the recharging section 143.

[0327] In the eighteenth embodiment described above, based on the potential detection result of the potential VA2 of the resistor section 192 connected in series to the photoelectric conversion section 191, the charge is discharged to the potential VRL, which is lower than the potential VRH of the potential difference from the ground potential GND. With this configuration, compared with the case where the charge remaining after quenching of the SPAD 151 is discharged to the potential VRH via the SPAD 151, power consumption can be reduced.

[0328] In addition, the structure of the 18th embodiment can also be applied to any of the structures of the above-mentioned 1st to 17th embodiments.

[0329] <19. Nineteenth Implementation>

[0330] In the first embodiment described above, charge is discharged to a potential VRL smaller than a potential VRH corresponding to a potential difference from the power supply potential VDD based on the detection signal AQ of the detection unit 144. In this nineteenth embodiment, a light receiving array unit in which a light receiving unit is arranged is provided on an upper chip, and a circuit array unit in which a circuit portion is arranged is provided on a lower chip.

[0331] Figure 40 is a perspective view showing an example in which a stack of pixel array units according to a nineteenth embodiment is stacked.

[0332] In the accompanying drawings, the pixel array unit includes a light receiving array unit 5002 and a circuit array unit 5001. The light receiving array unit 5002 can be stacked on the circuit array unit 5001. The light receiving array unit 5002 includes light receiving sections 5012. The light receiving sections 5012 are arranged in a matrix in the row and column directions. Each light receiving section 5012 can be equipped with a photoelectric conversion section 141, a resistor section 142, a detection section 144, and a discharge section 145. The resistor section 142, the detection section 144, and the discharge section 145 can be formed on the lower layer of the light receiving array unit 5002.

[0333] The circuit array unit 5001 includes circuit sections 5011. The circuit sections 5011 are arranged in a matrix in the row and column directions. The circuit sections 5011 can be arranged in a one-to-one relationship with the light receiving sections 5012. Each circuit section 5011 can be equipped with a recharge section 143, a readout circuit 132, a counter 133, etc.

[0334] The lower chip forming the circuit array unit 5001 and the upper chip forming the light receiving array unit 5002 can be directly bonded together. In this case, the pad electrodes 5021 and 5022 can be formed on the lower chip and the upper chip, respectively. The pad electrode 5021 is connected to the recharging unit 143. The pad electrode 5022 is connected to the photoelectric conversion unit 141, the resistor unit 142, the detection unit 144, and the discharge unit 145. The pad electrodes 5021 and 5022 can be arranged to face each other. For direct bonding between the upper chip and the lower chip, hybrid bonding can be used. In this case, the pad electrodes 5021 and 5022 can be Cu-Cu connected. The junction capacitance of the direct bonding between the lower chip and the upper chip is added to the parasitic capacitance C2. Here, by providing the resistor unit 142 on the lower chip, the parasitic capacitance C2 can be shielded from the photoelectric conversion unit 141 via the resistor unit 142.

[0335] As described above, in the nineteenth embodiment described above, the light receiving array unit 5002 provided with the light receiving portion 5012 is stacked on the circuit array unit 5001 provided with the circuit portion 5011. With this configuration, it is possible to increase the area of ​​the light receiving portion 5012 while suppressing an increase in chip size, and to improve sensitivity while reducing the size of the solid-state imaging device.

[0336] <20. Twentieth Implementation>

[0337] In the above-described nineteenth embodiment, the light receiving array unit 5002 provided with the light receiving section 5012 is stacked on the circuit array unit 5001 provided with the circuit section 5011. In this twentieth embodiment, the light receiving array unit in which the light receiving section equipped with a plurality of light receiving elements is arranged is provided on the upper layer chip, and the circuit array unit in which the circuit section is arranged is provided on the lower layer chip.

[0338] Figure 41 is a perspective view showing an example in which a stack of pixel array units according to a twentieth embodiment is stacked.

[0339] In the accompanying drawings, the pixel array unit includes a light receiving array unit 5102 and a circuit array unit 5101. The light receiving array unit 5102 can be stacked on the circuit array unit 5101. The light receiving array unit 5102 includes a light receiving section 5112. The light receiving sections 5112 are arranged in a matrix in the row direction and the column direction. Each light receiving section 5112 can be equipped with a photoelectric conversion section 141, a resistor section 142, a detection section 144, and a discharge section 145. At this time, each light receiving section 5112 can be equipped with a plurality of photoelectric conversion sections 141. In each light receiving section 5112, the photoelectric conversion section 141 can be arranged in a 2×2 array or a 3×3 array. The resistor section 142, the detection section 144, and the discharge section 145 can be formed on the lower layer of the light receiving array unit 5102.

[0340] The circuit array unit 5101 includes circuit sections 5111. The circuit sections 5111 are arranged in a matrix in the row and column directions. The circuit sections 5111 can be arranged in a one-to-one relationship with the light receiving sections 5112. Each circuit section 5111 can be equipped with a recharge section 143, a readout circuit 132, a counter 133, and the like.

[0341] The lower chip forming the circuit array unit 5101 and the upper chip forming the light receiving array unit 5102 can be directly bonded together. In this case, pad electrodes 5121 and 5122 can be formed on the lower chip and the upper chip, respectively. The pad electrodes 5121 and 5122 can be Cu-Cu connected.

[0342] As described above, in the twentieth embodiment described above, the light receiving array unit 5102, in which the light receiving units 5112 each equipped with a plurality of photoelectric conversion units 141 are arranged, is stacked on the circuit array unit 5101, in which the circuit unit 5111 is arranged. With this configuration, the area of ​​each photoelectric conversion unit 141 can be increased while suppressing an increase in chip size and increasing the light receiving frequency. Therefore, it is possible to improve sensitivity while reducing the size of the solid-state imaging device and increasing the S / N ratio.

[0343] <21. Twenty-first embodiment>

[0344] In the first embodiment described above, the solid-state imaging device is provided with the discharge section 145 that discharges the charge to a potential VRL having a potential difference from the power supply potential VDD smaller than the potential VRH. In this twenty-first embodiment described above, the distance measuring device is provided with the discharge section 145 that discharges the charge to a potential VRL having a potential difference from the power supply potential VDD smaller than the potential VRH.

[0345] Figure 42 is a block diagram showing a configuration example of a distance measuring device according to a twenty-first embodiment.

[0346] In the figure, a distance measuring device 6000 captures a distance image based on, for example, time of flight (ToF). The distance image can be generated from a distance pixel signal based on the distance from the distance measuring device 6000 to the subject 6001 for each pixel in the depth direction.

[0347] The distance measuring device 6000 includes a light emitting device 6100 and an imaging device 6200. The light emitting device 6100 includes a light emitting control unit 6101 and a light emitting unit 6102.

[0348] The light control unit 6101 controls the light irradiation pattern of the light emitting unit 6102 under the control of the control unit 6202. The light emitting unit 6102 emits light in a predetermined wavelength range under the control of the light control unit 6101. The predetermined wavelength range may also include an infrared range. The light emitting unit 6102 may include a laser diode or a light emitting diode.

[0349] The imaging device 6200 receives reflected light for each pixel, which is light emitted from the light emitting device 6100 and reflected by the subject 6001, to generate a distance image. The imaging device 6200 includes an imaging unit 6201, a control unit 6202, a storage unit 6203, and a display unit 6204. The imaging unit 6201 includes an optical system 6211, a light receiving unit 6221, and a signal processing unit 6231. Note that any of the configurations of the first to twentieth embodiments described above can be applied to the imaging unit 6201.

[0350] The optical system 6211 forms an image of incident light on a light receiving surface of the light receiving portion 6221. Note that the optical system 6211 may include a lens, a filter, an aperture, and the like.

[0351] The light receiving unit 6221 receives reflected light from the subject 6001. The light receiving unit 6221 may include a SPAD or a photodiode. Under the control of the control unit 6202, the light receiving unit 6221 receives reflected light from the subject 6001 and provides the resulting pixel signal to the signal processing unit 6231. This pixel signal represents a digital count value obtained by counting the time from the time the light emitting device 6100 emits illumination light to the time the light receiving unit 6221 receives the illumination light. A light emission timing signal indicating the timing of the light emitting unit 6102 emitting light is also provided to the light receiving unit 6221 from the control unit 6202.

[0352] The signal processing unit 6231 processes the pixel signal provided from the light receiving unit 6221 under the control of the control unit 6202. For example, the signal processing unit 6231 detects the distance from each pixel to the object based on the pixel signal provided from the light receiving unit 6221, and generates an image indicating the distance from each pixel to the object. For example, the signal processing unit 6231 obtains the time (count value) from the time when the light emitting unit 6102 emits light to the time when each pixel of the light receiving unit 6221 receives light multiple times for each pixel. The signal processing unit 6231 creates a histogram corresponding to the acquired time. Then, the signal processing unit 6231 measures the time until the light emitted from the light emitting unit 6102 is reflected and returned by the subject 6001 by detecting the peak of the histogram. In addition, the signal processing unit 6231 performs calculations to determine the distance to the object based on the measurement time and the speed of light. The signal processing unit 6231 provides the generated distance image to the control unit 6202.

[0353] The control unit 6202 controls the light-emitting control unit 6101 and the light-receiving unit 6221. For example, the control unit 6202 provides an illumination signal to the light-emitting control unit 6101 and provides a light-emitting timing signal to the light-receiving unit 6221. The light-emitting unit 6102 emits illumination light according to the illumination signal. The light-emitting timing signal can be an illumination signal provided to the light-emitting control unit 6101. In addition, the control unit 6202 provides the distance image obtained from the imaging unit 6201 to the display unit 6204 and causes the display unit 6204 to display the distance image. In addition, the control unit 6202 stores the distance image obtained from the imaging unit 6201 in the storage unit 6203. The control unit 6202 may include a processor, such as a central processing unit (CPU) or a graphics processing unit (GPU). In addition, the control unit 6202 may include a hardware circuit such as an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA).

[0354] The display unit 6204 displays a distance image, a user interface screen, and the like. The display unit 6204 may include a liquid crystal display device or an organic EL display device. The storage unit 6203 stores the distance image, configuration information for distance measurement, and the like. The storage unit 6203 may include a semiconductor memory such as a static random access memory (SRAM) or a dynamic random access memory (DRAM), or may include a storage device such as a hard disk device or a solid-state drive (SSD).

[0355] As described above, in the above-described twenty-first embodiment, the discharge section 145 that discharges charge to a potential VRL lower than the potential VRH is applied to the distance measuring device 6000, and the charge is discharged from the photoelectric conversion section 141 to the potential VRH. This configuration allows the distance measuring device 6000 to perform distance measurement while reducing the power consumption of the light receiving section 6221 during light reception.

[0356] <22. Twenty-second embodiment>

[0357] In the first embodiment described above, based on the detection result of the potential VK2 of the resistor 192 connected in series to the photoelectric converter 191, the charge is discharged to a potential VRL that is less than the potential difference VRH from the power supply potential VDD. In this twenty-second embodiment, based on the result of detecting the photon, the detection node for detecting the photon is connected to the ground potential.

[0358] Figure 43 is a block diagram showing a configuration example of an optical pulse response unit according to a twenty-second embodiment.

[0359] In the drawing, compared with the optical pulse response unit 441 of the fourth embodiment, the optical pulse response unit 501 further includes a latch circuit 511. Other components of the optical pulse response unit 501 of the twenty-second embodiment are similar to those of the optical pulse response unit 441 of the fourth embodiment.

[0360] The readout circuit 132 is connected downstream of the light pulse response unit 501. The inverter 530 is connected downstream of the readout circuit 132.

[0361] In the light pulse response unit 501, a detection node that detects a photon may be provided at the drain of the recharge transistor 433. The latch circuit 511 maintains the detection node where the photon is detected at a constant potential based on the output PLS of the readout circuit 132.

[0362] Latch circuit 511 includes a switching transistor 528. An N-channel field-effect transistor can be used as switching transistor 528. Switching transistor 528 is connected between the drain of recharge transistor 433 and ground potential. The output PLS of readout circuit 132 is input to the gate of switching transistor 528. With this configuration, switching transistor 528 and readout circuit 132 form a feedback loop, allowing the result of photon detection to be stored.

[0363] Here, when the output PLS of the readout circuit 132 rises, the switching transistor 528 turns on, and the gate potential VK3 of the readout transistor 442 is fixed to the ground potential. Furthermore, when the output PLS of the readout circuit 132 is reset based on the active signal INT, the switching transistor 528 turns off. At this time, the detection node where the photon is detected is disconnected from the constant potential, and the optical pulse response unit 501 transitions to the detection standby mode.

[0364] Note that, in the above-described fourth embodiment, an example has been described in which the initialization signal INQ is input to the gate of the anti-punch-through transistor 437 ; however, the anti-punch-through signal EAQ may be input to the gate of the anti-punch-through transistor 437 .

[0365] Inverter 530 inverts the output PLS of readout circuit 132 and outputs the result. Inverter 530 includes a P-channel field-effect transistor 534 and an N-channel field-effect transistor 533. P-channel field-effect transistor 534 and N-channel field-effect transistor 533 are connected in series. Output PLS of readout circuit 132 is input to the gates of P-channel field-effect transistor 534 and N-channel field-effect transistor 533.

[0366] Figure 44 is a timing chart showing the operation of the optical pulse response unit according to the twenty-second embodiment.

[0367] In the accompanying drawings, after initialization by the initialization transistor 436, the initialization signal INQ and the anti-punch-through signal EAQ are set to a low level. Then, when a photon enters the SPAD 151 (t31), the cathode potential VK1 of the SPAD 151 decreases. Then, when quenching occurs in the SPAD 151 in response to the decrease in the cathode potential VK1 of the SPAD 151, the cathode potential VK1 of the SPAD 151 begins to increase (t32). At this time, the gate potential VK3 of the readout transistor 442 decreases, and the output PLS of the readout circuit 132 rises. When the output PLS of the readout circuit 132 rises, the output OUT of the inverter 530 drops. Here, the detection transistor 434 does not work, and the detection signal AQ can be maintained at a low level.

[0368] Furthermore, when the output PLS of the readout circuit 132 rises, the switching transistor 528 turns on, and the gate potential VK3 of the readout transistor 442 is fixed at ground potential. Here, when a photon enters the SPAD 151 again (t33), the cathode potential VK1 of the SPAD 151 decreases. Then, when quenching occurs in the SPAD 151 in response to the decrease in the cathode potential VK1 of the SPAD 151, the cathode potential VK1 of the SPAD 151 begins to increase (t34). At this time, since the gate potential VK3 of the readout transistor 442 is fixed at ground potential, the output PLS of the readout circuit 132 remains at a high level, and the output OUT of the inverter 530 remains at a low level. Then, when the recharge control signal RCG falls (t35), the SPAD 151 is recharged via the resistor 142, and the cathode potential VK1 of the SPAD 151 and the gate potential VK3 of the readout transistor 442 increase. Thereafter, when the initialization signal INT rises (t36), the output PLS of the readout circuit 132 falls. When the output PLS of the readout circuit 132 falls, the output OUT of the inverter 530 rises.

[0369] Figure 45 is a timing chart showing a comparative example of the operation of the optical pulse response unit according to the twenty-second embodiment.

[0370] In the accompanying drawings, it is assumed that the light pulse response unit 501 does not include the latch circuit 511. At this time, when a photon enters the SPAD 151 (t41), the cathode potential VK1 of the SPAD 151 decreases. Then, when quenching occurs in the SPAD 151 in response to the decrease in the cathode potential VK1 of the SPAD 151, the cathode potential VK1 of the SPAD 151 begins to increase (t42). At this time, the gate potential VK3 of the readout transistor 442 decreases, and the output PLS of the readout circuit 132 increases. When the output PLS of the readout circuit 132 increases, the output OUT of the inverter 530 decreases.

[0371] Here, it is assumed that there is leakage in the clamp transistor 432 and the recharge transistor 433. At this time, after the gate potential VK3 of the readout transistor 442 drops, the cathode potential VK1 of the SPAD 151 and the gate potential VK3 of the readout transistor 442 rise, and the output PLS of the readout circuit 132 decreases. Then, as the output PLS of the readout circuit 132 further decreases, the output OUT of the inverter 530 rises. Here, due to the leakage in the clamp transistor 432 and the recharge transistor 433, the detection transistor 434 does not operate, and the detection signal AQ can be maintained at a low level.

[0372] Here, when a photon enters SPAD 151 again (t43), the cathode potential VK1 of SPAD 151 decreases. Then, when quenching occurs in SPAD 151 in response to the decrease in cathode potential VK1 of SPAD 151, cathode potential VK1 of SPAD 151 begins to increase (t44). At this time, the gate potential VK3 of readout transistor 442 decreases, and the output PLS of readout circuit 132 rises. When the output PLS of readout circuit 132 rises, the output OUT of inverter 530 falls. Therefore, in the case where light pulse response unit 501 does not include latch circuit 511, leakage in clamp transistor 432 and recharge transistor 433 leads to photon re-detection and unstable operation.

[0373] As described above, in the twenty-second embodiment, the latch circuit 511 is provided, which maintains the detection node where a photon is detected at a constant potential based on the output PLS of the readout circuit 132. With this configuration, even if there is leakage in the clamp transistor 432 and the recharge transistor 433, photon redetection and unstable operation can be prevented. In addition, even if the detection transistor 434 is not operating, photons can be correctly counted, allowing the detection margin to be increased.

[0374] <23. Twenty-third embodiment>

[0375] In the above-described twenty-second embodiment, the switching transistor 528 is provided to fix the gate potential VK3 of the readout transistor 442 to the ground potential when the output PLS of the readout circuit 132 goes high. In this twenty-third embodiment, the switching transistor is provided to fix the output PLS of the readout circuit 132 to the power supply potential when the output OUT of the inverter 530 goes low.

[0376] Figure 46 is a block diagram showing a configuration example of a pixel to which the light impulse response unit according to the twenty-third embodiment is applied.

[0377] In the drawing, compared with the pixel to which the optical pulse response unit 441 of the fourth embodiment is applied, this pixel further includes a latch circuit 512. Other components of the pixel of the twenty-third embodiment are similar to those of the pixel to which the optical pulse response unit 441 of the fourth embodiment is applied.

[0378] The readout circuit 132 is connected downstream of the light pulse response unit 441. The inverter 530 is connected downstream of the readout circuit 132.

[0379] In this pixel, a detection node where a photon is detected may be provided at the drain of the active transistor 443. The latch circuit 512 maintains the detection node where a photon is detected at a constant potential based on the output OUT of the inverter 530.

[0380] Latch circuit 512 includes a switching transistor 529. A P-channel field-effect transistor can be used as switching transistor 529. Switching transistor 529 is connected in series with readout transistor 442. Output OUT of inverter 530 is input to the gate of switching transistor 529. With this configuration, switching transistor 529 and inverter 530 form a feedback loop and can hold the result of photon detection.

[0381] Here, when the output OUT of the inverter 530 falls, the switch transistor 529 turns on, and the drain of the active transistor 443 is fixed to the ground potential. Furthermore, when the output PLS of the readout circuit 132 is reset based on the active signal INT, the switch transistor 529 turns off. At this time, the detection node where the photon was detected is disconnected from the constant potential, and the optical pulse response unit 441 transitions to the detection standby mode.

[0382] As described above, in the twenty-third embodiment described above, the latch circuit 512 maintains the detection node where a photon is detected at a constant potential based on the output OUT of the inverter 530. With this configuration, even in the presence of leakage in the clamp transistor 432 and the recharge transistor 433, photon redetection and unstable operation can be prevented. Furthermore, even when the detection transistor 434 is not operating, photons can be correctly counted, allowing for an increased detection margin. Furthermore, this eliminates the need to connect the latch circuit 511 to the input of the readout circuit 132, preventing an increase in the input capacitance of the readout circuit 132.

[0383] <24. Twenty-fourth embodiment>

[0384] In the above-mentioned 22nd embodiment, the detection node for detecting photons is connected to the ground potential based on the result of detecting photons. In this 24th embodiment, the detection node for detecting photons is connected to the ground potential based on the result of detecting photons, and recharging is stopped.

[0385] Figure 47 is a block diagram showing a configuration example of an optical pulse response unit according to a twenty-fourth embodiment.

[0386] In the figure, compared with the optical pulse response unit 501 of the twenty-second embodiment, the optical pulse response unit 503 further includes a charge control transistor 523. Other components of the optical pulse response unit 503 of the twenty-fourth embodiment are similar to those of the optical pulse response unit 501 of the twenty-second embodiment.

[0387] The charge control transistor 523 controls the recharging of the photoelectric conversion unit 141 based on the result of photon detection. A P-channel field-effect transistor can be used as the charge control transistor 523. The charge control transistor 523 is connected in series with the switching transistor 528. The source of the charge control transistor 523 is connected to the power supply potential VDD. The output PLS of the readout circuit 132 is input to the gate of the charge control transistor 523.

[0388] Here, when the output PLS of the readout circuit 132 rises, the switch transistor 528 turns on and the charge control transistor 523 turns off. As a result, the gate potential VK3 of the readout transistor 442 is fixed to the ground potential, and recharging of the photoelectric conversion unit 141 stops.

[0389] Furthermore, when the output PLS of the readout circuit 132 is reset based on the active signal INT, the switch transistor 528 is turned off, and the charge control transistor 523 is turned on. At this time, the detection node that has detected a photon is disconnected from the constant potential, the light pulse response unit 503 transitions to the detection standby mode, and the gate potential VK3 of the readout transistor 442 is reset.

[0390] In the twenty-fourth embodiment described above, the charge control transistor 523 controls recharging of the photoelectric converter 141 based on the result of detecting photons. With this configuration, recharging of the photoelectric converter 141 can be stopped when photons are detected, allowing a reduction in the number of elements used for recharging control.

[0391] <25. Twenty-fifth embodiment>

[0392] In the above-described twenty-second embodiment, based on the result of detecting a photon, the detection node for detecting a photon is connected to the ground potential. In this twenty-fifth embodiment, based on the result of detecting a photon, the detection node for detecting a photon is connected to the ground potential, and the readout circuit 132 and the recharging unit 143 are disconnected.

[0393] Figure 48 is a block diagram showing a configuration example of an optical pulse response unit according to a twenty-fifth embodiment.

[0394] In the figure, compared with the optical pulse response unit 501 of the twenty-second embodiment, the optical pulse response unit 504 further includes a blocking transistor 524. Other components of the optical pulse response unit 504 of the twenty-fifth embodiment are similar to those of the optical pulse response unit 501 of the twenty-second embodiment.

[0395] Based on the output PLS of the readout circuit 132, the blocking transistor 524 disconnects the switching transistor 528 from the charging section 143. A P-channel field-effect transistor can be used as the blocking transistor 524. The blocking transistor 524 is connected between the drain of the switching transistor 528 and the drain of the recharge transistor 433. The output PLS of the readout circuit 132 is input to the gate of the blocking transistor 524.

[0396] Here, when the output PLS of the readout circuit 132 rises, the switch transistor 528 turns on and the blocking transistor 524 turns off. As a result, the gate potential VK3 of the readout transistor 442 is fixed to the ground potential, and the switch transistor 528 and the charging portion 143 are disconnected.

[0397] Furthermore, when the output PLS of the readout circuit 132 is reset based on the active signal INT, the switch transistor 528 is turned off, and the blocking transistor 524 is turned on. At this time, the detection node where the photon is detected is disconnected from the constant potential, the switch transistor 528 and the recharge unit 143 are connected, and the light pulse response unit 504 transitions to the detection standby mode.

[0398] In the twenty-fifth embodiment described above, the blocking transistor 524 is provided to disconnect the switching transistor 528 and the charging portion 143 based on the output PLS of the readout circuit 132. With this configuration, the photoelectric converter 141 can be recharged when the detection node detecting a photon is fixed at a constant potential.

[0399] <26. Twenty-sixth embodiment>

[0400] In the tenth embodiment described above, based on the output PLS of the readout circuit 132, charge is discharged to a potential VRL having a potential difference from the power supply potential VDD smaller than the potential VRH. In this twenty-sixth embodiment, the output amplitude of the result of detecting photons is limited, and the reset transistor for resetting the result of detecting photons is placed in an amplitude-limited region to operate at a low voltage.

[0401] Figure 49 is a block diagram showing a configuration example of a pixel to which a light impulse response unit according to a twenty-sixth embodiment is applied.

[0402] In the figure, the optical pulse response unit 505 includes a latch circuit 511 instead of the drain unit 145 of the tenth embodiment. Furthermore, compared to the optical pulse response unit 921 of the tenth embodiment, the optical pulse response unit 505 does not include the clamp transistor 432. Other components of the optical pulse response unit 505 of the twenty-sixth embodiment are similar to those of the optical pulse response unit 921 of the tenth embodiment.

[0403] Furthermore, compared to the pixel to which the optical pulse response unit 921 of the tenth embodiment is applied, this pixel further includes an amplitude limiting transistor 525 and a reset transistor 536. Furthermore, this pixel is equipped with an inverter 530 instead of the buffer 922 of the tenth embodiment. Furthermore, compared to the pixel to which the optical pulse response unit 921 of the tenth embodiment is applied, this pixel does not include an active transistor 443. Other components of the pixel of the twenty-sixth embodiment are similar to those of the pixel to which the optical pulse response unit 921 of the tenth embodiment is applied.

[0404] The recharge transistor 433 and the resistor 152 are connected in series. The gate of the readout transistor 442 is connected to the connection point between the recharge transistor 433 and the resistor 152. The source of the active transistor 441 is connected to the power supply potential VDD. The detection interrupt signal DIS is input to the gate of the active transistor 441. The detection interrupt signal DIS changes its level at the same timing as the initialization signal INT. However, the amplitude of the detection interrupt signal DIS is different from that of the initialization signal INT. For example, the amplitude of the detection interrupt signal DIS may be set to 3V, and the amplitude of the initialization signal INT may be set to 0.8V.

[0405] The switch transistor 528 is connected between the drain of the recharge transistor 433 and the ground potential. The gate of the switch transistor 528 is connected to the drain of the readout transistor 442. At this time, the switch transistor 528 and the readout transistor 442 form a feedback loop and can store the result of detecting photons.

[0406] Note that with this configuration, the switch transistor 528 can also have the same function as the discharge transistor 435 of the above-described embodiment 10. In this case, the switch transistor 528 can discharge charge to the ground potential based on the output PLS of the readout transistor 442.

[0407] Amplitude limiting transistor 525 limits the output amplitude of the result of photon detection. In this case, the output PLS of readout transistor 442 can be used as the output of the result of photon detection. An N-channel field-effect transistor can be used as amplitude limiting transistor 525. Amplitude limiting transistor 525 is connected between the drain of readout transistor 442 and inverter 530. A constant voltage VT1 is applied to the gate of amplitude limiting transistor 525. For example, constant voltage VT1 can be set to 1.5V.

[0408] The reset transistor 536 resets the result of detecting photons. The reset transistor 536 is placed in a region where the amplitude is limited by the amplitude limiting transistor 525. At this time, the reset transistor 536 operates at a lower voltage than the latch circuit 511. For example, the latch circuit 511 can operate at 3V, while the reset transistor 536 can operate at 0.8V. The drain of the reset transistor 536 is connected to the source of the amplitude limiting transistor 525. The active signal INT is applied to the gate of the reset transistor 536. At this time, the amplitude of the output PLS of the readout transistor 442 is limited by the amplitude limiting transistor 525 and applied to the source of the reset transistor 536.

[0409] The light pulse response unit 505, the active transistor 441, the readout transistor 442, and the amplitude limiting transistor 525 are arranged on a first substrate 535. The reset transistor 536 and the inverter 530 are arranged on a second substrate 545. The first substrate 535 may be stacked on the second substrate 545. The first substrate 535 may support high voltage operation, and the second substrate 545 may support low voltage operation.

[0410] Here, when the output PLS of the readout transistor 442 rises, the switch transistor 528 turns on, and the gate potential VK2 of the readout transistor 442 is fixed to the ground potential. Furthermore, when the output PLS of the readout transistor 442 is reset based on the active signal INT, the switch transistor 528 turns off. At this time, the detection node where the photon was detected is disconnected from the constant potential, and the light pulse response unit 505 transitions to the detection standby mode.

[0411] In the twenty-sixth embodiment described above, an amplitude limiting transistor 525 that limits the output amplitude of photon detection and a reset transistor 536 that is placed in the amplitude limiting region and resets the result of detecting photons are provided. This configuration enables the reset transistor 536 to operate at a low voltage, allowing the reset transistor 536 to achieve high-speed operation and allowing the number of elements arranged on the first substrate 535 to be reduced.

[0412] Furthermore, the switching transistor 528 can not only connect the detection node to a constant potential during photon detection, but also discharge charge to the constant potential. Therefore, it is possible to prevent photon re-detection and unstable operation while suppressing an increase in the number of elements in the light pulse response unit 505, and reduce power consumption.

[0413] <27. Twenty-seventh embodiment>

[0414] In the above-described twenty-sixth embodiment, the output amplitude of the result of detecting photons is limited so as to enable the reset transistor 536 to operate at a low voltage. In this twenty-seventh embodiment, the output amplitude of the result of detecting photons is limited so as to enable the reset transistor 536 to operate at a low voltage, and recharging is interrupted based on the result of detecting photons.

[0415] Figure 50 : is a block diagram showing a configuration example of a pixel to which the light impulse response unit according to the twenty-seventh embodiment is applied.

[0416] In the drawing, compared with the optical pulse response unit 505 of the twenty-sixth embodiment, the optical pulse response unit 506 further includes a charge control transistor 526. Other components of the optical pulse response unit 506 of the twenty-seventh embodiment are similar to those of the optical pulse response unit 505 of the twenty-sixth embodiment.

[0417] The charge control transistor 526 controls the recharging of the photoelectric conversion unit 141 based on the result of detecting photons. A P-channel field-effect transistor can be used as the recharge control transistor 526. The charge control transistor 526 is connected in series with the recharge transistor 433. The source of the charge control transistor 526 is connected to the power supply potential VDD. The output PLS of the readout transistor 442 is input to the gate of the recharge control transistor 526.

[0418] The light pulse response unit 506, the active transistor 441, the readout transistor 442, and the amplitude limiting transistor 525 are arranged on a first substrate 536. The reset transistor 536 and the inverter 530 are arranged on a second substrate 545. The first substrate 536 may be stacked on the second substrate 545.

[0419] Here, when the output PLS of the read transistor 442 rises, the switch transistor 528 turns on and the charge control transistor 526 turns off. As a result, the gate potential VK2 of the read transistor 442 is fixed to the ground potential, and recharging of the photoelectric conversion unit 141 stops.

[0420] Furthermore, when the output PLS of the readout transistor 442 is reset based on the active signal INT, the switch transistor 528 is turned off, and the charge control transistor 526 is turned on. At this time, the detection node where the photon was detected is disconnected from the constant potential, the light pulse response unit 506 transitions to the detection standby mode, and recharging of the photoelectric conversion portion 141 is enabled.

[0421] In the twenty-seventh embodiment described above, a recharge control transistor 526 is provided that controls the recharging of the photoelectric converter 141 based on the result of photon detection. With this configuration, recharging of the photoelectric converter 141 can be stopped when a photon is detected, allowing a reduction in the number of elements used for recharge control. In addition, the reset transistor 536 can be made to operate at a low voltage, thereby allowing the reset transistor 536 to achieve high-speed operation.

[0422] <28. Twenty-eighth Implementation Method>

[0423] In the twenty-sixth embodiment, the output amplitude of the result of detecting photons is limited to enable low voltage operation of the reset transistor 536. In the twenty-eighth embodiment, the input amplitude of the recharge unit 143 is limited to enable low voltage operation of the recharge unit 143.

[0424] Figure 51 is a block diagram showing a configuration example of a pixel to which the light impulse response unit according to the twenty-eighth embodiment is applied.

[0425] In the drawing, compared with the optical pulse response unit 505 of the twenty-sixth embodiment, the optical pulse response unit 507 further includes an amplitude limiting transistor 527. Other components of the optical pulse response unit 507 of the twenty-eighth embodiment are similar to those of the optical pulse response unit 505 of the twenty-sixth embodiment.

[0426] Furthermore, in a pixel to which the optical pulse response unit 507 is applied, an amplitude limiting transistor 525 is connected between the readout circuit 132 and the inverter 530 of the twenty-second embodiment. The other components of the pixel to which the optical pulse response unit 507 of the twenty-eighth embodiment is applied are similar to the other components of the pixel to which the optical pulse response unit 505 of the twenty-sixth embodiment is applied.

[0427] Amplitude limiting transistor 527 limits the input amplitude of recharging section 143. A P-channel field-effect transistor can be used as amplitude limiting transistor 527. Amplitude limiting transistor 527 is connected between the drain of recharging transistor 433 and resistor 152. A constant voltage VT2 is applied to the gate of amplitude limiting transistor 527. For example, constant voltage VT2 can be set to 0V.

[0428] At this time, the recharge section 143 can be placed in a region where its amplitude is limited by the amplitude limiting transistor 527. Here, the recharge section 143 can operate at a lower voltage than the latch circuit 511. At this time, the amplitude of the gate potential VK2 of the readout transistor 442 is limited by the amplitude limiting transistor 527 and is input to the recharge transistor 433. Furthermore, the output PLS of the readout circuit 132 has its amplitude limited by the amplitude limiting transistor 525 and is input to the inverter 530.

[0429] The light pulse response unit 507 except the recharging section 143, the readout circuit 132, and the amplitude limiting transistor 525 is disposed on the first substrate 537. The recharging section 143 and the inverter 530 are disposed on the second substrate 547. The first substrate 537 may be stacked on the second substrate 547.

[0430] In the twenty-eighth embodiment described above, an amplitude limiting transistor 527 is provided to limit the input amplitude of the recharging section 143. This configuration enables the recharging section 143 to operate at a low voltage, allows the recharging section 143 to achieve high-speed operation, and allows reduced power consumption.

[0431] <29. Twenty-ninth embodiment>

[0432] In the above-described twenty-sixth embodiment, the output amplitude of the result of detecting photons is limited so that the reset transistor 536 can operate at a low voltage. In the twenty-ninth embodiment, the output amplitude of the result of detecting photons is limited so that the reset transistor 536 can operate at a low voltage, and the input amplitude of the recharge unit 143 is limited so that the recharge unit 143 can operate at a low voltage.

[0433] Figure 52 is a block diagram showing a configuration example of a pixel to which the light impulse response unit according to the twenty-ninth embodiment is applied.

[0434] In the drawing, the pixel includes the optical pulse response unit 507 of the twenty-eighth embodiment, instead of the optical pulse response unit 505 applied to the pixel of the twenty-sixth embodiment. Other components of the pixel involving the optical pulse response unit 507 of the twenty-ninth embodiment are similar to those of the pixel of the twenty-sixth embodiment.

[0435] In the twenty-ninth embodiment described above, an amplitude limiting transistor 525 is provided to limit the output amplitude of the result of detecting photons, and an amplitude limiting transistor 527 is provided to limit the input amplitude of the recharge unit 143. This configuration enables the reset transistor 536 and the recharge unit 143 to operate at a low voltage, allowing the reset transistor 536 and the recharge unit 143 to achieve high-speed operation. In addition, the number of components arranged on the first substrate 538 can be reduced, while reducing power consumption.

[0436] <30. Application Examples of Mobile Entities>

[0437] The technology according to the present disclosure (the present technology) can be applied to various types of products. For example, the technology according to the present disclosure can also be implemented as a device installed on any type of mobile entity (such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, and a robot).

[0438] Figure 53 7000 is a block diagram illustrating an example of a schematic configuration of a vehicle control system 7000 , which is an example of a moving body control system to which the technology according to the embodiment of the present disclosure can be applied.

[0439] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Figure 53 In the illustrated example, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an exterior information detection unit 12030, an interior information detection unit 12040, and an integrated control unit 12050. Furthermore, a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown as functional configurations of the integrated control unit 12050.

[0440] Drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, drive system control unit 12010 functions as a control device to control: a drive force generating device, such as an internal combustion engine or a drive motor, for generating the vehicle's drive force; a drive force transmission mechanism for transmitting the drive force to the wheels; a steering mechanism for adjusting the vehicle's steering angle; and a braking device for generating the vehicle's braking force.

[0441] The body system control unit 12020 controls the operation of various types of devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device to control the following: the keyless entry system, the smart key system, the power windows, or various lights such as the headlights, backup lights, brake lights, turn signals, and fog lights. In this case, the body system control unit 12020 can receive radio waves transmitted from a mobile device that replaces the key or signals from various switches as input. The body system control unit 12020 receives these input radio waves or signals to control the vehicle's door locks, power windows, lights, and other devices.

[0442] The vehicle exterior information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to the imaging unit 12031. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to image the exterior of the vehicle and receives the imaged image. Based on the received image, the vehicle exterior information detection unit 12030 can detect an object (such as a person, vehicle, obstacle, sign, symbol, etc. on the road) or detect the distance to the object.

[0443] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as information about the measured distance. The light received by the imaging unit 12031 can be visible light or invisible light such as infrared light.

[0444] The in-vehicle information detection unit 12040 detects information about the vehicle interior. A driver status detection unit 12041 may be connected to the in-vehicle information detection unit 12040 to detect the driver's condition. Driver status detection unit 12041 may include, for example, a camera that captures the driver's image. Based on the detection information input from driver status detection unit 12041, in-vehicle information detection unit 12040 can calculate the driver's fatigue level or concentration level, or determine whether the driver is dozing off.

[0445] The microcomputer 12051 can calculate control target values ​​for the driving force generation device, the steering mechanism, or the braking device based on information about the interior or exterior of the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control to implement functions of an advanced driver assistance system (ADAS), including collision avoidance or impact cushioning for the vehicle, following driving based on vehicle-to-vehicle distance, speed maintenance driving, vehicle collision warnings, vehicle lane departure warnings, and the like.

[0446] In addition, the microcomputer 12051 can control the driving force generating device, steering mechanism, braking device based on information about the outside or inside of the vehicle obtained by the outside information detection unit 12030 or the inside information detection unit 12040, thereby performing collaborative control intended for automatic driving, etc. that is not dependent on the driver's operation.

[0447] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on information about the exterior of the vehicle obtained by the exterior information detection unit 12030. For example, the microcomputer 12051 can control the headlights to change from high beam to low beam based on the position of a preceding vehicle or an oncoming vehicle detected by the exterior information detection unit 12030, thereby performing cooperative control aimed at preventing glare by controlling the headlights.

[0448] The sound / image output unit 12052 transmits an output signal of at least one of sound and image to an output device, which can notify information to the passengers of the vehicle or the outside of the vehicle in a visual or auditory manner. Figure 53 In the example of FIG, an audio speaker 12061, a display portion 12062, and an instrument panel 12063 are shown as output devices. The display portion 12062 may include, for example, at least one of an in-vehicle display and a head-up display.

[0449] Figure 54 12031 is a diagram showing an example of the installation position of the imaging unit 12031.

[0450] exist Figure 54 , the imaging unit 12031 includes imaging units 12101 , 12102 , 12103 , 12104 and 12105 .

[0451] Imaging units 12101, 12102, 12103, 12104, and 12105 can be positioned on the front nose, sideview mirrors, rear bumper, rear door, and upper portion of the windshield inside the vehicle 12100. Imaging unit 12101 positioned on the front nose and imaging unit 12105 positioned on upper portion of the windshield inside the vehicle primarily capture images of the front of the vehicle 12100. Imaging units 12102 and 12103 positioned on the sideview mirrors primarily capture images of the sides of the vehicle 12100. Imaging unit 12104 positioned on the rear bumper or rear door primarily captures images of the rear of the vehicle 12100. Imaging unit 12105 positioned on upper portion of the windshield inside the vehicle primarily detects vehicles ahead, pedestrians, obstacles, signals, traffic signs, lanes, and the like.

[0452] By the way, Figure 54 Examples of the imaging ranges of the respective imaging units 12101 and 12104 are shown. Imaging range 12111 represents the imaging range of imaging unit 12101, which is located at the front nose. Imaging ranges 12112 and 12113 represent the imaging ranges of imaging units 12102 and 12103, respectively, located at the side mirrors. Imaging range 12114 represents the imaging range of imaging unit 12104, which is located at the rear bumper or rear door. For example, by superimposing the image data captured by imaging units 12101-12104, a bird's-eye view image of vehicle 12100 viewed from above can be obtained.

[0453] At least one of the imaging units 12101-12104 may have a function of obtaining distance information. For example, at least one of the imaging units 12101-12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0454] For example, based on the distance information obtained from the imaging units 12101-12104, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging ranges 12111-12114 and the temporal change in that distance (relative speed to the vehicle 12100), thereby extracting the closest three-dimensional object as the leading vehicle, specifically one that is located on the driving path of the vehicle 12100 and is traveling at a predetermined speed (e.g., equal to or greater than 0 km / h) in substantially the same direction as the vehicle 12100. Furthermore, the microcomputer 12051 can pre-set a following distance to be maintained from the leading vehicle and execute automatic braking control (including following parking control), automatic acceleration control (including following starting control), etc. Thus, it is possible to execute cooperative control for automatic driving, etc., that is, independent of the driver's operation.

[0455] For example, based on the distance information obtained from the imaging units 12101-12104, the microcomputer 12051 can classify 3D object data regarding 3D objects into 3D object data for two-wheeled vehicles, standard-sized vehicles, large vehicles, pedestrians, utility poles, and other 3D objects. The microcomputer 12051 can then extract the classified 3D object data for automatic obstacle avoidance. For example, the microcomputer 12051 can determine whether obstacles around the vehicle 12100 are visually recognizable by the driver of the vehicle 12100 or obstacles that are difficult for the driver to visually identify. The microcomputer 12051 then determines a collision risk, indicating the risk of collision with each obstacle. If the collision risk is equal to or greater than a set value, indicating the possibility of a collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display unit 12062, and the drive system control unit 12010 executes forced deceleration or evasive steering. Thus, the microcomputer 12051 can assist in driving to avoid collisions.

[0456] At least one of the imaging units 12101-12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can identify pedestrians by determining whether a pedestrian exists in the images captured by the imaging units 12101-12104. This pedestrian recognition is performed, for example, by a program that extracts characteristic points from the images captured by the imaging units 12101-12104, which are infrared cameras, and a program that determines whether a pedestrian exists by performing pattern matching on a series of characteristic points representing the object's outline. When the microcomputer 12051 determines that a pedestrian exists in the images captured by the imaging units 12101-12104 and identifies the pedestrian, the audio / video output unit 12052 controls the display unit 12062 to display a square outline superimposed on the recognized pedestrian to emphasize the recognized pedestrian. The audio / video output unit 12052 can also control the display unit 12062 to display an icon representing the pedestrian at a desired location.

[0457] An example of a vehicle control system to which the technology of the present disclosure can be applied has been described above. For example, the technology of the present disclosure can be applied to the vehicle exterior information detection unit 12030 and the imaging unit 12031, among the aforementioned components. Specifically, for example, the imaging device 100 described above can be applied to the imaging unit 12031. Furthermore, the distance measuring device 6000 described above can be applied to the vehicle exterior information detection unit 12030. By applying the technology of the present disclosure to the vehicle control system 12000, the power required during imaging can be reduced.

[0458] It should be noted that the above-mentioned embodiments illustrate examples for embodying the present technology, and the matters in the embodiments and the matters specifying the present invention in the claims have a corresponding relationship. Similarly, the matters specifying the present invention in the claims have a corresponding relationship with the matters with the same names in the embodiments of the present technology. However, the present technology is not limited to the embodiments, and can be implemented by making various modifications to the embodiments without departing from the scope of the present technology. In addition, the effects described in this specification are merely examples and are not limited, and other effects can be provided.

[0459] It should be noted that the present technology can also have the following configurations.

[0460] (1) A light detection device comprising:

[0461] a photoelectric conversion portion having a first electrode connected to a first potential, the photoelectric conversion portion being configured to multiply charges generated from photons;

[0462] a resistor portion connected in series to a second electrode opposite to the first electrode of the photoelectric conversion portion;

[0463] a recharging unit that recharges the photoelectric conversion unit via the resistance unit; and

[0464] The discharge portion is connected to the resistor portion and to a second potential, wherein the second potential has a potential difference smaller than the first potential from a side opposite to the charging portion connected to the resistor portion.

[0465] (2) The light detection device according to (1) above, wherein

[0466] The resistance portion has a higher resistance than the photoelectric conversion portion.

[0467] (3) The light detection device according to (1) or (2) above, wherein

[0468] The charging section charges the photoelectric conversion section based on a detection result of the potential of the resistance section.

[0469] (4) The light detection device according to (1) or (2) above, wherein

[0470] The charging section charges the photoelectric conversion section based on a control signal received from the outside.

[0471] (5) The light detection device according to (4) above, wherein

[0472] The control signal serves as a periodic signal.

[0473] (6) The light detection device according to (5) above, wherein

[0474] The control signal includes a plurality of control signals having different periods, and

[0475] Whether or not to discharge the charge from the discharge section is determined in each cycle.

[0476] (7) The light detection device according to any one of (1) to (6) above, further comprising:

[0477] The detection unit detects the potential of the resistor unit.

[0478] (8) The light detection device according to (7), further comprising:

[0479] The readout circuit reads out the result of photon detection by the photoelectric conversion unit from the input side of the detection unit.

[0480] (9) The light detection device according to (7) above, further comprising:

[0481] The readout circuit reads out the result of photon detection by the photoelectric conversion unit from the output side of the detection unit.

[0482] (10) The light detection device according to any one of (7) to (9) above, further comprising:

[0483] The amplitude limiting transistor is connected between the detection unit and the discharge unit, and is configured to limit the output amplitude of the detection unit.

[0484] (11) The light detection device according to any one of (7) to (10) above, further comprising:

[0485] The initialization transistor is connected in series to the output side of the detection portion, and is configured to initialize the output of the detection portion.

[0486] (12) The light detection device according to any one of (7) to (11) above, further comprising:

[0487] The anti-punch-through transistor prevents a punch-through current from flowing through the detection portion.

[0488] (13) The light detection device according to any one of (7) to (12) above, further comprising:

[0489] The clamp transistor blocks the potential of the resistor portion from being input to a readout circuit that reads the result of photon detection.

[0490] (14) The light detection device according to any one of (7) to (13) above, further comprising:

[0491] an anti-punch-through transistor, the anti-punch-through transistor preventing a punch-through current from flowing through the detection portion;

[0492] an initialization transistor connected in series to an output side of the detection portion, the initialization transistor being configured to initialize the output of the detection portion; and

[0493] The clamp transistor blocks the potential of the resistor portion from being input to a readout circuit for reading out the result of photon detection.

[0494] At least one of the anti-punch-through transistor, the initialization transistor, or the clamp transistor is shared among the plurality of pixels.

[0495] (15) The light detection device according to any one of (7) to (14) above, further comprising:

[0496] an anti-punch-through transistor that prevents a punch-through current from flowing through the detection portion; and

[0497] an initialization transistor connected in series to the output side of the detection portion, the initialization transistor being configured to initialize the output of the detection portion, wherein

[0498] At least one of the anti-punch-through transistor or the initialization transistor includes a driver that limits input amplitude.

[0499] (16) The light detection device according to any one of (7) to (15) above, further comprising:

[0500] The resistor is connected between the charging unit and the resistance unit.

[0501] (17) The light detection device according to any one of (7) to (16), further comprising:

[0502] a first substrate in which at least one of a recharging portion, a readout circuit that reads out a result of detecting photons, or a counter that performs counting based on a readout result of the readout circuit is formed; and

[0503] A second substrate, in which the photoelectric conversion portion, the resistance portion, the detection portion, and the discharge portion are formed, is stacked on the first substrate.

[0504] (18) The light detection device according to any one of (7) to (16), further comprising:

[0505] a first substrate in which at least one of a recharging portion, a readout circuit that reads out a result of detecting photons, or a counter that performs counting based on a readout result of the readout circuit is formed;

[0506] a second substrate having a resistor portion, a detection portion, and a discharge portion formed thereon, the second substrate being stacked on the first substrate; and

[0507] A third substrate having a photoelectric conversion portion formed thereon is stacked on the second substrate.

[0508] (19) The light detection device according to any one of (7) to (18) above, further comprising:

[0509] a low breakdown voltage region in which a low breakdown voltage transistor is formed; and

[0510] A high breakdown voltage region, in which high breakdown voltage transistors are formed, the high breakdown voltage regions being arranged adjacent to each other across a plurality of pixels, wherein

[0511] The detection portion and the discharge portion are formed in a high breakdown voltage region.

[0512] (20) The light detection device according to (1) above further includes:

[0513] The readout circuit reads out the result of the detected photons, where

[0514] The discharge unit discharges at least a portion of the charge that can flow out to the photoelectric conversion unit to a second potential lower than the first potential based on the output of the readout circuit.

[0515] (21) The light detection device according to any one of (1) to (20) above, further comprising:

[0516] The latch circuit latches the detection result of the photon.

[0517] (22) The light detection device according to (21) above, wherein:

[0518] The latch circuit includes a switching transistor that connects a detection node where the photon is detected to a constant potential based on a result of detecting the photon.

[0519] (23) The light detection device according to (22) above, wherein:

[0520] The result of detecting the photon is input to the gate of the switching transistor for retention.

[0521] (24) The light detection device according to (22) or (23), further comprising:

[0522] The blocking transistor disconnects the switching transistor and the charging section based on the potential of the detection node.

[0523] (25) The light detection device according to any one of (21) to (24) above, wherein

[0524] The recharging unit recharges the photoelectric conversion unit based on the potential of the detection node.

[0525] (26) The light detection device according to any one of (21) to (25) above, further comprising:

[0526] a first amplitude limiting transistor that limits the output amplitude of a photon detection result; and

[0527] Reset transistor, reset the result of detecting photons, where

[0528] The reset transistor is placed in a region where the amplitude is limited by the first amplitude limiting transistor to operate at a low voltage compared with the latch circuit.

[0529] (27) The light detection device according to any one of (21) to (26) above, further comprising:

[0530] The charge control transistor controls recharging of the photoelectric conversion portion based on a result of detecting photons.

[0531] (28) The light detection device according to any one of (21) to (27) above, further comprising:

[0532] The second amplitude limiting transistor limits the input amplitude of the recharge unit, wherein

[0533] Compared to the latch circuit, the recharging section is placed in a region where the amplitude is limited by the second amplitude limiting transistor to operate at a low voltage.

[0534] Reference Symbol List

[0535] 100 Imaging Device

[0536] 101 Optical System

[0537] 102 Solid-state imaging device

[0538] 103 Imaging Control Unit

[0539] 104 Image Processing Unit

[0540] 105 storage units

[0541] 106 display units

[0542] 107 operating unit

[0543] 108 bus

[0544] 111 pixel array unit

[0545] 112 line scanning circuit

[0546] 113 column processing circuit

[0547] 114 Control signal generation circuit

[0548] 115 frame memory

[0549] 121 pixels

[0550] 122, 155 switches

[0551] 131 Optical Pulse Response Unit

[0552] 132 Readout Circuit

[0553] 133 Counter

[0554] 141 Photoelectric Conversion Unit

[0555] 142 Resistor

[0556] 143 Recharging Unit

[0557] 144 Testing Department

[0558] 145 discharge unit

[0559] 151SPAD

[0560] 152 resistor< / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A light detection device, comprising: a photoelectric conversion portion having a first electrode connected to a first potential, the photoelectric conversion portion being configured to multiply charges generated from photons; a resistor portion connected in series to a second electrode opposite to the first electrode of the photoelectric conversion portion; a recharging unit that recharges the photoelectric conversion unit via the resistor unit; as well as The discharge portion is connected to the resistor portion and a second potential having a smaller potential difference than the first potential from a potential opposite to a side of the recharge portion connected to the resistor portion.

2. The light detection device according to claim 1, wherein The resistance portion has a higher resistance than the photoelectric conversion portion.

3. The light detection device according to claim 1, wherein The recharging section recharges the photoelectric conversion section based on a detection result of the potential of the resistance section.

4. The light detection device according to claim 1, wherein The recharging section recharges the photoelectric conversion section based on a control signal received from the outside.

5. The light detection device according to claim 4, wherein The control signal serves as a periodic signal. The light detection device according to claim 5 , wherein: The control signal includes a plurality of control signals having different periods, and Whether or not to discharge the charge from the discharge section is determined for each cycle.

7. The light detection device according to claim 1, further comprising: The detection unit detects the potential of the resistor unit.

8. The light detection device according to claim 7, further comprising: The readout circuit reads out a result of detection of the photon by the photoelectric conversion unit from an input side of the detection unit.

9. The light detection device according to claim 7, further comprising: The readout circuit reads out the result of the detection of the photon by the photoelectric conversion unit from the output side of the detection unit.

10. The light detection device according to claim 7, further comprising: An amplitude limiting transistor is connected between the detection unit and the discharge unit, and is configured to limit an output amplitude of the detection unit.

11. The light detection device according to claim 7, further comprising: An initialization transistor is connected in series to an output side of the detection section, and is configured to initialize an output of the detection section.

12. The light detection device according to claim 7, further comprising: The anti-punch-through transistor prevents a punch-through current from flowing through the detection unit.

13. The light detection device according to claim 7, further comprising: The clamp transistor blocks the potential of the resistor portion from being input to a readout circuit for reading out a result of detection of the photon.

14. The light detection device according to claim 7, further comprising: an anti-punch-through transistor to prevent a punch-through current from flowing through the detection portion; an initialization transistor connected in series to an output side of the detection section, the initialization transistor being configured to initialize an output of the detection section; as well as The clamp transistor blocks the potential of the resistor portion from being input to a readout circuit for reading out the detection result of the photon, wherein At least one of the anti-punch-through transistor, the initialization transistor, or the clamp transistor is shared among a plurality of pixels.

15. The light detection device according to claim 7, further comprising: an anti-punch-through transistor to prevent a punch-through current from flowing through the detection portion; as well as an initialization transistor connected in series to the output side of the detection section, wherein the initialization transistor is configured to initialize the output of the detection section, At least one of the anti-punch-through transistor or the initialization transistor includes a driver that limits input amplitude.

16. The light detection device according to claim 7, further comprising: A resistor is connected between the recharging unit and the resistance unit.

17. The light detection device according to claim 7, further comprising: a first substrate on which at least one of the recharging portion, a readout circuit that reads out a result of detection of the photons, or a counter that performs counting based on a result of readout by the readout circuit is formed; as well as a second substrate on which the photoelectric conversion portion, the resistance portion, the detection portion, and the discharge portion are formed, the second substrate being stacked on the first substrate.

18. The light detection device according to claim 7, further comprising: a first substrate on which at least one of the recharging portion, a readout circuit that reads out a result of detection of the photons, or a counter that performs counting based on a result of readout by the readout circuit is formed; a second substrate on which the resistor portion, the detection portion, and the discharge portion are formed, the second substrate being stacked on the first substrate; as well as A third substrate on which the photoelectric conversion portion is formed is stacked on the second substrate.

19. The light detection device according to claim 2, further comprising: a low breakdown voltage region in which a low breakdown voltage transistor is formed; as well as a high breakdown voltage region in which high breakdown voltage transistors are formed, the high breakdown voltage regions being arranged adjacent to each other across a plurality of pixels, wherein The detection portion and the discharge portion are formed in the high breakdown voltage region.

20. The light detection device according to claim 1, further comprising: A readout circuit reads out the detection result of the photon, wherein: The discharge section discharges at least a portion of the charge that can flow out to the photoelectric conversion section to a second potential lower than the first potential based on the output of the readout circuit.

21. The light detection device according to claim 1, further comprising: A latch circuit latches the detection result of the photon.

22. The light detection device according to claim 21, wherein The latch circuit includes a switching transistor that connects a detection node where the photon is detected to a constant potential based on a result of the detection of the photon.

23. The light detection device according to claim 22, wherein The detection result of the photon is input to the gate of the switching transistor to be retained.

24. The light detection device according to claim 22, further comprising: The blocking transistor disconnects the switching transistor and the recharging unit based on the potential of the detection node.

25. The light detection device according to claim 21, wherein The recharging unit recharges the photoelectric conversion unit based on the potential of the detection node.

26. The light detection device according to claim 21, further comprising: a first amplitude limiting transistor, for limiting the output amplitude of the detection result of the photon; as well as A reset transistor is used to reset the detection result of the photon, wherein The reset transistor is placed in a region where the amplitude is limited by the first amplitude limiting transistor to operate at a low voltage compared with the latch circuit.

27. The light detection device according to claim 21, further comprising: A recharge control transistor controls recharging of the photoelectric conversion portion based on a result of detecting the photon.

28. The light detection device according to claim 21, further comprising: The second amplitude limiting transistor limits the input amplitude of the recharging unit, wherein The recharging section is placed in a region where the amplitude is limited by the second amplitude limiting transistor to operate at a low voltage compared with the latch circuit.

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