Interference suppression circuit for alternating current measurement

Abstract

The invention provides an interference suppression circuit for alternating current measurement, which belongs to the technical field of electrical variable measurement and comprises a current loop and a measurement loop. The current loop comprises a voltage signal source which is used for outputting a voltage signal with frequency fa; the first overturning circuit is controlled to overturn and output the signal according to a set period; a tested product is connected between the first turnover circuit and the ground end; the measurement loop comprises a second flip circuit which receives and amplifies the measurement signals at the two ends of the measured object and is controlled to flip and output the signals according to the frequency fa and a set period; the second low-pass filter is connected with the output end of the second flip circuit; and the analog-to-digital converter is connected with the output end of the second low-pass filter. According to the interference suppression circuit for alternating current measurement, useful signals can be reserved, and interference components can be filtered out. According to the invention, the current flowing through the tested product is constant, the voltage generated on the tested product does not fluctuate any more, and the measured value of the resistance value of the tested product does not fluctuate.

Description

Technical Field

[0001] The present invention belongs to the technical field of measuring electric variables, and in particular relates to an interference suppression circuit for AC measurement. Background Art

[0002] When testing AC resistance, the resistance of the resistor is determined by passing an AC current with a fixed frequency and fixed RMS value through the resistor and measuring the resulting AC voltage Vin. However, if there is an interference source with a frequency close to the test frequency near the AC resistance tester, the interfering voltage signal Ven will couple to the AC voltage Vin, and both the interference signal and the desired signal will be amplified by the inversion circuit. The closer the frequencies of the desired and interference signals, the longer the fluctuation period, which will affect the stability of the measurement results. Summary of the Invention

[0003] In order to solve the technical problem that existing AC measurement is easily interfered by interference signals with similar frequencies, the present invention proposes an interference suppression circuit for AC measurement, which can solve the above problem.

[0004] In order to solve the above technical problems, the present invention adopts the following technical solutions: An interference suppression circuit for AC measurement, comprising a current loop and a measurement loop; The current loop includes: A voltage signal source, configured to output a voltage signal having a frequency fa; A first inversion circuit is used to receive the output signal of the voltage signal source, amplify it, and invert and output the signal according to a set period under control; The product under test is connected between the first flip circuit and the ground terminal; The measurement circuit comprises: a second flipping circuit, which receives the measurement signal from both ends of the measured product, amplifies it, and is controlled to flip and output the signal according to the set period; a second low-pass filter connected to the output end of the second flip circuit; An analog-to-digital converter is connected to the output end of the second low-pass filter and is used to perform analog-to-digital conversion on the signal output by the second low-pass filter and then send the converted signal to the processor.

[0005] Compared with the prior art, the present invention offers the following advantages and positive effects: The interference suppression circuit for AC measurement of the present invention comprises a voltage signal source outputting a voltage signal of a specific frequency fa. This voltage signal generates a current that flows through the device under test, generating an AC voltage signal Vin. As Vin continues to propagate backward, it introduces an interference signal Ven with a similar frequency. This scheme employs a first flipping circuit that is controlled to flip the output signal according to a set period, thereby inverting the phase of the AC voltage Vin generated when it passes through the device under test. A second flipping circuit controls the input signal flipping based on the frequency of the voltage signal fa from the voltage signal source, flipping signals less than 0 to positive values. This flipping is synchronized with the flipping period of the first flipping circuit, maintaining a positive output signal. Because the interference signal Ven is externally introduced, it is only inverted once by the second flipping circuit. Therefore, the interference signal output by the second flipping circuit alternates between positive and negative signals for one set period. When a processor averages the signal using the two set periods as a calculation period T, the useful signal is retained and the interference component is eliminated. Consequently, the voltage value of Vin is no longer subject to fluctuation. The resistance of an AC resistor is related to the voltage and current across it. In the present invention, the current flowing through the measured product is constant, and the voltage generated across it no longer fluctuates, so the measured resistance value of the measured product also does not fluctuate.

[0006] Other features and advantages of the present invention will become more apparent after reading the detailed description of the embodiments of the present invention in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 This is a principle block diagram of an embodiment of an interference suppression circuit for AC measurement proposed by the present invention; Figure 2 This is a schematic diagram of an embodiment of an interference suppression circuit for AC measurement proposed by the present invention; Figure 3 This is an output signal waveform diagram of an embodiment of the interference suppression circuit for AC measurement proposed by the present invention. DETAILED DESCRIPTION

[0008] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0009] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0010] It should be noted that, in the description of the present invention, the terms "upper", "lower", "left", "right", "vertical", "horizontal", "inside", "outside" and the like indicating directions or positional relationships are based on the directions or positional relationships shown in the accompanying drawings. This is merely for the convenience of description and does not indicate or imply that the device or element must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it cannot be understood as a limitation on the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0011] In the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," "connect," "fixed," etc. should be understood broadly. For example, they may refer to fixed connection, detachable connection, or integration; mechanical connection or electrical connection; direct connection or indirect connection through an intermediate medium; internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0012] Example 1, see Figure 1 As shown, an interference suppression circuit for AC measurement includes a current loop and a measurement loop.

[0013] The current loop includes a voltage signal source and a first inversion circuit, wherein the voltage signal source is used to output a voltage signal with a frequency fa.

[0014] The first inversion circuit is used to receive the output signal of the voltage signal source, amplify it, and be controlled to invert and output the signal according to a set period.

[0015] The product under test is connected between the first flip circuit and the ground terminal to form a current loop. The current in the loop flows through the product under test, and an AC voltage is generated at both ends of the product under test.

[0016] The measurement loop includes a second inversion circuit, a second low-pass filter and an analog-to-digital converter.

[0017] The second inversion circuit receives the voltage signal at both ends of the measured product, that is, the measurement signal, amplifies it, and is controlled to invert and output the signal according to a set period.

[0018] The second low-pass filter is connected to the output end of the second flip circuit and is used to filter out the inverted interference signal while allowing the useful signal to pass normally.

[0019] The analog-to-digital converter is connected to the output end of the second low-pass filter and is used to perform analog-to-digital conversion on the signal output by the second low-pass filter and then send the converted signal to the processor, which calculates the resistance value of the product under test.

[0020] This embodiment of the interference suppression circuit for AC measurement uses a voltage signal source that outputs a voltage signal of a specific frequency fa. This voltage signal generates a current that flows through the device under test, generating an AC voltage signal Vin. As Vin continues to propagate, it introduces an interference signal Ven with a similar frequency. This solution employs a first flipping circuit that is controlled to flip the output signal according to a set period. This results in a phase inversion of the AC voltage Vin generated when it passes through the device under test. A second flipping circuit is provided that controls the flipping of signals less than 0 to positive values ​​based on the frequency of the voltage signal fa from the voltage signal source. This circuit also performs synchronous conversion based on the flipping period of the first flipping circuit, maintaining a positive output signal. Because the interference signal Ven is externally introduced, it is only inverted once by the second flipping circuit. Therefore, the interference signal output by the second flipping circuit alternates between positive and negative signals for one set period. If a processor averages the signal using the two set periods as a calculation period T, the useful signal is retained and the interference component is eliminated. Consequently, the voltage value of Vin is no longer subject to fluctuation. The resistance of an AC resistor is related to the voltage and current across it. In the present invention, the current flowing through the measured product is constant, and the voltage generated across it no longer fluctuates, so the measured resistance value of the measured product also does not fluctuate.

[0021] The interference suppression circuit of this embodiment is particularly suitable for suppressing interference signals having a frequency similar to or identical to the voltage signal output by the voltage signal source.

[0022] In some embodiments, Figure 2 As shown, the first flip circuit includes a second non-inverter, a second inverter, a second transfer switch and a counter.

[0023] The counter is controlled by the processor. Different states of control signal CTRL4 enable or disable the counter. When enabled, the counter begins counting based on signal CTRL6, changing the state of output signal S29 every time it reaches halfway through the processor's calculation cycle. When the counter is disabled, the second switch also has a default state. In this default state, signal S26 and the output pin of the second switch are conductive.

[0024] Input terminals of the second non-inverting element and the second inverter are respectively connected to output terminals of the voltage signal source.

[0025] The second isotropic transistor receives the voltage signal output by the voltage signal source, and performs isotropic amplification and output.

[0026] The second inverter receives the voltage signal output by the voltage signal source, performs reverse amplification and outputs the voltage signal.

[0027] The second switching switch has a common terminal serving as an output terminal, and two movable points of the second switching switch are connected to the output terminals of the second isocoupler and the second inverter, respectively. The second switching switch is controlled to connect the second isocoupler to the output terminal, or to connect the second inverter to the output terminal. Because the signals output by the second isocoupler and the second isocoupler have the same frequency but opposite phases, by controlling the second isocoupler to output the signal externally or the second inverter to output the signal externally at different times, the signal is inverted and output according to the set period.

[0028] The processor outputs a control signal containing information about the calculation period T to the counter. The counter counts according to the control signal and changes the state of the output signal every time the counter counts to T / 2. The output signal of the counter is used to control the gating state of the second conversion switch.

[0029] By controlling the output signal state to change once every T / 2 count, and because the interference signal and the useful signal have similar frequencies, the state of the second switching switch is controlled to control the output of the second inverter for signals less than 0 and the output of the second isotropic diode for signals greater than 0. The useful signal output is converted into a useful DC signal greater than 0 after a second low-pass filter. After the second low-pass filter, the interference signal output by the second switching switch is an interference DC signal greater than 0 during the first 0.5T period and less than 0 during the second 0.5T period, with the absolute values ​​of the amplitudes being equal. The processor averages the received signals according to the calculation period T. The received signal S17 includes a digital quantity related to the interference k*Ven and a digital quantity related to the useful signal k*Vin. As can be seen from the foregoing, the amplitude of the digital quantity related to the interference is opposite from that during the period from 0T to 0.5T to 1T, while the amplitude of the digital quantity related to the useful signal is the same during the two periods. Therefore, when the processor averages signal S17 according to calculation period T, the useful signal is retained, and interference components with the same or similar frequencies as the useful signal are eliminated. Consequently, the measured voltage value of Vin will no longer fluctuate. The resistance of an AC resistor is related to the voltage and current across it. In the present invention, the current flowing through the AC resistor is constant, and the voltage generated across it does not fluctuate, so the measured resistance value of the AC resistor does not fluctuate either.

[0030] In some embodiments, the interference suppression circuit further includes a first low-pass filter, which receives the signal output by the second conversion switch, performs low-pass filtering on the signal, and then outputs the signal.

[0031] In some embodiments, the current loop also includes a power amplifier, which receives the signal output by the first low-pass filter for power amplification and outputs the current I to the current input terminal C+. One of the two ends of the product under test is respectively connected to the current input terminal C+ and the current output terminal C-, and the current output terminal C- is connected to the ground terminal.

[0032] In some embodiments, the interference suppression circuit further includes a standard resistor, an operational amplifier circuit, a sampling resistor, and a phase shift compensation circuit.

[0033] One of the two ends of the standard resistor is connected to the current input terminal C+ and the current output terminal C- through a switch, and the other is connected to the measurement positive terminal S+ and the measurement negative terminal S- of the measurement circuit through a switch. One of the two ends of the measured product is connected to the current input terminal C+ and the current output terminal C- through a switch, and the other is connected to the measurement positive terminal S+ and the measurement negative terminal S- of the measurement circuit through a switch. The conduction state of the switch is controlled by the processor and is used to connect the standard resistor to the current loop and the measurement loop, or to connect the measured product to the current loop and the measurement loop. When the standard resistor is connected to the current loop and the measurement loop, the processor generates a phase modulation control signal according to the received signal.

[0034] The non-inverting input terminal of the operational amplifier circuit receives the signal output by the first flip circuit, and the output terminal of the operational amplifier circuit is connected to the input terminal of the power amplifier.

[0035] One end of the sampling resistor is connected to the current output terminal C-, and the other end is connected to the ground terminal. The sampling resistor outputs the sampling signal to the inverting input terminal of the operational amplifier circuit.

[0036] The phase shift compensation circuit receives the signal output by the first low-pass filter, performs zero-crossing detection on the signal to generate a square wave signal, and delays the phase of the square wave signal according to the phase modulation control signal. The delayed signal is used to control the flip output of the second flip circuit.

[0037] In some embodiments, the phase shift compensation circuit includes a zero-crossing comparator and a phase modulation circuit.

[0038] The input end of the zero-crossing comparator is connected to the output end of the first low-pass filter, and performs zero-crossing detection on the received signal to generate a square wave signal and output it.

[0039] The phase modulation circuit receives the square wave signal and the phase modulation control signal, and delays the phase of the square wave signal according to the phase modulation control signal. The output end of the phase modulation circuit is connected to the control end of the second flip circuit.

[0040] In some embodiments, the second flip circuit includes an amplifier circuit, a third non-inverter, a third inverter, and a third conversion switch.

[0041] The two input terminals of the amplifier circuit are respectively connected to the measurement positive terminal S+ and the measurement negative terminal S-.

[0042] The third isotropic transistor receives the output signal of the amplifier circuit, performs isotropic amplification and outputs the signal.

[0043] The third inverter receives the output signal of the amplifier circuit, performs inverse amplification and outputs it.

[0044] The common end of the third conversion switch is the output end, the two moving points of the third conversion switch are respectively connected to the output ends of the third isotropic device and the third inverter, and the control end of the third conversion switch is connected to the output end of the phase modulation circuit.

[0045] One of the moving points of the third conversion switch is connected to the output end of the third isochronous device, and the other moving point is connected to the output end of the third inverter. The control end of the third conversion switch is connected to the output end of the phase modulation circuit.

[0046] The output signal S28 of the second switch is connected to the input of the first low-pass filter. After passing through the output of the first low-pass filter, signal S30 is an AC signal with a frequency fa. Signal S30 is connected simultaneously to the input pin of the zero-crossing comparator and the non-inverting input pin of the op amp circuit. The zero-crossing comparator outputs a square wave signal S32 with high and low voltage amplitudes. The inverting input pin of the op amp circuit is connected to the ungrounded end of the sampling resistor (GND1 network). The output of the op amp circuit is connected to the power amplifier. The output current I of the power amplifier flows through point A, through the standard resistor, to point C, and then through the sampling resistor to the GND1 network. The frequency of current I is fa.

[0047] Due to the virtual short circuit concept of the op amp circuit, the voltage across the sampling resistor is equal to the voltage of signal S30. The sampling resistor has a constant resistance, so the current flowing through the sampling resistor is equal to the ratio of the voltage of signal S30 to the resistance of the sampling resistor. Due to the virtual short circuit concept of the op amp circuit, the phase of current I flowing through the sampling resistor is the same as the phase of signal S30. Therefore, the phase of signal S32 output by the zero-crossing comparator is the same as the phase of current I. Signal S32 is connected to the input pin of the high-speed isolator, which in turn outputs signal S18. Signal S18 is input to the signal input pin of the phase modulation circuit. Signal S13 output by the phase modulation circuit serves as the control signal for the switch state control pin of the third conversion switch. When signal S13 is high, the third conversion switch conducts signals S11 and S15. When signal S13 is low, the third conversion switch conducts signals S12 and S15.

[0048] The phase of signal S18 is the same as that of current I, but the input signal of the amplifier circuit undergoes some phase shift when passing through the amplifier circuit and the third isotropic transistor or the third inverter. Therefore, it is necessary to compensate for this phase shift by adjusting the phase between signal S18 and signal S13. Otherwise, there will be a phase difference between signal S13 and signals S11 and S12, and the signal output by the third switch will be incorrect.

[0049] When calculating the phase difference for the first time, a standard resistor needs to be connected to the measurement circuit and the current circuit, but the DUT should not be connected.

[0050] When a standard resistor is connected to the measurement circuit and the current loop, signal Vin is the AC voltage generated by the current on the standard resistor. If the phase between signal S18 and signal S13 does not match the phase shift introduced by the measurement conditioning circuit, the digital value k*Vin obtained by the processor will be too small. This is because there is a phase difference between signal S13 and signals S11 and S12. Therefore, when measuring the amplitude of the AC voltage signal Vin, the processor needs to continuously change the phase delay of the phase modulation circuit until the digital value k*Vin obtained by the processor is the maximum value, at which point the angle between the voltage phase and the current phase is zero. The processor records the phase point corresponding to the phase modulation circuit at this time and controls the phase modulation circuit to remain at the current phase delay point. The processor also stores the current configuration data of the phase modulation circuit. Because the signal phase shift caused by the conditioning circuit is fixed, the phase modulation circuit only needs to remain at a certain appropriate phase delay point to compensate for the phase shift.

[0051] The above adjustment of the phase modulation circuit is only performed when the AC resistance tester is used for the first time, or according to user needs, it is performed through the manual control system of the human-computer interaction module.

[0052] One of the current input terminals C+ is connected to the input terminal of the product under test through the first switch K1 , and the other is connected to the input terminal of the standard resistor through the fifth switch K5 .

[0053] The output end of the product under test is connected to the current output end C− through the third switch K3 , and the output end of the standard resistor is connected to the current output end C− through the seventh switch K7 .

[0054] One of the measurement positive terminals S+ is connected to the input terminal of the measured product through the second switch K2, and the other is connected to the input terminal of the standard resistor through the sixth switch K6.

[0055] Switches K1, K2, K3, K4, K5, K6, K7, and K8 are processor-controlled switches with extremely low on-resistance, which can be ignored. The common connection point of switches K1 and K5 is defined as point A, the common connection point of switches K2 and K6 is defined as point B, the common connection point of switches K3 and K7 is defined as point C, and the common connection point of switches K4 and K8 is defined as point D. Switches K1, K2, K3, and K4 are closed or opened simultaneously; switches K5, K6, K7, and K8 are closed or opened simultaneously; the standard resistor and the test product are not connected to the system at the same time.

[0056] The output end of the product under test is connected to the negative measurement end S− through the fourth switch K4 , and the output end of the standard resistor is connected to the negative measurement end S− through the eighth switch K8 .

[0057] In the default state, the control switches K1, K2, K3, and K4 are closed; and the control switches K5, K6, K7, and K8 are opened.

[0058] When the system measures the product under test, the processor controls the state of the control signal CTRL2 to keep the control switches K5, K6, K7, and K8 open; and keeps the control switches K1, K2, K3, and K4 closed. The product under test is connected to points A, B, C, and D through the closed switches.

[0059] Before the system starts measuring the product under test, the processor controls switches K1, K2, K3, and K4 to be disconnected and switches K5, K6, K7, and K8 to be closed through signal CTRL2. The standard resistor is connected to points A, B, C, and D through the closed switches.

[0060] When the system is ready to measure the product under test, the processor changes the state of the control signal CTRL2, controlling switches K5, K6, K7, and K8 to be disconnected and switches K1, K2, K3, and K4 to be closed. The product under test is connected to points A, B, C, and D through the closed switches.

[0061] In some embodiments, the enable terminal of the counter is connected to the processor, and the interference suppression circuit further includes: The human-computer interaction module is used to receive the interference suppression start command input by the user and send it to the processor.

[0062] The processor generates an enable signal according to the interference suppression enable command to control the enable state of the counter.

[0063] The human-computer interaction module receives the interference suppression enable command and transmits the corresponding instruction to the processor via signal S10. The processor changes the state of control signal CTRL3, which, through a high-speed optocoupler, generates a corresponding control signal CTRL4. Control signal CTRL4 enables the counter. The processor outputs signal CTRL5 containing information about the calculation period T. Signal CTRL5, through a high-speed optocoupler, generates a corresponding control signal CTRL6. The counter begins counting based on the information about the calculation period T contained in signal CTRL6. The state of output signal S29 changes every time the counter reaches half of the processor's calculation period T. This means that the second switch switches every 0.5T, and signal S30 inverts every 0.5T. Due to the virtual short circuit concept of the op amp circuit, the phase of the current I flowing through the sampling resistor inverts every 0.5T. Simultaneously, signal S32 also inverts every 0.5T, following signal S30.

[0064] Even if the current is in phase reversal, there is no need to re-adjust the phase modulation circuit because the phase shift brought by the modulation circuit is fixed.

[0065] When the current I reverses, the phase of the AC voltage Vin generated by the current I on the DUT also reverses. Since the interference signal Ven is interference introduced from the outside, when the phase of the system AC voltage Vin reverses, the phase of the interference signal Ven does not reverse. Figure 3 As shown, at time 0.5T, the current I reverses phase, and the signal Vin and the third switch control signal S13 also reverse phase accordingly. The switching state of the third switch and the phase of the signal Vin simultaneously change inversely, leaving the relationship between the switching state of the third switch and the signal Vin unchanged. The waveform of the useful signal component (the component related to the useful signal k*Vin) output by the third switch does not change before and after time 0.5T. However, because the phase of the interference signal Ven does not reverse, the waveform of the interference component (the component related to the interference k*Ven) output by the third switch before and after time 0.5T changes in phase. k represents the gain of the conditioning circuit. The useful signal output by the third switch undergoes low-pass filtering 2, becoming a useful DC signal greater than zero. The interference signal output by the third switch undergoes low-pass filtering 2, resulting in an interference DC signal greater than zero for the first 0.5T period and less than zero for the last 0.5T period, with the absolute amplitudes being equal. Signal S16 is the superposition of the useful and interference DC signals. Signal S17 is the digital value output by the analog-to-digital converter of signal S16.

[0066] In some embodiments, the voltage signal source includes a voltage source, a first isotropic converter, a first inverter, a first transfer switch, a first transfer switch, and a switch control module.

[0067] The voltage source is used to output a voltage signal. The first isotropic device receives the voltage signal output by the voltage source and performs isotropic amplification and output. The first inverting device receives the voltage signal output by the voltage source and performs inverse amplification and output.

[0068] The common end of the first conversion switch is the output end, and the two moving points of the first conversion switch are respectively connected to the output ends of the first isotropic device and the first inverter.

[0069] The switch control module is used to output a switch control signal with a frequency fa to the first conversion switch, and control the first conversion switch to switch the gating state according to the frequency fa.

[0070] In some embodiments, the switch control module includes a crystal oscillator and a frequency divider.

[0071] Crystal oscillators have high stability and are used to generate frequency signals.

[0072] The frequency divider receives the high-frequency signal S20 and divides the frequency according to the frequency fa, and outputs a control signal with the frequency fa to the first conversion switch.

[0073] The frequency divider is used to divide the high-frequency signal S20 generated by the crystal oscillator. The frequency of the frequency divider output signal S24 is fa. Signal S24 controls the switching state of the first switch according to the frequency fa. The two inputs of the first switch are time-sharing and the same output of the first switch is turned on.

[0074] In some embodiments, the first non-inverting transistor and the first inverter are composed of operational amplifier circuits.

[0075] The second non-inverting device and the second inverter are composed of an operational amplifier circuit.

[0076] The counter has an enable pin and is used to count half of the processor's calculation cycle, and changes the state of the output signal S29 every time the counter counts to half of the calculation cycle.

[0077] The switching state of the second switch is controlled by the signal S29. When the signal S29 is in a high impedance state, the second switch is in a default on state.

[0078] The first low-pass filter is a multi-order filter with a capacitor-coupled output.

[0079] The operational amplifier circuit is composed of operational amplifier, capacitor and resistor.

[0080] The zero-crossing comparator consists of a high-speed comparator.

[0081] Power amplifiers are made up of transistors.

[0082] The sampling resistor is a precision resistor.

[0083] The high-speed isolator has an extremely high bandwidth, which is sufficient to transmit the signal S32, the signal CTRL3, and the signal CTRL5 with negligible delay.

[0084] The phase modulation circuit is used to adjust the phase of signal S18. The phase modulation circuit has a register that, under the control of the processor, can change the delay between the input and output signals, resulting in a controllable phase difference between input signal S18 and output signal S13. This phase difference is used to compensate for the phase offset caused by the conditioning circuit.

[0085] The amplifier circuit is composed of a bandpass amplifier, which is used to suppress interference outside the passband and amplify the signal to be measured Vin. The interference voltage signal Ven is also amplified.

[0086] The third commutator and the third inverter are composed of operational amplifier circuits.

[0087] The second low-pass filter is used to implement low-pass filtering to make the output waveform smoother.

[0088] The analog-to-digital converter converts the analog signal into a digital signal S17.

[0089] The processor processes the digital signal S17 according to a calculation cycle and issues a control signal CTRL1, a control signal CTRL2, a control signal CTRL3 and a control signal CTRL5.

[0090] Of course, the above description is not a limitation of the present invention, and the present invention is not limited to the above examples. Changes, modifications, additions or substitutions made by ordinary technicians in this technical field within the essential scope of the present invention should also fall within the scope of protection of the present invention.

Claims

1. An interference suppression circuit for AC measurement, characterized in that: Including current loop and measurement loop; The current loop includes: A voltage signal source, configured to output a voltage signal having a frequency fa; A first inversion circuit is used to receive the output signal of the voltage signal source, amplify it, and invert and output the signal according to a set period under control; The product under test is connected between the first flip circuit and the ground terminal; The measurement circuit comprises: a second flipping circuit, which receives the measurement signal from both ends of the measured product, amplifies it, and is controlled to flip and output the signal according to the frequency fa and the set period; a second low-pass filter connected to the output end of the second flip circuit; An analog-to-digital converter is connected to the output end of the second low-pass filter and is used to perform analog-to-digital conversion on the signal output by the second low-pass filter and then send the converted signal to the processor.

2. The interference suppression circuit according to claim 1, characterized in that The first flip circuit includes: a second isotropic amplifier, which receives the voltage signal output by the voltage signal source and performs isotropic amplification and output; a second inverter, which receives the voltage signal output by the voltage signal source, performs reverse amplification and outputs the voltage signal; A second switching switch, the common end of which is the output end, and two moving points of the second switching switch are respectively connected to the output ends of the second isotropic device and the second inverter; a counter, wherein the processor outputs a control signal containing information of a calculation period T, the counter counts according to the control signal, and changes the state of the output signal every time the counter counts to T / 2, and the output signal of the counter is used to control the gating state of the second transfer switch; The interference suppression circuit further includes: The first low-pass filter receives the signal output by the second conversion switch, performs low-pass filtering on the signal, and then outputs the signal.

3. The interference suppression circuit according to claim 2, characterized in that: The current loop further includes: The power amplifier receives the signal output by the first low-pass filter and performs power amplification, outputting a current I to the current input terminal C+. One of the two ends of the DUT is connected to the current input terminal C+ and the current output terminal C-, respectively. The current output terminal C- is connected to the ground.

4. The interference suppression circuit according to claim 3, characterized in that: The interference suppression circuit further includes: A standard resistor, wherein one of its two ends is connected to a current input terminal C+ and a current output terminal C- via a switch, and the other end is connected to a measurement positive terminal S+ and a measurement negative terminal S- of a measurement circuit via a switch; one of its two ends is connected to a current input terminal C+ and a current output terminal C- via a switch, and the other end is connected to a measurement positive terminal S+ and a measurement negative terminal S- of the measurement circuit via a switch; the conduction state of the switch is controlled by a processor, and is used to connect the standard resistor to the current circuit and the measurement circuit, or connect the test product to the current circuit and the measurement circuit; when the standard resistor is connected to the current circuit and the measurement circuit, the processor generates a phase modulation control signal according to a received signal; an operational amplifier circuit, wherein a non-inverting input terminal thereof receives a signal output by the first flip circuit, and an output terminal of the operational amplifier circuit is connected to an input terminal of the power amplifier; a sampling resistor, one end of which is connected to the current output terminal C-, and the other end of which is connected to the ground terminal, and the sampling resistor outputs a sampling signal to the inverting input terminal of the operational amplifier circuit; A phase shift compensation circuit receives the signal output by the first low-pass filter, performs zero-crossing detection on the signal to generate a square wave signal, and delays the phase of the square wave signal according to the phase modulation control signal. The delayed signal is used to control the flip output of the second flip circuit.

5. The interference suppression circuit according to claim 4, characterized in that: The phase shift compensation circuit comprises: a zero-crossing comparator, whose input end is connected to the output end of the first low-pass filter, performing zero-crossing detection on the received signal to generate a square wave signal and output the square wave signal; A phase modulation circuit receives the square wave signal and a phase modulation control signal, and delays the phase of the square wave signal according to the phase modulation control signal. The output end of the phase modulation circuit is connected to the control end of the second flip circuit.

6. The interference suppression circuit according to claim 5, characterized in that: The second flip circuit includes: an amplifier circuit, wherein two input terminals of the amplifier circuit are respectively connected to a measurement positive terminal S+ and a measurement negative terminal S-; a third isotropic device, which receives the output signal of the amplifying circuit and performs isotropic amplification and output; a third inverter, which receives the output signal of the amplifier circuit and performs reverse amplification and output; The third conversion switch has a common end as an output end, two moving points of the third conversion switch are respectively connected to the output ends of the third isotropic inverter and the third inverter, and the control end of the third conversion switch is connected to the output end of the phase modulation circuit.

7. The interference suppression circuit according to claim 1, characterized in that: The voltage signal source includes: a voltage source for outputting a voltage signal; a first isotropic amplifier, which receives the voltage signal output by the voltage source and performs isotropic amplification and output; a first inverter, which receives the voltage signal output by the voltage source, performs reverse amplification and outputs the voltage signal; A first switching switch, wherein the common terminal is an output terminal, and two moving points of the first switching switch are respectively connected to the output terminals of the first isotropic device and the first inverter; The switch control module is used to output a switch control signal with a frequency of fa to the first conversion switch, and control the first conversion switch to switch the gating state according to the frequency fa.

8. The interference suppression circuit according to claim 7, characterized in that: The switch control module includes: a crystal oscillator, which is used to generate a high-frequency signal S20; The frequency divider receives the high-frequency signal S20 and divides the frequency according to the frequency fa, and outputs a control signal with the frequency fa to the first conversion switch.

9. The interference suppression circuit according to claim 2, characterized in that: The enable terminal of the counter is connected to the processor, and the interference suppression circuit further includes: A human-computer interaction module, configured to receive an interference suppression activation command input by a user and send the command to the processor; The processor generates an enable signal according to the interference suppression enable command to control the enable state of the counter.

10. The interference suppression circuit according to any one of claims 4 to 6, characterized in that: One of the current input terminals C+ is connected to the input terminal of the product under test through the first switch K1, and the other is connected to the input terminal of the standard resistor through the fifth switch K5; The output end of the tested product is connected to the current output end C- through the third switch K3, and the output end of the standard resistor is connected to the current output end C- through the seventh switch K7; One of the measurement positive terminals S+ is connected to the input terminal of the device under test through the second switch K2, and the other is connected to the input terminal of the standard resistor through the sixth switch K6; The output end of the measured product is connected to the measurement negative terminal S− through the fourth switch K4, and the output end of the standard resistor is connected to the measurement negative terminal S− through the eighth switch K8.

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