Digital clock jitter measuring circuit and measuring method

Abstract

The invention provides a digital clock jitter measuring circuit and a digital clock jitter measuring method. The measuring circuit comprises a time delay unit which comprises an edge detection unit, a plurality of coarse granularity time delay units and a plurality of fine granularity time delay units, the coarse granularity time delay units and the fine granularity time delay units are connected in series, and the time delay unit receives a signal to be measured and generates a first clock signal and a second clock signal; the adjustment control unit is configured to adjust the delay of the second clock signal by controlling the coarse granularity delay unit and the fine granularity delay unit; the measuring unit comprises a first ring oscillator, a second ring oscillator, a phase discriminator and a counter. According to the clock jitter measurement circuit and measurement method provided by the invention, clock jitter can be accurately measured in an integrated chip, and inconvenience caused by the need of a large instrument in the prior art is avoided.

Description

Technical Field

[0001] The present application relates to the field of digital circuit design, and in particular to a digital clock jitter measurement circuit and measurement method. Background Art

[0002] In high-speed digital system architectures, such as high-speed transceivers and system-on-chip (SoC), jitter in data and clock signals can have a significant adverse effect on system performance.

[0003] Specifically, clock signals generated by clock generation units such as phase-locked loops (PLLs) and delay-locked loops (DLLs) must be distributed to various submodules via clock tree synthesis (CTS). However, due to factors such as power supply noise, process variations, and temperature variations, the clock signal at the clock output node can deviate from the ideal clock period, leading to circuit errors. Therefore, addressing these jitter-induced issues has become a pressing technical challenge for those skilled in the art.

[0004] When measuring jitter using an off-chip measurement system, it is severely affected by the resistance-inductance-capacitance (RLC) effect, resulting in a significant loss of measurement accuracy and making it difficult to accurately reflect the actual jitter conditions within the chip. On-chip measurement systems, on the other hand, can measure jitter directly within the chip, avoiding interference introduced by the external environment and the transmission process, ensuring that the measurement results are closer to the actual on-chip jitter status.

[0005] Therefore, it is necessary to provide a circuit and method that can accurately measure digital clock jitter. Summary of the Invention

[0006] In view of this, the present application provides a digital clock jitter measurement circuit and measurement method to solve the above technical problems in the prior art.

[0007] According to one aspect of the present application, a digital clock jitter measurement circuit is provided, the circuit comprising: a delay unit comprising an edge detection unit and a plurality of coarse-grained delay units and a plurality of fine-grained delay units connected in series, the delay unit receiving a signal to be measured and generating a first clock signal and a second clock signal, the edge detection unit being configured to detect edges of the first clock signal and the second clock signal; an adjustment control unit configured to adjust the delay of the second clock signal by controlling the coarse-grained delay unit and the fine-grained delay unit; The measuring unit includes a first ring oscillator, a second ring oscillator, a phase detector, and a counter. The inputs of the first ring oscillator and the second ring oscillator are respectively the first clock signal and the second clock signal. The phase detector is used to detect the phase relationship between the oscillation signals in the first ring oscillator and the second ring oscillator. The counter is used to count the number of oscillations of the first ring oscillator and the second ring oscillator.

[0008] According to a preferred embodiment of the present application, the adjustment control unit is configured to adjust the delay of the second clock signal according to the detection result of the edge detection unit, so that the delay of the second clock signal relative to the first clock signal is one clock cycle.

[0009] According to a preferred embodiment of the present application, the delay time of a single coarse-grained delay unit is greater than the delay time of a single fine-grained delay unit; the sum of the delay times of multiple fine-grained delay units is greater than the delay time of a coarse-grained delay unit.

[0010] According to a preferred embodiment of the present application, the edge detection unit receives the clock output signals of each stage of the multiple coarse-grained delay units and the fine-grained delay units and outputs them in a tree structure.

[0011] According to a preferred embodiment of the present application, the measuring unit further includes a first register and a second register, the input of the first register is a first clock signal, the output of the first register is connected to a first ring oscillator, the input of the second register is a second clock signal, and the output of the second register is connected to a second ring oscillator.

[0012] According to a preferred embodiment of the present application, the oscillation frequency of the first ring oscillator is lower than the oscillation frequency of the second ring oscillator.

[0013] According to another aspect of the present application, a clock jitter measurement method is provided. The method is performed by the above-mentioned measurement circuit and includes the following steps: Step S1, setting the delay path of the second clock signal to the minimum delay path; Step S2, increasing the delay of a coarse-grained delay unit to the second clock signal; Step S3, detecting the edge of the second clock signal and the corresponding first clock signal, and determining whether the second clock signal and the first clock signal have reached a locked state. If so, proceed to step S4; if not, jump to step S2; Step S4, reducing the delay of the second clock signal by a coarse-grained delay unit; Step S5, increasing the delay of a fine-grained delay unit to the second clock signal; Step S6, detecting the edge of the second clock signal and the corresponding first clock signal, and determining whether the second clock signal and the first clock signal have reached a locked state. If so, controlling the measurement unit to perform jitter measurement; if not, jumping to step S5.

[0014] According to a preferred embodiment of the present application, the condition for the second clock signal and the first clock signal to reach a locked state in step S3 is: The first clock rising edge of the current second clock signal precedes the first clock rising edge of the corresponding first clock signal; and After the delay of a coarse-grained delay unit is added to the current second clock signal, the first clock rising edge of the second clock signal lags behind the first clock rising edge of the corresponding first clock signal.

[0015] According to a preferred embodiment of the present application, the condition for the second clock signal and the first clock signal to reach a locked state in step S6 is: The first clock rising edge of the current second clock signal precedes the first clock rising edge of the corresponding first clock signal; and After adding a delay of a fine-grained delay unit to the current second clock signal, the first clock rising edge of the second clock signal lags behind the first clock rising edge of the corresponding first clock signal.

[0016] According to a preferred embodiment of the present application, the minimum delay path is a path that does not pass through the coarse-grained delay unit and when the fine-grained delay unit is set to a light-load mode.

[0017] It can be seen from the above technical solutions that the measurement circuit provided in this application can be integrated inside the chip to quickly and accurately measure the clock signal jitter within the chip, avoiding the limitations of the existing technology that requires additional large instruments for monitoring, and for ultra-high frequency clock signals, it is difficult to directly lead the signal out of the chip for measurement. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings are used to provide a further understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application, but do not constitute a limitation on the technical solution of the present application.

[0019] Figure 1 A schematic structural diagram of a clock jitter measurement circuit according to an exemplary embodiment of the present application is shown; Figure 2 A schematic structural diagram of a delay unit according to an exemplary embodiment of the present application is shown; Figure 3 shows a waveform diagram of a first clock signal and a second clock signal of an exemplary embodiment of the present application; Figure 4 A schematic structural diagram of an edge detection circuit according to an exemplary embodiment of the present application is shown; Figure 5 shows a waveform diagram of edge detection of an exemplary embodiment of the present application; Figure 6 A schematic structural diagram of a measuring unit according to an exemplary embodiment of the present application is shown; Figure 7 The flowchart of the clock jitter measurement method according to the exemplary embodiment of the present application is shown. DETAILED DESCRIPTION

[0020] Various exemplary embodiments of the present application will be described in detail below with reference to the accompanying drawings. The description of the exemplary embodiments is merely illustrative and is not intended to limit the present application, its application, or use. The present application can be implemented in many different forms and is not limited to the embodiments described herein. These embodiments are provided to make the present application thorough and complete and to fully convey the scope of the present application to those skilled in the art.

[0021] Unless explicitly stated, if the number of an element is not specifically limited, the element may be one or more. The term "plurality" means two or more, the term "based on" should be interpreted as "based at least in part on," and the terms "and / or" and "at least one of..." encompass any and all possible combinations of the listed items. Furthermore, terms such as "first," "second," and the like are for descriptive purposes only and do not indicate or imply relative importance or implicitly specify the number of the technical features being referred to.

[0022] refer to Figure 1 , which shows a schematic structural diagram of a clock jitter measurement circuit according to an exemplary embodiment of the present application. Figure 1 As shown, the clock jitter measurement circuit can receive an input clock signal CK_IN and measure the jitter of the input clock signal CK_IN to generate a jitter output signal J_OUT. The digital clock jitter measurement circuit includes: a delay unit, an adjustment control unit, and a measurement unit.

[0023] The delay unit includes an edge detection unit and multiple coarse-grained delay units and multiple fine-grained delay units connected in series. The delay unit receives an input clock signal CK_IN to generate a first clock signal CK1 and a second clock signal CK2. The delay unit generates a phase detection output signal PD_O via the edge detection unit. The adjustment control unit outputs a coarse-grained delay selection signal SEL_C and a fine-grained delay selection signal SEL_F based on the phase detection output signal PD_O to control the coarse-grained and fine-grained delay units to adjust the delay of the second clock signal. When a phase-locked state is achieved, the measurement unit receives the first clock signal CK1 and the second clock signal CK2 generated by the delay unit and outputs a jitter output signal J_OUT.

[0024] refer to Figure 2 , which shows a schematic structural diagram of a delay unit according to an exemplary embodiment of the present application. Figure 2 As shown, the delay unit includes a plurality of coarse-grained delay units ("M" units) and a plurality of fine-grained delay units ("N" units) connected in series. The delay time of a single coarse-grained delay unit is greater than the delay time of a single fine-grained delay unit, and the sum of the maximum delay times of the N fine-grained delay units is greater than the maximum delay time of a coarse-grained delay unit. The coarse-grained delay unit receives the clock signal CK_IN to be measured, and each of the M coarse-grained delay units can generate a second clock signal C_CK2[1] to C_CK2[M] delayed by the coarse-grained delay unit, and a corresponding first clock signal C_CK1[1] to C_CK1[M] not delayed by the coarse-grained delay unit. The fine-grained delay unit receives the first clock signal C_CK1[M] and the second clock signal C_CK2[M] of the last coarse-grained level, and each of the N fine-grained delay units can generate the second clock signals F_CK2[1] to F_CK2[N] delayed by the fine-grained delay unit, and the first clock signals F_CK1[1] to F_CK1[N] not delayed by the fine-grained delay unit. The edge detection unit receives the first clock signal and the second clock signal generated by each level of the coarse-grained delay unit and the fine-grained delay unit to obtain a phase detection output signal PD_O. The automatic adjustment control unit adjusts and outputs the coarse-grained delay selection signal SEL_C and the fine-grained delay selection signal SEL_F in sequence according to the phase detection output signal PD_O. The embodiment of the present application does not limit the circuit structure of the coarse-grained delay unit and the fine-grained delay unit. For example, the coarse-grained delay unit can adopt the vernier delay chain of the fine-grained delay unit, and the fine-grained delay unit can adopt the buffer delay chain of the coarse-grained delay unit.

[0025] refer to Figure 3, which shows the waveforms of the first clock signal C_CK1 and the second clock signal C_CK2 of the coarse-grained delay unit and the first clock signal F_CK1 and the second clock signal F_CK2 of the fine-grained delay unit in the embodiment of the present application. Figure 3 As shown, the propagation delay length of a single delay module of the coarse-grained delay unit is △t1, and the minimum adjustable delay step is Figure 2 The length of the delay unit composed of multiple buffers shown. The embodiment of the present application does not limit the structure and number of delay units in the coarse-grained delay unit. For example, the delay unit can be composed of buffers or other combinational logic. The propagation delay length of the first clock signal F_CK1 of the fine-grained delay unit is △t2, and the propagation delay length of the second clock signal F_CK2 of the fine-grained delay unit is △t3. Therefore, the propagation delay length of a single delay module of the fine-grained delay unit is △t3 -△t2, and the minimum adjustable delay step is Figure 2 The delay difference between turning on and off a single stage of a switching load.

[0026] refer to Figure 4 , which shows a schematic diagram of the structure of the edge detection circuit of the exemplary embodiment of the present application. The edge detection circuit is used to implement Figure 2 The edge detection unit shown in FIG. Figure 4 As shown, the edge detection circuit receives the first clock signal and the second clock signal generated by each stage of the coarse-grained delay unit and the fine-grained delay unit to generate a phase detection output signal PD_O. The embodiment of the present application does not limit the tree structure and hierarchy of the edge detection circuit.

[0027] refer to Figure 5, which shows a waveform diagram of edge detection of an exemplary embodiment of the present application. In this embodiment, the condition for the phase detection output signal PD_O level to be pulled high 207 (i.e., the condition for meeting the locked state) must meet the following conditions: the first clock rising edge 203 of the k-th level second clock signal C_CK2[k] of the coarse-grained adjustment unit is ahead of the second clock rising edge 202 of the k-th level first clock signal C_CK1[k] of the coarse-grained adjustment unit, or the first clock rising edge 203 of the k-th level second clock signal F_CK2[k] of the fine-grained adjustment unit is ahead of the k-th level first clock signal F_CK1[k] of the fine-grained adjustment unit. k]; the first clock rising edge 206 of the k+1th level second clock signal C_CK2[k+1] of the coarse-grained adjustment unit lags behind the second clock rising edge 205 of the k+1th level first clock signal C_CK1[k+1] of the coarse-grained adjustment unit, or the first clock rising edge 206 of the k+1th level second clock signal F_CK2[k+1] of the fine-grained adjustment unit leads the second clock rising edge 205 of the k+1th level first clock signal F_CK1[k+1] of the fine-grained adjustment unit. Figure 5 The first rising edge of the clock C_CK1[k] or F_CK1[k] is marked as 201 , and the first rising edge of the clock C_CK1[k+1] or F_CK1[k+1] is marked as 204 .

[0028] refer to Figure 6 , which shows a schematic structural diagram of a measuring unit of an exemplary embodiment of the present application. Figure 6As shown, the measurement unit includes a first register and a second register, a first ring oscillator 301 and a second ring oscillator 302 with different oscillation frequencies, a phase detector, and a counter. The input of the first register is the first clock signal, and the output of the first register is connected to the first ring oscillator. The input of the second register is the second clock signal, and the output of the second register is connected to the second ring oscillator. The inputs of the first ring oscillator and the second ring oscillator are respectively connected to the first clock signal and the second clock signal. The oscillation frequency of the first ring oscillator is F1, and the oscillation frequency of the second ring oscillator is F2. It is required that the oscillation frequency of the first ring oscillator is lower than that of the second ring oscillator, that is, F1 < F2. The phase detector is used to detect the phase relationship between the clock signals generated by the two oscillators. For example, at the beginning, the phase of the clock signal oscillated by the first ring oscillator is ahead of the phase of the clock signal oscillated by the second ring oscillator. When the phase of the clock oscillated by the first ring oscillator lags behind the phase of the clock oscillated by the second ring oscillator, the phase detector will control the two oscillators to stop oscillating, and the counter records the number of oscillations N of the oscillators. The output jitter value J_OUT = N(1 / F2 - 1 / F1). By counting the number of oscillations in each measurement process, the clock jitter information of the signal to be measured can be obtained.

[0029] Reference Figure 7 , which shows the flowchart of the clock jitter measurement method of an exemplary embodiment of the present application. This clock jitter measurement method is executed by the measurement circuit described above. This measurement method includes the following steps: Step S1, set the delay path of the second clock signal to the minimum delay path; Step S2, make the second clock signal increase the delay of a coarse granularity delay unit; Step S3, detect the edges of the second clock signal and the corresponding first clock signal, and determine whether the second clock signal and the first clock signal reach the locked state. If they reach the locked state, continue to execute step S4. If they do not reach the locked state, jump to step S2; Step S4, make the second clock signal decrease the delay of a coarse granularity delay unit; Step S5, make the second clock signal increase the delay of a fine granularity delay unit; Step S6, detect the edges of the second clock signal and the corresponding first clock signal, and determine whether the second clock signal and the first clock signal reach the locked state. If they reach the locked state, control the measurement unit to execute step S7 of jitter measurement. If they do not reach the locked state, jump to step S5. ]>

[0030] In step S1 , the minimum delay path is a path that does not pass through a coarse-grained delay unit (a selector signal is set in the coarse-grained delay unit to select a path without a delay unit) and when the fine-grained delay unit is set to a light-load mode.

[0031] In step S2, a coarse-grained delay unit is set so that the second clock signal increases the delay of one coarse-grained delay unit.

[0032] In step S3, the edge detection unit output signal PD_O is used to determine whether the phase relationship between the first clock signal and the second clock signal satisfies the locked state. If the phase relationship between the first clock signal and the second clock signal does not satisfy the locked state, the process jumps to step S2, and the automatic adjustment unit gradually increases the delay length of the coarse-grained delay unit for the second clock signal. If the phase relationship between the first clock signal and the second clock signal satisfies the locked state, step S4 is executed. The condition for the second clock signal to reach a locked state with the first clock signal is: the first clock rising edge of the current second clock signal is ahead of the first clock rising edge of the corresponding first clock signal; and after adding a delay of a coarse-grained delay unit to the current second clock signal, the first clock rising edge of the second clock signal lags behind the first clock rising edge of the corresponding first clock signal.

[0033] In step S4, the automatic adjustment unit restores the configuration of the coarse-grained delay unit to the state that does not meet the phase lock in the previous step, that is, the second clock signal reduces the delay of one coarse-grained delay unit.

[0034] In step S5 , the fine-grained delay unit delays the second clock signal, so that the second clock signal increases the delay of one fine-grained delay unit.

[0035] In step S6, the edge detection unit outputs the signal PD_O to determine whether the phase relationship between the first clock signal and the second clock signal satisfies the locked state. If the phase relationship between the first clock signal and the second clock signal does not satisfy the locked state, the process jumps to step S5, and the automatic adjustment unit gradually increases the delay length of the fine-grained delay unit for the second clock signal. If the phase relationship between the first clock signal and the second clock signal does not satisfy the locked state, step S7 is executed. The condition for the second clock signal to reach a locked state with the first clock signal is: the first clock rising edge of the current second clock signal is ahead of the first clock rising edge of the corresponding first clock signal; and after adding a delay of a fine-grained delay unit to the current second clock signal, the first clock rising edge of the second clock signal lags behind the first clock rising edge of the corresponding first clock signal.

[0036] In step S7 , the measuring unit measures jitter information of the clock signal based on the first clock signal and the second clock signal.

[0037] The technical solutions described in this application can be supported by these various configurations of the electronic device 300 and are not limited to the specific examples of the technical solutions described in this application. The illustrations and descriptions of the present application in the foregoing text and the accompanying drawings are not restrictive. It is obvious to those skilled in the art that the present application is not limited to the details of the above-mentioned exemplary embodiments, and that the present application can also be implemented in other specific forms without departing from the spirit or basic features of the present application. Therefore, the scope of protection claimed in this application is defined by the claims rather than the above description, and all changes that fall within the meaning and scope of the equivalent elements of the claims are included in the scope of protection of this application.

Claims

1. A digital clock jitter measurement circuit, characterized in that: The measuring circuit comprises: a delay unit comprising an edge detection unit and a plurality of coarse-grained delay units and a plurality of fine-grained delay units connected in series, wherein the delay unit receives a signal to be measured and generates a first clock signal and a second clock signal, and the edge detection unit is configured to detect edges of the first clock signal and the second clock signal; an adjustment control unit configured to adjust the delay of the second clock signal by controlling the coarse-grained delay unit and the fine-grained delay unit; The measuring unit includes a first ring oscillator and a second ring oscillator, a phase detector, and a counter. The inputs of the first ring oscillator and the second ring oscillator are respectively a first clock signal and a second clock signal. The phase detector is used to detect the phase relationship between the oscillation signals in the first ring oscillator and the second ring oscillator. The counter is used to count the number of oscillations of the first ring oscillator and the second ring oscillator.

2. The measuring circuit according to claim 1, characterized in that The adjustment control unit is configured to adjust the delay of the second clock signal according to the detection result of the edge detection unit, so that the delay of the second clock signal relative to the first clock signal is one clock cycle.

3. The measurement circuit according to claim 1, characterized in that The delay time of a single coarse-grained delay unit is greater than the delay time of a single fine-grained delay unit; the sum of the delay times of the multiple fine-grained delay units is greater than the delay time of a coarse-grained delay unit.

4. The measurement circuit according to claim 1, characterized in that The edge detection unit receives the clock output signals of each stage of the multiple coarse-grained delay units and the fine-grained delay unit and outputs them in a tree structure.

5. The measurement circuit according to claim 1, characterized in that The measurement unit further includes a first register and a second register, wherein the input of the first register is a first clock signal and the output of the first register is connected to the first ring oscillator, the input of the second register is a second clock signal and the output of the second register is connected to the second ring oscillator.

6. The measurement circuit according to claim 1, characterized in that The oscillation frequency of the first ring oscillator is lower than the oscillation frequency of the second ring oscillator.

7. A clock jitter measurement method, the method being performed by the measurement circuit according to any one of claims 1 to 5, characterized in that: The method comprises the following steps: Step S1, setting the delay path of the second clock signal to the minimum delay path; Step S2, increasing the delay of a coarse-grained delay unit to the second clock signal; Step S3, detecting the edge of the second clock signal and the corresponding first clock signal, and determining whether the second clock signal and the first clock signal have reached a locked state. If so, proceed to step S4; if not, jump to step S2; Step S4, reducing the delay of the second clock signal by a coarse-grained delay unit; Step S5, increasing the delay of a fine-grained delay unit to the second clock signal; Step S6, detecting the edge of the second clock signal and the corresponding first clock signal, and determining whether the second clock signal and the first clock signal have reached a locked state. If so, controlling the measurement unit to perform jitter measurement; if not, jumping to step S5.

8. The method according to claim 7, characterized in that The condition for the second clock signal and the first clock signal to reach a locked state in step S3 is: The first clock rising edge of the current second clock signal precedes the first clock rising edge of the corresponding first clock signal; and After the delay of a coarse-grained delay unit is added to the current second clock signal, the first clock rising edge of the second clock signal lags behind the first clock rising edge of the corresponding first clock signal.

9. The method according to claim 7, characterized in that In step S6, the condition for the second clock signal to reach a locked state with the first clock signal is: The first clock rising edge of the current second clock signal precedes the first clock rising edge of the corresponding first clock signal; and After adding a delay of a fine-grained delay unit to the current second clock signal, the first clock rising edge of the second clock signal lags behind the first clock rising edge of the corresponding first clock signal.

10. The method according to claim 7, characterized in that The minimum delay path is a path that does not pass through the coarse-grained delay unit and when the fine-grained delay unit is set to a light-load mode.

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