High-precision current mirror

Abstract

The invention relates to a high-precision current mirror, and the current mirror comprises a main transistor group which is configured to receive a reference current; a slave transistor configured to generate a mirror current proportional to the reference current; wherein the main transistor group comprises a first transistor and a second transistor, and control electrodes of the first transistor and the second transistor are electrically connected with each other; second poles of the first transistor and the second transistor are grounded; wherein the equivalent dimension ratio of the slave transistor to the main transistor group is a ratio K; the size of the first transistor is 1-x times the ratio of the size of the slave transistor to the ratio K, and the size of the second transistor is x times the ratio of the size of the slave transistor to the ratio K; wherein x is the percentage of the difference between the actual value and the expected value of the ratio K in the expected value; and a first trimming circuit electrically connected to the second transistor and configured to reduce the ratio K; and / or a second trimming circuit electrically connected to the second transistor and configured to increase the ratio K.

Description

Technical Field

[0001] The present invention relates to the field of electrical control, and in particular to a high-precision current mirror. Background Art

[0002] Current mirrors are one of the fundamental building blocks of analog integrated circuits. Besides serving as bias modules for various circuits within analog integrated circuits, they are also widely used to amplify reference currents to drive current-source devices, such as LEDs. The ability of current mirrors to accurately replicate or scale the reference current impacts the accuracy and stability of the entire analog integrated circuit.

[0003] Figure 1 The basic cascode current mirror structure is shown, which includes a master transistor M0 and a slave transistor M1, with the gates of the two transistors electrically connected to each other and the sources electrically connected to each other. The mirror current Iout flowing through the slave transistor M1 can be understood as a mirror current scaled by the reference current Iin flowing through the master transistor M0. Ideally, Iout = K * Iin, where the ratio K is the ratio of the sizes of the slave transistor M1 to the master transistor M0, that is, .

[0004] Figure 2 and Figure 3 Figure 2 shows a schematic diagram of a conventional current mirror structure with trimming functionality. A conventional cascode current mirror typically includes common-gate transistors MC0 and MC1 connected in series with the drains of the master transistor M0 and slave transistor M1, respectively. This ensures that the drain voltages of the master and slave transistors are approximately equal, thereby improving the accuracy of the current mirror. However, due to manufacturing variations, the ratio K between the slave transistor M1 and the master transistor M0 cannot reach the ideal value. To obtain a more accurate mirror current Iout, the current mirror requires a trimming circuit or method to correct the ratio K.

[0005] Figure 2 The solution can only adjust the value of the ratio K in one direction. The more switches are closed, the smaller the value of the ratio K is, and the smaller the output current is. Figure 3 This solution enables bidirectional adjustment (increase or decrease) of the ratio K and exhibits excellent trimming characteristics when the ratio K = 1. However, when the ratio K is large (for example, 100), the sizes of transistors MT1 through MT3 must be increased by a factor of K. This significantly increases chip area and costs. Therefore, there is a growing desire to utilize a bidirectional trimming circuit that does not significantly increase the layout and cost, effectively improving the current mirror trimming accuracy and thereby obtaining a precise mirrored current. Summary of the Invention

[0006] In response to the technical problems existing in the prior art, the present application proposes a high-precision current mirror, comprising: a main transistor group, configured to receive a reference current; a slave transistor, configured to generate a mirror current proportional to the reference current; wherein the main transistor group includes a first transistor and a second transistor, the control electrodes of the two being electrically connected to each other; the second electrodes of the first transistor and the second transistor are both grounded; wherein the equivalent size ratio of the slave transistor to the main transistor group is a ratio K; the size of the first transistor is 1-x times the ratio of the size of the slave transistor to the ratio K, and the size of the second transistor is x times the ratio of the size of the slave transistor to the ratio K; wherein x is the percentage of the difference between the actual value and the expected value of the ratio K to its expected value; and a first trimming circuit, electrically connected to the second transistor, configured to reduce the ratio K; and / or, a second trimming circuit, electrically connected to the second transistor, configured to increase the ratio K.

[0007] In particular, the high-precision current mirror is characterized in that the value of x is a percentage not greater than 20%.

[0008] In particular, the high-precision current mirror is characterized in that, wherein, the first trimming circuit includes a first group of transistors, including one or more transistors connected in parallel with each other; the control electrode of each transistor in the first group of transistors is electrically connected to the control electrode of the first transistor and the second transistor; and the second electrode of each transistor in the first group of transistors is electrically connected to the second electrode of the second transistor; and, a first group of switches, including one or more switches, respectively electrically connected between the first electrode of the corresponding transistor in the first group of transistors and the first electrode of the second transistor.

[0009] In particular, the high-precision current mirror is characterized in that the length of each transistor in the first group of transistors is equal to the equivalent length of the main transistor group.

[0010] In particular, the high-precision current mirror is characterized in that the first electrode of the second transistor is electrically connected to the first electrode of the first transistor through a first switch; wherein the first end of the first switch is electrically connected to the first electrode of the first transistor.

[0011] In particular, the high-precision current mirror is characterized in that the second trimming circuit includes a second group of transistors, including one or more transistors connected in parallel with each other; the control electrodes of each transistor in the second group of transistors are electrically connected to the control electrodes of the first transistor and the second transistor; and the second electrode of each transistor in the second group of transistors is electrically connected to the first electrode of the second transistor; and a second group of switches, including one or more switches; each switch in the second group of switches is electrically connected between the first electrode of each transistor in the second group of transistors and the first electrode of the first transistor.

[0012] In particular, the high-precision current mirror is characterized in that the width of each transistor in the second group of transistors is equal to the width of the second transistor.

[0013] In particular, the high-precision current mirror is characterized in that the second trimming circuit includes a third group of transistors, including one or more transistors connected in series between the first electrode of the first transistor and the first electrode of the second transistor; the control electrode of each transistor in the third group of transistors is electrically connected to the control electrode of the first transistor and the second transistor; and a third group of switches, including one or more switches; each switch in the third group of switches is electrically connected between the first electrode and the second electrode of each transistor in the third group of transistors.

[0014] In particular, the high-precision current mirror is characterized in that the width of each transistor in the third group of transistors is equal to the width of the second transistor.

[0015] The present application also relates to an electronic device, characterized in that it comprises any of the high-precision current mirrors described above.

[0016] The present application also relates to a high-precision current mirror, which is characterized in that it includes: a main transistor, configured to receive a reference current; a slave transistor group, configured to generate a mirror current proportional to the reference current; wherein the slave transistor group includes a third transistor and a fourth transistor, and the control electrodes of the two are electrically connected to each other; the second electrodes of the third transistor and the fourth transistor are both grounded; wherein the ratio of the equivalent size of the slave transistor group to the size of the main transistor is a ratio K; the size of the third transistor is 1-x times the product of the size of the main transistor and the ratio K, and the size of the fourth transistor is x times the product of the size of the main transistor and the ratio K; wherein x is the percentage of the difference between the actual value and the expected value of the ratio K to its expected value; and a fifth adjustment circuit, electrically connected to the fourth transistor, configured to increase the ratio K; and / or a sixth adjustment circuit, electrically connected to the fourth transistor, configured to decrease the ratio K.

[0017] In particular, the high-precision current mirror is characterized in that the value of x is a percentage not greater than 20%.

[0018] In particular, the high-precision current mirror is characterized in that, wherein, the fifth trimming circuit includes a fifth group of transistors, including one or more transistors connected in parallel with each other, the control electrode of each transistor in the fifth group of transistors is electrically connected to the control electrode of the third transistor and the fourth transistor; and the second electrode of each transistor in the fifth group of transistors is electrically connected to the second electrode of the fourth transistor; and the fifth group of switches includes one or more switches, respectively electrically connected between the first electrode of the corresponding transistor in the fifth group of transistors and the first electrode of the fourth transistor.

[0019] In particular, the high-precision current mirror is characterized in that the length of each transistor in the fifth group of transistors is equal to the equivalent length of the secondary transistor group.

[0020] In particular, the high-precision current mirror is characterized in that the first electrode of the fourth transistor is electrically connected to the first electrode of the third transistor through a second switch; wherein the first end of the second switch is electrically connected to the first electrode of the third transistor.

[0021] In particular, the high-precision current mirror is characterized in that the sixth trimming circuit includes a sixth group of transistors, including one or more transistors connected in parallel with each other; the control electrodes of each transistor in the sixth group of transistors are electrically connected to the control electrodes of the third transistor and the fourth transistor; and the second electrode of each transistor in the sixth group of transistors is electrically connected to the first electrode of the fourth transistor; and the sixth group of switches includes one or more switches, and each switch in the sixth group of switches is electrically connected between the first electrode of each transistor in the sixth group of transistors and the first electrode of the third transistor.

[0022] In particular, the high-precision current mirror is characterized in that the width of each transistor in the sixth group of transistors is equal to the width of the fourth transistor.

[0023] In particular, the high-precision current mirror is characterized in that, wherein, the sixth trimming circuit includes a seventh group of transistors, including one or more transistors connected in series between the first electrode of the third transistor and the first electrode of the second transistor; the control electrode of each transistor in the seventh group of transistors is electrically connected to the control electrode of the third transistor and the fourth transistor; and a seventh group of switches, including one or more switches; each switch in the seventh group of switches is electrically connected between the first electrode and the second electrode of each corresponding transistor in the seventh group of transistors.

[0024] In particular, the high-precision current mirror is characterized in that the width of each transistor in the seventh group of transistors is equal to the width of the fourth transistor.

[0025] The present application also relates to an electronic device, characterized in that it comprises any of the high-precision current mirrors described above.

[0026] The high-precision current mirror proposed in this application can achieve high-precision bidirectional adjustment of the ratio of the reference current to the mirror current, thereby obtaining a higher-precision mirror current with higher reliability and stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Below, the preferred embodiments of the present application will be further described in detail with reference to the accompanying drawings, wherein: Figure 1 The basic cascode current mirror structure is shown; Figure 2 The figure shows a schematic diagram of a conventional current mirror structure with a trimming function; Figure 3 The figure shows another conventional current mirror structure with trimming function; Figure 4 FIG2 is a schematic diagram of a current mirror structure according to an embodiment of the present application; Figure 5 FIG2 is a schematic diagram of a current mirror structure according to another embodiment of the present application; Figure 6 FIG2 is a schematic diagram of a current mirror structure according to another embodiment of the present application; Figure 7 FIG. 1 is a schematic diagram of a current mirror structure according to another embodiment of the present application. DETAILED DESCRIPTION

[0028] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0029] In the detailed description that follows, reference may be made to the various drawings that form part of this application and illustrate specific embodiments of the present application. In the drawings, similar reference numerals describe substantially similar components in different figures. Each specific embodiment of the present application is described below in sufficient detail to enable a person of ordinary skill in the art to implement the technical solutions of the present application. It should be understood that other embodiments may be utilized or that structural, logical, or electrical changes may be made to the embodiments of the present application.

[0030] Technologies, methods, and devices known to persons of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, such technologies, methods, and devices should be considered part of the specification. The lines between the elements in the drawings are merely for ease of explanation, indicating that at least the elements at both ends of the line are communicating with each other, and are not intended to limit the unconnected elements from being unable to communicate. Furthermore, the number of lines between two elements is intended to indicate at least the number of signals involved in the communication between the two elements or at least the number of outputs provided, and is not intended to limit the two elements to communicating only with the signals shown in the figure.

[0031] The high-precision current mirror proposed in this application increases or decreases the ratio of the reference current to the mirror current through local trimming, significantly reducing the complexity of the trimming circuit in the current mirror, thereby providing a higher-precision mirror current and improving the operating efficiency of the current mirror. Compared with traditional current mirror solutions with trimming capabilities, the circuit is simpler, the trimming accuracy is higher, and the layout area is saved.

[0032] The high-precision current mirror proposed in this application converts the master or slave transistor in a conventional solution into two or more equivalent transistors based on an error ratio. The error ratio x is the percentage of the difference between the actual value of the ratio K and the expected value. Determining the error ratio x determines the adjustment range of the ratio K. A starting point for adjusting the ratio K is selected based on the error ratio x, and the master or slave transistor is split according to the error ratio x. The master or slave transistor is split into two larger and smaller transistors. The larger transistor can be understood as occupying the majority of the original master or slave transistor size, and the current mirror function is primarily performed by this transistor. The other transistor is smaller and can be understood as a portion of the original master or slave transistor. A trimming circuit is electrically connected in series or parallel with the smaller transistor, adjusting the equivalent size of the smaller transistor to change the equivalent size of the master or slave transistor, thereby changing the value of the ratio K and improving the precision of the mirrored current output by the current mirror. Through this equivalent splitting method, the size of the smaller transistors is adjusted, and the comparison value K is adjusted by local approximation or trimming, which greatly reduces the size of the transistors in the trimming circuit and significantly reduces the current mirror layout. For example, when the length of the main transistor is L and the desired error ratio x is 20%, the main transistor is equivalently split into two transistors according to 20%L and 80%L. The trimming circuit is used to adjust the size of the transistor with a length of 20%L, ultimately achieving the correction of the comparison value K. For another example, when the width of the slave transistor is W and the desired error ratio x is 10%, the slave transistor is equivalently split into two transistors according to 10%W and 90%W. The trimming circuit is used to adjust the size of the transistor with a width of 10%W to achieve the correction of the comparison value k.

[0033] According to one embodiment, the widths of the master transistor and the slave transistor are equal, and the length of the master transistor or the slave transistor is divided according to the error ratio x. Alternatively, the lengths of the master transistor and the slave transistor are equal, and the width of the master transistor or the slave transistor is divided according to the error ratio x. This can generally achieve a better ratio K value adjustment effect for the current mirror.

[0034] The following describes the operating principle of the high-precision current mirror proposed in this application, taking the current mirror as an example in which all transistors are N-type transistors. However, the transistor types in the current mirror of this application are not limited to this embodiment; they can also be P-type transistors, for example. Depending on the transistor type, the connection relationship between the transistors in the current mirror can also be adaptively adjusted or varied.

[0035] Hereinafter, transistor width refers to the transistor channel width, transistor length refers to the transistor channel length, and transistor size is the ratio of the transistor channel width to the channel length.

[0036] Figure 4 FIG. 1 is a schematic diagram of a current mirror structure according to an embodiment of the present application.

[0037] According to one embodiment, a current mirror includes a current source 41, a common-gate transistor T42, and a transistor T43. Common-gate refers to two or more transistors whose gates or control electrodes are electrically connected to each other. Current source 41 is configured to receive a power supply voltage VDD and provide a reference current Iin. A first electrode of transistor T42 is electrically connected to an output terminal of current source 41. A first electrode of transistor T43 provides a mirrored current Iout.

[0038] According to one embodiment, the current mirror includes a master transistor group 44 electrically connected to the second electrode of transistor T42 and a slave transistor T45 electrically connected to the second electrode of transistor T43. The master transistor group 44 is configured to receive a reference current Iin transmitted by transistor T42, and the slave transistor T45 is configured to generate a mirror current Iout proportional to the reference current Iin. The proportional relationship here refers to a ratio K.

[0039] According to one embodiment, the main transistor group 44 includes two transistors with a common gate and a common source, namely a first transistor T441 and a second transistor T442. Common gate and common source means that the gates or control electrodes of the transistors are electrically connected to each other, and the sources or second electrodes thereof are electrically connected to each other.

[0040] According to one embodiment, a first electrode of the first transistor T441 is electrically connected to a second electrode of the transistor T42 .

[0041] According to one embodiment, the current mirror may further include a first switch S443. The first electrode of the second transistor T442 is electrically connected between the first electrode of the first transistor T441 and the second electrode of the transistor T42 via the first switch S443. The first end of the first switch S443 is electrically connected between the first electrode of the first transistor T441 and the second electrode of the transistor T42, and the second end of the first switch S443 is electrically connected to the first electrode of the second transistor T442.

[0042] According to one embodiment, the second electrodes of the first transistor T441 and the second transistor T442 are electrically connected to the second electrode of the slave transistor T45 , respectively.

[0043] According to one embodiment, the control electrode of the slave transistor T45 is electrically connected to the control electrodes of the first and second transistors T441 and T442 and is also electrically connected to the first electrode of the transistor T42 . The first electrode of the slave transistor T45 is electrically connected to the second electrode of the transistor T43 .

[0044] According to one embodiment, the second electrode of the slave transistor T45 is connected to ground.

[0045] According to one embodiment, the ratio of the size of the slave transistor T45 to the equivalent size of the master transistor group 44 is K, and the error ratio of the ratio K is x. The size of the first transistor T441 may be 1-x times the ratio of the size of the slave transistor T45 to the ratio K, and the size of the second transistor T442 may be x times the ratio of the size of the slave transistor T45 to the ratio K.

[0046] In one embodiment of the present application, the lengths of the first transistor T441 , the second transistor T442 , and the slave transistor T45 may be substantially equal, but the widths thereof may be unequal.

[0047] According to one embodiment, the width of the second transistor T442 may be x times the equivalent width of the main transistor group 44, and the width of the first transistor T441 may be (1-x) times the equivalent width of the main transistor group 44. Wherein, x is a percentage not greater than 50%. In one embodiment of the present application, x is a percentage not greater than 20%. For example, the equivalent length of the main transistor group is L0 and the equivalent width is W0, and the ideal ratio is K, and the error ratio is set to x. In this case, the width of the first transistor T441 is and the width of the second transistor T442 , the lengths of the first transistor T441 and the second transistor T442 are both L0.

[0048] In another embodiment of the present application, the widths of the first transistor T441 , the second transistor T442 , and the slave transistor T45 may be substantially equal, but the lengths thereof may be unequal.

[0049] According to one embodiment, the transistor T42 , the transistor T43 , the slave transistor T45 , the first transistor T441 , and the second transistor T442 may be of the same type, for example, N-type transistors.

[0050] According to one embodiment, the current mirror may include a first trimming circuit 46 and / or a second trimming circuit 47 electrically connected to the second transistor T442 to achieve bidirectional adjustment of the contrast value K.

[0051] In one embodiment, the first trimming circuit 46 is configured to decrease the value of the ratio K. The second trimming circuit 47 is configured to increase the value of the ratio K.

[0052] In one embodiment, the first trimming circuit 46 includes a first group of transistors shared with the first transistor T441 and the second transistor T442, and a first group of switches. The first group of transistors includes transistors T460 through T46n, and the first group of switches includes switches S460 through S46n electrically connected between the first terminals of each of the transistors T460 through T46n and the first terminal of the first switch S443. The first group of switches is configured to electrically connect the first terminals of corresponding transistors T460 through T46n to the first terminal of the second transistor T442 when the first switch S443 is closed, thereby connecting the corresponding transistors in parallel with the second transistor T442 and increasing the equivalent size of the second transistor T442. Here, n is an integer greater than or equal to 1.

[0053] In one embodiment, the transistors T460 to T46n may be of the same type as the transistor T42, the transistor T43, the slave transistor T45, the first transistor T441, and the second transistor T442.

[0054] According to one embodiment, in the first trimming circuit 46 , the transistors T460 to T46 n in the first transistor group are connected in parallel.

[0055] According to one embodiment, the control electrodes of the transistors T460 to T46n in the first transistor group are electrically connected to each other and to the control electrodes of the first transistor T441 and the second transistor T442, and their respective second electrodes are electrically connected to the second electrode of the second transistor T442.

[0056] According to one embodiment, when the first switch S443 is closed, the first trimming circuit 46 operates. Through the first switch S443, the first trimming circuit 46 is electrically connected to the second transistor T442. Closing a switch in the first switch group connects the corresponding transistor in the first transistor group to the current mirror, increasing the equivalent size of the second transistor T442 and, consequently, the equivalent size of the main transistor group 44, thereby decreasing the ratio K. The number of closed switches in the first switch group can be freely combined to achieve the desired trimming accuracy.

[0057] According to one embodiment, when the lengths of the transistors T460 to T46n in the first transistor group of the first trimming circuit 46 are similar to or the same as the equivalent length of the main transistor group 44, the trimming accuracy of the ratio K can be more effectively improved.

[0058] In one embodiment of the present application, the master transistor group 44 has an equivalent width of W0 and an equivalent length of L0; the slave transistor T45 has a width of W1 and a length of L1; the ratio The widths of transistors T460 to T46n in the first trimming circuit 46 are Ws1, Ws2, ..., Wsn, respectively, and their lengths are the same as the equivalent length of the main transistor group 44. The trimmed ratio This is equivalent to increasing the width of the main transistor group 44 so that the ratio K decreases.

[0059] In one embodiment, the sizes of transistors T460 to T46n in the first transistor group may be, for example, 1%, 2%, 5%, etc., of the equivalent size of the main transistor group 44 , and the specific proportion is related to the actual trimming accuracy.

[0060] According to one embodiment, the second trimming circuit 47 includes a second group of transistors sharing a common gate with the first transistor T441 and the second transistor T442, and a second group of switches. The second group of transistors includes transistors T470 through T47n, ​​and the second group of switches includes switches S470 through S47n electrically connected between the first electrodes of transistors T470 through T47n and the first electrode of the first transistor T441, respectively. The second group of switches is configured to electrically connect the first electrodes of transistors T470 through T47n to the first electrode of the first transistor T441, thereby reducing the equivalent size of the second transistor T442.

[0061] According to one embodiment, the control electrodes of the transistors T470 to T47n are electrically connected to each other and to the control electrodes of the first transistor T441 and the second transistor T442, and the respective second electrodes are electrically connected to the first electrode of the second transistor T442.

[0062] In one embodiment, the transistors T470 to T47n may be of the same type as the transistor T42, the transistor T43, the slave transistor T45, the first transistor T441, and the second transistor T442.

[0063] In one embodiment, transistors T470 to T47n in the second trimming circuit 47 are connected in parallel.

[0064] According to one embodiment, when the first switch S443 is disconnected, switches S460 through S46n in the first trimming circuit 46 are disconnected, and the second trimming circuit 47 operates. By closing switches in the second switch group, the corresponding transistors are connected to the current mirror, reducing the equivalent size of the second transistor T442, thereby reducing the equivalent size of the main transistor group 44 and increasing the value of the ratio K. The number of closed switches in the second switch group is selected based on actual needs.

[0065] In one embodiment, the sizes of the transistors T470 to T47n may be, for example, 2%, 3%, 5%, etc., of the equivalent size of the main transistor group 44 , and the specific proportion is related to the actual trimming accuracy.

[0066] According to one embodiment, when the widths of the transistors T470 to T47n in the second trimming circuit 47 are similar to or the same as the width of the second transistor T442, the trimming accuracy of the ratio K can be more effectively improved.

[0067] According to one embodiment, the first trimming circuit 46 and the second trimming circuit 47 do not operate at the same time.

[0068] According to one embodiment, the sizes of transistors T460 through T46n in the first trimming circuit 46 increase in geometric proportion, with the size ratio being a first fixed value. That is, the size ratio of the preceding transistor to the succeeding transistor is a first fixed value, which can achieve a better trimming effect for the ratio K. For example, the size ratio of transistor T461 to transistor T460 is 2, the size ratio of transistor T462 to transistor T461 is 2, and so on.

[0069] According to one embodiment, the sizes of transistors T470 through T47n in the second trimming circuit 47 increase proportionally, with the size ratio being a second fixed value. That is, the size ratio of each transistor to the size of the previous transistor is a second fixed value. In this case, a better trimming effect of the ratio K can be achieved. For example, the size ratio of transistor T471 to transistor T470 is 3, the size ratio of transistor T472 to transistor T471 is 3, and so on.

[0070] In some embodiments, the first fixed value and the second fixed value may be equal to each other, which facilitates the control of the trimming circuit and achieves good trimming accuracy.

[0071] In some embodiments, the transistors T460 to T46n in the first trimming circuit 46 may not have a fixed size ratio with each other.

[0072] In some other embodiments of the present application, the transistors T470 to T47n in the second trimming circuit 47 may not have a fixed size ratio with each other.

[0073] For example, the equivalent width of the main transistor group 44 is W0, and the equivalent length is L0. The width of the first transistor T441 and the second transistor T442 are both 50% W0, that is, the value of x is 50%, and the lengths of both are L0. Ideally, the mirror current Transistor T45 has a channel width of KW0 and a channel length of L0. In this case, in the first trimming circuit 46, the channel lengths of transistors T460 to T46n in the first transistor group are all L0, the first fixed value is 2, and the channel widths can be 2% W0, 4% W0, and 8% W0, respectively. In the second trimming circuit 47, the channel widths of transistors T470 to T47n in the second transistor group can all be 50% W0, the second fixed value is 2, and the channel lengths can be 2% L0, 4% L0, and 8% L0, respectively.

[0074] When the ratio K is reduced, the first switch S443 is closed and the switches S470 to S47n in the second trimming circuit 47 are opened, and the first trimming circuit 46 is in operation. In this case, the switch S460 is closed, the other switches are opened, and the transistor T460 is connected to the current mirror. The trimmed ratio When switches S460 and S461 are closed and other switches are closed, the adjusted ratio .

[0075] When the ratio K is increased, the first switch S443 and the switches S460 to S46n in the first trimming circuit 46 are disconnected, and the second trimming circuit 47 is in operation. In this case, the switch S470 is closed, the other switches are disconnected, and the transistor T470 is connected to the current mirror. The trimmed ratio ; When switch S471 is closed and other switches are closed, the adjusted ratio When switch S472 is closed and other switches are closed, the adjusted ratio .

[0076] Figure 5 FIG. 1 is a schematic diagram of a current mirror structure according to another embodiment of the present application.

[0077] According to one embodiment, a current mirror includes a current source 51, a common-gate transistor T52, and a transistor T53. The current source 51 is configured to receive a power supply voltage VDD and provide a reference current Iin. A first electrode of the transistor T52 is electrically connected to an output terminal of the current source 51. A first electrode of the transistor T53 provides a mirror current Iout.

[0078] According to one embodiment, the current mirror further includes a master transistor group 54 electrically connected to the second electrode of the transistor T52 and a slave transistor T55 electrically connected to the second electrode of the transistor T53 .

[0079] According to one embodiment, the main transistor group 54 includes two transistors with a common gate and a common source, namely a first transistor T541 and a second transistor T542 .

[0080] According to one embodiment, a first electrode of the first transistor T541 is electrically connected to a second electrode of the transistor T52 .

[0081] According to one embodiment, the second electrodes of the first transistor T541 and the second transistor T542 are electrically connected to the second electrode of the slave transistor T55 , respectively.

[0082] According to one embodiment, the control electrode of the slave transistor T55 is electrically connected to the control electrodes of the first and second transistors T541 and T542 and is also electrically connected to the first electrode of the transistor T52. The first electrode of the slave transistor T55 is electrically connected to the second electrode of the transistor T53.

[0083] According to one embodiment, the second electrode of the slave transistor T55 is connected to ground.

[0084] According to one embodiment, the current mirror may include a first trimming circuit 56 electrically connected between the first electrode and the second electrode of the first transistor T541, and / or a third trimming circuit 57 electrically connected between the first electrode of the first transistor T541 and the first electrode of the second transistor T542, to achieve bidirectional adjustment of the contrast value K.

[0085] According to one embodiment, the first trimming circuit 56 is configured to reduce the value of the ratio K. The third trimming circuit 57 is configured to increase the value of the ratio K.

[0086] According to one embodiment, the first trimming circuit 56 can be connected to Figure 4 The first trimming circuit 46 has a similar structure.

[0087] In one embodiment, the first trimming circuit 56 includes a first group of transistors shared with the first transistor T541 and the second transistor T542, and a first group of switches. The first group of transistors includes transistors T560 through T56n, and the first group of switches includes switches S560 through S56n electrically connected between the first electrodes of the transistors T560 through T56n and the first electrode of the first transistor T541, respectively. The first group of switches is configured to electrically connect the first electrodes of corresponding transistors T560 through T56n to the first electrode of the first transistor T541, thereby increasing the equivalent size of the second transistor T542.

[0088] According to one embodiment, the control electrodes of the transistors T560 to T56n in the first transistor group are electrically connected to each other and to the control electrodes of the first transistor T541 and the second transistor T542, and their respective second electrodes are electrically connected to the second electrode of the second transistor T542.

[0089] According to one embodiment, the third trimming circuit 57 includes a third group of transistors sharing a common gate with the first transistor T541 and the second transistor T542, and a third group of switches. The third group of transistors includes transistors T570 through T57n, and the third group of switches includes switches S570 through S57n electrically connected between the first and second electrodes of transistors T570 through T57n, respectively. The third group of switches is configured to disconnect the first and second electrodes of corresponding transistors T570 through T57n, thereby reducing the size of the second transistor T542.

[0090] According to one embodiment, in the third group of transistors, the control electrodes of transistors T570 to T57n are electrically connected to each other and also to the control electrodes of the first transistor T541 and the second transistor T542. Transistors T570 to T57n are electrically connected in series between the first electrode of the first transistor T541 and the first electrode of the second transistor T542. That is, in the third group of transistors, the second electrode of transistor T570 is electrically connected to the first electrode of the second transistor T542, the second electrode of transistor T571 is electrically connected to the first electrode of transistor T570, and so on.

[0091] In one embodiment, the transistors T570 to T57n may also be of the same type as the transistor T52, the transistor T53, the slave transistor T55, the first transistor T541, and the second transistor T542.

[0092] According to one embodiment, when the number of disconnected switches in the third trimming circuit 57 increases, the number of transistors electrically connected between the first electrode of the first transistor T541 and the first electrode of the second transistor T542 increases, and the number of transistors connected to the current mirror increases.

[0093] According to one embodiment, when the widths of the transistors T570 to T57n in the third trimming circuit 57 are similar to or the same as the width of the second transistor T542, the trimming accuracy of the ratio K can be more effectively improved.

[0094] In one embodiment of the present application, the equivalent width of the main transistor group 54 is W0, and the equivalent length is L0. The width of the first transistor T541 is W01, and the width of the second transistor T542 is W02. The sum of their widths is the equivalent width W0 of the main transistor group 54, and the lengths of both are L0; the width of the slave transistor T55 is W1, and the length is L1; the ratio The lengths of transistors T570 to T57n in the third trimming circuit 57 are Ls1, Ls2, ..., Lsn, respectively, and their widths are the same as the width of the second transistor T542. The ratio obtained after trimming is This is equivalent to increasing the length of the main transistor group 54 so that the ratio K decreases.

[0095] In one embodiment, the sizes of the transistors T570 to T57n may be, for example, 1%, 2%, 5%, etc., of the equivalent size of the main transistor group 54 , and the specific proportion value is related to the actual trimming accuracy.

[0096] According to one embodiment, the first trimming circuit 56 and the third trimming circuit 57 do not operate at the same time.

[0097] According to one embodiment, when the first trimming circuit 56 is in operation, all switches S570 to S57n in the third trimming circuit 57 are closed, and the first trimming circuit 56 is electrically connected to the second transistor T542 via the third trimming circuit 57. When all switches in the first group are open, the ratio K is reduced by closing switches S560 to S56n.

[0098] According to one embodiment, when the third trimming circuit 57 is operating, all switches S560 through S56n in the first trimming circuit 56 are disconnected. By disconnecting one or more switches in the third set of switches, the equivalent size of the second transistor T542 is reduced, thereby reducing the equivalent size of the main transistor group 54 and increasing the value of the ratio K.

[0099] According to one embodiment, the sizes of transistors T570 through T57n in the third trimming circuit 57 increase in geometric proportion, with the size ratio being a third fixed value. That is, the size ratio of the preceding transistor to the succeeding transistor is a third fixed value, which can achieve a better trimming effect for the ratio K. For example, the size ratio of transistor T571 to transistor T570 is 5, the size ratio of transistor T572 to transistor T571 is 5, and so on.

[0100] In some embodiments, the third fixed value may be equal to the first fixed value of the size ratio between the transistors T560 to T56n in the first group of transistors.

[0101] In some other embodiments of the present application, in the third trimming circuit 57 , the transistors T570 to T57n in the third group of transistors may not have a fixed size ratio with each other.

[0102] In one embodiment of the present application, the slave transistors in the current mirror may also be equivalently divided according to the error ratio. Figure 6 FIG. 1 is a schematic diagram of a current mirror structure according to another embodiment of the present application.

[0103] According to one embodiment, a current mirror includes a current source 81, a common-gate transistor T82, and a transistor T83. The current source 81 is configured to receive a power supply voltage VDD and provide a reference current Iin. A first electrode of the transistor T82 is electrically connected to an output terminal of the current source 81. A first electrode of the transistor T83 provides a mirror current Iout.

[0104] According to one embodiment, the current mirror further includes a master transistor T84 and a slave transistor group 85. The master transistor T84 is configured to receive the reference current Iin delivered by the transistor T82. The first electrode of the master transistor T84 is electrically connected to the second electrode of the transistor T82, the second electrode thereof is grounded, and the control electrode thereof is electrically connected to the first electrode of the transistor T82.

[0105] According to one embodiment, the slave transistor group 85 is electrically connected to the second electrode of the transistor T83 and is configured to generate a mirror current Iout proportional to the reference current Iin.

[0106] According to one embodiment, the slave transistor group 85 includes two transistors with a common gate and a common source, namely, a third transistor T851 and a fourth transistor T852 .

[0107] According to one embodiment, a first electrode of the third transistor T851 is electrically connected to a second electrode of the transistor T83 .

[0108] According to one embodiment, the current mirror may further include a second switch S853. The first electrode of the fourth transistor T852 is electrically connected between the first electrode of the third transistor T851 and the second electrode of the transistor T83 via the second switch S853. The first end of the second switch S853 is electrically connected to the first electrode of the third transistor T851, and the second end thereof is electrically connected to the first electrode of the fourth transistor T852.

[0109] According to one embodiment, the second electrodes of the third transistor T851 and the fourth transistor T852 are both electrically connected to the second electrode of the main transistor T84. The control electrodes of the third transistor T851 and the fourth transistor T852 are electrically connected to the control electrode of the main transistor T84 and also electrically connected to the first electrode of the transistor T82.

[0110] According to one embodiment, the ratio of the equivalent size of the slave transistor group 85 to the size of the master transistor T84 is K, and the error ratio of the ratio K is x. The size of the third transistor T851 may be 1-x times the product of the size of the master transistor T84 and the ratio K, and the size of the fourth transistor T852 may be x times the product of the size of the master transistor T84 and the ratio K.

[0111] In one embodiment of the present application, the lengths of the third transistor T851 , the fourth transistor T852 , and the main transistor T84 may be substantially equal or the same, and their widths may be unequal.

[0112] According to one embodiment, the width of the fourth transistor T852 may be x times the equivalent width of the slave transistor group 85, and the width of the third transistor T851 may be (1-x) times the equivalent width of the slave transistor group 85. For example, the equivalent length of the slave transistor group 85 is L1 and the equivalent width is W1, and the ideal ratio is K, and the error ratio is set to x. In this case, the width of the third transistor T851 is and the width of the fourth transistor T852 , the lengths of the third transistor T851 and the fourth transistor T852 are both L1.

[0113] In another embodiment of the present application, the widths of the third transistor T851 , the fourth transistor T852 , and the main transistor T84 may be substantially equal or the same, and their lengths may be unequal.

[0114] According to one embodiment, the transistor T82 , the transistor T83 , the main transistor T84 , the third transistor T851 , and the fourth transistor T852 may be of the same type, for example, N-type transistors.

[0115] According to one embodiment, the current mirror may further include a fifth trimming circuit 86 and / or a sixth trimming circuit 87 electrically connected to the fourth transistor T852 to achieve bidirectional adjustment of the contrast value K.

[0116] In one embodiment, the fifth trimming circuit 86 is configured to increase the ratio K. In one embodiment, the sixth trimming circuit 87 is configured to decrease the ratio K.

[0117] According to one embodiment, the fifth trimming circuit 86 can be connected to Figure 4 The first trimming circuit 46 has a similar structure.

[0118] According to one embodiment, the sixth trimming circuit 87 can be connected to Figure 4 The second trimming circuit 47 has a similar structure.

[0119] In one embodiment, the fifth trimming circuit 86 includes a fifth group of transistors sharing a common gate with the third transistor T851 and the fourth transistor T852, and a fifth group of switches. The fifth group of transistors includes transistors T860 through T86n, and the fifth group of switches includes switches S860 through S86n electrically connected between the first terminals of the transistors T860 through T86n and the first terminal of the second switch S853, respectively. The fifth group of switches is configured to connect corresponding transistors T860 through T86n in parallel with the fourth transistor T852 when the second switch S853 is closed, thereby increasing the effective size of the fourth transistor T852.

[0120] In one embodiment, the control electrodes of the transistors T860 to T86n are electrically connected to each other and to the control electrodes of the third transistor T851 and the fourth transistor T852 , and the second electrodes of the transistors T860 to T86n are electrically connected to the second electrode of the fourth transistor T852 .

[0121] According to one embodiment, the transistors T860 to T86n in the fifth trimming circuit 86 are connected in parallel.

[0122] According to one embodiment, when the lengths of the transistors T860 to T86n in the fifth trimming circuit 86 are similar to or identical to the equivalent length of the transistor group 85, the trimming accuracy of the ratio K can be more effectively improved.

[0123] According to one embodiment, the sixth trimming circuit 87 includes a sixth group of transistors sharing a common gate with the third transistor T851 and the fourth transistor T852, and a sixth group of switches. The sixth group of transistors includes transistors T870 through T87n, and the sixth group of switches includes switches S870 through S87n electrically connected between the first electrodes of transistors T870 through T87n and the first end of the second switch S853, respectively. The sixth group of switches is configured to electrically connect the first electrodes of corresponding transistors T870 through T87n to the first electrode of the third transistor T851, thereby reducing the equivalent size of the fourth transistor T852.

[0124] According to one embodiment, control electrodes of the transistors T870 to T87n are electrically connected to each other and to control electrodes of the third and fourth transistors T851 and T852, and respective second electrodes are electrically connected to a first electrode of the fourth transistor T852.

[0125] According to one embodiment, when the widths of the transistors T870 to T87n in the sixth trimming circuit 87 are similar to or the same as the width of the fourth transistor T852, the trimming accuracy of the ratio K can be more effectively improved.

[0126] According to one embodiment, the fifth trimming circuit 86 and the sixth trimming circuit 87 do not operate at the same time.

[0127] According to one embodiment, when the second switch S853 is disconnected, all switches in the fifth group of switches in the fifth trimming circuit 86 are disconnected. The sixth trimming circuit 87 operates to close switches in the sixth group of switches, thereby reducing the equivalent size of the fourth transistor T852, thereby reducing the equivalent size of the transistor group 75, and reducing the value of the ratio K.

[0128] According to one embodiment, when the second switch S853 is closed, the fifth trimming circuit 86 operates and all the switches in the sixth trimming circuit 87 are opened. By closing the switches in the fifth switch group, the equivalent size of the slave transistor group 85 increases, and the value of the ratio K increases.

[0129] According to one embodiment, the sizes of transistors T860 to T86n in the fifth trimming circuit 86 increase proportionally, and the size ratio is a fifth fixed value. That is, the size ratio of each transistor to the previous transistor is a fifth fixed value.

[0130] According to one embodiment, the sizes of the transistors T870 to T87n in the sixth trimming circuit 87 are increased in geometric proportion, and the size ratio is a sixth fixed value.

[0131] In some embodiments, the fifth fixed value and the sixth fixed value may be equal.

[0132] In some other embodiments of the present application, the transistors T860 to T86n in the fifth trimming circuit 86 or the transistors T870 to T87n in the sixth trimming circuit 87 do not have a fixed size ratio with each other.

[0133] Figure 7 FIG. 1 is a schematic diagram of a current mirror structure according to another embodiment of the present application.

[0134] According to one embodiment, the current mirror includes a current source 91 , a transistor T92 and a transistor T93 with a common gate. A first electrode of the transistor T92 is electrically connected to an output terminal of the current source 91 .

[0135] According to one embodiment, the current mirror may further include a master transistor T94 and a slave transistor group 95. A first electrode of the master transistor T94 is electrically connected to the second electrode of the transistor T92, a second electrode thereof is grounded, and a control electrode thereof is electrically connected to the first electrode of the transistor T92. The master transistor T94 is configured to receive the reference current Iin transmitted by the transistor T92, and the slave transistor group 95 is configured to generate a mirror current Iout proportional to the reference current Iin.

[0136] According to one embodiment, the slave transistor group 95 includes two transistors with a common gate and a common source, namely a third transistor T951 and a fourth transistor T952. A first electrode of the third transistor T951 is electrically connected to a second electrode of the transistor T93. A second electrode of the third transistor T951 and a second electrode of the fourth transistor T952 are respectively electrically connected to a second electrode of the master transistor T94. The control electrodes of the third transistor T951 and the fourth transistor T952 are also electrically connected to the control electrode of the master transistor T94 and to the first electrode of the first transistor T92.

[0137] According to one embodiment, the current mirror further includes a fifth trimming circuit 96 and / or a seventh trimming circuit 97 electrically connected to the fourth transistor T952 to achieve bidirectional adjustment of the contrast value K.

[0138] According to one embodiment, the fifth trimming circuit 96 and the seventh trimming circuit 97 do not operate simultaneously. The fifth trimming circuit 96 is configured to increase the equivalent size of the slave transistor group 95, thereby increasing the value of the ratio K. The seventh trimming circuit 97 is configured to decrease the equivalent size of the slave transistor group 95, thereby decreasing the value of the ratio K.

[0139] According to one embodiment, the fifth trimming circuit 96 can be Figure 6 The fifth trimming circuit 86 has a similar structure. The seventh trimming circuit 97 can be Figure 5 The third trimming circuit 57 has a similar structure.

[0140] In one embodiment, the fifth trimming circuit 96 includes a fifth group of transistors sharing a common gate with the third transistor T951 and the fourth transistor T952, and a fifth group of switches. The fifth group of transistors includes transistors T960 through T96n, and the fifth group of switches includes switches S960 through S96n electrically connected between the first electrodes of transistors T960 through T96n and the first electrode of the third transistor T951, respectively. The fifth group of switches is configured to electrically connect the first electrodes of corresponding transistors T960 through T96n to the first electrode of the third transistor T951, thereby increasing the size of the fourth transistor T952.

[0141] According to one embodiment, the control electrodes of the transistors T960 to T96n are electrically connected to each other and to the control electrodes of the third transistor T951 and the fourth transistor T952 , and the second electrodes of the transistors T960 to T96n are electrically connected to the second electrode of the fourth transistor T952 .

[0142] According to one embodiment, the seventh trimming circuit 97 includes a seventh group of transistors sharing a common gate with the third transistor T951 and the fourth transistor T952, and a seventh group of switches. The seventh group of transistors includes transistors T970 through T97n, and the seventh group of switches includes switches S970 through S97n electrically connected between the first and second electrodes of transistors T970 through T97n, respectively. The seventh group of switches is configured to disconnect the first and second electrodes of corresponding transistors T970 through T97n, thereby reducing the size of the fourth transistor T952.

[0143] According to one embodiment, the control electrodes of transistors T970 to T97n are electrically connected to each other, and their respective control electrodes are electrically connected to the control electrodes of the third transistor T951 and the fourth transistor T952. Transistors T970 to T97n are electrically connected in series between the first electrode of the third transistor T951 and the first electrode of the fourth transistor T952. That is, the second electrode of transistor T970 is electrically connected to the first electrode of the fourth transistor T952, the second electrode of transistor T971 is electrically connected to the first electrode of transistor T970, and so on.

[0144] According to one embodiment, when the widths of the transistors T970 to T97n in the seventh trimming circuit 97 are similar to or the same as the width of the fourth transistor T952, the trimming accuracy of the ratio K can be more effectively improved.

[0145] According to one embodiment, when the seventh trimming circuit 97 is in operation, all switches in the fifth trimming circuit are turned off. By turning off one or more switches from switch S970 to switch S97n, the equivalent size of the transistor group 95 is reduced, and the value of the ratio K is reduced.

[0146] According to one embodiment, when fifth trimming circuit 96 is in operation, switches S970 through S97n in seventh trimming circuit 97 are all closed, electrically connecting fifth trimming circuit 96 between the first and second electrodes of fourth transistor T952. Closing the switches in the fifth set of switches increases the equivalent size of transistor group 95, thereby increasing the value of ratio K.

[0147] According to one embodiment, the sizes of the transistors T970 to T97n in the seventh trimming circuit 97 are increased in geometric proportion, and the size ratio is a seventh fixed value.

[0148] In some embodiments, the seventh fixed value may be equal to or different from the fifth fixed value of the fifth trimming circuit 96 .

[0149] The present application also includes an electronic device, comprising any of the above-mentioned current mirrors, the current mirror comprising a master transistor group and / or a slave transistor group, and any of the above-mentioned trimming circuits.

[0150] The high-precision current mirror proposed in this application can achieve precise adjustment of the ratio of the mirror current to the reference current, greatly improving the accuracy of the mirror current output by the current mirror. At the same time, it saves circuit layout and cost and has high reliability and stability.

[0151] The above embodiments are only used to illustrate the present application and are not intended to limit the present application. Ordinary technicians in the relevant technical field can make various changes and modifications without departing from the scope of the present application. Therefore, all equivalent technical solutions should also fall within the scope disclosed in the present application.

Claims

1. A high-precision current mirror, characterized in that: include: a main transistor group configured to receive a reference current; a slave transistor configured to generate a mirror current proportional to a reference current; The master transistor group includes a first transistor and a second transistor, the control electrodes of which are electrically connected to each other; the second electrodes of the first transistor and the second transistor are both grounded; the equivalent size ratio of the slave transistor to the master transistor group is a ratio K; the size of the first transistor is 1-x times the ratio of the size of the slave transistor to the ratio K, and the size of the second transistor is x times the ratio of the size of the slave transistor to the ratio K; x is the percentage of the difference between the actual value and the expected value of the ratio K to the expected value; and A first trimming circuit, electrically connected to the second transistor, configured to reduce the ratio K; and / or, The second trimming circuit is electrically connected to the second transistor and configured to increase the ratio K.

2. The high-precision current mirror according to claim 1, wherein: in, The value of x is a percentage not greater than 20%.

3. The high-precision current mirror according to claim 1, wherein: The first trimming circuit includes: a first group of transistors, comprising one or more transistors connected in parallel; a control electrode of each transistor in the first group of transistors being electrically connected to the control electrode of the first transistor and the control electrode of the second transistor; and a second electrode of each transistor in the first group of transistors being electrically connected to the second electrode of the second transistor; as well as, The first group of switches includes one or more switches, each electrically connected between a first electrode of a corresponding transistor in the first group of transistors and a first electrode of the second transistor.

4. The high-precision current mirror according to claim 3, wherein: The length of each transistor in the first group of transistors is equal to the equivalent length of the main transistor group.

5. The high-precision current mirror according to claim 1, wherein: The first electrode of the second transistor is electrically connected to the first electrode of the first transistor through a first switch; wherein the first end of the first switch is electrically connected to the first electrode of the first transistor.

6. The high-precision current mirror according to any one of claims 1 or 5, characterized in that: The second trimming circuit includes: a second set of transistors comprising one or more transistors connected in parallel with each other; The control electrodes of each transistor in the second group of transistors are electrically connected to the control electrodes of the first transistor and the second transistor; and the second electrodes of each transistor in the second group of transistors are electrically connected to the first electrode of the second transistor; and, The second group of switches includes one or more switches; each switch in the second group of switches is electrically connected between the first electrode of each transistor in the second group of transistors and the first electrode of the first transistor.

7. The high-precision current mirror according to claim 6, wherein: The width of each transistor in the second group of transistors is equal to the width of the second transistor.

8. The high-precision current mirror according to claim 1, wherein: The second trimming circuit includes: A third group of transistors includes one or more transistors connected in series between the first electrode of the first transistor and the first electrode of the second transistor; The control electrode of each transistor in the third group of transistors is electrically connected to the control electrodes of the first transistor and the second transistor; and The third group of switches includes one or more switches; each switch in the third group of switches is electrically connected between the first electrode and the second electrode of each transistor in the third group of transistors.

9. The high-precision current mirror according to claim 8, characterized in that: The width of each transistor in the third group of transistors is equal to the width of the second transistor.

10. An electronic device, characterized in that: The invention comprises the high-precision current mirror described in any one of claims 1-9.

11. A high-precision current mirror, characterized in that: include: a main transistor configured to receive a reference current; a slave transistor group configured to generate a mirror current proportional to a reference current; The slave transistor group includes a third transistor and a fourth transistor, the control electrodes of which are electrically connected to each other; the second electrodes of the third transistor and the fourth transistor are both grounded; the ratio of the equivalent size of the slave transistor group to the size of the master transistor is a ratio K; the size of the third transistor is 1-x times the product of the size of the master transistor and the ratio K, and the size of the fourth transistor is x times the product of the size of the master transistor and the ratio K; wherein x is the percentage of the difference between the actual value and the expected value of the ratio K as a percentage of the expected value; and a fifth trimming circuit, electrically connected to the fourth transistor, configured to increase the ratio K; and / or, A sixth trimming circuit is electrically connected to the fourth transistor and configured to reduce the ratio K.

12. The high-precision current mirror according to claim 11, wherein: in, The value of x is a percentage not greater than 20%.

13. The high-precision current mirror according to claim 11, wherein: in, The fifth trimming circuit includes: a fifth group of transistors, comprising one or more transistors connected in parallel, wherein a control electrode of each transistor in the fifth group of transistors is electrically connected to the control electrodes of the third transistor and the fourth transistor; and a second electrode of each transistor in the fifth group of transistors is electrically connected to the second electrode of the fourth transistor; as well as, The fifth group of switches includes one or more switches, each electrically connected between the first electrode of a corresponding transistor in the fifth group of transistors and the first electrode of the fourth transistor.

14. The high-precision current mirror according to claim 13, wherein: The length of each transistor in the fifth group of transistors is equal to the equivalent length of the slave transistor group.

15. The high-precision current mirror according to claim 11, wherein: in, The first electrode of the fourth transistor is electrically connected to the first electrode of the third transistor through a second switch; wherein the first end of the second switch is electrically connected to the first electrode of the third transistor.

16. The high-precision current mirror according to any one of claims 11 or 15, characterized in that: The sixth trimming circuit includes: a sixth group of transistors, comprising one or more transistors connected in parallel; a control electrode of each transistor in the sixth group of transistors being electrically connected to the control electrodes of the third transistor and the fourth transistor; and a second electrode of each transistor in the sixth group of transistors being electrically connected to the first electrode of the fourth transistor; and The sixth group of switches includes one or more switches, and each switch in the sixth group of switches is electrically connected between the first electrode of each transistor in the sixth group of transistors and the first electrode of the third transistor.

17. The high-precision current mirror according to claim 16, wherein: The width of each transistor in the sixth group of transistors is equal to the width of the fourth transistor.

18. The high-precision current mirror according to claim 11, wherein: in, The sixth trimming circuit includes: a seventh group of transistors, comprising one or more transistors connected in series between the first electrode of the third transistor and the first electrode of the second transistor; The control electrode of each transistor in the seventh group of transistors is electrically connected to the control electrodes of the third transistor and the fourth transistor; and The seventh group of switches includes one or more switches; each switch in the seventh group of switches is electrically connected between the first electrode and the second electrode of a corresponding transistor in the seventh group of transistors.

19. The high-precision current mirror according to claim 18, wherein: The width of each transistor in the seventh group of transistors is equal to the width of the fourth transistor.

20. An electronic device, characterized in that: The invention comprises the high-precision current mirror described in any one of claims 11-19.

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