Layout graph etching simulation method, product and equipment

Abstract

The invention provides a layout graph etching simulation method, a product and equipment. The method comprises the following steps: acquiring a target technological process and an initial layout graph operated by the target technological process; determining a plurality of etching operations in the target technological process, and obtaining a stage etching model corresponding to each etching operation; performing simulation processing on the etching operation through the stage etching model; and inputting a simulation result of the simulation processing of the stage etching model into the final etching model, and fitting the simulation result by using the final etching model to obtain a final simulation result corresponding to the target technological process. Through the method, the corresponding composite etching model can be established according to the target technological process, and simulation processing is performed on the target technological process through the composite etching model, so that the influence between etching operations in the target technological process is comprehensively considered, and finally an accurate simulation result is obtained for subsequent detection.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method, product and equipment for simulating etching of a layout graphic. Background Art

[0002] In the current field of semiconductor technology, the most core step in semiconductor chip manufacturing is to transfer the chip design pattern to the silicon wafer. Among the many process steps in chip manufacturing, the processes directly related to pattern transfer are mainly photolithography and etching. Both the photolithography process and the etching process will produce deviations, resulting in differences between the photolithography pattern, the etching pattern and the mask pattern. Therefore, when designing the mask pattern, it is necessary to compensate for the photolithography deviation and the etching deviation. At present, the photolithography deviation is mainly compensated by optical proximity correction (OPC). As for the etching deviation, the main method is to establish an etching deviation table to save the etching deviation corresponding to different graphics, and then match the corresponding etching deviation in the etching deviation table based on the corresponding graphic style. For example, the corresponding etching deviation is determined according to the line width (width) and spacing (space) of the edge of the current polygon; and then the etching deviation compensation is completed.

[0003] However, etching differs from photolithography in that its physical and chemical processes are more complex. For patterns with varying line widths and spacing, the etch deviation will vary. For simple patterns, current methods based on etch deviation tables are suitable. However, in actual production, the line density of the pattern also affects the etch deviation. For complex patterns, current methods based on etch deviation table searches struggle to achieve good results, resulting in an inability to accurately determine the etch deviation, and consequently, the final designed mask pattern fails to meet actual requirements. Summary of the Invention

[0004] In view of the above problems, the present invention proposes a layout pattern etching simulation method, product and device that overcome the above problems or at least partially solve the above problems.

[0005] One object of the present invention is to establish a composite etching model that can comprehensively consider the impact between various etching operations in a target process flow;

[0006] Another further object of the present invention is to improve the accuracy of simulation of complex etching processes.

[0007] In particular, the present invention provides a method for simulating etching of a layout pattern, comprising:

[0008] Obtaining a target process flow and an initial layout graphic of target process flow operations;

[0009] Determine multiple etching operations in a target process flow and obtain a stage etching model corresponding to each etching operation;

[0010] The etching operation is simulated through the stage etching model;

[0011] The simulation results of the stage etching model simulation processing are input into the final etching model, and the simulation results are fitted using the final etching model to obtain the final simulation results corresponding to the target process flow.

[0012] Optionally, the etching operation includes a dependent etching operation, the dependent etching operation corresponds to a dependent stage etching model, and the dependent stage etching model is used to perform simulation processing based on simulation results of a preceding operation on which the dependent etching operation depends;

[0013] The steps to simulate the etching operation using the staged etching model include:

[0014] In the case where the etching operation is a dependent etching operation, determining a target preceding operation on which the dependent etching operation depends;

[0015] Obtaining a pre-order stage etching model corresponding to a target pre-order operation, and simulating the target pre-order operation using the pre-order stage etching model to obtain a pre-order simulation result;

[0016] A dependent stage etching model corresponding to the dependent etching operation is obtained, and the previous simulation result is input into the dependent stage etching model for simulation processing.

[0017] Optionally, the target preceding operation includes a preceding etching operation and preceding process operations between the preceding etching operation and the dependent etching operation;

[0018] The steps of simulating the target pre-sequence operation through the pre-sequence stage etching model to obtain the pre-sequence simulation result include:

[0019] Use the pre-sequence stage etching model to simulate the pre-sequence etching operation to obtain the pre-sequence etching result;

[0020] Performing process logic operation on the previous etching result according to the previous process operation to obtain a previous logic operation result;

[0021] The preamble etching result and the preamble logic operation result are combined as the preamble simulation result.

[0022] Optionally, the step of inputting the previous simulation result into the dependent stage etching model for simulation processing includes:

[0023] Obtaining a pre-sequence etching profile corresponding to a pre-sequence simulation result;

[0024] The preceding etching profile is converted by a preset curve mask sampling method to obtain a preceding mask image;

[0025] The preceding mask image is input into the dependent stage etching model for simulation.

[0026] Optionally, the etching operation further includes an independent etching operation, the independent etching operation corresponds to an independent stage etching model, and the independent stage etching model is used to perform simulation processing based on the initial layout pattern;

[0027] The steps to simulate the etching operation using the staged etching model include:

[0028] In the case where the etching operation is an independent etching operation, an independent stage etching model corresponding to the independent etching operation is obtained, and the initial layout pattern is input into the independent stage etching model for simulation processing.

[0029] Optionally, the step of fitting the simulation results using the final etching model to obtain a final simulation result corresponding to the target process flow includes:

[0030] Obtaining dependent simulation results corresponding to the dependent stage etching model and independent simulation results corresponding to the independent stage etching model;

[0031] Perform process logic operations on dependent simulation results and independent simulation results according to the target process flow to obtain preprocessing results;

[0032] The preprocessing results, dependent simulation results and independent simulation results are input into the final etching model for simulation processing to obtain the final simulation results.

[0033] Optionally, the step of inputting the preprocessing result, the dependent simulation result, and the independent simulation result into the final etching model for simulation processing to obtain the final simulation result includes:

[0034] Obtaining etching profiles corresponding to preprocessing results, dependent simulation results, and independent simulation results respectively;

[0035] The etching profile is converted to obtain a mask image by using a preset curve mask sampling method;

[0036] The mask image is input into the final etching model for simulation processing to obtain the final simulation result.

[0037] Optionally, after the step of fitting the simulation results using the final etching model to obtain the final simulation results corresponding to the target process flow, the method further includes:

[0038] Perform simulation bad point detection on the final simulation results and determine whether the initial layout graphics meet the preset requirements based on the detection results.

[0039] According to another aspect of the present invention, a computer program product is provided, which includes a computer program. When the computer program is executed by a processor, the computer program implements the steps of any of the above-mentioned methods for simulating etching of layout graphics.

[0040] According to another aspect of the present invention, a computer device is also provided, comprising a memory, a processor, and a machine executable program stored in the memory and running on the processor, and the processor implements the steps of any of the above-mentioned etching simulation methods for layout graphics when executing the machine executable program.

[0041] The etching simulation method of the layout pattern of the present invention first obtains the target process flow and the initial layout pattern of the target process flow operation; then determines multiple etching operations in the target process flow and obtains the stage etching model corresponding to each etching operation; then simulates the etching operation using the stage etching model; finally, the simulation results of the stage etching model simulation are input into the final etching model, and the simulation results are fitted using the final etching model to obtain the final simulation result corresponding to the target process flow. Through this method, a corresponding composite etching model can be established according to the target process flow, and the target process flow can be simulated using the composite etching model, thereby comprehensively considering the influence between the various etching operations in the target process flow, and ultimately obtaining accurate simulation results for subsequent testing.

[0042] Based on the following detailed description of specific embodiments of the present invention in conjunction with the accompanying drawings, those skilled in the art will become more aware of the above and other objects, advantages and features of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Hereinafter, some specific embodiments of the present invention will be described in detail in an exemplary and non-limiting manner with reference to the accompanying drawings. The same reference numerals in the accompanying drawings indicate the same or similar components or parts. It should be understood by those skilled in the art that these drawings are not necessarily drawn to scale. In the accompanying drawings:

[0044] Figure 1 1 is a flow chart of a method for simulating etching of a layout pattern according to an embodiment of the present invention;

[0045] Figure 2 1 is a schematic diagram of a composite etching model architecture established by a layout pattern etching simulation method according to an embodiment of the present invention;

[0046] Figure 3 2 is a schematic diagram of a composite etching model architecture established by a layout pattern etching simulation method according to another embodiment of the present invention;

[0047] Figure 4is a schematic diagram of a computer program product according to one embodiment of the present invention;

[0048] Figure 5 is a schematic diagram of a computer-readable storage medium according to one embodiment of the present invention; and

[0049] Figure 6 is a schematic diagram of a computer device according to one embodiment of the present invention. DETAILED DESCRIPTION

[0050] It should be understood by those skilled in the art that the embodiments described below are only some embodiments of the present invention, rather than all embodiments of the present invention, and that these embodiments are intended to explain the technical principles of the present invention and are not intended to limit the scope of protection of the present invention. Based on the embodiments provided by the present invention, all other embodiments obtained by those skilled in the art without creative effort should still fall within the scope of protection of the present invention.

[0051] It should be noted that the logic and / or steps represented in the flowchart or described in other ways herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, device or equipment (such as a computer-based system, a system including a processor or other system that can fetch instructions from an instruction execution system, device or equipment and execute instructions), or used in combination with these instruction execution systems, devices or equipment.

[0052] In the current semiconductor technology landscape, and in the mainstream integrated circuit production process, photolithography involves chemically transforming photoresist under exposure to light of a specific wavelength. Development then transfers the pattern designed on the mask into the photoresist topography on the silicon wafer. Etching, on the other hand, selectively removes unwanted material with the help of the photoresist topography, ultimately creating the desired fine patterns on the silicon wafer.

[0053] As chip technology continues to evolve, the size of designed patterns has become much smaller than the wavelength of photolithography (193nm), leading to optical proximity effects and resulting in photolithography deviations. To compensate for this deviation, optical proximity correction (OPC) is required.

[0054] During the integrated circuit manufacturing process, etching is required after photolithography. This etching process can cause etch deviation, which means that the line width of the photoresist before and after etching is inconsistent. For example, when a wafer contains both sparse and dense patterns to be etched, the etch rate of the dense areas is lower than that of the sparse areas. This is called the micro-loading effect. For another example, when etching high-aspect-ratio structures, such as deep holes or deep trenches, the smaller holes or trenches have a lower etch rate than the larger ones. This is called the aperture effect.

[0055] As can be seen, etching different areas will correspond to different etching rates. This will not only cause the overall pattern size to change after etching, but more importantly, patterns of the same size after photolithography will also have different sizes after etching. When designing the mask pattern, etching deviation must be considered. Otherwise, even if the size of the lithographic pattern obtained after photolithography exposure meets the expected size, it will still deviate from the target size after etching.

[0056] For etching bias, the current approach is to create a bias table to store the corresponding etching biases for different graphics. Based on the corresponding graphic style, the corresponding etching bias is matched in the bias table. The current bias table mainly determines the corresponding etching bias based on the line width and spacing of the current polygon. For simple graphics, this can barely meet the requirements, but as the graphics become more complex, the accuracy of the traditional method decreases.

[0057] For two edges with exactly the same line width and spacing, if the surrounding pattern density is different, the final etching bias will also be different. Matching the etching bias according to the existing Bias-Table method will inevitably lead to errors. With the continuous evolution of semiconductor technology nodes, the accuracy requirements for pattern transfer (photolithography and etching) are getting higher and higher; and traditional methods cannot meet actual needs. In addition, with the continuous evolution of semiconductor manufacturing technology nodes, when the pattern period is less than, multiple patterning processes are required, that is, the transfer of patterns from the layout to the silicon wafer involves a combination of multiple patterning processes (photolithography + etching). At this time, if you want to consider the overall bad pixel simulation prediction based on the results of multiple etching processes, a single etching model cannot achieve it.

[0058] In order to solve the above problems, the present invention provides a method for simulating the etching of a layout pattern. The specific process is as follows: Figure 1 As shown, Figure 1 1 is a flow chart of a layout pattern etching simulation method according to an embodiment of the present invention. The layout pattern etching simulation method at least includes the following steps S101 to S104.

[0059] Step S101: Obtain a target process flow and an initial layout diagram for the target process flow operation. The target process flow is generally a multi-patterning process, such as self-aligned double patterning (SADP), self-aligned reverse patterning (SARP), and litho-etch-litho-etch (LELE).

[0060] Furthermore, taking the SARP process as an example, what's even more complex is that the final pattern isn't the same as the one formed by the SARP process. Instead, a cutting process (CUT) is added to it. In actual processes, there are multiple cutting layers (CUT layers), and the final patterning result is formed by multiple CUTs on top of the SARP result. Similarly, the results of multiple CUTs will affect each other when etching to form the final pattern, something that a single-etch model cannot account for. Accordingly, the LELE process will also add a CUT process due to actual needs, resulting in different types of multi-patterning processes, such as the LELE+CUT process and the LELELE+CUT process.

[0061] Step S102 : determining multiple etching operations in the target process flow, and obtaining a stage etching model corresponding to each etching operation.

[0062] In some optional embodiments, the etching operation may generally include a dependent etching operation and an independent etching operation. Among them, the dependent etching operation corresponds to a dependent stage etching model, and the dependent stage etching model is generally used to perform simulation processing based on the simulation results of the previous operation on which the dependent etching operation depends, while the independent etching operation corresponds to an independent stage etching model, and the independent stage etching model is generally used to perform simulation processing based on the initial layout graphics. Among them, the dependent stage etching model usually needs to consider the impact of the previous operation on the current stage operation, that is, consider the mutual coupling relationship between the two, and therefore needs to obtain the simulation results of the previous operation; while the independent stage etching model usually does not consider the impact of the previous operation on the current operation, and directly obtains the initial target graphics for simulation processing.

[0063] Taking the SARP process as an example, the first etch operation is performed in the SARP process. After the first etch, the mandrel structure (MDL) pattern is formed. Then, spacer layers (SPACER) are deposited on both sides of the MDL structure. The gap is then filled to form the non-mandrel pattern (NMDL) pattern. Finally, the MDL and NDML patterns are transferred to the hard mask through the second etch operation. In this process, the first etch and the final etch are somewhat different. The first etch is purely based on the results of the first photolithography. If modeling is required, it is a pure single-etch model. However, in the second etch, because the MDL pattern already exists, the final result is actually related to the previous etch results. Therefore, if the second etch results are to be modeled for simulated bad pixel prediction, the results of the first etch model must be included and the mutual coupling relationship between the two must be considered. From this, it can be seen that the second etch operation is a dependent etch operation, and its corresponding etch model is a dependent stage etch model, while the first etch operation is a precursor to the second etch operation.

[0064] It should be noted that the various stage etching models and the final etching model in the present invention can be obtained by pre-training, or can be established according to the specific process. And in order to further improve the accuracy of the etching model, the present invention chooses to introduce artificial intelligence (AI) in the stage etching model and the final etching model. The AI-assisted etching modeling can fit the effects that cannot be captured by traditional modeling methods, so that the etching model has higher accuracy, and then the accurate etching deviation can be determined. Those skilled in the art can determine the introduction method of artificial intelligence according to the actual situation, such as adding a neural network to the etching model, so that the corresponding etching model can autonomously simulate the corresponding simulation operation, or simulate each etching model through reinforcement learning.

[0065] Step S103 , simulating the etching operation using a stage etching model.

[0066] Optionally, when the etching operation is a dependent etching operation, the step of simulating the etching operation through a stage etching model may generally include: when the etching operation is a dependent etching operation, determining the target preceding operation on which the dependent etching operation depends; obtaining a preceding stage etching model corresponding to the target preceding operation, and simulating the target preceding operation through the preceding stage etching model to obtain a preceding simulation result; obtaining a dependent stage etching model corresponding to the dependent etching operation, and inputting the preceding simulation result into the dependent stage etching model for simulation.

[0067] Taking the SARP process as an example, the first and second etching steps differ somewhat. The first etch is based purely on the results of the first photolithography step, so if modeling is to be done, it is a pure single-shot etch model. However, in the second etch, because the MDL pattern already exists, the results of the second etch are related to the previous etch results. Therefore, if the second etch results are to be modeled for bad pixel prediction simulation, the results of the first etch modeling must be included and the mutual coupling relationship between the two must be considered, rather than simply using the photolithography results as input, as is the case with ordinary etch modeling.

[0068] Optionally, the target preceding operation includes a preceding etching operation and a preceding process operation between the preceding etching operation and the dependent etching operation; the step of simulating the target preceding operation through the preceding stage etching model to obtain a preceding simulation result may generally include: using the preceding stage etching model to simulate the preceding etching operation to obtain a preceding etching result; performing a process logic operation on the preceding etching result according to the preceding process operation to obtain a preceding logic operation result; and merging the preceding etching result and the preceding logic operation result as the preceding simulation result.

[0069] For example, the second etching operation in the SARP process is a dependent etching operation, while the first etching operation is a predecessor operation of the second etching operation. The process operations between the first and second etching operations are predecessor process operations, such as the spacer layer deposition and gap filling operations after the mandrel etching. Therefore, based on the SARP process, if you want to establish its corresponding composite etching model, you need to first obtain the predecessor stage etching model corresponding to the predecessor etching operation, simulate the predecessor etching operation to obtain the predecessor simulation result, and then perform process logic operation on the predecessor simulation result according to the predecessor process operations such as spacer layer deposition and gap filling to obtain the predecessor logic operation result, and then input the predecessor simulation result and the predecessor logic operation result into the dependent stage etching model corresponding to the second etching operation for simulation.

[0070] However, since the model obtained by the general modeling method usually needs to read in the mask image, and the simulation results of each etching model in the present invention are generally etching contours, the present invention chooses to convert them into mask images. Specifically, the step of inputting the preceding simulation results into the dependent stage etching model for simulation processing can generally include: obtaining the preceding etching contour corresponding to the preceding simulation results; converting the preceding etching contour by a preset curve mask sampling method to obtain a preceding mask image; and inputting the preceding mask image into the dependent stage etching model for simulation processing. The specific operation of the preset curve mask sampling method can be to regard the etching contour as a curve mask, and then convert the curve mask into a mask image by a curve mask sampling method. This etching contour to mask image conversion process can be called a CMI process (Contour to Mask Image). Through the CMI process, multiple results in the preceding operation can be converted into mask images and input into the dependent stage etching model for simulation processing. Those skilled in the art can determine the sampling logic in the preset curve mask sampling method and the subsequent specific algorithm according to actual conditions.

[0071] Optionally, when the etching operation is an independent etching operation, the step of simulating the etching operation using the stage etching model may generally include: obtaining an independent stage etching model corresponding to the independent etching operation, and inputting the initial layout pattern into the independent stage etching model for simulation. Some optional examples of independent etching operations include: obtaining a SARP result in a SARP process and then adding a cutting process (CUT). For such independent etching operations, the initial layout pattern can be simulated using its corresponding independent stage etching model to obtain a corresponding independent simulation result, and then fitting can be performed in a subsequent process.

[0072] Step S104 , inputting the simulation results of the stage etching model simulation processing into the final etching model, and fitting the simulation results using the final etching model to obtain the final simulation results corresponding to the target process flow.

[0073] In some optional embodiments, since the processing objects of the dependent stage etching model and the independent stage etching model are different, but each subsequent etching operation in the actual target process flow is processed based on the results of the previous step operation, it is necessary to perform a final fitting on each etching model after processing, so as to comprehensively consider the coupling effects between each operation. Therefore, the step of fitting the simulation results with the final etching model to obtain the final simulation results corresponding to the target process flow can generally include: obtaining the dependent simulation results corresponding to the dependent stage etching model and the independent simulation results corresponding to the independent stage etching model; performing process logic operations on the dependent simulation results and the independent simulation results according to the target process flow to obtain preprocessing results; inputting the preprocessing results, the dependent simulation results and the independent simulation results into the final etching model for simulation processing to obtain the final simulation results.

[0074] Optionally, since the final etching model generally also requires inputting a mask image for processing, the steps of inputting the preprocessing results, dependent simulation results, and independent simulation results into the final etching model for simulation processing to obtain the final simulation results can generally include: respectively obtaining the etching contours corresponding to the preprocessing results, dependent simulation results, and independent simulation results; converting the etching contours through a preset curve mask sampling method to obtain a mask image; and inputting the mask image into the final etching model for simulation processing to obtain the final simulation results.

[0075] This method can establish a corresponding composite etching model according to the target process flow, and simulate the target process flow through the composite etching model, so as to comprehensively consider the influence between each etching operation in the target process flow, and finally obtain accurate simulation results for subsequent testing.

[0076] In some optional embodiments, the cumulative effect of multiple patterning processes (such as SADP and LELE) can easily lead to hidden defects. Traditional methods that rely solely on single-step etching detection are unable to identify compound bad pixels caused by the coupling of multiple process steps. Therefore, in the method of the present invention, after using the final etching model to fit the simulation results to obtain the final simulation results corresponding to the target process flow, the method can generally also include: performing simulated bad pixel detection on the final simulation results and determining whether the initial layout pattern meets preset requirements based on the detection results. If bad pixels are detected during the detection, the parameters in the optical proximity effect correction scheme for the initial layout pattern can be adjusted accordingly.

[0077] In order to clearly illustrate the composite etching model established by the present invention for the multi-patterning process, an optional embodiment is provided. Figure 2 As shown, Figure 21 is a schematic diagram of a composite etching model architecture established by an etching simulation method for a layout pattern according to an embodiment of the present invention.

[0078] Figure 2 This is a composite etching model based on a SARP process. The specific process flow of the SARP process generally includes: first, performing a first etching operation on the initial layout pattern, forming a mandrel structure (MDL) pattern after the first etching; then depositing spacer layers (SPACER) on both sides of the MDL structure, followed by filling the gap to form a non-mandrel pattern (NMDL) pattern; finally, the MDL and NDML patterns are transferred to a hard mask through a second etching operation; after obtaining the SARP-formed pattern, multiple cutting processes are added to it. In this embodiment, two cutting processes are set (hereinafter referred to as CUT1 and CUT2) to obtain the final pattern.

[0079] Based on this target process flow, it can be determined that the first etching operation only needs to process the initial layout pattern after photolithography, while the second etching operation needs to rely on the results of the first etching operation to perform further processing. Therefore, the second etching operation is a dependent etching operation, and the first etching operation is a precursor etching operation to the dependent etching operation. In addition, the subsequent two cutting processes (CUT1 and CUT2) are not completely dependent on the second etching operation. They can first perform corresponding cutting operations on the initial layout pattern, and then perform unified fitting in the subsequent process. Therefore, they are independent etching operations.

[0080] The composite etching model established by the present invention based on this target process flow ultimately includes: a mandrel etching model 210 (MDL Etching Model), a self-aligned reverse patterning etching model 220 (SARP Etching Model), a first cutting process etching model 230 (CUT1 Etching Model), a second cutting process etching model 240 (CUT2 Etching Model), and a final etching model 250 (Final Etching Model). The SARP Etching Model 220 is a dependent stage etching model; the mandrel etching model 210 is a preceding stage etching model of the SARP Etching Model 220; and the first cutting process etching model 230 and the second cutting process etching model 240 are independent stage etching models.

[0081] The processing process of the composite etching model is as follows: first, the mandrel etching model 210 simulates the initial layout pattern to obtain the mandrel etching contour 211 (MDL Etch Contour). Since there are other process operations (deposition of spacer layers and filling of gaps) between the mandrel etching model 210 and the self-aligned reverse patterning etching model 220, a process logic operation is performed on the simulation result of the mandrel etching model 210 to obtain a non-mandrel virtual contour 212 (NMDLfake Contour). Considering that the size of the MDL here is different from the original MDL due to the subsequent etching process, and the size of the NDML is also affected by the existing MDL during etching, the mutual coupling effect of the MDL and NMDL must be considered here, so a process logic operation is performed on them to obtain the mandrel and non-mandrel combined contour 213 (NDML+MDLcontour). Subsequently, the mandrel etching profile 211, the non-mandrel virtual profile 212, and the mandrel and non-mandrel merged profile 213 are input together into the self-aligned reverse patterning etching model 220 for simulation processing. Since the model obtained by the general modeling method is usually required to read in the mask image, and the simulation results of each etching model in the present invention are generally etching profiles, the present invention chooses to convert them into mask images. The specific operation can be to regard the etching profile to be input as a curve mask, and then convert the curve mask into a mask image through the curve mask sampling method. This etching profile to mask image conversion process can be called a CMI process (Contour to Mask Image).

[0082] Finally, the mandrel etch profile 211, the non-mandrel virtual profile 212, and the mandrel and non-mandrel combined profile 213 are converted into a mask image and input into the self-aligned reverse patterning etching model 220 for simulation processing to obtain the self-aligned reverse patterning etching profile 221. In this way, all the results of the previous operations are input into the self-aligned reverse patterning etching model 220 for simulation processing, which can more comprehensively fit the coupling effect between the various results, thereby improving the accuracy of the etching model simulation.

[0083] Subsequently, the first cutting process etching model 230 and the second cutting process etching model 240 respectively obtain initial layout patterns for simulation processing to obtain a first cutting process etching contour 231 (CUT1 Etch Contour) and a second cutting process etching contour 241 (CUT2 Etch Contour).

[0084] To further ensure the accuracy of the final simulation results, the present invention performs process logic operations on the self-aligned reverse patterned etch profile 221, the first cutting process etch profile 231, and the second cutting process etch profile 241 according to specific process conditions, thereby merging them to obtain a preprocessed final profile 251 (preprocessed FinalContour). Furthermore, the simulation results of the patterned etch profile 221, the first cutting process etch profile 231, and the second cutting process etch profile 241, along with the preprocessed final profile 251 obtained through the process logic operations, are input into a final etch model 250. The final etch model 250 is fitted with the silicon wafer data after the final etching step. Because the model uses AI-based flexible terms, it can utilize the artificial intelligence embedded within it to fit coupling effects that cannot be captured using traditional modeling methods. Furthermore, the input of the final etch model 250 includes the other three etch profiles in addition to the preprocessed final profile 251, enabling the final etch model 250 to more accurately fit a large amount of data, thereby further improving the accuracy of the etch model simulation.

[0085] In addition, since the input of the final etching model 250 is generally also a mask pattern, it is also necessary to regard the etching profile to be input as a curve mask through the conversion operation of the present invention, and then convert the curve mask into a mask image through the curve mask sampling method.

[0086] Finally, after the entire modeling and fitting process is completed, the composite etching model composed of multi-level etching models can be used to simulate the final contour 252 after the final etching, and then simulated bad point detection can be carried out based on the final contour 252, making it possible to complete tasks that were previously impossible with ordinary etching models.

[0087] Figure 2 The example is described based on the specific process flow of the SARP process, but the method of the present invention can also be applied to other multiple patterning processes, such as the LELE process, the SADP process, the LELE+CUT process, the LELELE+CUT process, etc.

[0088] Taking the LELE process as an example, in some other optional embodiments, the composite etching model architecture constructed according to the LELE process is shown in Figure 3. Figure 3 2 is a schematic diagram of a composite etching model architecture established by an etching simulation method for a layout pattern according to another embodiment of the present invention.

[0089] The LELE process is also known as photolithography-etching-photolithography-etching, which is a double photolithography technology. First, the first photolithography is performed. After the first photolithography, the morphology of the photoresist is obtained. Then, through the first etching, the morphology of the photoresist is transferred to the hard mask. Then, the glue is applied, and the second photolithography and the second etching are performed. Finally, the left and right patterns will be transferred to the hard mask. During the first etching, there is no existing pattern on the hard mask, so the etching result is purely based on the result of the first photolithography. If modeling is to be done, it is a pure single-etching model. However, during the second etching, because the pattern of the first etching already exists on the hard mask, it will inevitably affect the second etching. The final result is not only related to the second photolithography result, but also to the result after the first etching. The effect of the final pattern transfer is actually the result of transferring all the patterns to the hard mask after the second etching. Therefore, if simulation bad pixel prediction is to be performed, the single-etching model cannot be used, and a composite etching model needs to be established using the method of the present invention.

[0090] First, the types of the two etching operations in the LELE process are determined. Since the two etching operations in the LELE process can be performed independently and then integrated, the two etching operations are determined to be independent etching operations, namely LE1 and LE2. The composite etching model established based on this target process flow ultimately includes: a first etching model 310 (LE1 Etching Model), a second etching model 320 (LE2 Etching Model), and a final etching model 330 (Final Etching Model).

[0091] The processing process of the composite etching model is as follows: the first etching model 310 and the second etching model 320 are each simulated according to the initial layout graphics to obtain corresponding simulation results, namely the first etching contour 311 (LE1 Etch Contour) and the second etching contour 321 (LE2 Etch Contour), and then the two simulation results are subjected to process logic operations according to the specific process conditions to obtain the preprocessed final contour 331 (preprocessed Final Contour). The preprocessed final contour 331 is then converted into a mask image together with the first etching contour 311 and the second etching contour 321 and input into the final etching model 330 for fitting. The target of the final etching model 330 fitting is the silicon wafer data after the final etching step is completed. The mutual coupling effect of LE1 and LE2 will be captured by artificial intelligence during the fitting process. Finally, the composite etching model is used to simulate the final etched Contour, and then the simulated bad point detection is carried out based on the Contour.

[0092] In summary, the present invention proposes the concept of a composite etching model (Comb Etching Modeling) and provides a composite etching modeling framework based on a multi-pattern process architecture, which makes it possible to directly simulate the final graphical effect of the multi-pattern process, so that simulated bad pixel detection can be carried out based on the model results. In addition, in order to better solve the problem of splicing the various etching sub-models into a composite model, the present invention also proposes a method of using existing curve mask sampling to convert the contour after the process logic operation into a "mask image", so that the contour after the process logic operation can be conveniently used as the input of the next model, thereby organically combining the models of each layer in the multi-pattern process architecture.

[0093] It should be noted that the composite etching model concept and modeling process proposed in the present invention are applicable to various multiple patterning processes. In addition to the SARP and LELE processes explicitly mentioned in the present invention, they can also be applied to SADP, LELE+CUT, LELELE+CUT and other processes. Those skilled in the art can determine the corresponding composite etching model architecture according to the actual process flow, thereby completing the simulation of the corresponding process.

[0094] The flowchart provided in this embodiment is not intended to indicate that the operations of the method will be performed in any particular order, or that all operations of the method are included in all every case. In addition, the method may include additional operations. Within the scope of the technical ideas provided by the method of this embodiment, additional changes can be made to the above method.

[0095] It should be understood that in some embodiments, each part can be implemented by hardware, software, firmware or a combination thereof. In the above embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system.

[0096] This embodiment also provides a computer program product 10 , a computer-readable storage medium 20 , and a computer device 30 . Figure 4 is a schematic diagram of a computer program product 10 according to one embodiment of the present invention, Figure 5 is a schematic diagram of a computer-readable storage medium 20 according to one embodiment of the present invention, Figure 6is a schematic diagram of a computer device 30 according to one embodiment of the present invention. A computer program product 10 includes a computer program 11. When executed by a processor 32, this computer program 11 implements the steps of any of the aforementioned methods for simulating etching of layout patterns. A computer-readable storage medium 20 stores the computer program 11. When executed by the processor 32, this computer program 11 implements the steps of any of the aforementioned methods for simulating etching of layout patterns. The computer device 30 may include a memory 31, a processor 32, and the computer program 11 stored in the memory 31 and executed by the processor 32.

[0097] The computer program 11 for performing the operations of the present invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, configuration data for an integrated circuit, or source code or object code written in any combination of one or more programming languages ​​and procedural programming languages. The computer program 11 may be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network (including a local area network (LAN) or a wide area network (WAN)), or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, to perform various aspects of the present invention, an electronic circuit including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA) may execute computer-readable program instructions by utilizing state information of the computer-readable program instructions to personalize the electronic circuit.

[0098] For the purposes of the present description, computer program product 10 is a product containing computer program 11. For the purposes of the present description, computer-readable storage medium 20 is a tangible device capable of retaining and storing computer program 11, and may be any device that can contain, store, communicate, propagate, or transmit program 11 for use by or in conjunction with an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable storage medium 20 include the following: a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, and any suitable combination of the foregoing.

[0099] The computer device 30 can be, for example, a server, a desktop computer, a laptop computer, a tablet computer, or a smartphone. In some examples, the computer device 30 can be a cloud computing node. The computer device 30 can be described in the general context of computer system executable instructions (such as program modules) executed by a computer system. Generally, program modules can include routines, programs, object programs, components, logic, data structures, etc. that perform specific tasks or implement specific abstract data types. The computer device 30 can be implemented in a distributed cloud computing environment where remote processing devices linked via a communication network perform tasks. In a distributed cloud computing environment, program modules can be located on local or remote computing system storage media, including storage devices.

[0100] The computer device 30 may include a processor 32 adapted to execute stored instructions, and a memory 31 that provides temporary storage for the instructions during operation. The processor 32 may be a single-core processor, a multi-core processor, a computing cluster, or any number of other configurations. The memory 31 may include random access memory (RAM), read-only memory, flash memory, or any other suitable storage system.

[0101] The computer device 30 may also include a network adapter / interface and an input / output (I / O) interface. The I / O interface allows data to be input and output with external devices that can be connected to the computer device. The network adapter / interface can provide communication between the computer device and a network, which is generally shown as a communication network.

[0102] At this point, those skilled in the art will recognize that, although a number of exemplary embodiments of the present invention have been shown and described in detail herein, many other variations or modifications consistent with the principles of the present invention may be directly determined or derived from the disclosure of the present invention without departing from the spirit and scope of the present invention. Therefore, the scope of the present invention should be understood and deemed to cover all such other variations or modifications.

Claims

1. A method for simulating etching of a layout pattern, comprising: Obtaining a target process flow and an initial layout graphic of the target process flow operation; Determine multiple etching operations in the target process flow, and obtain a stage etching model corresponding to each etching operation; simulating the etching operation using the stage etching model; The simulation results of the stage etching model simulation processing are input into the final etching model, and the simulation results are fitted using the final etching model to obtain the final simulation results corresponding to the target process flow.

2. The etching simulation method of the layout pattern according to claim 1, wherein: The etching operation includes a dependent etching operation, the dependent etching operation corresponds to a dependent stage etching model, and the dependent stage etching model is used to perform simulation processing based on the simulation results of the preceding operation on which the dependent etching operation depends; The step of simulating the etching operation by using the stage etching model includes: In a case where the etching operation is the dependent etching operation, determining a target preceding operation on which the dependent etching operation depends; Acquiring a preamble stage etching model corresponding to the target preamble operation, and performing simulation processing on the target preamble operation using the preamble stage etching model to obtain a preamble simulation result; The dependent stage etching model corresponding to the dependent etching operation is obtained, and the preceding simulation result is input into the dependent stage etching model for simulation processing.

3. The etching simulation method of the layout pattern according to claim 2, wherein: The target preceding operation includes a preceding etching operation and preceding process operations between the preceding etching operation and the dependent etching operation; The step of simulating the target pre-sequence operation by using the pre-sequence stage etching model to obtain a pre-sequence simulation result includes: Using the preceding stage etching model to simulate the preceding etching operation to obtain a preceding etching result; Performing a process logic operation on the preceding etching result according to the preceding process operation to obtain a preceding logic operation result; The preceding etching result and the preceding logic operation result are combined as the preceding simulation result.

4. The etching simulation method of the layout pattern according to claim 2, wherein: The step of inputting the previous simulation result into the dependent stage etching model for simulation processing includes: Obtaining a pre-sequence etching profile corresponding to the pre-sequence simulation result; Converting the preceding etching profile by a preset curve mask sampling method to obtain a preceding mask image; The preceding mask image is input into the dependent stage etching model for simulation processing.

5. The etching simulation method of the layout pattern according to claim 2, wherein: The etching operation also includes an independent etching operation, the independent etching operation corresponds to an independent stage etching model, and the independent stage etching model is used to perform simulation processing based on the initial layout pattern; The step of simulating the etching operation by using the stage etching model includes: In the case where the etching operation is the independent etching operation, an independent stage etching model corresponding to the independent etching operation is obtained, and the initial layout pattern is input into the independent stage etching model for simulation processing.

6. The etching simulation method of the layout pattern according to claim 5, wherein: The step of fitting the simulation results using the final etching model to obtain the final simulation results corresponding to the target process flow includes: Obtaining a dependent simulation result corresponding to the dependent stage etching model and an independent simulation result corresponding to the independent stage etching model; Performing process logic operations on the dependent simulation results and the independent simulation results according to the target process flow to obtain preprocessing results; The pre-processing result, the dependent simulation result and the independent simulation result are input into the final etching model for simulation processing to obtain the final simulation result.

7. The etching simulation method of a layout pattern according to claim 6, wherein: The step of inputting the preprocessing result, the dependent simulation result, and the independent simulation result into the final etching model for simulation processing to obtain the final simulation result includes: Respectively obtaining etching profiles corresponding to the preprocessing result, the dependent simulation result, and the independent simulation result; Converting the etching profile to obtain a mask image using a preset curve mask sampling method; The mask image is input into the final etching model for simulation processing to obtain the final simulation result.

8. The etching simulation method of a layout pattern according to claim 1, wherein: After the step of fitting the simulation results using the final etching model to obtain the final simulation results corresponding to the target process flow, the following step further includes: Perform simulation bad point detection on the final simulation result and determine whether the initial layout pattern meets the preset requirements based on the detection result.

9. A computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the computer program implements the steps of the etching simulation method of a layout pattern according to any one of claims 1 to 8.

10. A computer device comprising a memory, a processor, and a machine executable program stored in the memory and running on the processor, wherein the processor implements the steps of the etching simulation method of layout graphics according to any one of claims 1 to 8 when executing the machine executable program.

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