Chip design method and apparatus, chip, controller and vehicle

Abstract

The application is suitable for the chip design technical field, and provides a chip design method, device, chip, controller and vehicle. The chip design method provided by the application obtains a plurality of basic function blocks in a logic circuit diagram and fractal code information corresponding to each of the plurality of basic function blocks. The basic function block is a basic unit of a circuit of the chip. The fractal code information is used for indicating the position and connection mode of the basic function block in the chip. According to the fractal code information corresponding to each of the plurality of basic function blocks, a plurality of calculation intervals are determined. According to a self-defined integer corresponding to each of the plurality of basic function blocks in each calculation interval, a plurality of basic function blocks to be executed and an execution order in each calculation interval are determined. According to the plurality of basic function blocks to be executed and the execution order in each of the plurality of calculation intervals, a circuit wiring structure of the chip is reconstructed.

Description

Chip design methods, devices, chips, controllers, and vehicles Technical Field

[0001] This application belongs to the field of chip technology, and more specifically, relates to a chip design method, apparatus, chip, controller and carrier. Background Technology

[0002] EDA compilers play a crucial role in the design flow of Programmable Array Logic (FPGA) and Reconfigurable Computing Array (CGRA), serving as a bridge between the top-level logic design and the specific hardware implementation. In the process of generating logic circuit diagrams using EDA tools, both FPGA and CGRA require the EDA compiler to solve the solution space represented by the entire logic design to obtain a feasible logic circuit diagram.

[0003] Generally, modular design and standardized simulation models can reduce the time and complexity of this solution process, but they cannot adequately address the increasingly complex and ever-changing demands. For example, EDA tools often require the deployment of significant hardware resources to complete the actual circuit routing when generating logic circuit diagrams, resulting in low hardware resource utilization. Summary of the Invention

[0004] The purpose of this application is to provide a chip design method, apparatus, chip, controller, and carrier, which aims to solve the technical problem that existing EDA tools require a large amount of hardware resources to complete specific circuit routing when generating logic circuit diagrams, resulting in low hardware resource utilization.

[0005] To achieve the above objectives, according to the first aspect of this application, a chip design method is provided, the method comprising:

[0006] Obtain multiple basic functional blocks in the logic circuit diagram, as well as the fractal code information corresponding to each of the multiple basic functional blocks. The basic functional blocks are the basic units of the circuit that builds the chip. The fractal code information is used to indicate the position and connection method of the basic functional blocks in the chip.

[0007] Based on the fractal code information corresponding to each of the multiple basic functional blocks, multiple calculation intervals are determined, and each calculation interval includes at least: multiple basic functional blocks and the connection between the multiple basic functional blocks;

[0008] Based on the custom integers corresponding to the various basic functional blocks in each calculation interval, the various basic functional blocks to be executed in each calculation interval and their execution order are determined. The custom integers are used to define each basic functional block as an integer in the calculation interval.

[0009] The circuit wiring structure of the chip is reconstructed based on the multiple basic functional blocks to be executed in each of the multiple computation intervals and their execution order.

[0010] The beneficial effects of this application embodiment compared with the prior art are as follows: It obtains multiple basic functional blocks in a logic circuit diagram, and the fractal code information corresponding to each of the multiple basic functional blocks. The basic functional blocks are the basic units for constructing the chip's circuit, and the fractal code information is used to indicate the position and connection method of the basic functional blocks in the chip. Based on the fractal code information corresponding to each of the multiple basic functional blocks, it determines multiple computation intervals, each computation interval including at least: multiple basic functional blocks and the connections between them. Based on the custom integers corresponding to each of the multiple basic functional blocks in each computation interval, it determines the multiple basic functional blocks to be executed in each computation interval and their execution order. Based on the multiple basic functional blocks to be executed in each of the multiple computation intervals and their execution order, it reconstructs the circuit wiring structure of the chip.

[0011] This application demonstrates a method for reconfiguring the internal circuitry of a chip. Specifically, it dynamically reconfigures suitable hardware structures and routing paths based on different functional requirements, reducing the complexity of reconfigurable functional compilation routing. This enables the realization of reconfigurable circuit hardware or reconfigurable chips, thereby improving chip hardware performance and efficiency. Specifically, it eliminates the need for complex solution spaces and graph theory methods; simple constraints on the spatial range allow the chip to achieve self-reconfiguration without compilation, thus reducing the difficulty and cost of chip design.

[0012] Optionally, in one possible implementation of the first aspect, the fractal code information includes: a first similarity parameter; obtaining fractal code information corresponding to each of the plurality of basic functional blocks, including:

[0013] Determine the most similar functional block corresponding to each of the multiple basic functional blocks;

[0014] Based on the similarity relationship between the most similar functional blocks corresponding to each of the multiple basic functional blocks, a first similarity parameter corresponding to each of the multiple basic functional blocks is determined.

[0015] Optionally, in one possible implementation of the first aspect, determining multiple computation intervals based on the fractal code information corresponding to each of the multiple basic functional blocks includes:

[0016] The calculation interval to which each of the multiple basic functional blocks belongs is determined based on the first similarity parameter corresponding to each of the multiple basic functional blocks.

[0017] Optionally, in one possible implementation of the first aspect, determining the computation interval to which each of the plurality of basic functional blocks belongs based on a first similarity parameter corresponding to each of the plurality of basic functional blocks includes:

[0018] Based on the logic circuit diagram of the chip, multiple range blocks and multiple domain blocks are obtained, wherein the range blocks and the domain blocks are divided in different ways;

[0019] Based on multiple range blocks and multiple domain blocks, determine the second similarity parameter corresponding to each of the multiple range blocks;

[0020] The comparison results are obtained by comparing the first similarity parameters corresponding to each of the multiple basic functional blocks and the second similarity parameters corresponding to each of the multiple range blocks;

[0021] Based on the comparison results, the calculation interval to which each of the multiple basic functional blocks belongs is determined.

[0022] Optionally, in one possible implementation of the first aspect, determining the second similarity parameter corresponding to each of the plurality of range blocks based on the plurality of range blocks and the plurality of domain blocks includes:

[0023] Determine the most similar domain block corresponding to each of the multiple range blocks;

[0024] Based on the similarity relationship between the multiple range blocks and their respective most similar domain blocks, a second similarity parameter is determined for each of the multiple range blocks.

[0025] Optionally, in one possible implementation of the first aspect, determining the computation interval to which each of the plurality of basic functional blocks belongs based on a first similarity parameter corresponding to each of the plurality of basic functional blocks includes:

[0026] Obtain a pre-determined custom range number, wherein the custom range number is used to constrain the range of the calculation interval;

[0027] Based on the custom range number and the first similarity parameter corresponding to each of the multiple basic functional blocks, the calculation interval to which each of the multiple basic functional blocks belongs is calculated.

[0028] Optionally, in one possible implementation of the first aspect, determining the plurality of basic functional blocks to be executed and their execution order in each calculation interval based on the custom integers corresponding to the plurality of basic functional blocks in each calculation interval includes:

[0029] Based on the first similarity parameter corresponding to each of the multiple basic functional blocks in each calculation interval, and the custom integer corresponding to each of the multiple basic functional blocks in each calculation interval, the position of each of the multiple basic functional blocks in the calculation interval is calculated.

[0030] Based on the respective positions of the multiple basic functional blocks within the calculation interval, the multiple basic functional blocks to be executed within the calculation interval and their execution order are determined.

[0031] Optionally, in one possible implementation of the first aspect, reconstructing the circuit wiring structure of the chip based on the plurality of basic functional blocks to be executed in each of the plurality of computation intervals and their execution order includes:

[0032] The multiple basic functional blocks to be executed in a calculation interval and their execution order are placed into a first-in-first-out queue as the calculation result of the calculation interval.

[0033] When the next calculation interval begins, the calculation result of the calculation interval is retrieved from the first-in-first-out queue;

[0034] In the next calculation interval, the circuit wiring structure of the chip is reconstructed based on the calculation results of the calculation interval.

[0035] According to a second aspect of this application, a chip design apparatus is provided, the apparatus comprising:

[0036] The acquisition unit is used to acquire multiple basic functional blocks in the logic circuit diagram, as well as the fractal code information corresponding to each of the multiple basic functional blocks. The basic functional blocks are the basic units of the circuit that builds the chip, and the fractal code information is used to indicate the position and connection method of the basic functional blocks in the chip.

[0037] The first determining unit is configured to determine multiple calculation intervals based on the fractal code information corresponding to each of the multiple basic functional blocks, wherein each calculation interval includes at least: the multiple basic functional blocks and the connections between the multiple basic functional blocks;

[0038] The second determining unit is used to determine the multiple basic functional blocks to be executed in each calculation interval and their execution order based on the custom integers corresponding to the multiple basic functional blocks in each calculation interval. The custom integers are used to define each basic functional block as an integer in the calculation interval.

[0039] The reconfiguration unit is used to reconfigure the circuit wiring structure of the chip according to the multiple basic functional blocks to be executed in each of the multiple calculation intervals and their execution order.

[0040] Optionally, in one possible implementation of the first aspect, the fractal code information includes: a first similarity parameter, and the acquisition unit includes:

[0041] The first determining subunit is used to determine the most similar functional block corresponding to each of the plurality of basic functional blocks; and to determine the first similarity parameter corresponding to each of the plurality of basic functional blocks based on the similarity relationship between the most similar functional blocks corresponding to each of the plurality of basic functional blocks.

[0042] Optionally, in one possible implementation of the first aspect, the first determining unit includes:

[0043] The second determining subunit is used to determine the calculation interval to which each of the above-mentioned basic functional blocks belongs based on the first similarity parameter corresponding to each of the above-mentioned basic functional blocks, wherein the multiple basic functional modules in each of the above-mentioned calculation intervals are sequentially expanded in ascending order.

[0044] Optionally, in one possible implementation of the first aspect, the second determining subunit is specifically used for:

[0045] Based on the logic circuit diagram of the chip, multiple range blocks and multiple domain blocks are obtained, wherein the segmentation methods corresponding to the range blocks and the domain blocks are different;

[0046] Based on multiple range blocks and multiple domain blocks, determine the second similarity parameter corresponding to each of the aforementioned range blocks;

[0047] By comparing the first similarity parameters corresponding to each of the above basic functional blocks and the second similarity parameters corresponding to each of the above range blocks, the comparison results are obtained.

[0048] Based on the comparison results above, the calculation intervals to which each of the above basic functional blocks belongs are determined.

[0049] Optionally, in one possible implementation of the first aspect, the second determining subunit is further used for:

[0050] Determine the most similar domain block corresponding to each of the above range blocks;

[0051] Based on the similarity relationship between the aforementioned range blocks and their respective most similar domain blocks, the second similarity parameter corresponding to each of the aforementioned range blocks is determined.

[0052] Optionally, in one possible implementation of the first aspect, the second determining subunit is specifically used for:

[0053] Obtain a pre-determined custom range number, wherein the custom range number is used to constrain the range of the above calculation interval;

[0054] Based on the aforementioned custom range number and the first similarity parameter corresponding to each of the aforementioned basic functional blocks, the aforementioned calculation intervals to which each of the aforementioned basic functional blocks belongs are calculated.

[0055] Optionally, in one possible implementation of the first aspect, the second determining unit includes:

[0056] The first calculation subunit is used to calculate the position of each of the multiple basic functional blocks in the calculation interval based on the first similarity parameter corresponding to each of the multiple basic functional blocks in each of the above calculation intervals, and the custom integer corresponding to each of the multiple basic functional blocks in each of the above calculation intervals.

[0057] The third determining subunit is used to determine the multiple basic functional blocks to be executed in the calculation interval and their execution order based on the respective positions of the multiple basic functional blocks in the calculation interval.

[0058] Optionally, in one possible implementation of the first aspect, the aforementioned reconfiguration unit includes:

[0059] The second calculation subunit is used to put the multiple basic functional blocks to be executed in a calculation interval and their execution order into a first-in-first-out queue as the calculation result of the calculation interval; when the next calculation interval of the calculation interval begins to be calculated, the calculation result of the calculation interval is taken out from the first-in-first-out queue.

[0060] The reconstruction sub-unit is used to reconstruct the circuit wiring structure of the chip in the next calculation interval based on the calculation results of the calculation interval.

[0061] The second aspect and any implementation thereof correspond to the first aspect and any implementation thereof, respectively. The technical effects of the second aspect and any implementation thereof can be found in the technical effects of the first aspect and any implementation thereof, as described above, and will not be repeated here.

[0062] Thirdly, embodiments of this application provide a chip applied to an electronic device, the chip including one or more processors, the processors being configured to invoke computer instructions to cause the electronic device to perform any of the methods described herein.

[0063] Thirdly, embodiments of this application provide a controller, characterized in that it includes the aforementioned chip.

[0064] Fourthly, embodiments of this application provide a vehicle, characterized in that it includes the aforementioned controller.

[0065] Fifthly, embodiments of this application provide a terminal device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that the processor executes the computer program to implement any of the methods described above.

[0066] Sixthly, embodiments of this application provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements any of the methods described above.

[0067] In a seventh aspect, embodiments of this application provide a computer program product that, when run on a terminal device, causes the terminal device to execute the method described in any one of the first aspects.

[0068] It is understood that the beneficial effects of the second to seventh aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0069] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0070] Figure 1 shows a schematic flowchart of a chip design method provided in this application;

[0071] Figure 2 is a schematic diagram of an optional basic functional block provided in an embodiment of this application;

[0072] Figure 3 shows a schematic flowchart of an optional chip design method provided in this application;

[0073] Figure 4 shows a schematic flowchart of an optional chip design method provided in this application;

[0074] Figure 5 shows a schematic diagram of an optional chip design provided in this application;

[0075] Figure 6 is a schematic diagram of a chip design device provided in an embodiment of this application. Detailed Implementation

[0076] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0077] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0078] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0079] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0080] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0081] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0082] First, some terms used in the embodiments of this application will be explained to facilitate understanding by those skilled in the art.

[0083] Coarse-grained Reconfigurable Architecture (CGRA) is a spatial parallel computing paradigm that organizes computing resources of different granularities and functions using spatial hardware architecture. During runtime, based on the characteristics of the data flow, the configured hardware resources are interconnected to form relatively fixed computing paths, performing computations in a manner close to "dedicated circuits." When algorithms and applications change, they are reconfigured again to reconstruct different computing paths to execute different tasks.

[0084] Field Programmable Gate Array (FPGA) is a further development based on programmable devices such as PAL (Programmable Array Logic) and GAL (General Purpose Array Logic). It emerged as a semi-custom circuit in the field of Application-Specific Integrated Circuits (ASICs), solving the shortcomings of custom circuits and overcoming the limitation of the limited gate count of original programmable devices.

[0085] Electronic Design Automation (EDA) is a type of automation that evolved from the concepts of Computer-Aided Design (CAD), Computer-Aided Manufacturing (CAM), Computer-Aided Testing (CAT), and Computer-Aided Engineering (CAE) in the mid-1960s.

[0086] The above is a brief introduction to the terms used in the embodiments of this application, and will not be repeated below.

[0087] During the reconstruction process, the routing and functional blocks required for each function are regarded as a series of path combinations. Here we regard it as an evolutionary process. If these path combinations are broken down individually, they will have considerable similarity. Thus, we can classify them as isomorphic similarity. The isomorphic similarity constraints include: (1) acyclicity, which means that in the evolution of a multi-path system generated in a series of path combinations, no part of the path from any node to another node will be repeated. That is, the evolution order between nodes is non-repetitive; (2) non-confluence. (nt), which means that different branches in the evolution of a multi-path system will not lead to the same result. That is, each branch will inevitably lead to the generation of a new result node, or the subordinate nodes derived from the same branch will not be related to each other; (3) branchability, which means that a node can derive multiple subordinate nodes, that is, there can be multiple branch paths; and (4) non-feedback, which means that each node is derived from a node (superior node) and also derives one or more nodes (subordinate nodes) from itself, but the node will not derive superior nodes in the reverse direction, so the evolution process is unidirectional and will not reverse. Taking a tree structure diagram as an example, the initial node is located at the top, and from top to bottom to the multiple result nodes, there is a unique path from the initial node to any result node (guaranteed by the isomorphic similarity constraint).

[0088] The resulting evolution process of the multi-path system and its corresponding isomorphic basic unit can be viewed as an isomorphic extension based on this isomorphic basic unit. Furthermore, the isomorphic basic unit itself is also a state evolution process of reconstructing functional paths, and these multiple evolution processes also satisfy similarity constraints, namely: non-repetition, non-convergence, branching, and non-feedback.

[0089] This application provides a chip design method. Figure 1 shows a schematic flowchart of a chip design method provided in this application, which is illustrative and not limiting. Referring to Figure 1, the method includes:

[0090] S110: Obtain multiple basic functional blocks in the logic circuit diagram, as well as the fractal code information corresponding to each of the multiple basic functional blocks.

[0091] Specifically, the aforementioned basic functional blocks are the basic units of the circuitry that make up the chip, and the fractal code information is used to indicate the location and connection method of the basic functional blocks in the chip.

[0092] S112, Based on the fractal code information corresponding to each of the multiple basic functional blocks, determine multiple calculation intervals, and the calculation intervals include at least: multiple basic functional blocks and the connections between the multiple basic functional blocks.

[0093] S114. Based on the custom integers corresponding to the various basic functional blocks in each of the above calculation intervals, determine the various basic functional blocks to be executed in each of the above calculation intervals and their execution order. The custom integers are used to define each basic functional block as an integer in the calculation interval.

[0094] S116, reconstruct the circuit wiring structure of the chip according to the multiple basic function blocks to be executed in each of the multiple calculation intervals and their execution order.

[0095] Optionally, the aforementioned basic functional blocks, also known as basic unit blocks, are the most basic components that make up the circuits in a chip, such as logic gates and flip-flops.

[0096] Optionally, the chip in this application example is an integrated circuit (IC) chip, and the above logic circuit diagram is the IC logic circuit diagram, which can also be understood as the chip's circuit schematic. The solution provided in this application example can be applied to chips of the Field Programmable Gate Array (FPGA) or Coarse-grained Reconfigurable Architecture (CGRA) type, reconfiguring the chip's circuit routing structure to obtain the functions required by the designer.

[0097] Understandably, if the circuit routing structure on the IC logic circuit diagram (hereinafter referred to as the circuit) of a chip is considered as a routing path, then basic functional blocks can be considered as nodes on the circuit, and the connections between basic functional blocks can be considered as connections between nodes. Multiple basic functional blocks and the connections between multiple basic functional blocks can be considered as combinations of routing paths. Each basic functional block on the chip's circuit represents a specific function or operation, while the connections between multiple basic functional blocks represent the relationships between these functions or operations.

[0098] As shown in Figure 2, each basic functional block includes a brancher and multiple sub-functional blocks FU. The multiple sub-functional blocks FU are connected through the brancher, and the multiple basic functional blocks are also connected through the brancher.

[0099] In this application example, fractal theory can be used to determine the most similar basic functional block for each basic functional block. Specifically, the similarity parameters between the most similar basic functional blocks corresponding to multiple basic functional blocks are calculated by the similarity mapping method in fractal coding theory, thereby obtaining the fractal code information corresponding to each of the multiple basic functional blocks: s value and o value.

[0100] For example, suppose that the s value of each basic function block is equal to 1, and the o value is equal to the custom integer corresponding to each basic function block.

[0101] For example, each basic functional block can be assigned a custom integer according to its arrangement. This custom integer defines each basic functional block as an integer within the calculation range. For instance, it can be defined based on the function of the basic functional block, where the custom integer corresponding to the first type of basic functional block is 0, the custom integer corresponding to the second type of basic functional block is 1, the custom integer corresponding to the third type of basic functional block is 2, and so on. Furthermore, each basic functional block itself also has a basic number; for example, the first basic functional block is 1, the second basic functional block is 2, the third basic functional block is 3, and so on.

[0102] Next, the base number of each basic functional block and the custom integer of that basic functional block are added together. After the summation, a sequentially arranged computation interval (which can also be understood as a functional interval) is obtained. In the example of this application, each computation space can be arranged sequentially, and adjacent computation intervals can generally be regarded as an increasing expansion. The custom integer corresponding to each basic functional block must fall into a computation interval. Therefore, the multiple basic functional blocks to be executed in the computation interval and their execution order can be determined.

[0103] Furthermore, the circuit wiring structure of the chip can be reconstructed based on the multiple basic functional blocks to be executed in each of the multiple computation intervals and their execution order, that is, the winding path of the internal circuit of the chip can be reconstructed.

[0104] This application provides a compiler-free reconfigurable architecture that reconfigures the routing paths of internal circuits within a chip. Specifically, it dynamically reconfigures suitable hardware structures and routing paths based on different functional requirements, reducing the complexity of compiler-based routing for reconfigurable functions. This enables the realization of reconfigurable circuit hardware or reconfigurable chips, thereby improving chip hardware performance and efficiency. Specifically, it eliminates the need for complex solution spaces and graph theory methods; simple constraints on the spatial range are sufficient to allow the chip to achieve self-reconfiguration without compilation, thus reducing design difficulty and cost.

[0105] This application example can adapt to complex and ever-changing needs and the development trend of edge applications. It can flexibly adjust and optimize the functions and structure of hardware according to different scenarios and applications, thereby improving the adaptability and scalability of hardware.

[0106] As is understandable, fractal coding is an image compression technique that utilizes the self-similarity in images to reduce the amount of data required for storage or transmission. Simply put, it finds repeating parts in an image and replaces the corresponding parts in the original image with smaller versions of these parts. This application's example leverages this characteristic, employing similarity mapping techniques from fractal theory. Without complex solution spaces and graph theory methods, and only requiring simple spatial constraints, it can achieve code-free self-reconfiguration of the chip.

[0107] The following examples illustrate the detailed process of using fractal coding methods to optimize reconfigurable hardware designs. The core of this process lies in reducing the computational resources and memory required by traditional EDA tools when solving hardware design paths. This is analyzed in detail in the following method examples:

[0108] In one possible implementation, the fractal code information includes: a first similarity parameter. Figure 3 shows a schematic flowchart of an optional chip design method provided in this application. As shown in Figure 3, the fractal code information corresponding to each of the multiple basic functional blocks in the logic circuit diagram is obtained, including:

[0109] S301, determine the most similar functional block corresponding to each of the multiple basic functional blocks.

[0110] S302, determine the first similarity parameter corresponding to each of the multiple basic functional blocks based on the similarity relationship between the most similar functional blocks corresponding to each of the multiple basic functional blocks.

[0111] In this application example, the most similar functional block corresponding to each of the multiple basic functional blocks can be determined using the similarity mapping method in fractal coding theory. This is easily understood as mapping the similarity of each basic functional block to other basic functional blocks to obtain the most similar functional block corresponding to each of the multiple basic functional blocks. Then, based on the similarity relationship between the most similar functional blocks corresponding to each of the multiple basic functional blocks, the first similarity parameter corresponding to each of the multiple basic functional blocks is determined.

[0112] Specifically, using fractal coding / fractal compression formulas, the first similarity parameter between the most similar basic functional blocks corresponding to multiple basic functional blocks is calculated, thus obtaining the fractal code information corresponding to each basic functional block: s-value and o-value. For example, assume that the s-value of each basic functional block is equal to 1, and the o-value is equal to a custom integer corresponding to each basic functional block.

[0113] In this way, by utilizing the similarity mapping method in fractal theory, these basic functional blocks can be repeated and combined according to the rules of corresponding required functions to form a larger functional structure. This can reduce redundancy in the design, optimize the interconnection structure, and reduce the complexity and memory cost of the design.

[0114] In one possible implementation, multiple computation intervals are determined based on the fractal code information corresponding to each of the multiple basic functional blocks, including:

[0115] Based on the first similarity parameter corresponding to each of the multiple basic functional blocks, the calculation interval to which each of the multiple basic functional blocks belongs is determined.

[0116] Optionally, each basic functional block on the routing path can be defined as an arbitrary integer, i.e., a custom integer. For example, each basic functional block can be assigned a custom integer according to its arrangement order. This custom integer is used to define each basic functional block as an integer in the calculation interval. For example, it can be defined according to the function of the basic functional block. Then, the custom integer corresponding to the first type of basic functional block is 0, the custom integer corresponding to the second type of basic functional block is 1, the custom integer corresponding to the third type of basic functional block is 2, and so on.

[0117] In one possible implementation, the calculation interval to which each of the aforementioned basic functional blocks belongs is determined based on a first similarity parameter corresponding to each of the aforementioned basic functional blocks, including:

[0118] Obtain a pre-determined custom range number, where the custom range number is used to constrain the range of the calculation interval;

[0119] Based on the aforementioned custom range number and the first similarity parameter corresponding to each of the aforementioned basic functional blocks, the aforementioned calculation intervals to which each of the aforementioned basic functional blocks belongs are calculated.

[0120] For example, by multiplying the custom integer corresponding to each basic functional block by the first similarity parameter corresponding to that basic functional block, namely the s value and the o value, calculated by the fractal theory formula, the calculation interval to which each basic functional block belongs can be determined.

[0121] After determining the computation interval to which each of the multiple basic functional blocks belongs, the multiple basic functional blocks to be executed and their execution order are determined based on the custom integers corresponding to the multiple basic functional blocks in each computation interval. Then, the circuit routing structure of the chip can be reconstructed based on the multiple basic functional blocks to be executed in each of the multiple computation intervals and their execution order.

[0122] In this application example, the traditional EDA tool does not require a solution space when solving architectural paths. It only requires computation and a small amount of memory to combine the routing path, thereby realizing the self-reconfiguration function on the chip. That is, at runtime, it uses pre-configured hardware resources to interconnect and form a relatively fixed computing path, performing calculations in a manner close to "dedicated circuits". When the algorithm and application change, it is reconfigured again to form different computing paths to execute different tasks.

[0123] In one possible implementation, Figure 4 shows a schematic flowchart of an optional chip design method provided in this application. As shown in Figure 4, based on the first similarity parameters corresponding to each of the multiple basic functional blocks, the computational interval to which each of the multiple basic functional blocks belongs is determined, including:

[0124] S401, based on the logic circuit diagram of the chip, obtains multiple range blocks and multiple domain blocks, wherein the segmentation methods corresponding to the range blocks and domain blocks are different.

[0125] S402, based on multiple range blocks and multiple domain blocks, determine the second similarity parameter corresponding to each of the multiple range blocks.

[0126] S403, compare the first similarity parameters corresponding to each of the multiple basic functional blocks and the second similarity parameters corresponding to each of the multiple range blocks to obtain the comparison results.

[0127] S404. Based on the comparison results, determine the calculation interval to which each of the multiple basic function blocks belongs.

[0128] In this application example, the logic circuit diagram of the chip is divided by using different segmentation methods to obtain multiple range blocks and multiple domain blocks. For example, the range blocks can be obtained by dividing the range of the logic circuit diagram, and the domain blocks can be obtained by dividing the domain values ​​of the logic circuit diagram.

[0129] In one possible implementation, based on multiple range blocks and multiple domain blocks, a second similarity parameter corresponding to each of the multiple range blocks is determined, including:

[0130] Determine the most similar domain block corresponding to each of the multiple range blocks; based on the similarity relationship between the multiple range blocks and their respective most similar domain blocks, determine the second similarity parameter corresponding to each of the multiple range blocks.

[0131] In one example, the visual representation of a chip's logic circuit diagram is segmented into domain blocks and range blocks. Specifically, each logic circuit image can be subdivided into n*m range blocks. Meanwhile, a domain block consists of non-overlapping portions of the image. The goal for each range block is to find the most suitable corresponding block within the domain blocks using a fractal compression algorithm. This process continues until all range blocks have identified their corresponding most similar domain blocks, generating a series of fractal codes that can then be used to reconstruct the original circuit configuration.

[0132] Furthermore, fractal encoding facilitates the generation of a large number of inequalities. These inequalities represent various functions and directional paths within the circuit. With these inequalities, certain function timelines and constraints can be applied to customize the operation of the circuit. This step aims to minimize the mean square error and determine which inequalities are most relevant to the selected basic functional blocks. Ultimately, each inequality is associated with a specific circuit function or path determined by the preceding fractal encoding process, indicating the expected behavior or characteristics of the circuit.

[0133] This approach reduces design complexity and improves resource utilization without sacrificing design flexibility. It is particularly suitable for reconfigurable hardware platforms such as FPGAs and CGRAs, allowing for dynamic reconfiguration of hardware resources as needed.

[0134] Then, by comparing the first similarity parameters corresponding to each of the multiple basic functional blocks and the second similarity parameters corresponding to each of the multiple range blocks, the comparison results are obtained; based on the size relationship of the similarity parameters obtained from the comparison results, the calculation interval to which each of the multiple basic functional blocks belongs is determined.

[0135] By using comparisons of greater than or equal to and less than, the first and second similarity parameters can be calculated to determine which calculation interval a given value belongs to, thus quickly identifying the range of a specific function or operation in the circuit. Once the intervals of multiple basic functional blocks are determined, the basic unit blocks used by the corresponding combination paths within that interval can be mapped.

[0136] By employing continuous computation intervals and comparison operations to map combinational paths and basic functional blocks, the resource consumption of reconfiguration is reduced and the flexibility of reconfiguration is improved. In short, this process decomposes the complex structure of a circuit into smaller parts, and then quickly identifies and maps these parts through comparison operations. This can optimize circuit design, making it more efficient and reconfigurable.

[0137] In one possible implementation, based on the custom integers corresponding to the various basic functional blocks in each of the aforementioned computation intervals, the various basic functional blocks to be executed and their execution order in each computation interval are determined, including:

[0138] Based on the first similarity parameter corresponding to each of the multiple basic functional blocks in at least one calculation interval, and the custom integer corresponding to each of the multiple basic functional blocks in each calculation interval, the position of each of the multiple basic functional blocks in the calculation interval is calculated; based on the position of each of the multiple basic functional blocks in the calculation interval, the multiple basic functional blocks to be executed in the calculation interval and the execution order are determined.

[0139] In one example, when determining the multiple basic functional blocks to be executed in the computation interval and their execution order, during the computation process, each basic functional block (i.e., node) on the path is defined as a custom integer. This custom integer is multiplied by the first similarity parameter corresponding to the basic functional block, namely the s value and the o value, to determine the position of the basic functional block in the computation interval.

[0140] Furthermore, based on the positions of each basic functional block within the computation interval, the execution order of the multiple basic functional blocks to be executed within the computation interval can be determined. Each basic functional block's position within the computation interval is determined by a custom integer, and the basic functional blocks within each computation interval are incrementally expanded. This forms a path-combination computation method that can dynamically reconstruct the internal wiring paths of the chip as needed.

[0141] In one possible implementation, the circuit wiring structure of the chip is reconstructed based on the multiple basic functional blocks to be executed in each of the multiple computation intervals and their execution order, including:

[0142] The multiple basic functional blocks to be executed in the calculation interval and their execution order are placed into a first-in-first-out queue as the calculation result of the calculation interval. When the next calculation interval begins, the calculation result of the calculation interval is retrieved from the first-in-first-out queue. In the next calculation interval, the circuit wiring structure of the chip is reconstructed based on the calculation result of the calculation interval.

[0143] As shown in Figure 5, the path generator is connected to each of the multiple basic functional blocks. Based on the fractal code information corresponding to each of the basic functional blocks, the path generator determines multiple computation intervals. Then, based on the custom integers corresponding to the basic functional blocks within each computation interval, it determines the multiple basic functional blocks to be executed within that interval and their execution order. The multiple basic functional blocks to be executed within each computation interval and their execution order are then placed into a FIFO queue as the computation result of that interval.

[0144] After the computation of each computation interval is completed, the results of that computation space are placed into a First-In-First-Out (FIFO) queue. When the computation of the next computation interval begins, the results of the previous computation interval can be retrieved from the FIFO queue for computation.

[0145] For example, an arbitrary constant can be added to the value obtained in each round of calculation intervals to serve as the initial value for the next calculation space, thereby increasing the variation in the next calculation interval and enhancing the randomness and diversity of the reconstruction.

[0146] Understandably, fractal compression formulas allow chip designers to break down a large design problem into smaller, more manageable parts. These smaller parts (basic functional blocks) can be designed and optimized independently, and then combined into a complete design using the self-similarity principle in fractal theory. This reduces design complexity and improves resource utilization without sacrificing design flexibility.

[0147] For example, if a circuit design contains multiple similar adder modules, fractal compression can be used to identify these adders and determine, through computation, how to combine them most effectively. This can reduce repetitive work, speed up the design process, and may lead to more efficient hardware implementation.

[0148] Fractal encoding simplifies the compilation and routing complexity of reconfigurable hardware by leveraging the self-similarity principle in fractal theory to optimize the design. Within this framework, each computational interval comprises multiple basic functional blocks, which can be efficiently combined using fractal compression formulas. This allows for the effective combination of these basic functional blocks within a limited solution space to create the desired circuit design, achieving on-chip self-reconfiguration.

[0149] By employing the fractal coding-based chip design method described above, the windings and functional blocks required for each function are treated as a series of path combinations. Nodes are split and transformed into a series of large and small intervals. Using simple comparison operations, it becomes clear which interval corresponds to which type of path combination's basic unit block, thereby reducing resource consumption during refactoring and increasing its flexibility. By adding an arbitrary constant to the value of each round of calculation intervals, the value of each interval is unique, increasing the randomness and diversity of refactoring. Furthermore, this reduces the computational resources required by traditional EDA tools when solving architectural paths, improving the efficiency and flexibility of hardware design.

[0150] Fractal encoding simplifies the compilation and routing complexity of reconfigurable hardware. Specifically, it utilizes fractal theory to identify basic functional blocks and optimizes connection paths through computation. This not only reduces memory costs but also accelerates reconfiguration, enabling the hardware to quickly adapt to new computational tasks as needed.

[0151] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0152] Corresponding to the chip design method in the above embodiments, Figure 6 is a schematic diagram of a chip design device provided in an embodiment of this application. The device can be implemented by software, hardware or a combination of both as part or all of a computer device, which can be any kind of electronic device.

[0153] Referring to Figure 6, the chip design apparatus includes:

[0154] The acquisition unit 60 is used to acquire multiple basic functional blocks in the logic circuit diagram, as well as the fractal code information corresponding to each of the multiple basic functional blocks. The basic functional blocks are the basic units of the circuit that builds the chip, and the fractal code information is used to indicate the position and connection method of the basic functional blocks in the chip.

[0155] The first determining unit 62 is used to determine multiple calculation intervals based on the fractal code information corresponding to each of the multiple basic functional blocks. Each calculation interval includes at least: multiple basic functional blocks and the connection between the multiple basic functional blocks.

[0156] The second determining unit 64 is used to determine the multiple basic functional blocks to be executed and their execution order in each of the above calculation intervals based on the custom integers corresponding to the multiple basic functional blocks in each of the above calculation intervals. The custom integers are used to define each basic functional block as an integer in the calculation interval.

[0157] The reconstruction unit 66 is used to reconstruct the circuit wiring structure of the chip according to the multiple basic functional blocks to be executed in each of the multiple calculation intervals and their execution order.

[0158] Optionally, in one possible implementation of the first aspect, the fractal code information includes: a first similarity parameter, and the acquisition unit includes:

[0159] The first determining subunit is used to determine the most similar functional block corresponding to each of the plurality of basic functional blocks; and to determine the first similarity parameter corresponding to each of the plurality of basic functional blocks based on the similarity relationship between the most similar functional blocks corresponding to each of the plurality of basic functional blocks.

[0160] Optionally, in one possible implementation of the first aspect, the first determining unit includes:

[0161] The second determining subunit is used to determine the calculation interval to which each of the above-mentioned basic functional blocks belongs based on the first similarity parameter corresponding to each of the above-mentioned basic functional blocks, wherein the multiple basic functional modules in each of the above-mentioned calculation intervals are sequentially expanded in ascending order.

[0162] Optionally, in one possible implementation of the first aspect, the second determining subunit is specifically used for:

[0163] Based on the logic circuit diagram of the chip, multiple range blocks and multiple domain blocks are obtained, wherein the segmentation methods corresponding to the range blocks and the domain blocks are different;

[0164] Based on multiple range blocks and multiple domain blocks, determine the second similarity parameter corresponding to each of the aforementioned range blocks;

[0165] By comparing the first similarity parameters corresponding to each of the above basic functional blocks and the second similarity parameters corresponding to each of the above range blocks, the comparison results are obtained.

[0166] Based on the comparison results above, the calculation intervals to which each of the above basic functional blocks belongs are determined.

[0167] Optionally, in one possible implementation of the first aspect, the second determining subunit is further used for:

[0168] Determine the most similar domain block corresponding to each of the above range blocks;

[0169] Based on the similarity relationship between the aforementioned range blocks and their respective most similar domain blocks, the second similarity parameter corresponding to each of the aforementioned range blocks is determined.

[0170] Optionally, in one possible implementation of the first aspect, the second determining subunit is specifically used for:

[0171] Obtain a pre-determined custom range number, wherein the custom range number is used to constrain the range of the above calculation interval;

[0172] Based on the aforementioned custom range number and the first similarity parameter corresponding to each of the aforementioned basic functional blocks, the aforementioned calculation intervals to which each of the aforementioned basic functional blocks belongs are calculated.

[0173] Optionally, in one possible implementation of the first aspect, the second determining unit includes:

[0174] The first calculation subunit is used to calculate the position of each of the multiple basic functional blocks in the calculation interval based on the first similarity parameter corresponding to each of the multiple basic functional blocks in each of the above calculation intervals, and the custom integer corresponding to each of the multiple basic functional blocks in each of the above calculation intervals.

[0175] The third determining subunit is used to determine the multiple basic functional blocks to be executed in the calculation interval and their execution order based on the respective positions of the multiple basic functional blocks in the calculation interval.

[0176] Optionally, in one possible implementation of the first aspect, the aforementioned reconfiguration unit includes:

[0177] The second calculation subunit is used to put the multiple basic functional blocks to be executed in a calculation interval and their execution order into a first-in-first-out queue as the calculation result of the calculation interval; when the next calculation interval of the calculation interval begins to be calculated, the calculation result of the calculation interval is taken out from the first-in-first-out queue.

[0178] The reconstruction sub-unit is used to reconstruct the circuit wiring structure of the chip in the next calculation interval based on the calculation results of the calculation interval.

[0179] It should be noted that the chip design device provided in the above embodiments is only illustrated by the division of the above functional modules when designing chips. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0180] The functional units and modules in the above embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of the embodiments of this application.

[0181] It should be noted that the information interaction and execution process between the above-mentioned devices / units are based on the same concept as the method embodiments of this application. For details on their specific functions and technical effects, please refer to the method embodiments section, and they will not be repeated here.

[0182] This application also provides a controller, including the chip described above.

[0183] This application also provides a vehicle, including the controller described above.

[0184] Optionally, the aforementioned vehicle can be any type of vehicle. That is, the chip designed in this embodiment can be housed in a controller. Specifically, this controller can be installed in any type of vehicle to perform control tasks.

[0185] This application also provides an electronic device, which includes one or more processors and a memory;

[0186] The memory is coupled to one or more processors. The memory is used to store computer program code, which includes computer instructions. One or more processors call the computer instructions to cause the electronic device to perform the chip design method described above.

[0187] Electronic devices can be mobile phones, smart screens, tablets, wearable electronic devices, in-vehicle electronic devices, augmented reality (AR) devices, virtual reality (VR) devices, laptops, ultra-mobile personal computers (UMPCs), netbooks, personal digital assistants (PDAs), projectors, or communication devices such as servers, storage devices, and base stations, or smart cars, etc. This application does not limit the specific type of electronic device.

[0188] This application also provides a computer-readable storage medium storing computer instructions; when the computer-readable storage medium is used on an electronic device, it causes the electronic device to execute the chip design method described above.

[0189] Computer instructions can be stored in or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. A computer-readable storage medium can be any available medium that a computer can access, or it can contain one or more data storage devices such as servers or data centers that can be integrated with that medium. Available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media, or semiconductor media (e.g., solid-state disks (SSDs)).

[0190] This application also provides a computer program product containing computer instructions, which, when run on an electronic device, enables the electronic device to execute the chip design method described above.

[0191] The computer storage medium and computer program product provided in the embodiments of this application are used to execute the methods provided above. Therefore, the beneficial effects they can achieve can be referred to the beneficial effects corresponding to the methods provided above, and will not be repeated here.

[0192] In the above embodiments, implementation can also be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. A computer program product includes one or more computer instructions. When the computer instructions are loaded and executed on a computer, all or part of the flow or function according to the embodiments of this application is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line, DSL) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access, or a data storage device such as a server or data center that integrates one or more available media. Available media can be magnetic media (such as floppy disks, hard disks, and magnetic tapes), optical media (such as Digital Versatile Discs (DVDs)), or semiconductor media (such as Solid State Disks (SSDs)).

[0193] In one possible implementation, this application provides a chip design apparatus. The chip design apparatus includes a chip-based EDA device, which is referenced to the chip design method shown in FIG1, FIG3, or FIG4, or to a chip-based EDA tool.

[0194] The aforementioned chip design apparatus acquires multiple basic functional blocks in a logic circuit diagram, as well as fractal code information corresponding to each of the basic functional blocks. Based on the fractal code information, it determines multiple computation intervals. Based on the custom integers corresponding to each of the basic functional blocks within the computation intervals, it determines the multiple basic functional blocks to be executed within those intervals and their execution order. Based on the multiple basic functional blocks to be executed within the computation intervals and their execution order, it reconstructs the circuit routing structure of the chip. Thus, because the chip design method and chip-based EDA tool of this application reconstruct the routing path of the chip's internal circuitry, they can dynamically reconstruct suitable hardware structures and routing paths according to different functional requirements. This reduces the complexity of compiling and routing reconstructible functions, thereby enabling reconstructible circuit hardware or reconstructible chips, thus improving the performance and efficiency of the chip hardware. Therefore, this chip-based EDA apparatus does not require complex solution spaces and graph theory methods; with only simple constraints on the spatial range, the chip can achieve self-reconstruction without compilation, thereby reducing design difficulty and cost. The chip design apparatus using this chip-based EDA apparatus to generate circuit routing structures also has the beneficial technical effect of saving time and resources.

[0195] In one possible implementation, this application provides a neural network processor. The neural network processor includes a chip-based EDA device, which is referenced to the chip design method shown in FIG1, FIG3, or FIG4, or to a chip-based EDA tool. The neural network processor also includes multiple parallel GPUs. The neural network processor invokes the multiple parallel GPUs to determine, based on custom integers corresponding to the multiple basic functional blocks in the computation interval, the multiple basic functional blocks to be executed in the computation interval and their execution order, and to reconstruct the circuit wiring structure of the chip based on the multiple basic functional blocks to be executed in the computation interval and their execution order.

[0196] Thus, because the chip design method and chip-based EDA tool of this application embodiment greatly simplify the process of reconstructing the circuit routing structure of the chip, the chip-based EDA device can utilize limited hardware resources to realize the logic design and automatic synthesis stages of EDA tools that traditionally require a large amount of computing and storage resources. This achieves a compile-free reconfigurable architecture for the chip, which can be applied to chips of any edge or end-side device with limited resources. At the same time, it also provides efficient algorithm compilation, instruction generation, EDA simulation, and automatic synthesis functions. The neural network processor that uses the chip-based EDA device to implement the above-mentioned neural network algorithm model calculation also has the beneficial technical effect of saving time and resources.

[0197] Unless otherwise stated, the specific embodiments provided in this application can be implemented using any one or a combination of hardware, software, firmware, or solid-state logic circuits, and can be combined with signal processing, control, and / or dedicated circuitry. The devices or apparatuses provided in the specific embodiments of this application may include one or more processors (e.g., microprocessors, controllers, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), etc.) that process various computer-executable instructions to control the operation of the devices or apparatuses. The devices or apparatuses provided in the specific embodiments of this application may include a system bus or data transmission system that couples various components together. The system bus may include any one or a combination of different bus architectures, such as a memory bus or memory controller, a peripheral bus, a universal serial bus, and / or a processor or local bus utilizing any of a variety of bus architectures. The devices or apparatuses provided in the specific embodiments of this application may be provided separately, as part of a system, or as part of other devices or apparatuses.

[0198] Unless otherwise stated, the specific embodiments provided in this application may include computer-readable storage media or combinations thereof, such as one or more storage devices capable of providing non-transitory data storage. The computer-readable storage medium / storage device may be configured to store data, programs, and / or instructions that, when executed by a processor of the device or apparatus provided in the specific embodiments of this application, cause such devices or apparatus to perform relevant operations. The computer-readable storage medium / storage device may include one or more of the following features: volatile, non-volatile, dynamic, static, readable / writable, read-only, random access, sequential access, location addressable, file addressable, and content addressable.

[0199] In one or more exemplary embodiments, the computer-readable storage medium / storage device may be integrated into the device or apparatus provided in the specific embodiments of this application or belong to a common system. The computer-readable storage medium / storage device may include optical storage devices, semiconductor storage devices and / or magnetic storage devices, etc., and may also include random access memory (RAM), flash memory, read-only memory (ROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, removable disks, recordable and / or rewritable optical discs (CD), digital versatile optical discs (DVD), mass storage media devices, or any other suitable form of storage medium.

[0200] The above are implementation methods of the embodiments of this application. It should be noted that the steps in the methods described in the specific embodiments of this application can be adjusted, merged, and deleted according to actual needs. In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. It is understood that the structures shown in the embodiments of this application and the accompanying drawings do not constitute a specific limitation on the relevant device or system. In other embodiments of this application, the relevant device or system may include more or fewer components than in the specific embodiments and accompanying drawings, or combine some components, or split some components, or have different component arrangements. Those skilled in the art will understand that various modifications or changes can be made to the arrangement, operation, and details of the methods and devices described in the specific embodiments without departing from the spirit and scope of the specific embodiments of this application; several improvements and refinements can also be made without departing from the principle of the embodiments of this application, and these improvements and refinements are also considered to be within the protection scope of this application.

Claims

1. A chip design method, characterized in that, The method includes: acquiring multiple basic functional blocks in a logic circuit diagram, and fractal code information corresponding to each of the multiple basic functional blocks, wherein the basic functional blocks are the basic units for constructing the chip circuit, and the fractal code information is used to indicate the position and connection method of the basic functional blocks in the chip; determining multiple computation intervals based on the fractal code information corresponding to each of the multiple basic functional blocks, each computation interval including at least: the multiple basic functional blocks and the connections between the multiple basic functional blocks; determining the multiple basic functional blocks to be executed in each computation interval and their execution order based on the custom integers corresponding to each of the multiple basic functional blocks in each computation interval, wherein the custom integers are used to define each basic functional block in the computation interval. The definition is an integer; the circuit wiring structure of the chip is reconstructed according to the multiple basic functional blocks to be executed in each of the multiple calculation intervals and the execution order; wherein, the fractal code information includes: a first similarity parameter; obtaining the fractal code information corresponding to each of the multiple basic functional blocks includes: determining the most similar functional block corresponding to each of the multiple basic functional blocks; determining the first similarity parameter corresponding to each of the multiple basic functional blocks according to the similarity relationship between the most similar functional blocks corresponding to each of the multiple basic functional blocks; determining multiple calculation intervals according to the fractal code information corresponding to each of the multiple basic functional blocks includes: determining the calculation interval to which each of the multiple basic functional blocks belongs according to the first similarity parameter corresponding to each of the multiple basic functional blocks.

2. The method according to claim 1, characterized in that, The step of determining the computation interval to which each of the multiple basic functional blocks belongs based on a first similarity parameter corresponding to each of the multiple basic functional blocks includes: obtaining multiple range blocks and multiple domain blocks based on the logic circuit diagram of the chip, wherein the segmentation methods corresponding to the range blocks and the domain blocks are different; determining a second similarity parameter corresponding to each of the multiple range blocks based on the multiple range blocks and the multiple domain blocks; comparing the first similarity parameter corresponding to each of the multiple basic functional blocks and the second similarity parameter corresponding to each of the multiple range blocks to obtain a comparison result; and determining the computation interval to which each of the multiple basic functional blocks belongs based on the comparison result.

3. The method according to claim 2, characterized in that, The step of determining the second similarity parameter corresponding to each of the multiple range blocks and multiple domain blocks includes: determining the most similar domain block corresponding to each of the multiple range blocks; and determining the second similarity parameter corresponding to each of the multiple range blocks based on the similarity relationship between the multiple range blocks and their respective most similar domain blocks.

4. The method according to claim 2, characterized in that, The step of determining the calculation interval to which each of the multiple basic functional blocks belongs based on the first similarity parameter corresponding to each of the multiple basic functional blocks includes: obtaining a pre-determined custom range number, wherein the custom range number is used to constrain the range of the calculation interval; and calculating the calculation interval to which each of the multiple basic functional blocks belongs based on the custom range number and the first similarity parameter corresponding to each of the multiple basic functional blocks.

5. The method according to claim 2, characterized in that, The step of determining the multiple basic functional blocks to be executed and their execution order in each calculation interval based on the custom integers corresponding to the multiple basic functional blocks in each calculation interval includes: calculating the position of each of the multiple basic functional blocks in the calculation interval based on the first similarity parameter corresponding to each of the multiple basic functional blocks in each calculation interval and the custom integers corresponding to the multiple basic functional blocks in each calculation interval; and determining the multiple basic functional blocks to be executed and their execution order in the calculation interval based on the position of each of the multiple basic functional blocks in the calculation interval.

6. The method according to claim 5, characterized in that, The step of reconstructing the circuit wiring structure of the chip based on the multiple basic functional blocks to be executed in each of the multiple calculation intervals and their execution order includes: placing the multiple basic functional blocks to be executed in one calculation interval and their execution order as the calculation result of the calculation interval into a first-in-first-out queue; when the next calculation interval of the calculation interval begins calculation, retrieving the calculation result of the calculation interval from the first-in-first-out queue; and in the next calculation interval, reconstructing the circuit wiring structure of the chip based on the calculation result of the calculation interval.

7. A chip design apparatus, characterized in that, The device includes: an acquisition unit, configured to acquire multiple basic functional blocks in a logic circuit diagram, and fractal code information corresponding to each of the multiple basic functional blocks, wherein the basic functional blocks are the basic units for constructing the chip circuit, and the fractal code information is used to indicate the position and connection method of the basic functional blocks in the chip; and a determination unit, configured to determine multiple calculation intervals based on the fractal code information corresponding to each of the multiple basic functional blocks, each calculation interval including at least: multiple basic functional blocks and connections between the multiple basic functional blocks; and to determine multiple basic functional blocks to be executed in each calculation interval and their execution order based on custom integers corresponding to each of the multiple basic functional blocks in each calculation interval, wherein the custom integers are... An integer is used to define each of the basic functional blocks as an integer in the computation interval; a reconstruction unit is used to reconstruct the circuit wiring structure of the chip according to the multiple basic functional blocks to be executed in each of the multiple computation intervals and the execution order; wherein, the fractal code information includes: a first similarity parameter, and the acquisition unit is further used to determine the most similar functional block corresponding to each of the multiple basic functional blocks; determine the first similarity parameter corresponding to each of the multiple basic functional blocks according to the similarity relationship between the most similar functional blocks corresponding to each of the multiple basic functional blocks; the determination unit is further used to determine the computation interval to which each of the multiple basic functional blocks belongs according to the first similarity parameter corresponding to each of the multiple basic functional blocks.

8. A chip, characterized in that, The chip is used in an electronic device, the chip including one or more processors, the processors being configured to invoke computer instructions to cause the electronic device to perform the method as described in any one of claims 1 to 6.

9. A controller, characterized in that, Includes the chip as described in claim 8.

10. A vehicle, characterized in that, Includes the controller as described in claim 9.

11. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the method as described in any one of claims 1 to 6.

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