A layout routing optimization method, device, storage medium and product

Abstract

The present application relates to the technical field of integrated circuit design, and particularly relates to a layout wiring optimization method, device, storage medium and product.The method comprises the following steps: providing a design rule file and layout information of an initial integrated circuit design, and generating a violation database; performing violation detection on the initial layout to obtain layout violations, and dividing the layout violations into to-be-divided violations and second-type violations; obtaining violation information of the to-be-divided violations, dividing the to-be-divided violations into third-type violations and first-type violations; performing first-type repair on the first-type violations, and updating the layout information and the layout violation information; performing second-type repair on the second-type violations, and updating the layout information and the layout violation information; repeating the repair steps of the first-type violations and the second-type violations until a preset termination condition is met, performing first-type repair on the third-type violations, and updating the layout information to obtain an optimized layout.The method solves the problems of poor repair efficiency and effect of existing violations.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to a layout routing optimization method, device, storage medium, and product. Background Technology

[0002] In the design of very large-scale integrated circuit (VLSI) chips, as manufacturing process nodes advance, physical design rules become increasingly complex. If the routing results do not meet the constraints of these design rules, design rule violations occur, leading to a significant decrease in yield. To correct these violations, two methods are generally used: small-scale correction, which involves local adjustments to the layer causing the violation and adjacent layers; and large-scale correction, which involves adjusting the routing pattern across multiple layers over a larger area. Considering both routing runtime and violation correction, small-scale correction is generally prioritized, with large-scale correction only used when small-scale correction fails.

[0003] However, in a lot of practice, we have found that due to the iteration of design rules and the improvement of utilization, small-scale repairs of some rules will occupy adjacent wiring resources, leading to increased congestion of subsequent wiring. This results in insufficient wiring resources when large-scale repairs resolve complex violations, ultimately leading to slow running time and inability to repair all violations in actual practice. Summary of the Invention

[0004] To address the technical problems of poor efficiency and effectiveness in repairing existing cabling violations, this invention provides a layout cabling optimization method, device, storage medium, and product.

[0005] The present invention provides a layout routing optimization method, comprising: providing a design rule file and an initial layout; generating a violation database based on the design rule file and the initial layout, wherein the violation database pre-stores violation information for multiple layout violations, the violation information including the layer where the violation is located, the type of violation, the scope of violation repair, and the method of violation repair, the repair method including a first type of repair and a second type of repair; performing violation detection on the initial layout to obtain layout violations; classifying the layout violations into unclassified violations and a second type of violation based on the size of the violation repair scope; obtaining the violation information of the unclassified violations; and classifying the unclassified violations that satisfy preset constraints into a third type of violation. Conversely, if the condition is not met, it is classified as a first-type violation, wherein the preset constraints are that the layer where the violation is located is a metal layer, the violation type is a spacing violation and does not violate the corner spacing rule, and the violation repair method is to add metal or cut metal on the edge perpendicular to the preferred routing direction; the first-type violation in the current layout is repaired in the first type, and the layout information and layout violation information are updated; the second-type violation in the current layout is repaired in the second type, and the layout information and layout violation information are updated; the repair steps for the first-type violation and the second-type violation are repeated until a preset termination threshold is met, and then the first-type violation is repaired in the third type, and the layout information is updated to obtain an optimized layout.

[0006] Preferably, the initial layout is subjected to violation detection to obtain layout violations. Based on the size of the violation repair range, the layout violations are divided into unclassified violations and second-class violations, including: performing violation detection on the initial layout based on the design rule file to obtain layout violations; obtaining the violation repair range corresponding to each layout violation based on the violation database, wherein the violation repair range includes the repair layer and the repair magnitude; and classifying layout violations whose repair layer is the layer where the violation is located and / or adjacent layers, and whose repair magnitude is less than a preset threshold, as unclassified violations, otherwise, they are classified as second-class violations.

[0007] Preferably, the preset threshold is the spacing between adjacent routing tracks perpendicular to the preferred routing direction; when the repair layer of the layout violation includes non-adjacent layers of the layer where the violation is located, and / or the repair magnitude is greater than or equal to the preset threshold, the layout violation is classified as a second type of violation; the first type of repair is the repair of the layer where the violation is located and / or adjacent layers, and the repair magnitude is less than the preset threshold; the second type of repair is the repair of non-adjacent layers of the layer where the violation is located, and / or the repair magnitude is greater than or equal to the preset threshold.

[0008] Preferably, before performing the first type of repair on the first type of violation in the current map, the method includes: dividing the current map into multiple repair areas.

[0009] Preferably, when repairing the current map, multiple repair areas can be processed in parallel.

[0010] Preferably, the second type of violation in the current layout is repaired in a second way, including: detecting whether there is a first type of violation in the current layout, and if so, repairing the first type of violation and the second type of violation in the current layout in a second way.

[0011] Preferably, the preset termination threshold includes the number of repeated repairs reaching a preset value, and / or the total number of first-type violations and second-type violations in the current layout reaching a preset value.

[0012] To solve the above-mentioned technical problems, the present invention provides another technical solution as follows: an electronic device, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the layout routing optimization method as described in any of the above claims.

[0013] To solve the above-mentioned technical problems, the present invention provides another technical solution as follows: a computer storage medium storing computer program instructions thereon, wherein the computer program instructions, when executed, implement the layout routing optimization method as described in any of the preceding claims.

[0014] To solve the above-mentioned technical problems, the present invention provides another technical solution as follows: a computer program product, comprising a computer program, wherein the computer program, when executed by a processor, implements the layout routing optimization method as described in any of the above claims.

[0015] Compared with the prior art, the layout routing optimization method, device, storage medium and product provided by the present invention have the following advantages:

[0016] 1. This invention provides a layout routing optimization method. By dynamically classifying layout violations into three categories and repairing different categories of violations in stages, it decouples locally repairable violations from those requiring large-scale rerouting. This avoids timing disruptions and layout oscillations caused by large-scale modifications, and allows for the rapid elimination of a large number of easily repairable violations in the early stages of the repair process. This facilitates the concentration of resources to resolve stubborn violations later, significantly reducing iterative conflicts during the repair process. Simultaneously, it delays the repair of the third category of violations that occupy adjacent routing resources and meet specific constraints, avoiding the impact of early local optimization on global routing. By controlling the repair order of different categories of violations through a staged repair strategy, it suppresses the chain reaction of violations caused by local repair in traditional violation repair processes. Furthermore, by combining the repair process with preset termination conditions, it shortens the overall convergence time, improves optimization efficiency while ensuring repair quality, increases routing success rate, and significantly reduces the number of manual interventions, ultimately generating a highly reliable integrated circuit layout.

[0017] 2. The layout routing optimization method provided in this embodiment of the invention achieves automatic classification based on a quantitative comparison between the violation repair range and the preset repair range. Specifically, it first obtains the violation repair range of each layout violation from the violation database. The initial classification can be completed by comparing the "violation repair range" with the "preset repair range" in one step. The algorithm has low complexity and is simple to implement. It identifies and classifies layout violations that require large-scale chain modifications into the second type of violation at one time, avoiding repeated judgments in subsequent iterations, and significantly reducing CPU usage and memory peaks. By accurately distinguishing between "violations to be classified" and "second type of violations", it lays the foundation for subsequent phased repair strategies, improves classification efficiency and accuracy, and reduces computing resource consumption.

[0018] 3. The layout routing optimization method provided in this embodiment of the invention uses both the repair layer and the repair range of the violation as the criteria for determining the violation to be divided, thereby achieving precise quantification of the dual constraints of modification position and modification range. This prevents the second type of violation, which requires large-scale repair across layers or across tracks, from being misjudged as a violation that only requires local fine-tuning. This makes the set of violations to be divided purer, laying a reliable foundation for further subdividing the first and third types of violations and further reducing the false repair rate.

[0019] Secondly, by defining the size of the "repair scope", two types of repair methods are defined to match the repair strategy with the violation classification and clarify the applicable scenarios of the two repair methods. The first type of repair is used for local fine-tuning, and the second type of repair is used to handle large-scale wire disconnection and wiring. The two work together to achieve fine allocation of resources and reduce invalid calculations. During the repair process, the appropriate repair method is selected according to the violation classification to improve the accuracy of the repair and avoid the problem of secondary violations or incomplete repair due to improper selection of repair methods.

[0020] 4. The layout routing optimization method provided in this embodiment of the invention divides the current layout into multiple repair regions, and performs repair in parallel on a region-by-region basis when performing violation repair. This fully utilizes the parallel capabilities of multi-core processors to accelerate the repair of high-frequency, low-complexity Type I violations, enabling the repair of a large number of Type I violations to be completed in a short time, significantly shortening the total optimization time. Furthermore, the division of repair regions makes the repair work more focused, the boundaries between regions are controlled, reducing mutual interference between regions, and local modifications will not immediately spread to the entire chip, maintaining the stability of the early layout and improving the overall optimization efficiency and quality.

[0021] 5. In the layout routing optimization method provided in this embodiment of the invention, first-type violations that cannot be repaired by the first type of repair or that would cause other design rule violations after repair are temporarily suspended for second-type repair together with second-type violations. In the second-type repair, first-type violations left over from the aforementioned steps are detected and processed simultaneously, and the second-type repair strategy is uniformly applied for one-time repair. This avoids the introduction of new graphics by the first type of repair and the resulting cross-influence with the second-type violations to be processed, ensuring the comprehensiveness of the repair. By collaboratively repairing related violations, secondary violations caused by step-by-step repair are reduced, improving the layout routing optimization. Figure 1 Consistency and repair success rate.

[0022] 6. The layout routing optimization method provided in this embodiment of the invention provides two iteration termination conditions: "number of repetitions" and "total number of violations". Through the synergistic cooperation of these two termination conditions, the optimization depth and computational cost are balanced, ensuring convergence within a controllable time, taking into account both quality and schedule, avoiding infinite loops or premature termination, improving optimization efficiency and saving optimization time and computational resources while ensuring that the repair effect meets expectations.

[0023] 7. An electronic device also provided in this embodiment of the invention includes a memory, a processor, and a computer program stored in the memory. The processor executes the computer program to implement the layout routing optimization method as described in any of the preceding claims.

[0024] The electronic device implements the layout routing optimization method by executing a corresponding computer program through a processor, transforming the method into a practically operable electronic device function. This facilitates its application in actual integrated circuit design work, improves the work efficiency of designers, and promotes the automation and intelligence of the integrated circuit design process. The electronic device in this embodiment also has the same beneficial effects as the layout routing optimization method described above, which will not be elaborated here.

[0025] 8. The present invention also provides a computer storage medium storing computer program instructions, which, when executed, implement the layout routing optimization method as described in any of the preceding claims.

[0026] The computer storage medium stores the relevant calculation program instructions, which makes the layout and routing optimization method convenient to store, transmit and execute. This facilitates the promotion of the layout and routing optimization method, lowers the threshold for use and maintains algorithm consistency. It helps more integrated circuit design scenarios to adopt the layout and routing optimization method to improve design quality. The computer storage medium in this embodiment also has the same beneficial effects as the layout and routing optimization method described above, which will not be elaborated here.

[0027] 9. The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the layout and routing optimization method as described in any of the preceding claims. It has the same beneficial effects as the aforementioned layout and routing optimization method, and will not be elaborated upon here. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a flowchart of the layout routing optimization method provided in an embodiment of the present invention.

[0030] Figure 2 This is an example diagram illustrating the small-scale repair of rule violations in a layout routing optimization method provided by an embodiment of the present invention.

[0031] Figure 3 This is an example of a large-scale repair of design rule violations in the layout routing optimization method provided in this embodiment of the invention. Figure 1 .

[0032] Figure 4 This is an example of a large-scale repair of design rule violations in the layout routing optimization method provided in this embodiment of the invention. Figure 2 .

[0033] Figure 5 This is a detailed flowchart of step 2 in the layout routing optimization method provided in this embodiment of the invention.

[0034] Figure 6 This is a schematic diagram of the structure of the electronic device provided in an embodiment of the present invention.

[0035] Figure 7 This is a schematic diagram of the structure of a computer storage medium provided in an embodiment of the present invention.

[0036] Figure 8 This is a schematic diagram of the structure of a computer program product provided in an embodiment of the present invention.

[0037] Explanation of reference numerals in the attached diagram:

[0038] 1. Electronic equipment; 11. Memory; 12. Processor; 2. Computer storage medium; 3. Computer program product. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0040] In the embodiments provided by this invention, it should be understood that "B corresponding to A" means that B is associated with A, and B can be determined based on A. However, it should also be understood that determining B based on A does not mean determining B solely based on A; B can also be determined based on A and / or other information.

[0041] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of the invention. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Those skilled in the art should also recognize that the embodiments described in the specification are optional embodiments, and the actions and modules involved are not necessarily essential to the invention.

[0042] In various embodiments of the present invention, it should be understood that the sequence number of each process does not necessarily imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0043] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, or they may sometimes be executed in reverse order, depending on the functions involved. It is particularly important to note that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0044] Wiring tracks refer to predefined parallel paths used for laying metal interconnects on each metal wiring layer of an integrated circuit chip; the wiring track directions of different metal layers are usually alternating.

[0045] Please see Figure 1-4 This invention provides a layout routing optimization method, comprising:

[0046] Step S1: Provide design rule files and initial layout. Generate a violation database based on the design rule files and initial layout. The violation database pre-stores violation information for multiple layout violations. The violation information includes the layer where the violation is located, the type of violation, the scope of violation repair, and the violation repair method. The repair methods include first-type repair and second-type repair.

[0047] Step S2: Perform violation detection on the initial layout to obtain layout violations. Based on the size of the violation repair range, classify the layout violations into unclassified violations and second-class violations.

[0048] Step S3: Obtain the violation information of the violations to be classified. Classify the violations that meet the preset constraints as the third type of violations, and otherwise classify them as the first type of violations. The preset constraints are that the layer where the violation is located is a metal layer, the type of violation is a spacing violation and does not violate the corner spacing rule, and the violation repair method is to add metal or cut metal on the side perpendicular to the preferred routing direction.

[0049] Step S4: Perform first-type repair on the first type of violation in the current map, and update the map information and map violation information;

[0050] Step S5: Perform second-type repairs on the second type of violations in the current map, and update the map information and map violation information;

[0051] Step S6: Repeat the repair steps for the first and second types of violations until the preset termination threshold is met. Then, perform the first type of repair for the third type of violation and update the layout information to obtain the optimized layout.

[0052] Specifically, the layout routing optimization method provided in this embodiment is used for routing optimization in multilayer integrated circuit design.

[0053] It should be understood that updating the layout information and layout violation information in steps S3 and S5 includes updating the routing status of the current layout, updating the violations existing in the current layout, and the classification of the violations.

[0054] Specifically, "repeating the repair steps for Type I and Type II violations" in step S6 means repeating the operations of steps S4 and S5.

[0055] It should be noted that, based on the scope of the violation repair, the violation repair methods can be broadly divided into two types: small-scale repair and large-scale repair. Small-scale repair involves minimal changes to the layout, representing localized fine-tuning, which is highly efficient and has less impact on other routing violations. However, some violations, after small-scale repair, will occupy additional routing resources, leading to increased congestion in subsequent routing. Repairing such violations early may significantly reduce the utilization rate of routing resources or increase the difficulty of subsequent repairs. The layout routing optimization method provided by this invention intelligently and dynamically classifies layout violations into three categories and performs targeted repairs on different categories of violations in stages, avoiding mutual interference during the repair process. This effectively improves the compliance and optimized structure of layout routing, thereby enhancing the quality of layout design.

[0056] Understandably, the layout routing optimization method provided by this invention first classifies layout violations into two categories based on the size of the violation repair range: unclassified violations and second-category violations. This decouples locally repairable violations from those requiring large-scale dismantling and rerouting. Then, violations that occupy adjacent routing resources and meet specific constraints are further classified into a third category. Violations requiring only minor adjustments and not affecting subsequent routing are classified as first-category violations. Based on the characteristics of different categories of violations, specific violations are repaired at different stages: first-category violations with small repair ranges are prioritized, followed by second-category violations with large repair ranges. This avoids timing disruptions and layout fluctuations caused by large-scale modifications while ensuring efficient repair. The repair process can quickly eliminate a large number of easily repairable violations in the early stages, facilitating the concentration of resources to solve stubborn violations in the later stages, significantly reducing iterative conflicts during the repair process. At the same time, it will delay the repair of third-type violations that occupy adjacent routing resources and meet specific constraints, avoiding the impact of early local optimization on global routing. By controlling the repair order of different types of violations through a phased repair strategy, it suppresses the chain reaction of violations caused by local repair in the traditional violation repair process. Secondly, the repair process is controlled by combining preset termination conditions, which shortens the overall convergence time, improves optimization efficiency and routing success rate while ensuring repair quality, and significantly reduces the number of manual interventions, ultimately generating a highly reliable integrated circuit layout.

[0057] Furthermore, step S1 also includes preprocessing the information of the design rule file and the initial layout to obtain data information that can be used to build the violation database, and generating the violation database based on the data information.

[0058] It should be noted that there are various routing templates in the design rule file. Some specific templates may contain violations or be prone to causing certain violations. By comparing the initial layout with the routing templates in the design rule file, we can obtain the possible violations in the initial layout and the corresponding repair methods. Based on this information, a violation database can be built so that the layout violations can be quickly and accurately classified and repaired in subsequent steps.

[0059] Specifically, the aforementioned data information includes, but is not limited to: wiring tracks, preferred wiring direction, vias, whether to add graphic corrections for violations, and violation information.

[0060] Please see Figure 5 Step S2: Perform violation detection on the initial layout to obtain layout violations. Based on the size of the violation repair range, classify the layout violations into unclassified violations and a second type of violation, including:

[0061] Step S21: Perform violation detection on the initial layout based on the design rule file to obtain layout violations;

[0062] Step S22: Obtain the violation repair range corresponding to each map violation based on the violation database. The violation repair range includes the repair layer and the repair extent.

[0063] Step S23: Classify layout violations that are repaired on the layer where the violation is located and / or adjacent layers, and whose repair magnitude is less than a preset threshold, as violations to be classified; otherwise, classify them as second-class violations.

[0064] Understandably, using the "repair layer and repair scope of the violation" as the dividing criterion between the violation to be classified and the second type of violation, through clear scope definition, allows for rapid classification by comparing the "violation repair scope" of the violation in the database with the "preset repair scope". The algorithm has low complexity and is simple to implement. It identifies and classifies map violations that require large-scale chain modifications into the second type of violation in one go, avoiding repeated judgments in subsequent iterations, and significantly reducing CPU usage and memory peaks. By accurately distinguishing between "violations to be classified" and "second type of violation", it lays the foundation for subsequent phased repair strategies, avoids early local and ineffective fine-tuning of the second type of violation, improves classification efficiency and accuracy, and reduces computational resource consumption.

[0065] Specifically, the preset threshold is the spacing between adjacent routing tracks perpendicular to the preferred routing direction; when the repair layer of a layout violation includes non-adjacent layers of the layer where the violation is located, and / or the repair range is greater than or equal to the preset threshold, the layout violation is classified as a second type of violation.

[0066] Specifically, the non-adjacent layer of the layer where the violation occurs refers to other metal layers or via layers besides the layer where the violation occurs and its adjacent layers.

[0067] It should be noted that within the same layer, the direction of the cabling tracks is consistent, while the direction of the cabling tracks on different layers may be inconsistent, i.e., there may be multiple parallel tracks. The spacing between adjacent cabling tracks perpendicular to the preferred cabling direction refers to the distance between the cabling track where the violation to be repaired is located and the adjacent cabling track in the repair direction. Here, the repair direction refers to the direction perpendicular to the preferred cabling direction.

[0068] Specifically, if the rectification of a violation requires multiple adjustments, the standard for judging the extent of the rectification should be the wiring track spacing of the specific layer in which the adjustment is performed. That is, the adjustment of the first layer cannot be compared with the wiring track spacing of the second layer.

[0069] For example, in a certain metal layer, the preferred routing path direction is the X direction, and the direction perpendicular to the preferred routing path is the Y direction. Assuming that the violation is repaired by moving a line along the Y direction in the current layer or the adjacent layer of the layer where the violation is located, and the moving range does not reach the nearest routing path in the moving direction, then the violation is defined as a violation to be classified. If the repair method is to repair the non-adjacent layer of the layer where the violation is located, and / or the moving range of the line that needs to be moved during the repair is to move to its adjacent routing path or cross the adjacent routing path, then the violation is defined as a second type of violation.

[0070] Understandably, if the number of layers to be adjusted during violation repair is greater than 3, it is classified as a Type II violation. If the number of layers to be adjusted during violation repair is equal to 3, the relationship between the repair layer and the layer containing the violation needs to be determined. For example, if the repair layer is two layers above or two layers below the layer containing the violation, and one of the repair layers is a non-adjacent layer of the layer containing the violation, then the violation is also classified as a Type II violation. If the violation repair requires adjustment of the layer above and the layer below the layer containing the violation, although the repair adjustment also involves 3 layers, since both repair layers are adjacent layers of the layer containing the violation, the violation is not necessarily a Type II violation. Only when the repair range is greater than or equal to the spacing between adjacent wiring tracks perpendicular to the preferred wiring direction is the violation defined as a Type II violation. If the repair range is less than the spacing between adjacent wiring tracks perpendicular to the preferred wiring direction, the violation is defined as a violation to be classified.

[0071] Understandably, using both the repair layer and the repair extent of a violation as criteria for determining the violation to be classified allows for the precise quantification of the dual constraints of modification location and modification extent. This prevents the misclassification of Type II violations that require extensive repair across layers or tracks as violations that only require local fine-tuning, resulting in a purer set of violations to be classified. This lays a reliable foundation for further subdividing Type I and Type III violations and further reduces the false repair rate.

[0072] It should be noted that when the scope of a map violation exceeds either the first threshold or the second threshold, the map violation will be classified as a second type of violation.

[0073] This embodiment enhances the reliability of violation classification by using a dual threshold joint judgment, fully considers the spatial relationships and routing rules in the multilayer integrated circuit layout, making the violation classification more scientific and reasonable, and ensuring the stability and reliability of subsequent repairs.

[0074] Specifically, the first type of repair is to repair the layer where the violation occurs and / or the adjacent layer, and the repair amount is less than the preset threshold; the second type of repair is to repair the non-adjacent layer where the violation occurs, and / or the repair amount is greater than or equal to the preset threshold.

[0075] Understandably, defining two types of repair methods by the size of the "repair scope" allows the repair strategy to match the violation classification and clarifies the applicable scenarios for the two repair methods. The first type of repair is used for local fine-tuning, while the second type of repair is used to handle large-scale wire disconnection and rewiring. The two work together to achieve fine-grained resource allocation, reduce invalid calculations, and select the appropriate repair method according to the violation classification during the repair process to improve the accuracy of the repair and avoid problems such as secondary violations or incomplete repair due to improper selection of repair methods.

[0076] Furthermore, before performing the first type of repair on the first type of violation in the current map, the process includes: dividing the current map into multiple repair areas.

[0077] Specifically, when repairing the current map, multiple repair areas can be processed in parallel.

[0078] In some embodiments, by setting the side length, the current layout is divided into multiple rectangular regions of the same size, and different regions are assigned to different computing threads for parallel computing.

[0079] Specifically, the initial layout can be directly divided into regions, and subsequent iterative repair processes can directly reference the divided regions of the initial layout for repair calculations, avoiding multiple layout region division operations, simplifying the operation process, and improving calculation efficiency.

[0080] In other embodiments, the division of the repair area can also be based on the amount of computation, that is, a pre-set amount of computation for each area, that is, the number of Type I violations that need to be calculated in each area. The current map is divided into rectangular areas of different sizes, and the number of Type I violations to be calculated in each area is roughly the same. This makes the time required to repair the Type I violations in each area in parallel roughly the same, avoiding the situation where the computation amount of individual threads is large, causing other computing threads to wait.

[0081] It should be understood that parallel processing of multiple repair areas can be performed at different repair stages. The specific choice can be made according to the actual situation. It can be that each repair stage is processed in parallel in partitions, or that some repair stages are processed in parallel in partitions, while some repair stages are processed globally in a unified manner.

[0082] It should be noted that in this embodiment, after performing the first type of repair on the first type of violation in each repair area, the map information and map violation information of that area are updated simultaneously. That is, the first type of violation repair and information update calculation are performed on the map in different areas, and the calculations of different areas are processed in parallel, thereby improving the calculation efficiency. Specifically, when performing the second type of repair on the second type of violation or the first type of repair on the third type of violation, the repair and update are also performed in parallel on a multi-area basis.

[0083] Understandably, dividing the current layout into multiple repair regions and performing violation repairs in parallel on a region-by-region basis fully leverages the parallel capabilities of multi-core processors to accelerate the repair of high-frequency, low-complexity Type I violations. This allows for the repair of a large number of Type I violations in a short time, significantly shortening the overall optimization time. Furthermore, the division of repair regions makes the repair work more focused, controls the boundaries between regions, reduces mutual interference between regions, and prevents local modifications from immediately spreading to the entire chip, maintaining the stability of the early layout and improving overall optimization efficiency and quality.

[0084] Furthermore, a second type of repair is performed on the second type of violation in the current map, including: detecting whether there is a first type of violation in the current map, and if so, performing a second type of repair on the first type of violation and the second type of violation in the current map.

[0085] It should be noted that some Type 1 violations will generate new design rule violations after Type 1 fixes. Therefore, in the actual fix process, the fix results for such violations will be withdrawn, and the violation will be retained for Type 2 fixes in the next step, together with Type 2 violations.

[0086] Understandably, first-type violations that cannot be repaired using the first-type repair method or that would create other design rule violations after repair will be temporarily suspended and repaired together with second-type violations using the second-type repair method. In the second-type repair, first-type violations remaining from the previous steps will be detected and processed simultaneously, and all will be repaired in one go using the second-type repair strategy. This avoids cross-influence between new graphics introduced by the first-type repair and the second-type violations to be processed, ensuring the comprehensiveness of the repair. By collaboratively repairing related violations, secondary violations caused by step-by-step repair are reduced, resulting in an improved version. Figure 1 Consistency and repair success rate.

[0087] Furthermore, the preset termination thresholds include the number of repeated repairs reaching a preset value, and / or the total number of Type I and Type II violations in the current layout reaching a preset value.

[0088] Optionally, the specific value of the preset termination threshold can be adjusted according to actual usage needs, without imposing too many restrictions here.

[0089] Understandably, controlling the number of iterations for repair can prevent infinite iteration. Terminating the loop early when the total number of remaining violations reaches the target can avoid over-optimization, balancing efficiency and quality. Providing two iteration termination conditions, namely "number of repetitions" and "total number of violations," balances optimization depth and computational cost through the synergy of these two termination conditions, ensuring convergence within a controllable time, balancing quality and schedule, avoiding infinite loops or premature termination, and improving optimization efficiency while saving optimization time and computational resources, all while ensuring that the repair effect meets expectations.

[0090] Specifically, Table 1 lists three different violation classification methods and repair timings for an area of ​​614825.16um. 2 The chip design layout of a 7nm process node with 1,676,845 standard cells was repaired, resulting in different design rule violation results. The three schemes in this embodiment use the exact same design rule file and layout information, and the termination iteration condition is set to either the number of repeated repairs reaches 20 or the total number of Type I and Type II violations in the current layout is 0.

[0091]

[0092] Table 1. Impact of different remediation schemes on the final number of design rule violations for the same design

[0093] As shown in Table 1, classifying third-category violations and addressing them only after the threshold requirement is met optimizes runtime and significantly reduces the number of remaining violations in the layout. Compared to not classifying third-category violations, runtime is reduced by 14.51%, and the number of final violations in the layout is reduced by 99.17%. Furthermore, compared to not classifying third-category violations, the scheme that classifies third-category violations and does not address them after the threshold requirement is met reduces the number of violations by 96.81%. This indicates that prematurely addressing third-category violations does indeed consume significant cabling resources and makes it difficult to address remaining violations. Delaying the repair of third-category violations effectively suppresses cabling congestion and improves repair efficiency.

[0094] Please refer to further information. Figure 6 The present invention also provides an electronic device 1, including a memory 11, a processor 12 and a computer program stored on the memory 11, wherein the processor 12 executes the computer program to implement the layout routing optimization method as described in any of the preceding claims.

[0095] Specifically, the electronic device 1 can be a smartphone, tablet computer, computer, or portable computer.

[0096] It should be noted that the processor 12 may include one or more cores for processing data and message matrix units. The processor 12 connects to various parts of the entire electronic device 1 using various interfaces and lines, and performs various functions of the electronic device 1 and processes data by running or executing instructions, programs, code sets or instruction sets stored in the memory 11, and by calling data stored in the memory 11.

[0097] Optionally, the processor 12 can be implemented using at least one of the following hardware forms: digital signal processing, field-programmable gate array (FPGA), and programmable logic array (PLA). The processor 12 can integrate one or more of the following: a central processing unit (CPU), a graphics processor (GPU), and a modulation / decoder (MDD). Alternatively, the MDD may not be integrated into the processor 12 and can be implemented separately using a communication chip.

[0098] Understandably, the electronic device 1 implements the layout routing optimization method by executing a corresponding computer program through the processor 12, transforming the method into a function of the actually operable electronic device 1, which is convenient for application in actual integrated circuit design work, improves the work efficiency of designers, and promotes the automation and intelligence of integrated circuit design process. The electronic device 1 in this embodiment also has the same beneficial effects as the layout routing optimization method described above, which will not be elaborated here.

[0099] Please see Figure 7 The present invention also provides a computer storage medium 2, on which computer program instructions are stored, and when the computer program instructions are executed, the layout routing optimization method as described in any of the preceding claims is implemented.

[0100] Understandably, the computer storage medium 2 stores the relevant calculation program instructions, which makes the layout and routing optimization method convenient to store, transmit and execute. This facilitates the promotion of the layout and routing optimization method, lowers the threshold for use and maintains algorithm consistency. It helps more integrated circuit design scenarios to adopt the layout and routing optimization method to improve design quality. The computer storage medium 2 in this embodiment also has the same beneficial effects as the layout and routing optimization method described above, which will not be elaborated here.

[0101] Please see Figure 8 The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the layout routing optimization method as described in any of the preceding claims.

[0102] Understandably, the computer program product 3 provided in this embodiment includes computer instructions, which can be stored in a computer storage medium. The processor 12 of the electronic device 1 reads the computer instructions from the storage medium and executes the computer instructions, causing the electronic device 1 to perform the layout routing optimization method described in the various optional implementations above.

[0103] It is understood that, according to the embodiments disclosed in this invention, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication component, and / or installed from a removable medium. When the computer program is executed by a central processing unit (CPU), it performs the functions defined in the methods of this application. It should be noted that the computer-readable medium described in this application can be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two. Computer-readable storage media include, but are not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatuses, or devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this application, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in connection with an instruction execution system, apparatus, or device. In this application, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on a computer-readable medium can be transmitted using any suitable medium, including but not limited to: wireless, wire, optical fiber, RF, etc., or any suitable combination thereof.

[0104] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0105] The foregoing has provided a detailed description of a layout routing optimization method, device, storage medium, and product disclosed in the embodiments of the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of the present invention. Furthermore, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention. Any modifications, equivalent substitutions, and improvements made within the principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A layout routing optimization method, characterized in that, include: Provide design rule files and initial layouts, and generate a violation database based on the design rule files and initial layouts. The violation database pre-stores violation information for multiple layout violations. The violation information includes the layer where the violation is located, the type of violation, the scope of violation repair, and the method of violation repair. The repair methods include first-type repair and second-type repair. The initial layout is subjected to violation detection to obtain layout violations. Based on the size of the violation repair range, the layout violations are divided into unclassified violations and second-class violations. Obtain the violation information of the violation to be classified, and classify the violation to be classified into the third type of violation if it meets the preset constraints, otherwise classify it into the first type of violation. The preset constraints are that the layer where the violation is located is a metal layer, the type of violation is a spacing violation and does not violate the corner spacing rule, and the violation repair method is to add metal or cut metal on the side perpendicular to the preferred wiring direction. Perform the first type of repair on the first type of violation in the current map, and update the map information and map violation information; Perform the second type of repair on the second type of violations in the current map, and update the map information and map violation information; Repeat the repair steps for the first type of violation and the second type of violation until the preset termination threshold is met. Then, perform the first type of repair on the third type of violation and update the layout information to obtain an optimized layout.

2. The layout routing optimization method as described in claim 1, characterized in that, The initial layout is subjected to violation detection to obtain layout violations. Based on the size of the violation repair range, the layout violations are divided into unclassified violations and a second type of violation, including: Based on the design rule file, violation detection is performed on the initial layout to obtain layout violations; The violation repair scope corresponding to each of the map violations is obtained based on the violation database, and the violation repair scope includes the repair layer and the repair range; Layout violations that are repaired at the layer where the violation is located and / or adjacent to the layer, and whose repair magnitude is less than a preset threshold, are classified as unclassified violations; otherwise, they are classified as second-class violations.

3. The layout routing optimization method as described in claim 2, characterized in that: The preset threshold is the spacing between adjacent wiring tracks perpendicular to the preferred wiring direction; When the repair layer of the layout violation includes a non-adjacent layer of the layer where the violation is located, and / or the repair magnitude is greater than or equal to a preset threshold, the layout violation is classified as a second type of violation. The first type of repair is to repair the layer where the violation occurs and / or adjacent layers, and the repair magnitude is less than a preset threshold; The second type of repair is the repair of non-adjacent layers of the layer where the violation occurs, and / or the repair magnitude is greater than or equal to a preset threshold.

4. The layout routing optimization method as described in claim 1, characterized in that, Before performing the first type of repair on the first type of violation in the current map, the process includes: dividing the current map into multiple repair areas.

5. The layout routing optimization method as described in claim 4, characterized in that: When repairing the current map, multiple repair areas can be processed in parallel.

6. The layout routing optimization method as described in claim 1, characterized in that, The second type of violation in the current map will be corrected in the second type, including: Check if there are any Category 1 violations in the current map. If so, perform Category 2 repairs on both Category 1 and Category 2 violations in the current map.

7. The layout routing optimization method as described in claim 1, characterized in that: The preset termination threshold includes the number of repeated repairs reaching a preset value, and / or the total number of Type I and Type II violations in the current layout reaching a preset value.

8. An electronic device, characterized in that: The system includes a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the layout routing optimization method as described in any one of claims 1-7.

9. A computer storage medium, characterized in that: It stores computer program instructions, which, when executed, implement the layout routing optimization method as described in any one of claims 1-7.

10. A computer program product, comprising a computer program, characterized in that: When the computer program is executed by the processor, it implements the layout routing optimization method as described in any one of claims 1-7.

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