Superconducting quantum controller for use in a low temperature superconducting quantum computer

Abstract

The application discloses a super-low-temperature quantum controller applied to a low-temperature superconducting quantum computer, comprising an analog circuit part and a digital circuit part, the analog circuit part comprises two XY channels and three Z channels, each XY channel comprises two signal paths and an on-chip balun, the signal path comprises a nonlinear digital-to-analog converter (NLDAC), an intermediate frequency filter, a variable gain amplifier (VGA), a quadrature mixer and a quadrature local oscillator signal generator, the input end of the quadrature mixer is connected with the output end of the quadrature local oscillator signal generator, the output ends of the two signal paths of the XY channel are combined through the on-chip balun to generate an XY channel control signal of the XY channel, and the three Z channels each comprise three independent independently adjustable digital-to-analog converters (DACs) for generating Z channel control signals of the three Z channels. The application aims to shorten the distance between the controller and the quantum chip, improve the fidelity of the quantum computer and reduce the overhead of quantum error correction.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of quantum computing, and particularly relates to a super-low-temperature quantum controller applied to a low-temperature superconducting quantum computer. BACKGROUND

[0002] With the rapid development of quantum computing technology, superconducting qubits and spin qubits have shown the potential to realize practical quantum computing. However, the manipulation and reading of qubits require high-precision and low-noise electronic control systems, and the long-distance interconnection between traditional room-temperature electronic devices and low-temperature quantum processors will introduce thermal noise, signal attenuation and timing delay, which seriously restricts the scalability and operation fidelity of quantum systems. To solve this challenge, Cryo-CMOS quantum controller chips for low-temperature superconducting quantum computers have emerged, which significantly shorten the signal path, reduce power consumption and noise by integrating control circuits directly in a low-temperature environment (such as 4K or lower), providing a feasible solution for integrated control of large-scale quantum processors.

[0003] A two-qubit module is the smallest representative subcircuit that demonstrates the basic functions required for general control of large-scale quantum processors. For example, the qubits in the Sycamore quantum processor architecture of Google are interconnected on a two-dimensional grid through adjustable couplers, and these qubits are implemented using magnetic flux adjustable Transmon (transmon), which is essentially a nonlinear LC resonator, in which a superconducting quantum interference device (SQUID) acts as a magnetic flux adjustable nonlinear inductance. Each transmon requires two control signals: a microwave signal for qubit resonant excitation (XY channel), and a baseband current for adjusting the qubit frequency through SQUID magnetic flux bias (Z channel). There is also a readout port that detects the qubit state through microwave reflection measurement technology. The adjustable coupler is implemented using an additional transmon embedded between two qubits and coupled through a capacitor between adjacent qubits. The transmon in the adjustable coupler works in a non-resonant state, acting as a magnetic flux adjustable impedance. By tuning the transmon of the adjustable coupler to a specific frequency, the coupling between qubits can be completely eliminated; while deviating from this bias point, a continuously adjustable deterministic coupling between qubits can be achieved, thereby forming the basis of a two-qubit gate. Each coupler has a single bias current (g channel) for controlling the operating frequency of the coupler transmon. Therefore, the control of a two-qubit module requires a qubit controller that can provide control waveforms for two XY channels, two Z channels, and one g channel, and a microwave pulse transmitter for two XY channels, two Z channels, and one g channel to generate the required microwave pulse signals.

[0004] The system architecture of the quantum bit controller needs to balance among multi-channel integration, control pulse precision and power consumption constraints, wherein the microwave pulse transmitter of the XY channel consumes large power consumption, which restricts the multi-channel integration. The microwave pulse transmitter of the XY channel of the quantum bit controller in the prior art includes a direct up-conversion transmitter, a polar coordinate transmitter, a transmitter based on direct digital frequency synthesis (DDS) and an arbitrary signal generator (AWG) transmitter. However, the direct up-conversion transmitter needs a separate clock line for each quantum bit, the polar coordinate transmitter is not conducive to large-scale integration, and the transmitter based on direct digital frequency synthesis (DDS) and the arbitrary signal generator (AWG) needs a lookup table and a waveform memory, which consumes large area and power consumption. At present, this field still faces many challenges, including extremely multi-channel integration, low-power design and noise suppression. SUMMARY

[0005] The technical problem solved by the present application: In view of the above problems of the prior art, the present application provides an ultra-low temperature quantum controller applied to a low-temperature superconducting quantum computer, which aims to shorten the distance between the controller and the quantum chip, improve the fidelity of the quantum computer and reduce the overhead of quantum error correction.

[0006] In order to solve the above technical problems, the technical scheme adopted by the present application is:

[0007] An ultra-low temperature quantum controller applied to a low-temperature superconducting quantum computer, comprising an analog circuit part and a digital circuit part, the analog circuit part comprising two XY channels and three Z channels, each XY channel comprising two signal paths and an on-chip balun, each signal path comprising a nonlinear digital-to-analog converter NLDAC, an intermediate frequency filter, a variable gain amplifier VGA, a quadrature mixer and a quadrature local oscillator signal generator, the input end of the nonlinear digital-to-analog converter NLDAC being connected to the triangular wave output end of the digital circuit part for outputting a sinusoidal current signal according to the input triangular wave, the input end of the quadrature mixer being further connected to the quadrature local oscillator signal output end of the quadrature local oscillator signal generator, the output ends of the quadrature mixers in the two signal paths of the XY channel being combined through the on-chip balun to generate an XY channel control signal of the XY channel, and each Z channel comprising three independent independently adjustable digital-to-analog converters DAC for generating a Z channel control signal of the three Z channels.

[0008] Optionally, the nonlinear digital-to-analog converter NLDAC comprises a nonlinear coarse adjustment DAC and a linear fine adjustment DAC, the nonlinear coarse adjustment DAC adopts a resistance R1 with an adjustment precision of 8-bit digital control to generate a reference current, the generated reference current enters the drain and gate of a transistor Q1 from the drain and gate of the transistor Q1 of the common source and gate transistors Q1, Q2 and Q3, and is then copied into two paths, and then outputs from the drains of the transistors Q2 and Q3, and then inputs a wide swing common source and gate current mirror composed of transistors Q4, Q5, Q6, Q7, Q8, Q9 and Q10 to drive a coarse adjustment current generation unit with a size of 8*8, the coarse adjustment current generation unit is composed of the transistors Q10 and Q11 in series, the gates of the transistors Q10 and Q11 are connected to the output ends of the common source and gate current mirror respectively, and the current size of the coarse adjustment current generation unit is determined by the size ratio between the transistors Q10 and Q11, each current generation unit generates a current which is switched by a switch S1 to access a main path or a linear fine adjustment DAC, and the main path is switched by a switch S2 to output a positive electrode out_p or a negative electrode out_n; the current input into the linear fine adjustment DAC is first copied into a circuit with a ratio of 1 / 16 by the transistors Q12, Q13 and Q14, and then output to four fine adjustment current generation units each composed of a single transistor Q15, the transistors Q15 of the four fine adjustment current generation units are 1 times, 2 times, 4 times and 8 times respectively, and are connected to corresponding switches S3 to switch output a positive electrode out_p or a negative electrode out_n, so as to combine with the output currents of the positive electrode out_p and the negative electrode out_n of the main path to form a differential current output.

[0009] Optionally, the switches S1-S3 of the nonlinear digital-to-analog converter NLDAC are connected with a digital control array, the digital control array comprises a row binary-to-thermometer encoder, a column binary-to-thermometer encoder and a current matrix unit with a size of 8*8, each current matrix unit stores a signal for controlling the switches S1-S2, 64 current matrix units are divided into a half of a sine wave period to sequentially control the signal of the switches S1-S2 to turn on the coarse adjustment current generation unit to generate a sine wave, the 8th-10th bits din<9:7> of the 10-bit control word of the nonlinear digital-to-analog converter NLDAC are input into the row binary-to-thermometer encoder to generate a row code, the 5th-7th bits din<6:4> are input into the column binary-to-thermometer encoder to generate a column code, the row code and the column code are combined to select a current matrix unit to generate the signal for controlling the switches S1-S2, and the 1st-4th bits din<3:0> of the 10-bit control word of the nonlinear digital-to-analog converter NLDAC generate a signal for controlling the switches S3 to control the fine adjustment current generation unit to generate a subdivided current, and finally combine with the output currents of the positive electrode out_p and the negative electrode out_n of the main path to form a differential current output.

[0010] Optionally, the intermediate frequency filter comprises digital adjustable capacitors C1 and C2 and 8-bit switches S4 and S5, the digital adjustable capacitors C1 and C2 are arranged in parallel between the positive electrode out_p and the negative electrode out_n of the nonlinear digital-to-analog converter NLDAC, the positive electrode out_p of the nonlinear digital-to-analog converter NLDAC is connected with one input terminal of the 8-bit switch S4, the other input terminal of the 8-bit switch S4 is grounded; the negative electrode out_n of the nonlinear digital-to-analog converter NLDAC is connected with one input terminal of the 8-bit switch S5, the other input terminal of the 8-bit switch S5 is grounded; the output terminals of the 8-bit switches S4 and S5 are connected with the input terminals of the adjustable gain amplifier VGA as the positive electrode output and the negative electrode output respectively.

[0011] Optionally, the adjustable gain amplifier VGA comprises transistors Q16 and Q17, digital adjustable capacitors C3-C6, and resistors Rb1 and Rb2; the source electrode of the transistor Q16 is connected with the positive electrode output of the intermediate frequency filter, the source electrode of the transistor Q17 is connected with the negative electrode output of the intermediate frequency filter, the gate electrode of the transistor Q16 is connected with the gate electrode of the transistor Q17 in sequence through the resistors Rb1 and Rb2, so that the transistors Q16 and Q17 constitute a second-order low-pass filter in a common gate configuration, the digital adjustable capacitor C3 is connected in parallel between the drain electrode and the source electrode of the transistor Q16, the digital adjustable capacitor C4 is connected in parallel between the drain electrode and the source electrode of the transistor Q17, the drain electrodes of the transistors Q16 and Q17 are connected through the digital adjustable capacitors C5 and C6, the drain electrode of the transistor Q16 outputs the positive electrode differential current in_p to the quadrature mixer, and the drain electrode of the transistor Q17 outputs the negative electrode differential current in_n to the quadrature mixer.

[0012] Optionally, the quadrature mixer comprises two I-channels and Q-channels, each channel is composed of four transistors Q18-Q21, the source electrodes of the transistors Q18 and Q19 are connected with the positive electrode differential current of the corresponding channel, and the drain electrodes are connected with the primary side of the on-chip balun, the source electrodes of the transistors Q20 and Q21 are connected with the negative electrode differential current of the corresponding channel, and the drain electrodes are connected with the primary side of the on-chip balun, the gate electrode of the transistor Q18 is connected with the voltage V B and the positive local oscillator signal output by the quadrature local oscillator signal generator through the capacitor C7, the gate electrodes of the transistors Q19 and Q20 are connected with each other and connected with the negative local oscillator signal output by the quadrature local oscillator signal generator through the capacitor C8, and the gate electrode of the transistor Q21 is connected with the voltage V B and the positive local oscillator signal output by the quadrature local oscillator signal generator through the capacitor C9.

[0013] Optionally, the on-chip balun is connected with a band-pass filter composed of adjustable capacitors C10 and C11, the adjustable capacitor C10 is connected in parallel with the primary side of the on-chip balun, and the adjustable capacitor C11 is connected in parallel with the secondary side of the on-chip balun.

[0014] Optionally, the quadrature local oscillator signal generator comprises a duty cycle adjustment driver and a frequency division circuit, the duty cycle adjustment driver comprises capacitors C12 and C13, resistors R2 and R3, and transistors Q20-Q23, the 2 times frequency local oscillator signal provided externally is coupled to the gates of transistors Q20 and Q21 through capacitors C12 and C13 respectively, the gate of transistor Q20 is connected to a positive gate voltage V BP through resistor R2, the gate of transistor Q21 is connected to a negative gate voltage V BN through resistor R3, the source of transistor Q20 is connected to a power supply, the source of transistor Q21 is connected to ground, the drains of transistors Q20 and Q21 are connected and connected to the gates of transistors Q22 and Q23 as output terminals, the source of transistor Q22 is connected to a power supply, the source of transistor Q23 is connected to ground, and the drains of transistors Q22 and Q23 are connected and connected to the frequency division circuit as output terminals, the frequency division circuit is composed of two latch circuits in cascade to output two positive local oscillator signals and two negative local oscillator signals.

[0015] Optionally, the positive gate voltage V BP and the negative gate voltage V BN are generated by digital adjustment resistors to adjust the duty cycle of the duty cycle adjustment driver, the control end of the digital adjustment resistor is connected to a control logic, the input end of the control logic is also connected to a comparator, a resistor R4 and a capacitor C14, the output end of the duty cycle adjustment driver is also connected to the input end of the comparator through resistor R4, the input end of the comparator is connected to ground through capacitor C14, and the integrator composed of resistor R4 and capacitor C14 extracts the average value of the duty cycle of the output signal and realizes automatic duty cycle adjustment of the digital adjustment resistor through the comparator and the control logic.

[0016] Optionally, the digital circuit part comprises a digital control oscillator NCO, a phase modulator and a triangular wave generator TRI, which are connected in sequence to generate a triangular wave.

[0017] Compared with the prior art, the super-low-temperature quantum controller has the following beneficial effects: the super-low-temperature quantum controller adopts a single sideband adjustment structure of direct digital frequency synthesis DDS, adopts two-channel phase modulation, and designs a nonlinear digital-to-analog converter NLDAC to realize direct digital frequency synthesis DDS, including two XY channels and three Z channels, compared with the traditional DDS mode, the embodiment does not need a lookup table, reduces the size of the required memory, can shorten the distance between the controller and the quantum chip, improve the fidelity of the quantum computer, and reduce the overhead of quantum error correction. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1Circuit schematic diagram of the ultra-low temperature quantum controller in the embodiment of the present application.

[0019] Figure 2 Circuit schematic diagram of the nonlinear digital-to-analog converter NLDAC in the embodiment of the present application.

[0020] Figure 3 Circuit schematic diagram of the digital control array in the embodiment of the present application.

[0021] Figure 4 Circuit schematic diagram of the intermediate frequency filter and the variable gain amplifier VGA in the embodiment of the present application.

[0022] Figure 5 Circuit schematic diagram of the quadrature mixer and the on-chip balun part in the embodiment of the present application.

[0023] Figure 6 Circuit schematic diagram of the quadrature local oscillator signal generator in the embodiment of the present application.

[0024] Figure 7 Input and output waveform simulation results of the nonlinear digital-to-analog converter NLDAC in the embodiment of the present application, wherein (a) is the input triangular wave and (b) is the output sine wave.

[0025] Figure 8 Output spectrum simulation results of the nonlinear digital-to-analog converter NLDAC in the embodiment of the present application.

[0026] Figure 9 Output single-tone spectrum of the on-chip balun simulation in the embodiment of the present application.

[0027] Figure 10 Circuit schematic diagram of the digital circuit part in the embodiment of the present application.

[0028] Figure 11 Circuit interface schematic diagram of the digital circuit part and the analog circuit part in the embodiment of the present application.

[0029] Figure 12 Circuit schematic diagram of the phase modulator in the embodiment of the present application.

[0030] Figure 13 Multiple pulse test results in the embodiment of the present application. DETAILED DESCRIPTION

[0031] In order to make the person skilled in the art better understand the technical solutions of the present application, the technical solutions of the present application will be further described in detail below in combination with the drawings in the embodiments of the present application.

[0032] As Figure 1As shown, the ultra-low temperature quantum controller applied in the low-temperature superconducting quantum computer of the embodiment comprises an analog circuit part and a digital circuit part, the analog circuit part comprises two XY channels and three Z channels, each XY channel comprises two signal paths and an on-chip balun, each signal path comprises a nonlinear digital-to-analog converter NLDAC, an intermediate frequency filter, a variable gain amplifier VGA, a quadrature mixer and a quadrature local oscillator signal generator, the input end of the nonlinear digital-to-analog converter NLDAC is connected to the triangular wave output end of the digital circuit part to output a sinusoidal wave current signal according to the input triangular wave, the input end of the quadrature mixer is also connected to the quadrature local oscillator signal output end of the quadrature local oscillator signal generator, the outputs of the quadrature mixers in the two signal paths of the XY channel are combined through the on-chip balun to generate an XY channel control signal of the XY channel, and each Z channel comprises three independent independently adjustable digital-to-analog converters DAC to generate a Z channel control signal of the three Z channels.

[0033] The nonlinear digital-to-analog converter NLDAC of the embodiment realizes direct digital frequency synthesis DDS. Figure 2 As shown, the nonlinear digital-to-analog converter NLDAC of the embodiment comprises a nonlinear coarse adjustment DAC and a linear fine adjustment DAC, the nonlinear coarse adjustment DAC adopts a resistance R1 with an adjustment precision of 8-bit digital control to generate a reference current, the generated reference current enters the drain and gate of the transistor Q1 from the drain and gate of the transistors Q1, Q2 and Q3, is copied into two paths after the transistor Q1, and is then output through the drains of the transistors Q2 and Q3, and is then input to a wide-swing common-gate current mirror composed of the transistors Q4, Q5, Q6, Q7, Q8, Q9 and Q10 to drive an 8x8 size coarse adjustment current generation unit, the coarse adjustment current generation unit is composed of the transistors Q10 and Q11 in series, the gates of the transistors Q10 and Q11 are connected to the output ends of the common-gate current mirror respectively, and the current size of the coarse adjustment current generation unit is determined by the size ratio between the transistors Q10 and Q11, and the current generated by each current generation unit is switched to be connected to a main path or a linear fine adjustment DAC by the switch S1, and the output of the main path is switched to be a positive electrode out_p or a negative electrode out_n by the switch S2; the current input to the linear fine adjustment DAC is first copied into 1 / 16 (represented as x16 in the figure) by the transistors Q12, Q13 and Q14, and is then output to four fine adjustment current generation units each composed of a single transistor Q15, the transistors Q15 of the four fine adjustment current generation units are 1 times, 2 times, 4 times and 8 times (represented as x1, x2, x4 and x8 in the figure) respectively and are connected to corresponding switches S3 to switch the output to be a positive electrode out_p or a negative electrode out_n, so that the output currents of the positive electrode out_p and the negative electrode out_n of the main path are combined to form a differential current.

[0034] As shown, the nonlinear digital-to-analog converter NLDAC of the embodiment comprises a nonlinear coarse adjustment DAC and a linear fine adjustment DAC, the nonlinear coarse adjustment DAC adopts a resistance R1 with an adjustment precision of 8-bit digital control to generate a reference current, the generated reference current enters the drain and gate of the transistor Q1 from the drain and gate of the transistors Q1, Q2 and Q3, is copied into two paths after the transistor Q1, and is then output through the drains of the transistors Q2 and Q3, and is then input to a wide-swing common-gate current mirror composed of the transistors Q4, Q5, Q6, Q7, Q8, Q9 and Q10 to drive an 8x8 size coarse adjustment current generation unit, the coarse adjustment current generation unit is composed of the transistors Q10 and Q11 in series, the gates of the transistors Q10 and Q11 are connected to the output ends of the common-gate current mirror respectively, and the current size of the coarse adjustment current generation unit is determined by the size ratio between the transistors Q10 and Q11, and the current generated by each current generation unit is switched to be connected to a main path or a linear fine adjustment DAC by the switch S1, and the output of the main path is switched to be a positive electrode out_p or a negative electrode out_n by the switch S2; the current input to the linear fine adjustment DAC is first copied into 1 / 16 (represented as x16 in the figure) by the transistors Q12, Q13 and Q14, and is then output to four fine adjustment current generation units each composed of a single transistor Q15, the transistors Q15 of the four fine adjustment current generation units are 1 times, 2 times, 4 times and 8 times (represented as x1, x2, x4 and x8 in the figure) respectively and are connected to corresponding switches S3 to switch the output to be a positive electrode out_p or a negative electrode out_n, so that the output currents of the positive electrode out_p and the negative electrode out_n of the main path are combined to form a differential current. Figure 3As shown, the switches S1-S3 of the nonlinear digital-to-analog converter NLDAC of the embodiment are connected with a digital control array, the digital control array includes a row binary-to-thermometer encoder, a column binary-to-thermometer encoder, and 8x8 current matrix units, each current matrix unit stores a signal for controlling the switches S1-S2, and 64 current matrix units are divided into half a sine wave period to sequentially control the signal of the switches S1-S2 to turn on the coarse current generation unit to generate a sine wave, the 8th-10th bits din<9:7> of the 10-bit control word of the nonlinear digital-to-analog converter NLDAC are input into the row binary-to-thermometer encoder to generate row encoding, the 5th-7th bits din<6:4> are input into the column binary-to-thermometer encoder to generate column encoding, the row encoding and the column encoding are combined to select a current matrix unit to generate the signal for controlling the switches S1-S2, and the 1st-4th bits din<3:0> of the 10-bit control word of the nonlinear digital-to-analog converter NLDAC generate a signal for controlling the switches S3 to control the fine current generation unit to generate a subdivided current, and finally the output current of the positive electrode out_p and the negative electrode out_n of the main path is combined to form an output differential current. In the embodiment, 4-bit binary code + 6-bit thermometer code is used for control to achieve 10-bit precision, 6-bit thermometer code is used for coarse adjustment, 8 rows and 8 columns are used for control, and 4-bit binary code is used for fine adjustment, and the sine weight encoding of each current source current matrix unit is used to achieve nonlinear control. In the 8x8 current matrix unit, the current of each unit is a segmented quantized value of a half sine period. For example, in Figure 3 the upper gray current matrix units in the figure are positive current output ends, the white current matrix units switch the current to the negative current output end, the current matrix unit with a value of 24 is copied to the fine adjustment DAC, the switches S3 of the 4-bit linear fine adjustment DAC control 1 / 2, 1 / 4, 1 / 8, and 1 / 16 parts of the current to flow to the positive or negative current output end respectively to achieve linear interpolation. In the embodiment, the nonlinear digital-to-analog converter NLDAC is simulated, the frequency control word used is 1000, the digital input is a triangular wave in the range of 0-1023, the frequency of the output sine wave is 15.3 MHz, the reference current is 1 uA, and the output load is 100 ohms, Figure 7 is the input and output waveform simulation result of the nonlinear digital-to-analog converter NLDAC in the embodiment, wherein (a) is the input triangular wave, and (b) is the output sine wave. Figure 8 is the output spectrum simulation result of the nonlinear digital-to-analog converter NLDAC in the embodiment, the maximum spur in the simulation is the third harmonic, and the spur-free dynamic range SFDR of the output waveform is 52 dB.

[0035] In the embodiment, an intermediate frequency filter based on a current mode common gate configuration amplifier is used to achieve the intermediate frequency filtering function. As shown inFigure 4 As shown, the intermediate frequency filter in this embodiment includes digitally adjustable capacitors C1 and C2, and 8-bit switches S4 and S5. The digitally adjustable capacitors C1 and C2 are connected in parallel between the positive terminal out_p and the negative terminal out_n of the nonlinear digital-to-analog converter NLDAC to further provide filtering effect. The positive terminal out_p of the nonlinear digital-to-analog converter NLDAC is connected to one input terminal of the 8-bit switch S4, and the other input terminal of the 8-bit switch S4 is grounded. The negative terminal out_n of the nonlinear digital-to-analog converter NLDAC is connected to one input terminal of the 8-bit switch S5, and the other input terminal of the 8-bit switch S5 is grounded. The output terminals of the 8-bit switches S4 and S5 are connected to the input terminals of the adjustable gain amplifier VGA as positive and negative outputs, respectively.

[0036] like Figure 4 As shown, the adjustable gain amplifier VGA in this embodiment includes transistors Q16 and Q17, digitally adjustable capacitors C3 to C6, and resistors Rb1 and Rb2. The source of transistor Q16 is connected to the positive output of the intermediate frequency filter, and the source of transistor Q17 is connected to the negative output of the intermediate frequency filter. The gate of transistor Q16 is connected to the gate of Q17 in sequence through resistors Rb1 and Rb2 so that transistors Q16 and Q17 form a second-order low-pass filter in a common-gate configuration. A digitally adjustable capacitor C3 is connected in parallel between the drain and source of transistor Q16, and a digitally adjustable capacitor C4 is connected in parallel between the drain and source of transistor Q17. The drains of transistors Q16 and Q17 are connected through digitally adjustable capacitors C5 and C6. The drain of transistor Q16 is output as the positive differential current in_p, and the drain of transistor Q17 is output as the negative differential current in_n.

[0037] This embodiment employs an adjustable bias voltage quadrature mixer, which can adjust the bias to balance harmonics and achieve single-ended output and impedance matching through an on-chip balun at the output. Figure 5 As shown, the quadrature mixer includes two quadrature channels: an I-channel and a Q-channel. Each channel consists of four transistors Q18 to Q21. The sources of transistors Q18 and Q19 are connected to the positive differential current of the corresponding channel, and their drains are connected to the primary side of the on-chip balun. The sources of transistors Q20 and Q21 are connected to the negative differential current of the corresponding channel, and their drains are connected to the primary side of the on-chip balun. The gate connection voltage of transistor Q18 is V. B It is connected to the positive local oscillator signal output by the quadrature local oscillator signal generator through capacitor C7. The gates of transistors Q19 and Q20 are interconnected and connected to the negative local oscillator signal output by the quadrature local oscillator signal generator through capacitor C8. The gate connection voltage of transistor Q21 is V. B It is connected to the positive local oscillator signal output by the quadrature local oscillator signal generator through capacitor C9. Figure 5 middle, and respectively represent the positive and negative differential currents of the I-channel, and respectively represent the positive and negative differential currents of the Q-channel. The voltage V B The problem of the increase of the switching threshold voltage at low temperature can be solved by adjusting the bias voltage through digital control.

[0038] As shown in Figure 5 , the two outputs of the quadrature mixer are combined and converted from differential to single-ended through an on-chip balun. The on-chip balun is a kind of balanced-unbalanced converter integrated in a semiconductor chip, which is widely used in the fields of RF integrated circuit, wireless communication, microwave system, etc. The on-chip balun in the embodiment is a transformer balun. The on-chip balun is connected with a band-pass filter composed of adjustable capacitors C10 and C11. The adjustable capacitor C10 is connected in parallel to the primary side of the on-chip balun, and the adjustable capacitor C11 is connected in parallel to the secondary side of the on-chip balun. The DC path is provided by the center tap of the primary side of the on-chip balun. The on-chip balun provides the DC path, provides the load at high frequency, filters the high harmonic components of the local oscillator, and realizes the conversion from differential to single-ended. The on-chip balun adopts a planar structure, uses top layer super-thick metal winding, and superimposes thick metal layer to improve the quality factor of the winding. The primary side coil is 2 turns, and the secondary side coil is 1 turn. The AP layer and the thick metal layer are used to realize the cross connection and the center tap. The line width is 9um, the line spacing is 3um, the inner diameter is 183um, and the outer part includes a ground isolation ring. At a frequency of 5GHz, the quality factor of the primary side coil of the on-chip balun is 15.3, the quality factor of the secondary side coil is 7.4, the inductance value of the primary side coil is 1.47nH, the inductance value of the secondary side coil is 0.43nH, the coupling coefficient is 0.73, and the self-resonance frequency is 12GHz. The resonance capacitors C10 and C11 of the primary side coil and the secondary side coil can be digitally controlled and adjusted, so that the output signal frequency point is a real impedance. Figure 9 is the output single tone spectrum of the on-chip balun simulation in the embodiment of the present application, as shown in Figure 9 , it can be seen that the spurious signals are suppressed, and the spurious-free dynamic range SFDR of the output is less than 40dB.

[0039] The local oscillator signal in the embodiment is realized through a quadrature local oscillator signal generator. The quadrature local oscillator signal generator can realize the conversion from a single-ended clock signal to a four-phase quadrature signal, and can balance the harmonics by adjusting the duty cycle of the quadrature signal. As shown in Figure 6 , the quadrature local oscillator signal generator in the embodiment includes a duty cycle adjustment driver and a frequency division by two circuit. The duty cycle adjustment driver includes capacitors C12 and C13, resistors R2 and R3, and transistors Q20-Q23. The externally provided local oscillator signal with frequency of 2fLO The gate of transistor Q20 is connected to a positive gate voltage V BP through resistor R2, and the gate of transistor Q21 is connected to a negative gate voltage V BN through resistor R3. The source of transistor Q20 is connected to a power supply, the source of transistor Q21 is connected to ground, the drains of transistors Q20 and Q21 are connected together and connected as an output terminal to the gates of transistors Q22 and Q23, the source of transistor Q22 is connected to a power supply, the source of transistor Q23 is connected to ground, the drains of transistors Q22 and Q23 are connected together and connected as an output terminal (the frequency of the output is 2f LO ) to a frequency dividing circuit, and the frequency dividing circuit is composed of two latches connected in series to output two positive local oscillator signals and two negative local oscillator signals (the frequency is f LO ). The frequency dividing circuit is composed of two latches connected in series, and by adjusting the duty cycle, the problem of local oscillator IQ phase imbalance can be effectively solved.

[0040] As shown in Figure 6 , the positive gate voltage V BP and the negative gate voltage V BN in the embodiment are generated by digital adjusting resistors to adjust the duty cycle of the driver, the control end of the digital adjusting resistor is connected to a control logic, the input end of the control logic is also connected to a comparator, a resistor R4 and a capacitor C14, the output end of the duty cycle adjusting driver is also connected to the input end of the comparator through the resistor R4, the input end of the comparator is connected to ground through the capacitor C14, and the integrator composed of the resistor R4 and the capacitor C14 extracts the average value of the duty cycle of the output signal and realizes automatic duty cycle adjustment of the digital adjusting resistor through the comparator and the control logic.

[0041] As shown in Figure 1 , the digital circuit part in the embodiment includes a digital control oscillator NCO, a phase modulator and a triangular wave generator TRI, and the digital control oscillator NCO, the phase modulator and the triangular wave generator TRI are connected in sequence to generate a triangular wave.

[0042] As shown in Figure 1 , Figure 10 and Figure 11As shown, the digital circuit part in the embodiment is based on DDS architecture, including an SPI module, a main controller, an instruction memory, a parameter memory, a current DAC memory and a waveform memory. The SPI module is responsible for memory data writing and parameter configuration, and the controller is responsible for instruction decoding and waveform playing control. The clock of the digital circuit is inputted from outside. The quadrature intermediate frequency sinusoidal signal is generated based on the DDS mode, through a digital controlled oscillator NCO and a phase modulator to generate a triangular wave through a nonlinear digital-to-analog converter NLDAC. Compared with the traditional DDS mode, the embodiment does not need a lookup table, reducing the size of the required memory. The output waveform of the embodiment is adjusted through the adjustable gain amplifier of the analog circuit part, avoiding the multiplication operation of the digital part. The architecture can also generate a DRAG waveform, which is decomposed into amplitude and phase waveforms based on the polar coordinate mode, and the phase waveform is added through the digital circuit part. Therefore, the structure does not increase the size of the analog circuit and the data bit width of the digital circuit, which is beneficial to reduce power consumption and area. The main controller and the waveform memory are connected with the DDS controller channel 1 and the DDS controller channel 2 respectively, to control the two orthogonal channels of I-channel and Q-channel. The current DAC memory is connected with the analog circuit part through the current DAC controller channel 1-current DAC controller channel 3, to control three independent and independently adjustable digital-to-analog converters DAC of the three Z channels. In the embodiment, the instruction memory is 256x22b in size, the instruction memory address line width is 8 bits, 256 instructions can be stored, and each instruction is 22 bits long, including the parameter memory addresses of the two XY channels, the address line width is 4 bits, the enable signals of the two XY channels, the IDAC memory addresses of the three Z channels, and the address line width is 4 bits. The parameter memory is 16x56b in size, the parameter memory address line width is 4 bits, 16 groups of parameters can be stored, each group of parameters includes a 16-bit frequency control word, a 16-bit initial phase, a 1-bit sideband selection, an 8-bit waveform memory initial address, a 3-bit idle period number, an 8-bit waveform playing period number and a 4-bit frequency divider upper limit. A total of 56 bits. The sideband selection is to select the upper sideband or the lower sideband, the idle period number is the number of periods needed to delay before playing the waveform, and the waveform playing period number is the waveform length. If the clock frequency is 1GHz and the period is 1ns, the waveform period number is 30, then from the waveform memory, 30 waveform data are played, and the pulse length is 30ns. The frequency divider can extend the waveform period time, if the parameter is set to 5, the above pulse length can be changed from 30ns to 150ns. The waveform memory is 256x16b in size, the waveform memory address line width is 8 bits, 255 waveform data can be stored, and each data includes 8 bits of amplitude and 8 bits of phase.The current DAC memory is 16*22b in size, the IDAC memory address line width is 8 bits, 16 groups of parameters can be stored, each group of parameters includes 10-bit current DAC control word, 8-bit current duration period and 4-bit frequency divider upper limit. The required memory size of the above-mentioned memory in the embodiment is 10976 bits, which has the advantage of small storage capacity.

[0043] The structure of the phase modulator in the embodiment is shown in Figure 12 The phase modulator is used for generating control signals for the nonlinear digital-to-analog converter NLDAC, and the phase modulator is composed of a phase accumulator, a phase adder and a triangular wave generator. The phase modulator mainly realizes phase accumulation and generates a triangular wave control signal to control the nonlinear digital-to-analog converter NLDAC, so that the nonlinear digital-to-analog converter NLDAC can generate an arbitrary decimal intermediate frequency signal. At the same time, the phase modulator can set the initial phase to realize the orthogonal intermediate frequency output. The input control word is a 16-bit frequency control word, and the intermediate frequency output frequency is f IF =F CW × f CLK / 2 b , wherein F CW is a frequency control word, f CLK is a digital clock, and b is the bit width of the DDS accumulator, so the frequency control accuracy is ∆ f IF = f CLK / 2 b . When the digital clock f CLK is 1GHz, the frequency accuracy corresponding to 16 bits is 15.26kHz, and when it is 2GHz, the frequency accuracy corresponding to 16 bits is 30.52kHz, which meets the requirements of the quantum controller. The phase accumulation is a two-stage structure, and in two clock periods, the phase is added through two 8-bit full adders, which is beneficial to high-speed operation compared with a 16-bit full adder. The phase adder also operates, and the phase of the accumulator is sequentially added to the 16-bit initial phase and the 8-bit phase control word. The I-path and the Q-path are realized by different initial phases, and the phase control word is constant in the conventional waveform generation mode and is variable in the DRAG waveform generation. The triangular wave generator obtains the highest bit and each bit by taking exclusive OR operation in sequence. Finally, the first 10 bits are intercepted and output, and the encoder sequentially outputs the coarse adjustment row control word and the fine adjustment control word required by the nonlinear digital-to-analog converter NLDAC.

[0044] In the embodiment, pulse test results of square wave, raised cosine and DRAG waveforms are respectively carried out. When the square wave pulse test is carried out, the local oscillator frequency of the pulse is f LOis 5.1 GHz, intermediate frequency f IF is 125 MHz, output frequency is f LO − f IF is 4.975 GHz, pulse width is 10 ns. Pay attention to the frequency range, which is usually 150 MHz to 300 MHz smaller than the frequency of the qubit, where represents the process by which a quantum system transitions from a low energy level state ( ) to a high energy level state ( ), which usually requires an external energy input (such as photon irradiation, electric field or magnetic field action, etc.) to make the system absorb energy and change. The suppression ratio of the tested square wave pulse spectrum at -150 MHz is 18.4 dB, at -200 MHz is 23.4 dB, at -2500 MHz is 23.1 dB, and at -300 MHz is 24.7 dB. The left side lobe is outside the band of the low-pass filter, so it is suppressed to a certain extent, with a lower amplitude than the right side lobe. The average suppression ratio in the range of -300 MHz to -150 MHz is 23.52 dB. The suppression ratio of the tested raised cosine pulse spectrum at -150 MHz is 17.9 dB, at -200 MHz is 25.8 dB, at -250 MHz is 29.4 dB, and at -300 MHz is 26.8 dB. Compared with the spectrum of the square wave, the energy is more concentrated and the side lobe amplitude is lower. The average suppression ratio in the range of -300 MHz to -150 MHz is 26.28 dB. The suppression ratio of the tested DRAG pulse spectrum at -150 MHz is 21.7 dB, at -200 MHz is 28.4 dB, at -250 MHz is 29.9 dB, and at -300 MHz is 29.8 dB. Compared with the spectrum of the raised cosine pulse, the amplitude on the left side is suppressed to a certain extent. The average suppression ratio in the range of -300 MHz to -150 MHz is 28.34 dB. The pulse test results of the square wave, raised cosine and DRAG waveforms are compared as Figure 13 shown. Normalize the amplitude of the spectrum to obtain the normalized spectrum. From Figure 13 it can be seen that in the spectrum range of -150 MHz to -300 MHz, for the square wave pulse, raised cosine to DRAG pulse, the amplitude decreases in turn, and the average suppression ratios are 23.52 dB, 26.28 dB and 28.34 dB. The DRAG pulse has a 2 dB increase compared with the raised cosine and a 4.8 dB increase compared with the square wave pulse. Therefore, the DRAG pulse generated by the ultra-low temperature quantum controller in this embodiment is beneficial to suppressing excitation. [[ID=The ultra-low temperature quantum controller of the embodiment is tested for power consumption, with a power supply voltage of 1.0 V and a clock of 1 GHz for the digital circuit. The power consumption of the XY channel is 2.87 mW, the power consumption of the Z channel is 0.45 mW, the power consumption of the local oscillator frequency division module is 1.449 mW, the digital power consumption is 17.6 mW, and the total power consumption is 26.2 mW. In the XY channel, the power consumption of the DDS is 1.3 mW, the power consumption of the DC channel of the transformer is 1.3 mW, and the power consumption of the amplitude modulator is 0.27 mW. The analog power consumption of each XY channel is 2.87 mW, the digital power consumption is about 8.8 mW, and the total power consumption of each XY channel is about 11.67 mW, excluding the Z channel.

[0046] The performance comparison of the ultra-low temperature quantum controller of the embodiment and other existing quantum controllers (ISSCC'23, ISSCC'22, ISSCC'20 and ISSCC'19) is shown in Table 1.

[0047] Table 1: Performance comparison table of the ultra-low temperature quantum controller of the embodiment and other existing quantum controllers

[0048]

[0049] As can be seen from Table 1, the ultra-low temperature quantum controller of the embodiment supports a range of 4-6 GHz superconducting quantum bit control, the DAC resolution of pulse generation reaches 10 bits, and the sampling rate is greater than 1 GS / s. The output power is -20 dBm, the SFDR of the single tone is greater than -40 dB, the fidelity of the controlled target reaches 99.9%, and DRAG pulse generation is supported. The power consumption of each channel is 11.67 mW, of which the analog power consumption is 2.87 mW, and the area of each channel is 0.2 mm2. The power consumption of ISSCC'19 is within 2 mW, and a direct up-conversion structure is used, so the local oscillator of each channel needs to be externally provided, and therefore the number of cables cannot be reduced, which is not conducive to subsequent multi-channel integration. Compared with ISSCC'23, ISSCC'22 and ISSCC'20, the DAC indicators also reach the same level, the SFDR meets the requirements of the quantum controller, the single sideband architecture is more suitable for multi-channel integration, the power consumption and area of each channel are more optimal, and the ultra-low temperature quantum controller of the embodiment also supports DRAG pulse.

[0050] To sum up, for the application of superconducting quantum computing, the superconducting quantum controller of the embodiment is designed, which contains 2-channel XY control and 3-channel Z channel control, and the digital circuit supports the generation of multiple instructions and pulses. In view of the problem of high power consumption of quantum bit control, the superconducting quantum controller of the embodiment adopts current multiplexing technology, and the intermediate frequency filter and the variable gain controller VGA adopt current mode, thereby reducing the power consumption of the analog circuit. The nonlinear digital-to-analog converter NLDAC and the current source controlled by the switch array are adopted, the lookup table is removed, the area is reduced, and the power consumption is also reduced. The amplitude and phase modulation mode is adopted, the DRAG waveform is supported, and a quadrature modulation circuit is not needed, thereby reducing the area and power consumption. In addition, the single sideband structure is adopted for the XY channel, multiple channels can share one local oscillator module, multiple quantum bit control frequency division multiple access modes can be compatible, and multi-channel integration is beneficial. In view of the problem of large change of threshold voltage of the transistor in the low-temperature use scene, the superconducting quantum controller of the embodiment adopts a more stable bias current generation mode, and a local oscillator duty cycle calibration module and an adjustable bias mixer structure are designed. Test results show that the superconducting quantum controller of the embodiment has an SFDR of greater than-40 dB for outputting a single tone, the area of each channel is only 0.2mm 2 , and the power consumption of each channel is 11.67mW, of which the analog power consumption is only 2.87mW, so that the distance between the controller and the quantum chip can be shortened, the fidelity of the quantum computer can be improved, and the overhead of quantum error correction can be reduced.

[0051] The above only describes the preferred embodiments of the present application, and the protection scope of the present application is not limited to the above-mentioned embodiments. Any technical solutions falling within the concept of the present application shall be considered as falling within the protection scope of the present application. It should be noted that, for ordinary skilled persons in the art, some improvements and refinements without departing from the principles of the present application shall also be considered as falling within the protection scope of the present application.

Claims

1. A cryogenic quantum controller for use in cryogenic superconducting quantum computers, characterized in that, The analog circuit part includes two XY channels and three Z channels, each XY channel includes two signal paths and an on-chip balun, each signal path includes a nonlinear digital-to-analog converter, an intermediate frequency filter, an adjustable gain amplifier, a quadrature mixer and a quadrature local oscillator signal generator, the input of the nonlinear digital-to-analog converter is connected to the triangular wave output of the digital circuit part for outputting a sine wave current signal according to the input triangular wave, the input of the quadrature mixer is also connected to the quadrature local oscillator signal output of the quadrature local oscillator signal generator, the outputs of the quadrature mixers in the two signal paths of the XY channel are combined through the on-chip balun to generate an XY channel control signal of the XY channel, and the three Z channels each include three independent independently adjustable digital-to-analog converters for generating Z channel control signals of the three Z channels.

2. The ultra-low temperature quantum controller for use in a low temperature superconducting quantum computer of claim 1, wherein, The nonlinear digital-to-analog converter includes a nonlinear coarse adjustment DAC and a linear fine adjustment DAC, the nonlinear coarse adjustment DAC adopts a resistance (R1) with an 8-bit digital control adjustment precision to generate a reference current, the generated reference current enters the drain and gate of a transistor (Q1) from the gates of transistors (Q1), (Q2) and (Q3), is copied into two paths, and is then output through the drains of transistors (Q2) and (Q3) and then input to a wide-swing cascode current mirror composed of transistors (Q4), (Q5), (Q6), (Q7), (Q8), (Q9) and (Q10) to drive an 8x8 size coarse adjustment current generating unit, the coarse adjustment current generating unit is composed of transistors (Q10) and (Q11) in series, the gates of the transistors are connected to the outputs of the cascode current mirror respectively, and the current size of the coarse adjustment current generating unit is determined by the size ratio between the transistors (Q10) and (Q11), the current generated by each current generating unit is switched to be input to a main path or a linear fine adjustment DAC by a switch (S1), and the output of the main path is switched to be a positive electrode (out_p) or a negative electrode (out_n) by a switch (S2); the current input to the linear fine adjustment DAC is first copied into a 1 / 16 circuit by transistors (Q12), (Q13) and (Q14) and then output to four fine adjustment current generating units each composed of a single transistor (Q15), the transistors (Q15) of the four fine adjustment current generating units are 1 times, 2 times, 4 times and 8 times respectively and are connected to corresponding switches (S3) to switch the output to be a positive electrode (out_p) or a negative electrode (out_n), so that the output currents of the positive electrode (out_p) and the negative electrode (out_n) of the main path are combined to form a differential current.

3. The ultra-low temperature quantum controller for use in a low temperature superconducting quantum computer of claim 2, wherein, The switch (S1)~switch (S3) of the nonlinear digital-to-analog converter is connected with a digital control array, the digital control array includes a row binary-to-thermometer encoder, a column binary-to-thermometer encoder and 8*8 size current matrix units, each current matrix unit stores a signal for controlling the switch (S1)~switch (S2), 64 current matrix units are divided into half a sine wave period to sequentially control the signal of the switch (S1)~switch (S2) to turn on a coarse adjustment current generating unit to generate a sine wave, the 8th~10th bits of a 10-bit control word of the nonlinear digital-to-analog converter are input into the row binary-to-thermometer encoder to generate a row code, the 5th~7th bits are input into the column binary-to-thermometer encoder to generate a column code, the row code and the column code are combined to select a current matrix unit to generate a signal for controlling the switch (S1)~switch (S2), the 1st~4th bits of the 10-bit control word of the nonlinear digital-to-analog converter generate a signal for controlling the switch (S3) to control a fine adjustment current generating unit to generate a subdivided current, and finally the output current of the positive electrode (out_p) and the negative electrode (out_n) of the main path is combined to form an output differential current.

4. The ultra-low temperature quantum controller for use in a low temperature superconducting quantum computer of claim 1, wherein, The intermediate frequency filter includes digital adjustable capacitors (C1) and (C2) and 8-bit switches (S4) and (S5), the digital adjustable capacitors (C1) and (C2) are arranged in parallel between the positive electrode (out_p) and the negative electrode (out_n) of the nonlinear digital-to-analog converter, the positive electrode (out_p) of the nonlinear digital-to-analog converter is connected with one input end of the 8-bit switch (S4), and the other input end of the 8-bit switch (S4) is grounded; the negative electrode (out_n) of the nonlinear digital-to-analog converter is connected with one input end of the 8-bit switch (S5), and the other input end of the 8-bit switch (S5) is grounded; the output ends of the 8-bit switches (S4) and (S5) are connected with the input ends of the adjustable gain amplifier as the positive electrode output and the negative electrode output respectively.

5. The ultra-low temperature quantum controller for use in a low temperature superconducting quantum computer of claim 4, wherein, The adjustable gain amplifier includes transistors (Q16) and (Q17), digital adjustable capacitors (C3)~(C6), and resistors (Rb1) and (Rb2); The source of the transistor (Q16) is connected with the positive electrode output of the intermediate frequency filter, the source of the transistor (Q17) is connected with the negative electrode output of the intermediate frequency filter, the gate of the transistor (Q16) is connected with the gate of the transistor (Q17) through the resistors (Rb1) and (Rb2) in sequence to make the transistors (Q16) and (Q17) form a second-order low-pass filter in a common gate configuration, the digital adjustable capacitor (C3) is connected in parallel between the drain and the source of the transistor (Q16), the digital adjustable capacitor (C4) is connected in parallel between the drain and the source of the transistor (Q17), the drains of the transistors (Q16) and (Q17) are connected through the digital adjustable capacitors (C5) and (C6), the drain of the transistor (Q16) outputs a positive differential current (in_p) to the quadrature mixer, and the drain of the transistor (Q17) outputs a negative differential current (in_n) to the quadrature mixer.

6. The ultra-low temperature quantum controller for use in a low temperature superconducting quantum computer of claim 1, wherein, The quadrature mixer comprises two I-channel and Q-channel paths, each path comprising four transistors (Q18)-(Q21), the sources of the transistors (Q18) and (Q19) being connected to the positive differential current of the corresponding path, the drains being connected to the primary side of the on-chip balun, the sources of the transistors (Q20) and (Q21) being connected to the negative differential current of the corresponding path, the drains being connected to the primary side of the on-chip balun, the gate of the transistor (Q18) being connected to the voltage (V B ) and via a capacitor (C7) to the positive local oscillator signal output by the quadrature local oscillator signal generator, the gates of the transistors (Q19) and (Q20) being connected to each other and via a capacitor (C8) to the negative local oscillator signal output by the quadrature local oscillator signal generator, the gate of the transistor (Q21) being connected to the voltage (V B ) and via a capacitor (C9) to the positive local oscillator signal output by the quadrature local oscillator signal generator.

7. The ultra-low temperature quantum controller for use in a low temperature superconducting quantum computer of claim 1, wherein, The on-chip balun is connected with a band-pass filter composed of adjustable capacitors (C10) and (C11), the adjustable capacitor (C10) is connected in parallel to the primary side of the on-chip balun, and the adjustable capacitor (C11) is connected in parallel to the secondary side of the on-chip balun.

8. The ultra-low temperature quantum controller for use in a low temperature superconducting quantum computer of claim 1, wherein, The quadrature local oscillator signal generator comprises a duty cycle adjustment driver and a frequency division by two circuit. The duty cycle adjustment driver comprises capacitors (C12) and (C13), resistors (R2) and (R3), and transistors (Q20)-(Q23). A 2 times frequency local oscillator signal provided externally is coupled to the gates of transistors (Q20) and (Q21) through capacitors (C12) and (C13) respectively. The gate of transistor (Q20) is connected to a positive gate voltage (V BP ) through resistor (R2), the gate of transistor (Q21) is connected to a negative gate voltage (V BN ) through resistor (R3), the source of transistor (Q20) is connected to a power supply, the source of transistor (Q21) is connected to ground, the drains of transistors (Q20) and (Q21) are connected together and connected as an output terminal to the gates of transistors (Q22) and (Q23), the source of transistor (Q22) is connected to the power supply, the source of transistor (Q23) is connected to ground, the drains of transistors (Q22) and (Q23) are connected together and connected as an output terminal to the frequency division by two circuit. The frequency division by two circuit is composed of two latches connected in cascade to output two positive local oscillator signals and two negative local oscillator signals.

9. The ultra-low temperature quantum controller for use in a low temperature superconducting quantum computer of claim 8, wherein, The positive gate voltage (V BP ) and negative gate voltage (V BN ) are generated by digital regulating resistance to regulate the duty cycle of the duty cycle regulating driver, the control end of the digital regulating resistance is connected with a control logic, the input end of the control logic is also connected with a comparator, a resistance (R4) and a capacitor (C14), the output end of the duty cycle regulating driver is also connected to the input end of the comparator through the resistance (R4), the input end of the comparator is grounded through the capacitor (C14), the integrator composed of the resistance (R4) and the capacitor (C14) extracts the average value of the output signal duty cycle, and the automatic duty cycle regulation of the digital regulating resistance is realized through the comparator and the control logic.

10. The ultra-low temperature quantum controller for use in a low temperature superconducting quantum computer of claim 1, wherein, The digital circuit part comprises a digitally controlled oscillator, a phase modulator and a triangular wave generator, which are sequentially connected to generate a triangular wave.

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