Shaped die for semiconductor package
By shaping the die to reduce its base surface and increase its top surface, the inventory complexity problem caused by different die pad sizes is solved, and larger dies can be accommodated in smaller interconnects, simplifying manufacturing and reducing costs.
Patent Information
- Application Number
- CN202510331918.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-03-29
- Filing Date
- 2025-03-20
- Publication Date
- 2025-09-30
AI Technical Summary
In the prior art, since different sizes of die attach pads require different interconnects, inventory complexity increases and manufacturing processes become complicated, making it difficult to effectively package integrated circuits in a limited physical space.
By shaping the die to reduce its base surface area and increase its top surface area, it can be mounted on smaller interconnect pads, electrically connected through bonding layers and leads, and finally encapsulated with molding compound, simplifying the manufacturing process.
This allows larger dies to be accommodated in smaller interconnects, reducing inventory complexity, simplifying the manufacturing process, and lowering manufacturing costs.
Smart Images
Figure CN120727686A_ABST
Abstract
Description
Technical Field
[0001] The present description relates to a semiconductor package having a die formed to have a base surface that is smaller than a top surface. Background Art
[0002] A wide range of electronic devices, such as cell phones, digital cameras, and music players, are packing more integrated circuits into ever-shrinking physical spaces, with the desire to reduce costs. Integrated circuits used in a variety of electronic devices are typically manufactured on semiconductor wafers. For example, the die of a semiconductor wafer is processed and packaged, and then attached to the die attach pads of an interconnect. However, devices in the same package group may have a variety of die of different sizes. Consequently, a corresponding variety of interconnects with die attach pads of varying sizes are maintained in inventory to accommodate the variety of die. Summary of the Invention
[0003] A first example relates to a device comprising a die attach pad and a die. The die attach pad has a surface area. The die includes a substrate surface mounted within the surface area of the die attach pad. The die also includes a top surface opposite the substrate surface. The top surface is larger than the substrate surface.
[0004] A second example relates to a method for forming an integrated circuit (IC) package. The method includes providing a semiconductor wafer having a first surface and a second surface opposite the first surface. The method also includes etching a plurality of voids in the first surface of the semiconductor wafer to a first depth. The method further includes attaching the first surface of the semiconductor wafer to a dicing tape. The method further includes dicing the semiconductor wafer to form a plurality of dies. A die in the plurality of dies has a base surface and a top surface opposite the base surface. The top surface has a larger surface area than the base surface. The method includes mounting the die to die attach pads. The method also includes singulating the mounted die.
[0005] A third example relates to an IC package. The IC package includes a die attach pad having a surface area. The IC package also includes leads separated from the die attach pad. The IC package further includes a die having a base surface mounted within the surface area of the die attach pad and a top surface opposite the base surface. The top surface is larger than the base surface. The IC package further includes bonding wires attached to the die and the leads. The IC package includes a molding compound encapsulating the bonding wires, leads, die, and die attach pad. BRIEF DESCRIPTION OF THE DRAWINGS
[0006] Figure 1A Illustrated is a cross-sectional view of an example of a semiconductor device having a shaped die.
[0007] Figure 1B illustrate Figure 1AA top-down view of an example of a semiconductor device.
[0008] Figure 1C A cross-sectional view illustrating an alternative example of a semiconductor device having a shaped die.
[0009] Figure 2A One example of a shaped die having a T-shape is illustrated.
[0010] Figure 2B Another example of a shaped die having a trapezoidal shape is illustrated.
[0011] Figure 3 A flow chart illustrating an example method for forming a semiconductor device including a shaped die.
[0012] Figure 4 An example of the first stage of a method for forming a semiconductor device is described.
[0013] Figure 5 An example of the second stage of the method for forming a semiconductor device is described.
[0014] Figure 6 An example of the third stage of the method for forming a semiconductor device is described.
[0015] Figure 7 An example of the fourth stage of the method for forming a semiconductor device is described.
[0016] Figure 8 An example of the fifth stage of the method for forming a semiconductor device is described.
[0017] Figure 9 An example of the sixth stage of the method for forming a semiconductor device is described.
[0018] Figure 10 An example of the seventh stage of the method for forming a semiconductor device is described.
[0019] Figure 11 An example of the eighth stage of the method for forming a semiconductor device is described.
[0020] Figure 12 An example of a ninth stage of the method for forming a semiconductor device is described.
[0021] Figure 13 An example of the tenth stage of the method for forming a semiconductor device is described.
[0022] Figure 14 An example of the eleventh stage of the method for forming a semiconductor device is described. DETAILED DESCRIPTION
[0023] Semiconductor devices include multiple semiconductor components, such as semiconductor dies. A variety of interconnects are maintained in inventory to accommodate the diversity of die sizes. For example, some dies in a package group have smaller sizes accommodated by a first interconnect with smaller die attach pads, while other dies in the package group have larger sizes accommodated by a second interconnect with larger die attach pads. Given the push for miniaturization of electronic devices, first interconnects are maintained in inventory to create a smaller device footprint, and second interconnects are maintained in inventory to accommodate dies with larger footprints. Keeping different interconnects in inventory complicates manufacturing and reduces interconnect sharing and consolidation within and across package groups.
[0024] In the semiconductor devices and methods described herein, a die is shaped to create a substrate surface with a smaller die footprint so that the shaped die can be mounted to the smaller die attach pads of an interconnect. For example, plasma etching is used to etch the die so that it has a substrate surface that fits within the surface area of the die attach pads. The top surface of the die, which is opposite the substrate surface, has a surface area that is larger than the substrate surface area. The size of the die can be increased by approximately sixty-five percent and still fit in an interconnect with a smaller die attach pad. Continuing with the above example, even if the top surface is larger than the die attach pad of the first interconnect, the shaped die is accommodated by the first interconnect, rather than requiring a second interconnect. Thus, the shaped die facilitates interconnect sharing, reduces inventory complexity, and simplifies the manufacture of semiconductor devices, thereby reducing manufacturing costs.
[0025] Figure 1A A cross-sectional view illustrating an example of a semiconductor device having a formed die. Semiconductor device 100 includes a die attach pad 102 and a plurality of leads 104 formed of interconnects. The interconnects are formed of a conductive material such as copper, palladium, gold, silver, or other suitable conductive metals or metal alloys having similar properties. For example, the interconnects are formed of a thin sheet of copper.
[0026] A bonding layer 106 bonds the die 108 to the die attach pad 102. The bonding layer 106 is, for example, a film-like adhesive such as an epoxy. Bonding wires 110 are attached to the die 108 and the leads 104 and form an electrical connection between the die 108 and the leads 104. The die attach pad 102, the one or more leads 104, the bonding layer 106, the die 108, and the one or more bonding wires are at least partially encapsulated in a mold compound 112 to form a packaged semiconductor device 100, such as an integrated circuit (IC) or a system on a chip (SOC). The mold compound 112 is formed from one or more insulating materials, such as an organic resin (e.g., an epoxy resin), an inorganic resin, and / or other suitable materials.
[0027] In some examples, the interconnect includes an angled portion that separates horizontal sections corresponding to the die attach pad 102 and the one or more leads 104. For example, a first plane extends through and defines a surface area 114 of the die attach pad 102. A second plane extends through and defines a bonding surface 116 for the one or more leads 104. The first plane is substantially parallel to the second plane and is separated by a vertical distance 118. The vertical distance 118 is caused by the angled portion of the interconnect. The die attach pad 102 is vertically lower than the one or more leads 104 by the vertical distance 118, such that the die attach pad 102 is inset relative to the one or more leads 104.
[0028] One or more leads 104 are laterally separated from the die attach pad 102 by a gap distance 124. For example, the proximal lead edge 120 is the surface of the lead 104 proximal to the die attach pad 102. The proximal pad edge 122 is the surface of the die attach pad 102 proximal to the lead 104. The proximal pad edge 122 defines an edge plane that includes the surface of the die attach pad 102 proximal to the lead 104. The proximal lead edge 120 and the proximal pad edge 122 are separated by a gap distance 124.
[0029] A die edge 126 of the die 108 separates a base surface 128 of the die 108 from a top surface 130 of the die 108. The die edge 126 is the surface of the die 108 proximate to one or more leads 104. The base surface 128 is attached to the surface area 114 of the die attach pad 102. The top surface 130 is larger than the base surface 128 of the die 108. The die edge 126 extends to an edge plane proximate to the pad edge 122 or beyond the edge plane into the gap distance 124. Thus, the die edge 126 of the die 108 is as laterally close to the leads 104 as the die attach pad 102 or closer to the leads. Thus, the top surface 130 of the die 108 extends to or beyond the edge plane.
[0030] Steering Figure 1B , a plurality of leads 104 may be disposed around (e.g., surrounding) the die attach pad 102. Bonding wires 110 provide electrical connections between the die 108 and a given lead 104. During packaging, the semiconductor device 100 is singulated, such that the leads 104 form leads exposed to the external environment. The leads of the singulated semiconductor device 100 enable the die 108 to be electrically coupled to one or more other electrical components external to the semiconductor device 100.
[0031] The surface area 114 of the die attach pad 102 has a die attach pad perimeter 132. The base surface 128 of the die 108 fits within the die attach pad perimeter 132 of the surface area 114, while the top surface 130 of the die 108 extends beyond the die attach pad perimeter 132. For example, the base surface 128 has a base perimeter 134, and the top surface 130 has a top perimeter 136. The base perimeter 134 fits within the die attach pad perimeter 132. The top perimeter 136 overlaps or extends beyond the die attach pad perimeter 132 in at least one direction. In some embodiments, a ground line 138 is embedded in the die attach pad 102. A ground conductor 140 is attached to the die 108 and the ground line 138.
[0032] Return to Figure 1A Because the top perimeter 136 overlaps or extends beyond the die attach pad perimeter 132 in at least one direction, the gap distance 124 is greater than the lead separation distance 142 defined by the distance between the proximal lead edge 120 of the lead 104 and the die edge 126 of the die 108. In some examples, the lead separation distance 142 varies between one or more different leads 104 based on the shape of the die. For example, for a first lead 104, the lead separation distance 142 may be substantially equal to the gap distance 124, but for a second lead 104, the lead separation distance 142 may be less than the gap distance 124. Figure 1C for Figure 1A An alternative example of the semiconductor device 100 in FIG. 1 is shown in FIG. 2 , wherein the leads 104 are located in the same plane as the die attach pad 102. In this example, the bottom surfaces of both the leads 104 and the die attach pad 102 are exposed on the bottom surface of the die attach pad 102.
[0033] Figure 2A An example of a shaped die 200 having a T-shape is described. For example, die 200 includes a base portion and an overhang portion. The base portion includes a first base sidewall 202 opposite a second base sidewall 204, the first base sidewall and the second base sidewall being separated by a base width 206. The overhang portion includes a first overhang sidewall 208 opposite a second overhang sidewall 210, the first overhang sidewall and the second overhang sidewall being separated by an overhang width 212. Overhang width 212 is greater than base width 206. Consequently, a base surface 214 of die 200 has a smaller surface area than a top surface 216 of die 200.
[0034] The base sidewalls 202, 204 extend from the base surface 214 to the overhang surface 218. The overhang sidewalls 208, 210 extend from the overhang surface 218 to the top surface 216, such that the die sidewalls are discontinuous. For example, the first die sidewall 220, including the first base sidewall 202 and the first overhang sidewall 208, is discontinuous at the overhang surface 218.
[0035] Figure 2B Another example of a shaped die 250 having a trapezoidal shape is illustrated. The die 250 includes a first die sidewall 252 opposite a second die sidewall 254. The die sidewalls 252, 254 extend continuously from a base surface 256 to a top surface 258 at an angle. Figure 1A The surface area of the die attach pad 102) (eg, Figure 1A 14. The angle of the die sidewall 252 at the surface area 114 of the die 250 is less than ninety degrees. For example, if the die 250 is attached to the surface area of the die attach pad at the base surface 256, the first die sidewall 252 forms a first angle 260 and the second die sidewall 254 forms a second angle 262. The angles 260, 262 form tapered die sidewalls 252, 254 such that the base surface 256 of the die 250 has a smaller surface area than the top surface 258 of the die 250. For example, the base width 264 of the die 250 is shorter than the upper width 266.
[0036] Insert the die attach pads (e.g. Figure 1A In the example of the die attach pad 102 ), the die attach pad (eg, Figure 1A The surface area of the die attach pad 102) (eg, Figure 1A The surface area 114 of the first plane is defined, and one or more leads (eg, Figure 1A The bonding surface of one or more leads 104) (e.g., Figure 1A The engaging surface 116 of the embodiment of the present invention defines a vertical distance (eg, Figure 1A Even if the top surface (e.g., Figure 1A The top surface 130, Figure 2A The top surface 216, Figure 2B The larger width of the top surface 258) (e.g., Figure 2A Overhang width 212, Figure 2B The upper width 266 of the substrate exceeds the smaller surface area, the substrate surface (e.g., Figure 1A The base surface 128, Figure 2A The base surface 214, Figure 2B The smaller surface area of the substrate surface 256) is also attached to a substrate that can accommodate the width of the substrate (e.g., Figure 2AThe base width is 206, Figure 2B Thus, even if the footprint of the die attach pad is smaller than the size of the top surface of the die, a smaller interconnect can be used to support the die.
[0037] In addition, the bare die (e.g. Figure 1A Bare chip 108, Figure 2A Bare chip 200, Figure 2B of bare die) and bonding wires (e.g., Figure 1A For example, the die attach pad provides mechanical support to the die because the die is supported by the bonding layer (e.g., Figure 1A The die attach pad is attached to the bonding layer 106 of the die attach pad. Furthermore, because, in some examples, the leads define a second plane that is vertically higher than the die attach pad, the leads and the top surface of the die are closer in height. Consequently, there is less vertical strain on the bonding wires connecting the leads to the die.
[0038] Figure 3 Description of the method for forming a die having a shaped die (e.g., Figure 1A Bare chip 108, Figure 2A Bare chip 200, Figure 2B bare die) of a semiconductor device (e.g. Figure 1A Method 300 of the semiconductor device 100). Figure 3 The method 300 will be described with respect to an example of a semiconductor device 100 at different stages of fabrication. Figures 4 to 14 For simplicity, Figures 4 to 14 Like reference numerals are used to refer to like structures.
[0039] At block 302, method 300 includes providing a semiconductor. For example, Figure 4 An example of a semiconductor wafer 400 provided in a first stage having a first surface 402 opposite a second surface 404 is illustrated. A semiconductor wafer is a substrate, such as silicon, silicon carbide, or other suitable material, in substantially pure form or in combination with additional materials. As another example, the semiconductor wafer 400 is a single crystal material, such as a single crystal silicon substrate. As yet another example, the semiconductor wafer 400 is a complementary metal oxide semiconductor (CMOS) substrate and includes circuitry formed thereon. The formation of the semiconductor wafer 400 depends on the semiconductor device being manufactured (e.g., Figure 1A Application of the semiconductor device 100).
[0040] exist Figure 3 At block 304, method 300 includes etching a plurality of voids in a first surface of semiconductor wafer 400 to a first depth. Figure 5 As shown in the example of FIG, in the second stage, a feature tool 500 removes wafer material from the first surface 402 of the semiconductor wafer 400 to form a void 502. For example, the feature tool 500 is an etching device, a laser, a saw, etc. The void 502 can have a variety of shapes. In some examples, the void 502 has spaced-apart sidewalls that extend substantially perpendicularly from the first surface 402 toward the second surface 404 to form spaced-apart die sidewalls (e.g., Figure 2A In other examples, the void 502 may have tapered sidewalls to form angled die sidewalls (e.g., Figure 2B tapered die sidewalls 252, 254).
[0041] In some examples, a photoresist layer 504 is formed on the first surface 402 of the semiconductor wafer 400 and patterned by performing selective irradiation. The irradiated or non-irradiated portions are removed by applying a developer material. For example, dry plasma etching is performed on the first surface 402 to form the voids 502. The dry plasma etching is based on the type of material forming the semiconductor wafer 400. For example, the plasma etching is a chlorine-based plasma etching, and the feature tool is a parallel plate reactive ion etching device, an inductively coupled plasma reactor, or alternatively an electron cyclotron resonance plasma reactor. In response to forming the voids 502, the photoresist layer 504 is removed from the first surface 402 of the semiconductor wafer 400, as Figure 6 This is shown in the third stage described in .
[0042] In some examples, the initial wafer thickness of the semiconductor wafer 400, defined by the distance between the first surface 402 and the second surface 404, is adjusted by back grinding. Figure 7 , a back grinding tape 700 is applied to the second surface 404 of the semiconductor wafer 400. The back grinding tape 700 supports the semiconductor wafer 400 during back grinding. In addition, the back grinding tape 700 can serve as a layer for protecting the second surface 404 of the semiconductor wafer 400 during back grinding. Figure 8 In the fifth stage described in
[0045] , the first surface 402 of the semiconductor wafer 400 is ground using a grinding tool 800 to remove material from the first surface 402, thereby forming an adjusted first surface 802. The adjusted wafer thickness is defined as the distance between the adjusted first surface 802 and the second surface 404. Due to the removal of wafer material, the adjusted wafer thickness is no thicker than the initial wafer thickness. In some examples, the semiconductor wafer 400 is positioned upside down for backside grinding.
[0043] exist Figure 3At block 306, method 300 includes attaching the first surface of semiconductor wafer 400 to dicing tape 900, e.g., Figure 9 . In the sixth stage shown in FIG. , in addition, in the example where the first surface 402 undergoes back grinding, the back grinding tape 700 is removed from the conditioned first surface 802. A dicing tape 900 (e.g., ultraviolet (UV) tape) is applied to the conditioned first surface 802 of the semiconductor wafer 400. In some examples, the semiconductor wafer 400 with the dicing tape 900 is positioned on a carrier, frame, or other suitable surface. The dicing tape 900 supports the semiconductor wafer 400 during the singulation process. As an example, the dicing tape 900 includes dicing marks that indicate where the semiconductor wafer 400 will be cut during the singulation process.
[0044] exist Figure 3 At block 308, method 300 includes dicing semiconductor wafer 400 to form a plurality of dies. Figure 10 . For example, the severing tool 1000 is a saw including a saw blade 1002 that scribes, saws, or cuts through the height of the semiconductor wafer 400 in a lateral direction in the seventh stage. The saw blade 1002 travels along a path from the second surface 404 to the first surface 402 through the semiconductor wafer 400 to the dicing strip 900 without severing the dicing strip 900. In other examples, the severing tool 1000 is laser-based or plasma-based.
[0045] Because the singulation process does not cut the dicing tape 900, the first formed die 1004, the second formed die 1006, the third formed die 1008, and the fourth formed die 1010 remain supported due to adhesion to the dicing tape 900. The plurality of dies have a base surface 1012 (e.g., Figure 1A The base surface 128, Figure 2A The base surface 214, Figure 2B and a top surface 1014 opposite the base surface 1012 (e.g., Figure 1A The top surface 130, Figure 2A The top surface 216, Figure 2B Depending on whether back grinding is performed, base surface 1012 corresponds to first surface 402 or adjusted first surface 802 of semiconductor wafer 400. Top surface 1014 corresponds to second surface 404.
[0046] exist Figure 3 At block 310 of the method 300, the method 300 includes mounting a die to a die attach pad of an interconnect. For example, the interconnect includes a die attach pad 1102 ( Figure 1Adie attach pad 102) and leads 1104 (e.g., Figure 1A Lead 104), such as Figure 11 The first formed die 1004 (e.g., Figure 1A Bare chip 108, Figure 2A Bare chip 200, Figure 2B die) using a bonding layer 1106 (e.g., Figure 1A The bonding layer 106 is applied to a surface area 1108 (eg, Figure 1A The bonding layer 1106 is a film adhesive, such as epoxy resin. Figure 12 In the ninth stage shown in FIG, the base surface 1012 of the first formed die 1004 is attached to the surface region 1108 using the bonding layer 1106 .
[0047] Although described with respect to the first formed die 1004, other dies (e.g., the second formed die 1006, the third formed die 1008, and the fourth formed die 1010) are described with respect to Figure 11 The eighth stage to Figure 14 Thus, the first formed die 1004 is mounted to the corresponding die attach pads 1102 using the bonding layer 1106 .
[0048] exist Figure 3 At block 312 of , method 300 includes attaching bond wires from the die to the lead fingers. For example, Figure 13 Bond wires 1300 are shown attached at the first formed die 1004 and leads 1104, thereby producing a semiconductor device 1306 (eg, Figure 1A 1. The semiconductor device 100 of FIG. 1 is shown. The bonding wire 1300 forms an electrical connection between the first formed die 1004 and the lead 1104. In some examples, the first formed die 1004 includes a first bonding pad 1302, the lead 1104 defines a second bonding pad 1304, and the bonding wire 1300 is coupled between the first bonding pad 1302 and the second bonding pad 1304.
[0049] exist Figure 3 At block 314, method 300 includes providing a molding compound to at least partially encapsulate the semiconductor device. For example, Figure 14 The semiconductor device 1306 is shown encapsulated in a mold compound 1400 (e.g., Figure 1A of the mold compound 112) to form a semiconductor device (e.g., Figure 1AThe semiconductor device 100 is formed of a mold compound 1400 formed of one or more insulating materials, such as an organic resin (e.g., epoxy resin), an inorganic resin, and / or other suitable materials. The mold compound 1400 at least partially encapsulates the first formed die 1004 and the die attach pads 1102, the leads 1104, and the bonding wires 1300.
[0050] exist Figure 3 At block 316, method 300 includes singulating the mounted die from the strip, such as Figure 13 . The top surface 1014 of the first formed die 1004, which is opposite the base surface 1012, has a larger surface area than the base surface area of the base surface 1012. Thus, the first formed die 1004 is accommodated by an interconnect having a smaller footprint because the base surface 1012 fits within the footprint, while the top surface would not. Thus, no second interconnect is required and the smaller interconnect can accommodate the first formed die 1004. Thus, the formed die described herein facilitates interconnect sharing, reduces inventory complexity, and simplifies the manufacture of semiconductor devices, thereby reducing manufacturing costs.
[0051] In this specification, unless otherwise stated, "about," "approximately," or "substantially" preceding a parameter means within a + / - 10% range of the parameter. Modifications may be made in the described embodiments, and other embodiments are possible, within the scope of the claims.
[0052] Throughout this specification, the term "coupled" encompasses any connection, communication, or signal path that enables a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B via a direct connection; or (b) in a second instance, device A is coupled to device B via an intermediate component C, provided that intermediate component C does not alter the functional relationship between devices A and B such that device B is controlled by device A via the control signal generated by device A. The phrase "based on" means "based, at least in part, on." Thus, if X is based on Y, then X can be a function of Y and any number of other factors. Modifications may be made in the described embodiments, and other embodiments are possible, within the scope of the claims.
Claims
1. A device comprising: a die attach pad having a surface area; and A die has a base surface mounted within the surface area of the die attach pad and a top surface opposite the base surface, wherein the top surface is larger than the base surface.
2. The apparatus of claim 1 , wherein the die further comprises: A die sidewall includes a base sidewall and an overhang sidewall, wherein the base sidewall extends from the base surface to an overhang surface, and the overhang sidewall extends from the overhang surface to the top surface such that the die sidewall is discontinuous.
3. The apparatus of claim 1 , wherein the die further comprises: A die sidewall extends continuously from the base surface to the top surface at an angle, wherein the angle relative to the surface area of the die attach pad is less than ninety degrees.
4. The apparatus according to claim 1, further comprising: A lead is laterally spaced apart from an edge of the die attach pad, wherein the edge defines an edge plane and the top surface extends to the edge plane.
5. The apparatus according to claim 4, further comprising: bonding wires attached to the die and the leads; and A mold compound encapsulates the bond wires, the leads, the die, and the die attach pad. 6 . The apparatus of claim 1 , wherein the base surface of the die is attached to the die attach pad using a bonding layer. The device of claim 6 , wherein the top surface of the die extends beyond the bonding layer.
8. The apparatus according to claim 1, further comprising: a ground line embedded in the die attach pad; and A ground conductor is attached to the die and the ground line.
9. A method of forming an integrated circuit (IC), comprising: providing a semiconductor wafer having a first surface and a second surface opposite to the first surface; etching a plurality of voids in the first surface of the semiconductor wafer to a first depth; attaching the first surface of the semiconductor wafer to a dicing tape; dicing the semiconductor wafer to form a plurality of dies, wherein a die in the plurality of dies has a base surface and a top surface opposite the base surface, wherein the top surface has a larger surface area than the base surface; mounting the die to a die attach pad; and Singulate the mounted die.
10. The method of claim 9, wherein at least one void of the plurality of voids has spaced-apart die sidewalls extending substantially perpendicular to the first surface toward the second surface.
11. The method of claim 9, wherein at least one of the plurality of voids has spaced-apart die sidewalls that taper in a direction and angle extending from the first surface. 12 . The method of claim 9 , wherein leads are spaced apart in a lateral direction from an edge of the die attach pad, wherein the edge defines an edge plane and the top surface extends to the edge plane.
13. The method of claim 12, wherein the top surface of the die includes a first bond pad and the lead defines a second bond pad, the method further comprising: coupling a bonding wire between the first bonding pad and the second bonding pad; and A molding compound is provided to encapsulate the bond wires, the leads, the die, and the die attach pad.
14. The method of claim 9, wherein the die is mounted to corresponding die attach pads using a bonding layer, and the top surface of the die extends beyond the bonding layer.
15. The method of claim 9, further comprising: embedding a ground wire in the die attach pad; and A ground conductor is coupled between the die and the ground line.
16. An integrated circuit (IC) package, comprising: a die attach pad having a surface area; a lead spaced apart from the die attach pad; a die having a base surface mounted within the surface area of the die attach pad and a top surface opposite the base surface, wherein the top surface is larger than the base surface; bonding wires attached to the die and the leads; and A mold compound encapsulates the bond wires, the leads, the die, and the die attach pad.
17. The IC package of claim 16, wherein the die further comprises: A die sidewall includes a base sidewall and an overhang sidewall, wherein the base sidewall extends from the base surface to an overhang surface, and the overhang sidewall extends from the overhang surface to the top surface such that the die sidewall is discontinuous.
18. The IC package of claim 16, wherein the die further comprises: A die sidewall extends continuously from the base surface to the top surface at an angle, wherein the angle relative to the surface area of the die attach pad is less than ninety degrees.
19. The IC package of claim 16, wherein the leads are spaced apart in a lateral direction from an edge of the die attach pad, wherein the edge defines an edge plane and the top surface extends to the edge plane.
20. The IC package of claim 16, wherein the die is mounted to corresponding die attach pads with a bonding layer, and the top surface of the die extends beyond the bonding layer.