Intelligent power stage circuit and buck overcurrent protection circuit

Abstract

The present disclosure provides a kind of intelligent power stage circuit and step-down overcurrent protection circuit, belongs to circuit control technical field, the output end of its drive unit is connected with the control end of first switch device and second switch device, the first end of first switch device is connected with direct current input end, the second end is connected with the first end of second switch device to output node, the second end of second switch device is grounded;The input end of detection unit is connected with the control end of first switch device, the control end of second switch device and output node respectively, and the output end is connected with drive unit;Detection unit is used to obtain the first fitting current of output node before the conduction of first switch device and lasts first blanking time, when the first fitting current is higher than POCP threshold value, first control signal is sent to drive unit, so that drive unit controls first switch device to be cut off, and second switch device is turned on;The intelligent power stage circuit of the present disclosure can effectively avoid the adverse effects caused by the output current being too high on the load.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of circuit control, and particularly relates to an intelligent power stage circuit and a step-down overcurrent protection circuit. BACKGROUND

[0002] In the current artificial intelligence and big data era, server systems are mostly used in parallel, for example, the composition of an AI server system is multiple AI computing cards in parallel in a server, and then multiple machines are connected in parallel. Since the composition of the AI server system is multiple machines connected in parallel, the reliability requirement is particularly high, and the failure of any computing card or device on the motherboard will affect the system operation. The current various computing chips, such as GPU, NPU, TPU and CPU, all use a multi-phase power supply circuit of DC-DC BUCK topology to provide a low-voltage and high-current power management scheme for them, and the multi-phase power supply circuit includes a multi-phase controller and an intelligent power stage circuit (SPS), and the overcurrent protection of the SPS itself is a very important function to ensure that the computing chip is not burned out and the entire system can run reliably.

[0003] With the increasing demand of current various applications for the operation rate of computing chips, the parallel computing capability of server systems is getting stronger and stronger, the amount of data processed is increasing day by day, and the energy consumption will also continue to rise. In this case, the process of the computing chip is required to be more advanced, and the output voltage of the power management scheme is required to be lower and lower, and the switching frequency is required to be higher and higher, while the input voltage remains basically unchanged. This will make the on time TON of the upper transistor smaller and smaller, which may cause the positive overcurrent protection of the current SPS to no longer be effective, and the safety of the computing chip is no longer guaranteed. SUMMARY

[0004] In view of the above problems, the present disclosure provides an intelligent power stage circuit and a step-down overcurrent protection circuit, which can effectively avoid the adverse effects of high output current on the load under the demand of low voltage output.

[0005] In a first aspect, an embodiment provides the following technical solutions:

[0006] The intelligent power stage circuit comprises a driving unit, a first switching device, a second switching device, a detection unit, a PWM input end, a direct current input end and an output node; an input end of the driving unit is used for connecting the PWM input end to obtain a PWM input signal, output ends of the driving unit are connected to control ends of the first switching device and the second switching device, a first end of the first switching device is connected to the direct current input end, a second end and a first end of the second switching device are connected to the output node, and a second end of the second switching device is grounded; input ends of the detection unit are respectively connected to the control end of the first switching device, the control end of the second switching device and the output node, and an output end of the detection unit is connected to the driving unit; the detection unit is used for obtaining a first fitting current of the output node before the first switching device is turned on and lasts for a first blanking time, sending a first control signal to the driving unit when the first fitting current is higher than a POCP threshold value, so that the driving unit controls the first switching device to be turned off and the second switching device to be turned on, obtaining a first measured current of the output node after the first switching device is turned on and lasts for the first blanking time, and sending the first control signal to the driving unit when the first measured current is higher than the POCP threshold value; wherein the first fitting current is determined according to a measured current of the second switching device in a previous turn-on period.

[0007] In some embodiments, the detection unit is further used for: obtaining a second fitting current of the output node before the second switching device is turned on and lasts for a second blanking time, continuously sending the first control signal to the driving unit when the second fitting current is higher than a HOCP threshold value; and sending a second control signal to the driving unit to make the driving unit control the first switching device and the second switching device according to the PWM input signal when the second fitting current is lower than the HOCP threshold value; obtaining a second measured current of the output node after the second switching device is turned on and lasts for the second blanking time, and sending the first control signal to the driving unit when the second measured current is higher than the HOCP threshold value, and sending the second control signal to the driving unit when the second measured current is lower than the HOCP threshold value; wherein the HOCP threshold value is lower than the POCP threshold value, and the second fitting current is determined according to the measured current of the second switching device in the previous turn-on period.

[0008] In some embodiments, the driving unit comprises a comparison circuit, a first logic circuit and a driving control circuit; an input terminal of the comparison circuit is connected to the PWM input terminal, and an output terminal of the comparison circuit is connected to an input terminal of the first logic circuit; the input terminal of the first logic circuit is also connected to an output terminal of the detection unit, an output terminal of the first logic circuit is connected to an input terminal of the driving control circuit, and an output terminal of the driving control circuit is connected to a control terminal of the first switching device and a control terminal of the second switching device; the comparison circuit is configured to output a VH high-level signal when a level of the PWM input signal is higher than a first reference level, output a VH low-level signal when the level of the PWM input signal is lower than the first reference level, output a VL low-level signal when the level of the PWM input signal is higher than a second reference level, and output a VL high-level signal when the level of the PWM input signal is lower than the second reference level; the first reference level is higher than the second reference level; the first logic circuit is configured to output a VH1 high-level signal to the driving control circuit when the second control signal and the VH high-level signal are detected, otherwise output a VH1 low-level signal to the driving control circuit; and output a VL1 low-level signal to the driving control circuit when the second control signal and the VL low-level signal are detected, otherwise output a VL1 high-level signal to the driving control circuit; and the driving control circuit is configured to output a GH high-level signal to make the first switching device conductive according to the VH1 high-level signal, output a GH low-level signal to make the first switching device non-conductive according to the VH1 low-level signal, and output a GL high-level signal to make the second switching device conductive according to the VL1 high-level signal, and output a GL low-level signal to make the second switching device non-conductive according to the VL1 low-level signal.

[0009] In some embodiments, the comparison circuit comprises a first comparator and a second comparator; a non-inverting input terminal of the first comparator is connected to the PWM input terminal, and an inverting input terminal of the first comparator is connected to the first reference level, and the first comparator is configured to output a VH high-level signal when a level of the PWM input signal is higher than the first reference level, and output a VH low-level signal when the level of the PWM input signal is lower than the first reference level; a non-inverting input terminal of the second comparator is connected to the second reference level, and an inverting input terminal of the second comparator is connected to the PWM input terminal, and the second comparator is configured to output a VL low-level signal when the level of the PWM input signal is higher than the second reference level, and output a VL high-level signal when the level of the PWM input signal is lower than the second reference level.

[0010] In some embodiments, the first control signal is a high-level signal and the second control signal is a low-level signal; the first logic circuit includes an AND gate and a first OR gate, the AND gate includes an input end and an inverting input end, the input end of the AND gate is connected to the output end of the first comparator, the inverting input end is connected to the output end of the detection unit, for inputting the level of the first control signal or the second control signal after being flipped to the first comparator; the output end of the AND gate is connected to the drive control circuit; the input end of the first OR gate is connected to the output end of the detection unit and the output end of the second comparator, and the output end of the first OR gate is connected to the drive control circuit.

[0011] In some embodiments, the detection unit includes a first detection circuit, a second detection circuit and a second logic circuit; the input end of the first detection circuit is connected to the control end, the first end and the second end of the first switch device, and the output end is connected to the first input end of the second logic circuit; the input end of the second detection circuit is connected to the control end, the first end and the second end of the second switch device, and the output end is connected to the second input end of the second logic circuit; the output end of the second logic circuit is connected to the drive unit; the first detection circuit is used to obtain a first fitting current of the output node before the first switch device is turned on and lasts for a first blanking time, output a F POCP high-level signal when the first fitting current is higher than a POCP threshold value, and output a F POCP low-level signal when the first fitting current is lower than the POCP threshold value; and obtain a first measured current of the first switch device after the first switch device is turned on and lasts for the first blanking time, and output the F POCP high-level signal when the first measured current is higher than the POCP threshold value, and output the F POCP low-level signal when the first measured current is lower than the POCP threshold value; the second detection circuit is used to obtain a second fitting current of the output node before the second switch device is turned on and lasts for a second blanking time, output a F HOCP low-level signal when the second fitting current is higher than a HOCP threshold value, and output a F HOCP high-level signal when the second fitting current is lower than the HOCP threshold value; and obtain a second measured current of the second switch device after the second switch device is turned on and lasts for the second blanking time, and output the F HOCP low-level signal when the second measured current is higher than the HOCP threshold value, and output the F HOCP high-level signal when the second measured current is lower than the HOCP threshold value; the second logic circuit outputs the first control signal when receiving the F POCP high-level signal and the F HOCP low-level signal, maintains outputting the first control signal when the F POCP high-level signal becomes the F POCP low-level signal and receiving the F HOCP low-level signal, and outputs the second control signal otherwise.

[0012] In some embodiments, the first detection circuit comprises: a first delay analog sub-circuit, a first switch, a second switch, a third comparator and a second OR gate; a non-inverting input terminal of the third comparator is connected to a first terminal of the first switch device through the first switch, a first inverting input terminal of the third comparator is connected to a second terminal of the first switch device through the second switch, a second inverting input terminal is connected to the POCP threshold value, and an output terminal of the third comparator is connected to a first input terminal of the second OR gate; an input terminal of the first delay analog sub-circuit is connected to a control terminal of the first switch device, a first output terminal of the first delay analog sub-circuit is connected to an enable terminal of the third comparator, the first switch and the second switch, and a second output terminal is connected to a second input terminal of the second OR gate; the first delay analog sub-circuit is configured to calculate a first fitting current according to a measured current of the second switch device in a last conduction period before the first switch device is turned on and lasts for a first blanking time, output an E_POCP high level signal to the second OR gate when the first fitting current is higher than the POCP threshold value, and output an E_POCP low level signal to the second OR gate when the first fitting current is lower than the POCP threshold value; and after the first switch device is turned on and lasts for the first blanking time, the first switch and the second switch are controlled to be closed and enable the third comparator, and when the first switch device is detected to be turned off, the first switch and the second switch are controlled to be turned off and the third comparator is not enabled; the third comparator is configured to obtain the current of the first switch device when enabled, output a CP3 high level signal when the current of the first switch device is detected to be higher than the POCP threshold value, and output a CP3 low level signal when not enabled and when the current of the first switch device is detected to be lower than the POCP threshold value; an enable terminal of the second OR gate is connected to the control terminal of the first switch device, and is enabled when the first switch device is turned on and is not enabled when the first switch device is turned off; the second OR gate outputs an F_POCP low level signal when not enabled, outputs the F_POCP low level signal when enabled and when receiving the E_POCP low level signal and the CP3 low level signal, and outputs an F_POCP high level signal otherwise.

[0013] In some embodiments, the second detection circuit comprises: a second delay analog sub-circuit, a third switch, a fourth switch, a fourth comparator, and a third OR gate; a first non-inverting input terminal of the fourth comparator is connected to a second terminal of the second switch device through the fourth switch, a second non-inverting input terminal is connected to the HOCP threshold, an inverting input terminal of the fourth comparator is connected to a first terminal of the second switch device through the third switch; an input terminal of the second delay analog sub-circuit is connected to a control terminal of the second switch device, a first output terminal of the second delay analog sub-circuit is connected to an enable terminal of the third switch, the fourth switch, and the fourth comparator, and a second output terminal is connected to the third OR gate; the second delay analog sub-circuit is configured to calculate a second fitting current according to a measured current of the second switch device in a last conduction period before the second switch device is turned on and lasts for a second blanking time, output an E_HOCP low-level signal to the third OR gate when the second fitting current is higher than the HOCP threshold, and output an E_HOCP high-level signal to the third OR gate when the second fitting current is lower than the HOCP threshold; and after the second switch device is turned on and lasts for the second blanking time, the third switch and the fourth switch are controlled to be closed and enable the fourth comparator, and when the second switch device is detected to be turned off, the third switch and the fourth switch are controlled to be opened and not to enable the fourth comparator; the fourth comparator is configured to obtain a current of the second switch device when enabled, and output a CP4 high-level signal when the current of the second switch device is detected to be lower than the HOCP threshold, and output a CP4 low-level signal when not enabled and the current of the second switch device is higher than the HOCP threshold; an enable terminal of the third OR gate is connected to the control terminal of the second switch device, and is enabled when the second switch device is turned on and is not enabled when the second switch device is turned off; the third OR gate outputs an F_HOCP low-level signal when not enabled, outputs an F_HOCP low-level signal when enabled and receives the E_HOCP low-level signal and the CP4 low-level signal, and outputs an F_HOCP high-level signal otherwise.

[0014] In some embodiments, the second logic circuit comprises an RS flip-flop, an inverter and a fourth OR gate; the S input terminal of the RS flip-flop is connected to the output terminal of the first detection circuit, the R input terminal is connected to the output terminal of the second detection circuit, the output terminal is connected to the first input terminal of the fourth OR gate, for inputting the F_POCP high level signal at the S input terminal and the F_HOCP low level signal at the R input terminal, and outputting the F_POCP1 high level signal when the F_POCP high level signal at the S input terminal changes to the F_POCP low level signal and the F_HOCP low level signal at the R input terminal; outputting the F_POCP1 low level signal when the F_HOCP low level signal at the R input terminal changes to the F_HOCP high level signal; the input terminal of the inverter is connected to the output terminal of the second detection circuit, the output terminal is connected to the input terminal of the fourth OR gate, and the enable terminal is connected to the control terminal of the second switching device, for enabling when the second switching device is turned on and not enabling when the second switching device is turned off; the inverter is used for outputting the F_HOCP1 low level signal when not enabled, and outputting the F_HOCP1 low level signal when enabled and receiving the F_HOCP high level signal, and outputting the F_HOCP1 high level signal when enabled and receiving the F_HOCP low level signal; the fourth OR gate outputs a high level signal as the first control signal when receiving the F_POCP1 high level signal or the F_HOCP1 high level signal, and outputs a low level signal as the second control signal when receiving the F_POCP1 low level signal and the F_HOCP1 low level signal.

[0015] In some embodiments, the smart power stage circuit further comprises an event detection unit and a counting unit, the input terminal of the event detection unit is connected to the PWM input terminal, the output terminal of the first detection circuit and the output terminal of the second logic circuit, the output terminal of the event detection unit is connected to the input terminal of the counting unit, for generating and outputting the POCP event signal when detecting the F_POCP high level signal, and generating and outputting the HOCP event signal when detecting the first control signal and the level of the PWM input signal changes from low to high; the smart power stage circuit further comprises a monitoring node for connecting an external controller, the output terminal of the counting unit is connected to the monitoring node, for counting the POCP event signal and the HOCP event signal, and sending a report signal to the monitoring node when the count reaches a preset value.

[0016] In some embodiments, the counting unit comprises a counter and a third switching device, an input end of the counter is connected to an output end of the event detection unit, an output end of the counter is connected to a control end of the third switching device, a first end of the third switching device is connected to a set voltage end, and a second end of the third switching device is connected to the monitoring node; the counter is configured to count up when the POCP event signal or the HOCP event signal is acquired, and the counter controls the third switching device to be turned on when the count reaches a preset value, so that the voltage of the monitoring node is raised and the voltage signal of the set voltage end is taken as the report signal.

[0017] In a second aspect, based on the same inventive concept, an embodiment provides the following technical solution:

[0018] A voltage reduction overcurrent protection circuit comprises a multiphase controller and at least one intelligent power stage circuit provided by the first aspect, the multiphase controller comprises a plurality of PWM output ends, the intelligent power stage circuit comprises a PWM input end, a direct current input end and an output node, one PWM output end is connected to the PWM input end of one intelligent power stage circuit; the multiphase controller is configured to send a PWM input signal to the intelligent power stage circuit, and the intelligent power stage circuit is configured to output an input voltage signal of the direct current input end to a load through the output node after reducing the input voltage signal, the load comprising at least one of a CPU, a GPU, an NPU and a TPU.

[0019] According to the technical solution in one of the above embodiments, the following advantages or benefits are achieved:

[0020] The embodiment of the present disclosure provides a kind of intelligent power stage circuit, including drive unit, first switching device, second switching device and detection unit, detection unit is used to obtain the first fitting current of output node before the conduction of first switching device and continues first blanking time, when the first fitting current is higher than POCP threshold, POCP protection is started, and first control signal is output to make drive unit control first switching device cut-off, second switching device is turned on, so that the current of output node drops;And after the conduction of first switching device and continues first blanking time, first measured current of output node is obtained to judge, when the first measured current is higher than POCP threshold, first control signal is output, so that first switching device cut-off, and second switching device is turned on;Because the switching noise of first switching device exists at this time, accurate measured current cannot be obtained, so that POCP protection cannot be normally carried out, and the first fitting current based on the measured current of second switching device in the last conduction period is simulated, and the first fitting current can avoid the influence of switching noise, so that POCP can be enabled to protect before the conduction time of first switching device reaches first blanking time, and the output current is prevented from being too high;On the other hand, after the conduction time of first switching device reaches first blanking time, the first measured current is used for POCP protection, because at this time, the influence of the switching noise of first switching device is no longer received, and the first measured current obtained by measurement is more accurate than the first fitting current obtained by simulation, so as to improve the precision of POCP protection.

[0021] The above description is only a summary of the technical scheme of the present disclosure, in order to more clearly understand the technical means of the present disclosure, the contents of the specification can be implemented, and in order to make the above and other purposes, characteristics and advantages of the present disclosure more obvious and easy to understand, the specific embodiments of the present disclosure are described below. BRIEF DESCRIPTION OF DRAWINGS

[0022] Various other advantages and benefits will become apparent to those of ordinary skill in the art, upon reading the following detailed description of the preferred embodiments. The accompanying drawings are included to provide a description of preferred embodiments, and are not meant to limit the present disclosure. Moreover, the same reference numerals are used in different drawings to denote the same or similar components; in the drawings.

[0023] Figure 1 An architecture schematic diagram of a power supply circuit of a server system is shown.

[0024] Figure 2 An architecture schematic diagram of an intelligent power stage circuit is shown.

[0025] Figure 3 A block diagram of an intelligent power stage circuit according to an embodiment of the present disclosure is shown.

[0026] Figure 4 A constituent diagram of a driving unit and a detecting unit in an intelligent power stage circuit according to one embodiment of the present disclosure is shown.

[0027] Figure 5 A detailed structure diagram of an intelligent power stage circuit according to one embodiment of the present disclosure is shown.

[0028] Figure 6 A circuit structure diagram of an analog module in a first delay analog sub-circuit according to one embodiment of the present disclosure is shown.

[0029] Figure 7 A circuit structure diagram of an analog module in a second delay analog sub-circuit according to one embodiment of the present disclosure is shown.

[0030] Figure 8 A framework diagram of an intelligent power stage circuit including an event detecting unit and a counting unit according to one embodiment of the present disclosure is shown.

[0031] Figure 9 A circuit structure diagram of a counting unit according to one embodiment of the present disclosure is shown.

[0032] Figure 10 A comparison diagram of a PWM waveform and a waveform of an output node SW in a scenario 1 according to one embodiment of the present disclosure is shown.

[0033] Figure 11 A comparison diagram of a PWM waveform and a waveform of an output node SW in a scenario 2 according to one embodiment of the present disclosure is shown.

[0034] Figure 12 A comparison diagram of a PWM waveform and a waveform of an output node SW in a scenario 3 according to one embodiment of the present disclosure is shown.

[0035] Figure 13 A framework diagram of a buck over-current protection circuit according to one embodiment of the present disclosure is shown.

[0036] Figure 14 A structure diagram of a 8+0 phase buck over-current protection circuit according to one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0037] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood, however, that the description is merely exemplary and is not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid obscuring the concept of the present disclosure.

[0038] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the drawings. These diagrams are not drawn to scale in which certain details are shown exaggerated and others omitted in the interest of clarity and conciseness, in the various views of the drawings, the depiction of the various regions, layers, and / or regions, layers of various shapes, and their relative sizing and positional relationship to one another are merely exemplary, and in practice can deviate due to manufacturing tolerances or technical limitations, and one skilled in the art can additionally design regions / layers with different shapes, sizes, relative positions according to actual needs.

[0039] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meaning commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terms "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different components. Similarly, the terms "one", "a", or "the" and similar terms do not denote a quantity restriction, but mean that there is at least one. The terms "connected" or "coupled" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right", and the like are used only to indicate relative positional relationships, which can change when the absolute positions of the described objects change.

[0040] The English abbreviations, English full names and Chinese explanations of some nouns related to the embodiments of the present disclosure are as follows.

[0041] POCP: Positive Over Current Protection, peak overcurrent protection.

[0042] POCP BT: Positive Over Current Protection Blanking Time, peak overcurrent protection blanking time.

[0043] POCP Threshold: POCP threshold.

[0044] POCP RS: Positive Over Current Protection Real Sensing, POCP real-time detection.

[0045] HOCP: Hysteresis Over Current Protection, hysteresis overcurrent protection.

[0046] HOCP Threshold: HOCP threshold.

[0047] HOCP BT: Hysteresis Over Current Protection Blanking Time

[0048] HOCP RS: Hysteresis Over Current Protection Real Sensing

[0049] COT: Constant ON Time

[0050] BT&CE: Blanking Time & Current Emulation

[0051] For the AI or operation server system in parallel connection, the load includes Graphics Processing Unit (GPU), Neural network Processing Unit (NPU), Tensor Processing Unit (TPU) and Central Processing Unit (CPU) and other computing chips, and these computing chips can use multi-phase power supply of DC-DC BUCK topology to provide low-voltage and large-current power management scheme.

[0052] Figure 1 An overall architecture example of a power supply circuit of a server system is provided. Alternating current from a power grid is converted into 48V or 12V direct current input through an alternating current / direct current conversion unit AC / DC PSU. If the direct current input is 12V, the power management circuit can be directly supplied with power. If the direct current input is 48V, the 48V direct current input can be first reduced to 12V direct current output through a direct current voltage reduction circuit Regulator, and then provided to the power management circuit. In addition, other ways can also be used to provide 12V direct current power supply, such as a battery assembly. The power management circuit includes a multi-phase controller Controller and a smart power stage circuit (SPS). The multi-phase controller Controller is used to generate a PWM (Pulse Width Modulation) signal to the SPS circuit. The input end of the SPS circuit is connected to the output end of the direct current voltage reduction circuit Regulator, or directly connected to the 12V input of the direct current voltage end, and used to provide low-voltage and large-current signal V_Supply for the load: computing chip under the control of the PWM signal. The current and voltage end can be connected to the battery module to provide 12V direct current input.

[0053] An architecture of an SPS circuit can be found in Figure 2 The PWM input signal from the controller enters the SPS circuit through the PWM input terminal PI, and under the action of the drive unit CU, the on-off of the upper transistor HS and the lower transistor LS is controlled according to the waveform of the PWM, so as to output the input voltage signal of the DC input terminal Vin to the output node SW (also known as the switching node), and the output node SW is connected to the external inductor L, and the external load is powered through the inductor L.

[0054] Through research, it is found that as the operation rate of the computing chip is getting higher and higher, the parallel computing capability is getting stronger and stronger, the amount of data processed is increasing day by day, and the energy consumption will also continue to rise, so the output voltage Vout of the SPS circuit is required to be lower and lower, the switching frequency Fsw of the upper transistor is required to be higher and higher, but at the same time, the input voltage Vin needs to be kept basically unchanged, and according to formula (1), the conduction time or opening time TON of the upper transistor HS can be obtained.

[0055] TON=Vout / (Vin×Fsw) (1)

[0056] Under the above three conditions, it can be known that the conduction time TON of the upper transistor HS will become shorter and shorter, and will be less than or equal to the upper transistor blanking time (HS Blanking Time), wherein the blanking time Blanking Time is a time set to avoid switching noise of the switching device, and in the case that the conduction time TON of the upper transistor HS is shorter than the blanking time, the peak over current protection function (Positive Over Current Protection, abbreviated as POCP) of turning off the upper transistor will not work normally, so the stable operation of the computing chip at the load end cannot be guaranteed.

[0057] In view of the above problems, in a first aspect, in an optional embodiment, please refer to Figure 3The application provides an intelligent power stage circuit (SPS), comprising a driving unit (CU), a first switching device (HS), a second switching device (LS), a detection unit (DU), a PWM input terminal (PI), a direct current input terminal (Vin) and an output node (SW); an input terminal of the driving unit (CU) is used for connecting the PWM input terminal (PI) to obtain a PWM input signal; output terminals of the driving unit (CU) are connected to control terminals of the first switching device (HS) and the second switching device (LS); a first terminal of the first switching device (HS) is connected to the direct current input terminal (Vin); a second terminal of the first switching device (HS) and a first terminal of the second switching device (LS) are connected to the output node (SW); a second terminal of the second switching device (LS) is grounded; input terminals of the detection unit (DU) are respectively connected to the control terminal of the first switching device (HS), the control terminal of the second switching device (LS) and the output node (SW); and an output terminal of the detection unit (DU) is connected to the driving unit (CU); the detection unit (DU) is used for obtaining a first fitting current of the output node (SW) before the first switching device (HS) is turned on and lasts for a first blanking time; when the first fitting current is higher than a POCP threshold value, the detection unit (DU) sends a first control signal to the driving unit (CU) to make the driving unit (CU) control the first switching device (HS) to be turned off and the second switching device (LS) to be turned on; and after the first switching device (HS) is turned on and lasts for the first blanking time, a first measured current of the output node (SW) is obtained, and when the first measured current is higher than the POCP threshold value, the detection unit (DU) sends the first control signal to the driving unit (CU); wherein the first fitting current is determined according to a measured current of the second switching device (LS) in a previous turn-on period.

[0058] Specifically, the SPS circuit receives a PWM input signal sent by an external controller from a PWM input end PI (i.e., a PWM pin) in normal operation, and first and second switching devices HS and LS are turned on or off (turned off) according to a duty cycle waveform of the PWM input signal under the driving of a control circuit. When the first switching device HS is turned on and the second switching device LS is turned off, a voltage signal of a DC input end Vin is outputted to an external load through the first switching device HS and an output node SW (also referred to as a switching node), and the external inductor L stores energy and the capacitor charges, thereby maintaining the voltage of the load end stable. When the first switching device HS is turned off and the second switching device LS is turned on, the external inductor L releases energy to generate a reverse electromotive force, thereby continuously supplying power to the load. The first end of the first switching device HS is connected to the DC input end Vin, which can be referred to as an upper tube, and the second end of the second switching device LS is grounded, which can be referred to as a lower tube. When the upper tube is turned on, current flows from the DC input end Vin to the output node SW through the upper tube, and when the lower tube is turned on, current flows from the ground end to the output node SW through the lower tube. The first and second switching devices HS and LS are not turned on at the same time, and are alternately turned on under the control of the PWM input signal, thereby realizing the function of "Vin voltage reduction-stable output" of the SPS circuit. Therefore, the waveform of the output node SW or the external inductor current IL is the superposition of the current waveforms of the first and second switching devices HS and LS.

[0059] The first and second switching devices HS and LS can be switching devices such as field effect transistors (FETs) or triodes. Unless otherwise specified, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are used as examples in the embodiments of the present disclosure and the accompanying drawings. Please refer to Figure 3 The first switching device HS is an NMOS tube, the first end of which is a drain connected to the DC input end Vin, the second end of which is a source connected to the output node SW, and the control end of which is a gate connected to the driving unit CU. The second switching device LS is an NMOS tube, the first end of which is a drain connected to the output node SW, the second end of which is a source connected to the ground end PGND, and the control end of which is a gate connected to the driving unit CU. In normal control, the driving unit CU outputs two control signals according to the PWM input signal, one of which is used to control the on-off of the first switching device HS, and the other of which is used to control the on-off of the second switching device LS.

[0060] For the power supply demand of low-voltage large-current at the load end, the SPS circuit can be protected by the POCP (Positive Over Current Protection, peak overcurrent protection) mechanism. The idea is to turn off the first switch device HS (upper tube) when the output current or inductor current IL is greater than a certain set value, such as the POCP threshold, so that the IL current decreases. However, as the demand for low-voltage large-current power supply at the load end continues to rise, according to formula (1), the on-time of the first switch device HS will become shorter and shorter, and even shorter than the first switch device HS blanking time (HS Blanking Time, also known as POCP BT), the POCP protection will not work properly. This is because the drive unit CU introduces a "blanking time" in the control timing to avoid switch noise of the switch device to achieve accurate current measurement, so the usual POCP protection needs to take effect after the blanking time, which leads to the fact that when the on-time of the first switch device HS is shorter than the first blanking time, the IL current cannot be reduced by POCP protection.

[0061] To solve the above problems, the scheme proposed by the embodiments of the present disclosure is a peak overcurrent protection (Positive Over Current Protection, POCP) with blanking time. When the on-time (TON) of the first switch device is lower than the first blanking time (POCP BT), the POCP can also be protected. Specifically, the detection unit DU obtains the first fitting current of the output node before the first switch device HS is turned on and lasts for the first blanking time. When the first fitting current is higher than the POCP threshold (POCP Threshold), the POCP protection is started, and the first control signal is output to make the drive unit CU control the first switch device HS to be off, and the second switch device LS to be on, so that the current of the output node decreases. The reason why the measured current is not used for judgment before the on-time of the first switch device HS reaches the first blanking time is that the switch noise of the first switch device HS at this time leads to the inability to obtain accurate measured current, so that the POCP protection cannot be normally performed. The first fitting current obtained by simulating the measured current of the second switch device LS in the last on-time period can avoid the influence of switch noise, so that the SPS circuit can still enable POCP protection before the on-time of the first switch device HS reaches the first blanking time, and the output current is prevented from being too high.

[0062] It should be noted that the first switch device HS and the second switch device LS are selectively turned on during the output process, the second switch device LS is turned off when the first switch device HS is turned on, and the second switch device LS is turned on when the first switch device HS is turned off; the current period is the period of the PWM input signal corresponding to the current time, before that, the last on period of the second switch device LS refers to the period in which the first switch device HS is turned off and the second switch device LS is turned on in the period of the last PWM input signal; in addition, the first fitting current of the output node SW is actually the fitting current of the first switch device HS turned on; when the first fitting current is simulated, it is first set that the inductance value L of the external inductor has no significant change within a PWM period, and the inductance value L can be calculated according to formula (2).

[0063] -V0=L×(di / dt) (2)

[0064] In the above formula, V0 is a known value, which is the average voltage value of the SW signal (the output signal of the output node SW), that is, the weighted average value calculated according to the high voltage and low voltage of the SW signal combined with the duty cycle, and the value corresponds to the output voltage of the output node SW, and the "-" sign indicates that the inductance voltage is reversed in the low level section of the PWM input signal, di is the change amount of the current, and dt is the change amount of the time, which is also a known value within the last on period, so the inductance value of the external inductor in the last period can be calculated according to formula (2).

[0065] When the first switch device HS is turned on and the second switch device LS is turned off in the current period, the inductance value L of the external inductor uses the known value in the last period, and the current change amount di of the first switch device HS after dt time can be calculated according to formula (3).

[0066] Vin-V0=L×(di / dt) (3)

[0067] In the above formula, Vin is the input voltage of the direct current input terminal Vin.

[0068] Therefore, according to the time variable dt, the current change amount di of the first switch device HS after dt time of the conduction time can be calculated, and the initial current I01 of the first switch device HS just turned on, that is, the first fitting current of the output node SW can be obtained, and the value of the first fitting current corresponds to the current value flowing through the first switch device HS.

[0069] In another aspect, the POCP protection can also be effective when the on-time of the first switching device HS is greater than the first blanking time (POCP BT). Specifically, after the first switching device HS is turned on and lasts for the first blanking time, the first measured current of the output node SW is obtained for judgment. When the first measured current is higher than the POCP threshold, the first control signal is outputted to turn off the first switching device HS and turn on the second switching device LS, so as to reduce the current of the output node SW. At this time, it is normal POCP protection. The reason for using the first measured current for judgment is that the first switching device HS will not be affected by the switching noise at this time. The first measured current obtained by measurement is more accurate than the first fitting current obtained by simulation, thereby improving the accuracy of the POCP protection.

[0070] In some embodiments, the detection unit DU is further configured to: obtain a second fitting current of the output node SW before the second switching device LS is turned on and lasts for the second blanking time, and continuously send the first control signal to the drive unit CU when the second fitting current is higher than the HOCP threshold; and send a second control signal to the drive unit CU to control the first switching device HS and the second switching device LS according to the PWM input signal when the second fitting current is lower than the HOCP threshold; obtain a second measured current of the output node SW after the second switching device LS is turned on and lasts for the second blanking time, and send the first control signal to the drive unit CU when the second measured current is higher than the HOCP threshold, and send the second control signal to the drive unit CU when the second measured current is lower than the HOCP threshold; wherein the HOCP threshold is lower than the POCP threshold, and the second fitting current is determined according to the measured current of the second switching device LS in the last on-time.

[0071] Specifically, the embodiment of the present disclosure also provides a hysteresis over current protection (HOCP) with a blanking time. The idea of the scheme is to perform HOCP detection and protection after the second switching device LS (lower tube) is turned on. Specifically, before the second switching device LS is turned on but the duration reaches a second blanking time (HOCP BT), in order to avoid the influence of switching noise on the HOCP protection accuracy, a second fitting current is used for judgment. Before the second fitting current is lower than the HOCP threshold (HOCP Threshold), the first switching device HS is continuously kept off and the second switching device LS is continuously turned on by the first control signal. At this time, even if the first switching device HS should be turned on according to the PWM input signal, it is not allowed to be turned on. After the current of the output node SW is lower than the HOCP threshold, the first switching device HS and the second switching device LS are controlled to be turned on and off according to the PWM input signal by the second control signal, that is, at this time, the first switching device HS is allowed to be turned on, so that the current of the output node SW rises.

[0072] The second fitting current of the output node SW is actually the fitting current of the turned-on second switching device LS. When the first fitting current is determined, the inductance value L of the external inductor in the last on period is obtained, and the on time Ton of the second switching device LS in the last period is also known. According to Ton and L, the current variable di after the second switching device LS is turned on can be simulated in real time according to formula (2), and then the second fitting current can be obtained by combining the current I02 of the output node SW when the second switching device LS is just turned on.

[0073] After the second switching device LS is turned on and the duration reaches the second blanking time, a more accurate second measured current is obtained for judgment, and the protection logic is the same as that of using the second fitting current for judgment. The first control signal and the second control signal can be two different signals or the high level state and the low level state of the same signal, which can be configured according to actual needs.

[0074] Briefly, whether the second fitting current or the second measured current is used, the idea of HOCP protection is to keep the first switching device HS in an off state before the current of the output node SW is lower than the HOCP threshold, skip the high level waveform in the PWM input signal, and then restore the normal control of the PWM input signal when the current of the output node SW is lower than the HOCP threshold. In this way, the adverse effects of the output current of the intelligent power stage circuit SPS on the load end (such as a computing chip) in the application scenario of low-voltage output and high switching frequency can be effectively avoided.

[0075] So far, the SPS circuit provided by the embodiment of the present disclosure has the function of POCP protection and HOCP protection interlocking. When the on time TON of the first switching device HS is less than the first blanking time (POCP BT), POCP protection is performed by the first fitting current, thereby avoiding the influence of switching noise. When the continuous on time of the first switching device HS is higher than the first blanking time, POCP protection is performed by the first measured current of the output node, thereby improving the POCP protection accuracy. Whether it is the first fitting current or the first measured current, when it is detected that it is higher than the POCP threshold, the first switching device HS is turned off and the second switching device LS is turned on to reduce the current. After the second switching device LS is turned on, the HOCP protection starts to take effect. When the on time of the second switching device LS is less than the second blanking time (HOCP BT), protection is performed by the second fitting current, thereby avoiding the influence of switching noise. When the continuous on time of the second switching device LS is higher than the second blanking time, protection is performed by the second measured current of the output node, thereby improving the HOCP protection accuracy. Whether it is the second fitting current or the second measured current, when it is detected that it is greater than or equal to the HOCP threshold, the first switching device HS is not allowed to be turned on, even if the PWM input signal is in a high state at this moment. Only when the current is less than the HOCP threshold, the second switching device LS is allowed to be turned off and the first switching device HS is allowed to be turned on, thereby restoring the normal control of the PWM input signal, so as to ensure the overcurrent protection of the external load.

[0076] It can be understood that the POCP threshold is greater than the HOCP threshold, and there is a positive difference between the two, which is the hysteresis. The actual values of the POCP threshold and the HOCP threshold need to be set according to the different load end requirements and combined with the circuit design, and the embodiment of the present disclosure does not limit the specific values thereof.

[0077] The above embodiment introduces the POCP protection and HOCP protection interlocking function in the SPS circuit. In the following embodiments, the driving unit CU and the detection unit DU will be discussed in detail.

[0078] First, the driving unit CU part in the SPS circuit. In some embodiments, please refer to Figure 4 The circuit framework diagram of the SPS provided by the present disclosure, the driving unit CU includes a comparison circuit CC, a first logic circuit LC1 and a drive control circuit DCC; the input end of the comparison circuit CC is connected with the PWM input end PI, and the output end is connected with the input end of the first logic circuit LC1; the input end of the first logic circuit LC1 is also connected with the output end of the detection unit DU, the output end of the first logic circuit LC1 is connected with the input end of the drive control circuit DCC, and the output end of the drive control circuit DCC is connected with the control end of the first switching device HS and the control end of the second switching device LS.

[0079] Specifically, the comparison circuit CC is configured to output a comparison result of the PWM level according to a waveform of the PWM input signal, the first logic circuit LC1 is configured to perform a logical judgment according to the comparison result and the first control signal and the second control signal fed back by the detection unit DU, and output a judgment signal for controlling the on-off of the first switch device HS and the second switch device LS, and the drive control circuit DCC is configured to process and amplify the judgment signal, so as to complete the on-off control of the first switch device HS and the second switch device LS.

[0080] In some embodiments, referring to Figure 4 , the comparison circuit CC is configured to output a VH high-level signal when the level of the PWM input signal is higher than a first reference level, output a VH low-level signal when the level of the PWM input signal is lower than the first reference level, output a VL low-level signal when the level of the PWM input signal is higher than a second reference level, and output a VL high-level signal when the level of the PWM input signal is lower than the second reference level; and the first reference level is higher than the second reference level.

[0081] As a comparison reference, the values of the first reference level and the second reference level can be set according to actual conditions, as long as the comparison circuit CC can output a VH high and a VL low comparison result when the PWM input signal is in a high-level wave band, and can output a VH low and a VL high comparison result when the PWM input signal is in a low-level wave band.

[0082] A comparison circuit CC composition scheme can refer to Figure 5 , comprising a first comparator COMP1 and a second comparator COMP2, the non-inverting input terminal of the first comparator COMP1 is connected to the PWM input terminal PI, and the inverting input terminal is connected to the first reference level PWM_HI, which is configured to output a VH high-level signal when the level of the PWM input signal is higher than the first reference level PWM_HI, and output a VH low-level signal when the level of the PWM input signal is lower than the first reference level PWM_HI; the non-inverting input terminal of the second comparator COMP2 is connected to the second reference level PWM_LO, and the inverting input terminal is connected to the PWM input terminal PI, which is configured to output a VL low-level signal when the level of the PWM input signal is higher than the second reference level PWM_LO, and output a VL high-level signal when the level of the PWM input signal is lower than the second reference level PWM_LO.

[0083] The output of the comparison circuit CC and one of the first control signal and the second control signal are inputs of the first logic circuit LC1, and in some embodiments, the first logic circuit LC1 is configured to output a VH1 high-level signal to the drive control circuit DCC when the second control signal and the VH high-level signal are detected, and otherwise output a VH1 low-level signal to the drive control circuit DCC; and output a VL1 low-level signal to the drive control circuit DCC when the second control signal and the VL low-level signal are detected, and otherwise output a VL1 high-level signal to the drive control circuit DCC; and the drive control circuit DCC is configured to output a GH high-level signal to turn on the first switching device HS according to the VH1 high-level signal, and output a GH low-level signal to turn off the first switching device HS according to the VH1 low-level signal; and output a GL high-level signal to turn on the second switching device LS according to the VL1 high-level signal, and output a GL low-level signal to turn off the second switching device LS according to the VL1 low-level signal.

[0084] Specifically, the above scheme is designed by taking the first switching device HS and the second switching device LS as NMOS tubes, the control end of the first switching device HS is turned on when GH is high, and is turned off when GH is low; the control end of the second switching device LS is turned on when GL is high, and is turned off when GL is low; in order to facilitate logical judgment, the first control signal can be a high-level signal, and the second control signal can be a low-level signal; if the first control signal is marked as OCP_Faults=1, the second control signal is marked as OCP_Faults=0, and VH high-level signal, VL high-level signal, VH1 high-level signal and VL1 high-level signal are marked as 1, and VH low-level signal, VL low-level signal, VH1 low-level signal and VL1 low-level signal are marked as 0, then the operation logic of the first logic circuit LC1 can be as shown in Table 1.

[0085] Table 1: Operation logic of the first logic circuit LC1.

[0086]

[0087] It can be seen that for the first switching device HS, the first logic circuit LC1 only outputs the VH1 high level signal when the input is the second control signal (OCP_Faults=0) and the VH high level signal (VH=1), so as to make the driving control circuit DCC open the first switching device HS and close the second switching device LS, at this time, the corresponding is that the current of the output node SW is lower than the H OCP threshold and the PWM input signal is in the high level wave band, and in other cases, the first switching device HS is kept in the state of being cut off and the second switching device LS is kept in the state of being turned on; for the second switching device LS, the on-off state is opposite to that of the first switching device HS, that is, the second switching device LS is cut off when the first switching device HS is turned on, and the second switching device LS is turned on when the first switching device HS is cut off.

[0088] For the logic operation of Table 1, a composition scheme of the first logic circuit LC1 can be referred to Figure 5 , which includes an AND gate and a first OR gate OR1. The AND gate includes an input end and an inverting input end. The input end of the AND gate is connected to the output end of the first comparator COMP1, and the inverting input end is connected to the output end of the detection unit DU, for inputting the level of the first control signal or the second control signal after being flipped to the first comparator COMP1. The output end of the AND gate is connected to the driving control circuit DCC. The input end of the first OR gate OR1 is connected to the output end of the detection unit DU and the output end of the second comparator COMP2, and the output end of the first OR gate OR1 is connected to the driving control circuit DCC.

[0089] Specifically, the inverting input end of the AND gate circuit integrates a NOT gate, for inputting the level of the first control signal or the second control signal after being flipped, for example, if the first control signal is a high level signal of OCP_Faults=1, the inverting input end first flips it to OCP_Faults=0 and then inputs it to the AND gate, and if the first control signal is OCP_Faults=0, the inverting input end first flips it to OCP_Faults=1 and then inputs it to the AND gate. The AND operation is that when the two input ends are both 1, the VH1 high level signal is outputted to open the first switching device HS, that is, only when the input is the VH high level signal and the second control signal (OCP_Faults=0) can the upper tube be opened.

[0090] The composition scheme of the first logic circuit LC1 above is designed by taking NMOS tubes as the first switching device HS and the second switching device LS as an example; it can be understood that if the first switching device HS and the second switching device LS are PMOS tubes, the control logic is opposite, that is, turned on when GH and GL are low, and cut off when GH and GL are high, so that under the same input, the output of the first logic circuit LC1 is required to be opposite to the result of Table 1, as shown in Table 2.

[0091] Table 2: The judging logic of the first logic circuit LC1 when using PMOS transistor.

[0092]

[0093] According to the logic operation of Table 2, the output result corresponding thereto can be obtained by adaptively adjusting the composition of the first logic circuit LC1 through designing the combination of gate circuits; for example, for the input of VH and OCP_Faults, first use the NOT gate to negate VH, and then input the OR gate together with OCP_Faults, and the output of the OR gate is VH1; for VL and OCP_Faults, two NOT gates can be used to negate VL and OCP_Faults at the same time, and then the judging results of the NOT gates are input into the AND gate to obtain the output VL1.

[0094] The above is the driving unit CU part in the SPS circuit, and the following is the part of the detection unit DU. In some embodiments, please refer to Figure 4The detection unit DU includes a first detection circuit DC1, a second detection circuit DC2 and a second logic circuit LC2; an input end of the first detection circuit DC1 is connected with a control end, a first end and a second end of the first switch device HS, and an output end is connected with a first input end of the second logic circuit LC2; an input end of the second detection circuit DC2 is connected with a control end, a first end and a second end of the second switch device LS, and an output end is connected with a second input end of the second logic circuit LC2; and an output end of the second logic circuit LC2 is connected with the driving unit CU; the first detection circuit DC1 is used for obtaining a first fitting current of the output node SW before the first switch device HS is turned on and lasts for a first blanking time, outputting a F_POCP high level signal when the first fitting current is higher than a POCP threshold value, and outputting a F_POCP low level signal when the first fitting current is lower than the POCP threshold value; and obtaining a first measured current of the first switch device HS after the first switch device HS is turned on and lasts for the first blanking time, and outputting the F_POCP high level signal when the first measured current is higher than the POCP threshold value, and outputting the F_POCP low level signal when the first measured current is lower than the POCP threshold value; the second detection circuit DC2 is used for obtaining a second fitting current of the output node SW before the second switch device LS is turned on and lasts for a second blanking time, outputting a F_HOCP low level signal when the second fitting current is higher than a HOCP threshold value, and outputting a F_HOCP high level signal when the second fitting current is lower than the HOCP threshold value; and obtaining a second measured current of the second switch device LS after the second switch device LS is turned on and lasts for the second blanking time, and outputting the F_HOCP low level signal when the second measured current is higher than the HOCP threshold value, and outputting the F_HOCP high level signal when the second measured current is lower than the HOCP threshold value; the second logic circuit LC2 outputs a first control signal when receiving the F_POCP high level signal and the F_HOCP low level signal, and keeps outputting the first control signal when the F_POCP high level signal becomes the F_POCP low level signal and receiving the F_HOCP low level signal, otherwise, outputs a second control signal.

[0095] Specifically, the first detection circuit DC1 can determine whether the first switch device HS is turned on by obtaining the level of the control end of the first switch device HS, for example, for an NMOS tube, if the input of the control end is detected as a high level signal, it indicates that the first switch device HS is turned on, if the input of the control end is detected as a low level signal, it indicates that the first switch device HS is cut off; the on-off state of the second switch device LS is judged in the same way; after the first switch device HS or the second switch device LS is turned on, the corresponding detection circuit starts timing first, and the fitting current is calculated for judgment when the conduction time of the switch device is lower than the corresponding blanking time, and the measured current is obtained for judgment when the conduction time exceeds the blanking time.

[0096] In some embodiments, referring to Figure 5 , the first detection circuit DC1 comprises: a first delay analog sub-circuit BT&CE1, a first switch SW1, a second switch SW2, a third comparator COMP3 and a second OR gate OR2; the non-inverting input terminal of the third comparator COMP3 is connected to the first terminal of the first switching device HS through the first switch SW1, the first inverting input terminal of the third comparator COMP3 is connected to the second terminal of the first switching device HS through the second switch SW2, the second inverting input terminal is connected to the POCP threshold value, and the output terminal of the third comparator COMP3 is connected to the first input terminal of the second OR gate OR2; the input terminal of the first delay analog sub-circuit BT&CE1 is connected to the control terminal of the first switching device HS, the first output terminal of the first delay analog sub-circuit BT&CE1 is connected to the enable terminal EN3 of the third comparator COMP3, the first switch SW1 and the second switch SW2, and the second output terminal is connected to the second input terminal of the second OR gate OR2; the first delay analog sub-circuit BT&CE1 is used to calculate the first fitting current according to the actually measured current of the second switching device LS in the last conduction period before the first switching device HS is turned on and lasts for the first blanking time, output an E_POCP high level signal to the second OR gate OR2 when the first fitting current is higher than the POCP threshold value, and output an E_POCP low level signal to the second OR gate OR2 when the first fitting current is lower than the POCP threshold value; and after the first switching device HS is turned on and lasts for the first blanking time, the first switch SW1 and the second switch SW2 are controlled to be closed and the third comparator COMP3 is enabled, and when the first switching device HS is detected to be turned off, the first switch SW1 and the second switch SW2 are controlled to be opened and the third comparator COMP3 is disabled; the third comparator COMP3 is used to obtain the current of the first switching device HS when enabled, output a CP3 high level signal when detecting that the current of the first switching device HS is higher than the POCP threshold value, and output a CP3 low level signal when not enabled and when detecting that the current of the first switching device HS is lower than the POCP threshold value; the enable terminal OR2EN of the second OR gate OR2 is connected to the control terminal of the first switching device HS, and is enabled when the first switching device HS is turned on and is not enabled when the first switching device HS is turned off; the second OR gate OR2 outputs an F_POCP low level signal when not enabled, outputs an F_POCP low level signal when enabled and when receiving the E_POCP low level signal and the CP3 low level signal, and otherwise outputs an F_POCP high level signal.

[0097] Specifically, the first delay simulation sub-circuit BT&CE1 is configured to: before the on-time of the first switching device HS reaches the first blanking time (POCP BT), its first output end sends a control instruction (GH1 low level) to turn off the first switch SW1 and the second switch SW2 and disable the third comparator COMP3, at this time the first delay simulation sub-circuit BT&CE1 calculates the first fitting current to make a judgment, according to the judgment result of the first fitting current, the second or gate OR2 outputs an E_POCP high level signal or an E_POCP low level signal through the second output end.

[0098] The first delay simulation sub-circuit BT&CE1 includes two functional modules, one of which is a timer module, which judges whether the first switching device HS is on and whether the on-time reaches the first blanking time through a preset delay time (i.e. POCP BT); for example, if the first switching device HS is an NMOS tube, when the control end signal of the first switching device HS is low, it is judged to be in the off state, the first switch SW1 and the second switch SW2 are controlled to be turned off and the third comparator COMP3 is disabled through the control instruction (GH1 low level); when the control end signal of the first switching device HS is high, it is judged to be in the on state, and the timing starts, before the preset time POCP BT is reached, the first switch SW1 and the second switch SW2 are controlled to be turned off and the third comparator COMP3 is disabled through the control instruction (GH1 low level); after the preset time POCP BT is reached, the first switch SW1 and the second switch SW2 are controlled to be closed and the third comparator COMP3 is enabled through the control instruction (GH1 high level); if the first switching device HS is a PMOS tube, timing starts when the control end signal is detected to be low, and the first switch SW1 and the second switch SW2 are turned off and the third comparator COMP3 is disabled when the control end signal becomes high.

[0099] The second functional module of the first delay simulation sub-circuit BT&CE1 is an analog module used to determine the first fitting current; in the foregoing embodiment, a method for determining the first fitting current has been provided, and accordingly, the analog module can be a programmable logic device developed according to the first fitting current determination method.

[0100] In some embodiments, the analog module of the first delay simulation sub-circuit BT&CE1 can also adopt, for example, Figure 6The circuit design shown includes an AND gate U1 with an inverting input, an operational amplifier U2, a controlled source F1, a resistor R1, and a capacitor C1. The two ends of the capacitor C1 are connected to the control terminals of the first switch SW1 and the second switch SW2, respectively. The input terminal of the AND gate U1 is connected to the control terminal of the first switching device HS, and the inverting input is connected to the output terminal of the timer module. At the moment when the input GL is at a low level, the voltage is transmitted to the capacitor C1 and maintained, i.e., the voltage value equivalent to the current signal detected by the second switching device LS at the falling edge of the GL signal is transmitted to the capacitor C1. When the input GH is at a high level and GH1 is at a low level (inverted to become high), the operational amplifier U2 is enabled, and the capacitor C1 is charged. The input terminals of the operational amplifier U2 are connected to the DC input terminal Vin and the output node SW, respectively, to obtain the voltage difference Vin-Vout. The input control terminal of the controlled source F1 is connected to the output terminal of the operational amplifier U2, and the output terminal is connected to the resistor R1 and the capacitor C1. Therefore, by setting the resistance value of the resistor R1 to match the external inductor L, the current change rate di / dt of the first switching device HS after conduction can be calculated by formula (4), and the first fitting current can be obtained by combining the measured current of the second switching device LS in the previous conduction period.

[0101] di / dt = (Vin-Vout) / R1 (4)

[0102] After a delay of the first blanking time (POCP BT), the first delay analog subcircuit BT&CE1 outputs a GH1 high level signal to close the first switch SW1 and the second switch SW2, and enables the third comparator COMP3. After the first switch SW1 and the second switch SW2 are closed, the third comparator COMP3 can obtain the current of the first switching device HS. Please refer to Figure 5 The third comparator COMP3 has two inverting input terminals and one non-inverting input terminal, and has the functions of detecting current and comparison. The first non-inverting input terminal and the inverting input terminal are connected to the first end and the second end of the first switching device HS to detect the current of the first switching device HS, and then compared with the POCP threshold value connected to the second inverting input terminal. When the current is higher than the POCP threshold value, a CP3 high level signal is output, and when the current is lower than the POCP threshold value, a CP3 low level signal is output.

[0103] The output logic of the second OR gate OR2 is to output a F_POCP high level signal when either the CP3 high level signal or the E_POCP high level signal is enabled and received, and to output a F_POCP low level signal in other cases.

[0104] In some embodiments, similar to the principle of the first detection circuit DC1, please refer to Figure 5, the second detection circuit DC2 comprises: a second delay analog sub-circuit BT&CE2, a third switch SW3, a fourth switch SW4, a fourth comparator COMP4 and a third OR gate OR3; the first non-inverting input terminal of the fourth comparator COMP4 is connected to the second end of the second switching device LS through the fourth switch SW4, the second non-inverting input terminal is connected to the HOCP threshold, the inverting input terminal of the fourth comparator COMP4 is connected to the first end of the second switching device LS through the third switch SW3; the input terminal of the second delay analog sub-circuit BT&CE2 is connected to the control terminal of the second switching device LS, the first output terminal of the second delay analog sub-circuit BT&CE2 is connected to the enable terminal EN4 of the third switch SW3, the fourth switch SW4 and the fourth comparator COMP4, and the second output terminal is connected to the third OR gate OR3; the second delay analog sub-circuit BT&CE2 is used to calculate the second fitting current according to the actually measured current of the second switching device LS in the last conduction period before the second switching device LS is turned on and lasts for the second blanking time, output an E_HOCP low-level signal to the third OR gate OR3 when the second fitting current is higher than the HOCP threshold, and output an E_HOCP high-level signal to the third OR gate OR3 when the second fitting current is lower than the HOCP threshold; and after the second switching device LS is turned on and lasts for the second blanking time, the third switch SW3 and the fourth switch SW4 are controlled to be closed and the fourth comparator COMP4 is enabled, and when the second switching device LS is detected to be turned off, the third switch SW3 and the fourth switch SW4 are controlled to be opened and the fourth comparator COMP4 is disabled; the fourth comparator COMP4 is used to obtain the current of the second switching device LS when enabled, and output a CP4 high-level signal when the current of the second switching device LS is detected to be lower than the HOCP threshold, and output a CP4 low-level signal when disabled and the current of the second switching device LS is higher than the HOCP threshold; the enable terminal OR3EN of the third OR gate OR3 is connected to the control terminal of the second switching device LS, and is enabled when the second switching device LS is turned on, and is not enabled when the second switching device LS is turned off; the third OR gate OR3 outputs a F_HOCP low-level signal when disabled, outputs a F_HOCP low-level signal when enabled and receives the E_HOCP low-level signal and the CP4 low-level signal, and otherwise outputs a F_HOCP high-level signal.

[0105] Specifically, the second delay analog sub-circuit BT&CE2 is configured to issue a control command (GL1 low level) at its first output terminal before the conduction time of the second switching device LS reaches the second blanking time (HOCP BT), causing the third switch SW3 and the fourth switch SW4 to turn off and the fourth comparator COMP4 to be disabled. At this time, the second delay analog sub-circuit BT&CE2 calculates the second fitted current for judgment. Based on the judgment result of the second fitted current, it outputs an E_HOCP high level signal or an E_HOCP low level signal to the third OR gate OR3 through the second output terminal.

[0106] Similar to the first delay analog sub-circuit BT&CE1, the second delay analog sub-circuit BT&CE2 includes two functional modules: a timer module and an analog module. The analog module is used to determine the second fitted current, and the method for determining it has been described in the previous embodiments. Therefore, similarly, the analog module can be a programmable logic device developed based on the method for determining the second fitted current.

[0107] In some embodiments, the analog module of the second delay analog sub-circuit BT&CE2 can also be as follows: Figure 7 The circuit design shown includes an AND gate U4 with an inverted input, an operational amplifier U3, a controlled source F2, a resistor R2, and a capacitor C2. The two ends of the capacitor C2 are connected to the control terminals of the third switch SW3 and the fourth switch SW4, respectively. The input terminal of the AND gate U4 is connected to the control terminal of the second switching device HS. The inverted input terminal is connected to the output terminal of the timer module of the second delay analog sub-circuit BT&CE2. At the instant the input GL1 is high, the voltage is transferred to the capacitor C2 and held. When the input GL is high and GL1 is low (becomes high after inversion), the operational amplifier U3 is enabled, and the capacitor C2 is discharged. The input terminal of the operational amplifier U3 is connected to the output node SW and the ground terminal, respectively, to obtain the output voltage Vout. The input control terminal of the controlled source F2 is connected to the output terminal of the operational amplifier U3, and the output terminal is connected to the resistor R2 and the capacitor C2. Therefore, by setting the resistance value of the resistor R2, the current change rate di / dt of the second switching device LS after conduction can be calculated by formula (5), thereby obtaining the second fitted current.

[0108] di / dt=Vout / R2 (5)

[0109] The second delay analog sub-circuit BT&CE2 is also configured to send a control instruction (GL1 high level) to close the third switch SW3 and the fourth switch SW4 and enable the fourth comparator COMP4 after the on-time of the second switching device LS reaches the second blanking time (HOCP BT), so that the fourth comparator COMP4 can start to acquire the current of the second switching device LS and compare it with the HOCP threshold value; the second delay analog sub-circuit BT&CE2 can also be regarded as a timer, if the second switching device LS is an NMOS tube, the timer starts to count when the control terminal signal of the second switching device LS is detected to be high level, and after the preset time HOCP BT is reached, the third switch SW3 and the fourth switch SW4 are controlled to be closed and the fourth comparator COMP4 is enabled, and when the control terminal signal is low level, it indicates that the second switching device LS is cut off, then the control instruction (GL1 low level) is sent to control the third switch SW3 and the fourth switch SW4 to be disconnected and the fourth comparator COMP4 to be disabled; please refer to Figure 5 The fourth comparator COMP4 has two same-phase input terminals and one opposite-phase input terminal, and has the functions of detecting current and comparison, wherein the opposite-phase input terminal and the first same-phase input terminal are connected to the first end and the second end of the second switching device LS to detect the current of the second switching device LS, and then compared with the HOCP threshold value connected to the second same-phase input terminal, and when the current is lower than the HOCP threshold value, a CP4 high level signal is output, and when the current is higher than the HOCP threshold value, a CP4 low level signal is output.

[0110] The output logic of the third OR gate OR3 is to output a F_HOCP high level signal when the enablement and any one of the CP4 high level signal or the E_HOCP high level signal are received, and output a F_HOCP low level signal in other cases.

[0111] The output results of the first detection circuit DC1 and the second detection circuit DC2 are taken as the inputs of the second logic circuit LC2, if the first control signal is marked as OCP_Faults=1 and the second control signal is marked as OCP_Faults=0, the logic operation of the second logic circuit LC2 is shown in Table 3.

[0112] Table 3: Logic operation of the second logic circuit LC2.

[0113]

[0114] In Table 3, the POCP protection takes effect, which means that when the first fitting current or the first measured current is higher than the POCP threshold value, the first control signal OCP_Faults=1 is used to control the first switching device HS to be turned off and the second switching device LS to be turned on; the HOCP protection takes effect, which means that the first switching device HS remains in the off state until the second fitting current or the second measured current is lower than the HOCP threshold value, and then the normal PWM input signal control is restored; in Table 3, 1→0 is the conversion moment when the POCP protection action is completed and the HOCP protection is about to take effect, at which time the current of the output node SW is less than the POCP threshold value, and F_POCP changes from high level to low level; it should be noted that F_POCP and F_HOCP cannot be 1 at the same time.

[0115] According to the logic operation rules in Table 3, the composition structure of the second logic circuit LC2 can be designed, and in some embodiments, referring to Figure 5 , a circuit scheme is provided, the second logic circuit LC2 includes an RS flip-flop TR, an inverter INV and a fourth OR gate OR4; the S input end of the RS flip-flop TR is connected to the output end of the first detection circuit DC1, the R input end is connected to the output end of the second detection circuit DC2, the output end is connected to the first input end of the fourth OR gate OR4, which is used to input the F_POCP high level signal at the S input end and the F_HOCP low level signal at the R input end, and output the F_POCP1 high level signal when the F_POCP high level signal at the S input end changes to the F_POCP low level signal and the F_HOCP low level signal at the R input end is input; the F_POCP1 low level signal is output when the F_HOCP low level signal at the R input end changes to the F_HOCP high level signal; the input end of the inverter INV is connected to the output end of the third OR gate OR3, the output end is connected to the input end of the fourth OR gate OR4, and the enable end EN-INV is connected to the control end of the second switching device LS, which is used to enable when the second switching device LS is turned on and not to enable when the second switching device LS is turned off; the inverter INV is used to output the F_HOCP1 low level signal when not enabled, and output the F_HOCP1 low level signal when enabled and receiving the F_HOCP high level signal, and output the F_HOCP1 high level signal when enabled and receiving the F_HOCP low level signal; the fourth OR gate OR4 outputs the high level signal OCP_Faults=1 as the first control signal when receiving the F_POCP1 high level signal or the F_HOCP1 high level signal, and outputs the low level signal OCP_Faults=0 as the second control signal when receiving the F_POCP1 low level signal and the F_HOCP1 low level signal.

[0116] The RS flip-flop TR in the above scheme can be an AND-OR RS flip-flop, and in some embodiments, an NAND-OR RS flip-flop or a JK flip-flop can also be used, and then the connection mode of the adaptive adjustment flip-flop and the output end of the first detection circuit DC1 and the output end of the second detection circuit DC2 is adjusted according to the truth table of the two flip-flops.

[0117] In some embodiments, referring to Figure 8 , the intelligent power stage circuit SPS further includes an event detection unit EU and a counting unit NU, the input end of the event detection unit EU is connected with the PWM input end PI, the output end of the first detection circuit DC1 and the output end of the second logic circuit LC2, the output end of the event detection unit EU is connected with the input end of the counting unit NU, for generating and outputting a POCP event signal when detecting a F_POCP high-level signal, and generating and outputting a HOCP event signal when detecting the first control signal and the level of the PWM input signal changes from low to high; the intelligent power stage circuit SPS further includes a monitoring node TMON, the monitoring node TMON is used for connecting an external controller, the output end of the counting unit NU is connected with the monitoring node TMON, for counting the POCP event signal and the HOCP event signal, and sending a report signal to the monitoring node TMON when the counting reaches a preset value.

[0118] Specifically, the event detection unit EU is used for detecting a POCP protection event and a HOCP protection event of the SPS circuit, the detection basis of the POCP protection event is detecting a F_POCP high-level signal, indicating that the first fitting current or the first measured current is higher than the POCP threshold value at this time; the detection basis of the HOCP protection event is continuously detecting the first control signal (such as OCP_Faults is always in a high-level state) and the PWM input signal changes from low to high, as long as the above conditions are met once, the corresponding event signal is sent once, and the counting unit NU is counted by 1 when receiving an event signal, and after accumulating to a preset value, it is indicated that the number of POCP events and / or HOCP events is large and needs to be concerned, and a report signal can be sent to an external controller for error reporting; the specific value of the preset value and the action of the controller after receiving the report signal, such as stopping sending the PWM input signal or recording the report signal, can be configured according to actual needs.

[0119] In some embodiments, referring to Figure 9A circuit structure diagram of a counting unit NU is provided, which comprises a counter CT and a third switching device Q3. An input end of the counter CT is connected to an output end of an event detection unit EU, an output end of the counter CT is connected to a control end of the third switching device Q3, a first end of the third switching device Q3 is connected to a set voltage end Vup, and a second end of the third switching device Q3 is connected to a monitoring node TMON. The counter CT is used to count up when any one of a POCP event signal and a HOCP event signal is acquired. After the count reaches a preset value, the counter CT outputs a high-level signal CO to make the third switching device Q3 conductive, and the voltage of the monitoring node TMON is raised and takes the voltage signal of the set voltage end Vup as a report signal.

[0120] So far, the design principles of the driving unit CU and the detection unit DU have been introduced. In the following embodiment, the complete control flow and application scenarios of the POCP protection and the HOCP protection interlocking provided by the present disclosure will be described in combination with the detailed design of the circuit structure of the Figure 5

[0121] Figure 5 ​The provided SPS circuit provides POCP protection control with a first blanking time (POCP BT), and the control process is as follows: during the process that the level of the PWM square wave from the external controller changes from low to high, when the first reference level PWM_HI of the first comparator COMP1 is exceeded, the VH signal output by the first comparator COMP1 changes from low to high, and the second control signal OCP_Faults output by the fourth OR gate OR4 is low in the case that no POCP or HOCP error occurs, the input end of the AND gate is inverted to high, so that the output signal VH1 of the AND gate at this time depends on the state of the VH signal, and after the GH output by the drive control circuit DCC after the level of the VH signal changes from low to high changes from low to high, the first switching device HS: upper tube changes from closed to open; at the same time, the GH high level signal triggers the first delay analog sub-circuit BT&CE1, and the delay time (POCP BT) of the first delay analog sub-circuit BT&CE1 can be set through a register, before the delay time ends, the first delay analog sub-circuit BT&CE1 outputs a GH1 low level signal through the first output end, and judges the first fitting current, if the first fitting current is higher than the POCP threshold, the E_POCP high level signal is output through the second output end to the second OR gate OR2, otherwise the E_POCP low level signal is output; after the delay time ends, the second output end of the first delay analog sub-circuit BT&CE1 outputs the E_POCP low level signal, and the output signal GH1 of the first output end changes from low to high, GH1 controls the first switch SW1 and the second switch SW2 to be closed and enable COMP3 at the same time, and after being closed, the third comparator COMP3 starts to detect the current of the first switching device HS as the first measured current, at this time, the current of the first switching device HS (equivalent output inductance current) gradually rises, when the current of the first switching device HS exceeds the POCP threshold set by the third comparator COMP3, the level of the output CP3 signal of the third comparator COMP3 changes from low to high, the second OR gate OR2 outputs the F_POCP high level signal, and the event detection unit EU marks the event that F_POCP changes from low to high as a POCP event (POCP Event); since no HOCP event is triggered at this time, the output signal CP4 of the fourth comparator COMP4 and the output signal E_HOCP of the second delay analog sub-circuit BT&CE2 are both in low level state, the third OR gate OR3 outputs the F_HOCP low level signal, so that after the output signal F_POCP of the second OR gate OR2 changes from low to high, the level of the input S / R of the RS flip-flop is 1 / 0, so that the RS flip-flop outputs the F_POCP1 high level signal, and the fourth OR gate OR4 outputs the first control signal OCP_Faults high level.After OCP_Faults becomes high, the inverted input of the AND gate actually inputs a low signal, at this time the output VH1 of the AND gate changes from high to low, and no matter whether the VH signal is high or low, VH1 remains at a low level; on the other hand, since the input signal of the first OR gate OR1 is OCP_Faults high, the output signal VL1 of the first OR gate OR1 changes from low to high, that is, the first switching device HS (upper tube) is finally closed and the second switching device LS (lower tube) is opened, in the process of VH1 changing from high to low to close the first switching device HS, the current of the first switching device HS decreases and is less than the POCP threshold value, so the output F_POCP of the second OR gate OR2 changes from high to low, and at this time the output F_HOCP of the third OR gate OR3 is still low, that is, the two inputs S / R of the RS flip-flop are both 0, at this time the RS flip-flop output remains the last state, the fourth OR gate OR4 still outputs the first control signal, that is, OCP_Faults is still high.

[0122] Meanwhile, the SPS circuit also provides HOCP protection control with a second blanking time (HOCP BT), and the control flow is as follows: as mentioned above, after the fourth OR gate OR4 outputs the first control signal OCP_Faults from low to high, and the output signal VH1 of the AND gate changes from high to low, the first OR gate OR1 obtains the high-level input of OCP_Faults, and the output signal VL1 changes from low to high, and after passing through the drive control circuit DCC, GL changes from low to high, that is, the first switching device HS is closed and the second switching device LS is opened, and then, even if F_POCP changes from high to low, the output OCP_Faults of the fourth OR gate OR4 remains high due to the previous state of the RS flip-flop, the output VH1 of the AND gate with an inverting input end remains low, the output VL1 of the first OR gate OR1 remains high, and therefore the first switching device HS remains in the off state and the second switching device LS remains in the on state; at the same time, the rising edge of the GL level of the control end of the second switching device LS triggers the second delay analog sub-circuit BT&CE2, and the delay time (HOCP BT) of the second delay analog sub-circuit BT&CE2 can be set through a register. Before the delay time ends, the second delay analog sub-circuit BT&CE2 outputs a low-level signal GL1 through the first output end, and obtains the second fitting current for judgment. If the second fitting current is lower than the HOCP threshold, the second delay analog sub-circuit BT&CE2 outputs a high-level signal E_HOCP through the second output end to the third OR gate OR3, otherwise, a low-level signal E_HOCP is output; after the delay time ends, the second output end of the second delay analog sub-circuit BT&CE2 outputs a low-level signal E_HOCP, and the output signal GL1 of the first output end changes from low to high, at the same time, the third switch SW3 and the fourth switch SW4 are closed, and the fourth comparator COMP4 and the inverter INV are enabled, and the fourth comparator COMP4 starts to detect the current of the second switching device LS as the second measured current (corresponding to the current drop process of the output inductor) after being enabled. At this time, the current of the second switching device LS gradually decreases, and when the current is lower than the HOCP threshold set by the fourth comparator COMP4, the output signal CP4 of the fourth comparator COMP4 changes from low to high, and the F_HOCP output by the third OR gate OR3 changes from low to high; as known from the above, at this time, F_POCP is low, and therefore, after F_HOCP changes from low to high, the input end S / R of the RS flip-flop is 0 / 1, the RS flip-flop outputs a low-level signal F_POCP1, and the inverter INV also outputs a low-level signal F_HOCP1, and therefore the fourth OR gate OR4 outputs the second control signal OCP_Faults from high to low, and enters the initial state, and the outputs of the AND gate and the first OR gate OR1 are controlled by the states of the output VH of the first comparator COMP1 and the output VL of the second comparator COMP2, that is, the PWM input signal control is restored.In addition, before the current of the second switching device LS is lower than the HOCP threshold set by the fourth comparator COMP4, the fourth OR gate OR4 keeps outputting the first control signal, i.e., OCP_Faults is always high. At this time, even if the external controller sends a high-level PWM input signal to make the output VH of the first comparator COMP1 high, the output VH1 of the AND gate will not be high because OCP_Faults is always high (and always low after being inverted), thus preventing the first switching device HS from being turned on before the current of the second switching device LS is lower than the HOCP threshold. In the above process, the event detection unit EU marks the event that OCP_Faults is always high and the PWM level changes from low to high as a HOCP event (HOCP Event).

[0123] The SPS circuit also has an event counting and error reporting function, which is described as follows: any one of the POCP event and the HOCP event triggers the counter CT to count. The counter CT can also be set to count the POCP event or the HOCP event through a register. The preset value M of the trigger reporting time can be set through a register. In some embodiments, after the first POCP event or HOCP event is triggered, N cycles can be allowed to pass without triggering, but the counter CT does not clear. The value of N can also be set through a register. When the counter CT reaches the preset value M of the register, the output signal CO of the counter CT changes from low to high to turn on the third switching device Q3, pull up the voltage of the monitoring node TMON to the set voltage Vup, and report to the external controller. In some embodiments, P switching cycles (SW) can be set, and if no POCP event or HOCP event is triggered, the output signal CO of the counter CT changes from high to low, the third switching device Q3 is turned off, and the monitoring node TMON returns to the voltage at which the SPS normally reports the temperature. The value of P can be set through a register.

[0124] The above circuit composition and control scheme have the following three application scenarios in actual application, as shown in Figure 10~Figure 12 In Figure 10~Figure 12 , the waveform PWM represents the normal pulse width signal output by the controller, the waveform SW represents the actual output pulse width of the switching node (i.e., the output node SW), IL is the current waveform of the external inductor L (composed of the current waveform of the first switching device HS and the current waveform of the second switching device LS), ILoad is the current waveform of the load end, TON is the time when the first switching device HS is turned on, and TOFF is the time when the first switching device HS is turned off.

[0125] Scenario 1: Normal response waveform, when the first switch device HS (referred to as upper tube) conduction time TON is longer than the first blanking time, POCP real-time detection and protection can be carried out, that is, POCP can play a role by obtaining the measured current of the upper tube, and HOCP protection with the second blanking time can also play a role, that is, when the current (or inductance current) of the output node SW is greater than the HOCP threshold, the upper tube is not allowed to be turned on.

[0126] Please refer to Figure 10 , in normal circumstances, the conduction time TON of the upper tube or is greater than the first blanking time POCPBT , so the time of POCP RS (Positive Over Current Protection Real Sensing) is greater than 0, that is, there is time for POCP real-time detection and protection when the upper tube is turned on ; since the conduction time of the second switch device LS (referred to as lower tube) or is also greater than the time of HOCP BT , so the time of HOCP RS is greater than 0, that is, there is time for HOCP real-time detection and protection when the lower tube is turned on, that is, the upper tube is not allowed to be turned on when the inductance current IL is greater than the HOCP threshold.

[0127] When the load or other conditions make TON become larger, the inductance current IL becomes larger, when the IL current rises and exceeds the POCPThreshold, the output node SW pulse width will be cut off by closing the upper tube, so that the actual output pulse width is less than the normal pulse width of PWM , which is the normal protection action of POCP; since POCP BT does not change, POCP RS is longer than the detection time POCP RS in normal operation; when the conduction time of the upper tube becomes longer, POCP can normally detect and protect within the conduction time of the upper tube; since the lower tube conduction time is long, even if the upper tube turn-on time is lengthened and occupies some of the lower tube conduction time, but the lower tube conduction time is still greater than the time of HOCP BT , so the HOCP protection can always be in effect .

[0128] Scenario 2: The steady-state TON of the upper tube is small, but the transient TON is large.

[0129] When steady state TON is less than POCP BT, but transient load TON is greater than POCP BT, so POCP protection can play a real-time detection and protection role in transient load by getting the measured current of the upper tube, and in steady state load by getting the fitted current of the upper tube; while for HOCP, it always works, that is, it does not allow the upper tube to open when IL current is greater than HOCP Threshold, regardless of whether the TON of the upper tube is greater than the blanking time.

[0130] Please refer to Figure 11 When steady state Ton is less than POCP BT , it is protected by HOCP, and the lower tube starts to detect and protect the current of the lower tube in real time after the lower tube is turned on for HOCP BT . Since the conduction time of the lower tube is long, the conduction time of the entire lower tube will be longer than the HOCP BT time, and there is time for HOCP real-time detection and protection during the conduction of the lower tube.

[0131] When loading or other conditions cause the TON of the upper tube to increase, at this time TON is greater than POCP BT , so POCP RS time is greater than 0, and POCP can get the measured current during the conduction time of the upper tube to perform real-time detection and protection, and the pulse width of the output node SW at is not clipped because the IL current at this time does not exceed the POCP Threshold, and the output node SW at is skipped because the HOCP protection takes effect, because the corresponding PWM wave is emitted when the IL current is greater than the HOCPThreshold, at this time the upper tube remains in the off state.

[0132] When loading or other conditions cause TON to further increase, at this time TON is still greater than POCP BT , so POCP RS time is greater than 0, that is, there is time for POCP real-time detection and protection during the conduction of the upper tube; it can be seen from Figure 11 that due to the increase of TON , the IL current rises and exceeds the POCP Threshold, so the output node SW at The pulse width at the location is clipped. When the IL current exceeds the POCP Threshold, the pulse width of the output node SW is clipped, which is the protection action of POCP. It should be noted that the output node SW at... The pulse width is skipped because HOCP is active at this time, because... The corresponding PWM waveform output has an IL current greater than the HOCP Threshold.

[0133] Scenario 3: The TON time of the upper tube is very short under any circumstances.

[0134] For example, in COT (Constant On Time) control, since the TON time of the upper transistor is fixed, protection can be provided by obtaining the fitted current of the upper transistor when the TON time is less than the blanking time of the upper transistor; for example, please refer to [link to relevant documentation]. Figure 12 During COT control, each TON ( , , The time is fixed, and TON is always less than POCPBT. POCP protection can be achieved by calculating the fitted current of the upper tube, or HOCP protection can be achieved.

[0135] Taking HOCP protection as an example, the normal operating frequency of the power management system is n MHz. (n>0) When loaded, the COT control mode is to increase the switching frequency. To increase the energy of the injected system, increasing the switching frequency will cause the IL current to gradually rise. When the IL current is still greater than the HOCP Threshold at the moment the PWM waveform is generated, the HOCP protection will take effect, the upper transistor will remain in the off state, and the pulse width of the output node SW will be increased. The pulse width of the output node SW will be ignored or clipped at the beginning to limit the IL current from continuing to rise, thus achieving the purpose of current limiting. After the pulse width of the output node SW is ignored or clipped at the beginning, the IL current will continue to decrease. When the IL current is less than the HOCP Threshold, normal PWM control will resume. When the PWM is emitted again, the pulse width of the output node SW will be ( , , It will respond normally to the PWM pulse width, and during normal control, it will not clip the PWM pulse width of the current segment when the IL current is greater than the HOCP Threshold. Because the lower transistor has a long turn-on time, the entire lower transistor turn-on time will be greater than the HOCP BT time. In other words, even if the switching frequency is further increased, there is still time for HOCP real-time detection and protection when the lower transistor is turned on.

[0136] Secondly, based on the same inventive concept, in another alternative embodiment, please refer to...Figure 13 The application provides a buck over-current protection circuit, comprising a multi-phase controller Controller and at least one intelligent power stage circuit SPS provided by the first aspect, the multi-phase controller Controller comprises a plurality of PWM output terminals, the intelligent power stage circuit SPS comprises a PWM input terminal PI, a direct current input terminal Vin and an output node SW (a switch node), one PWM output terminal is connected with the PWM input terminal PI of one intelligent power stage circuit SPS; the multi-phase controller Controller is used for sending a PWM input signal to the intelligent power stage circuit SPS, and the intelligent power stage circuit SPS is used for outputting an input voltage signal of the direct current input terminal Vin to a load through the output node SW after voltage reduction according to the PWM input signal, and the load comprises at least one of a CPU, a GPU, an NPU and a TPU.

[0137] Figure 14 The application provides an application scheme of an 8+0-phase buck over-current protection circuit for supplying power to a CPU, wherein a multi-phase controller Controller receives a voltage demand instruction of a load CPU through serial voltage identification SVID, a power management bus PMBus and the like, outputs a PWM control signal through a PWM interface, coordinates the work of each phase circuit, realizes accurate regulation and control of an output voltage, and can guarantee stable operation of the multi-phase controller Controller by means of a bias voltage BIAS and the like; in addition, a CS interface of the multi-phase controller Controller is connected with a pin IMON of an intelligent power stage circuit SPS, and is used for current detection and feedback; an AVSEN+ interface and an AVSEN- interface are used for voltage detection and feedback, and the PWM input signal output can be dynamically adjusted according to the working load of the CPU.

[0138] The phase part includes 8 groups of intelligent power stage circuit (SPS) chips, each of which has a power supply pin VCC connected to 5V power supply, an enable pin EN indicating control activation, a PWM input end PI for receiving a PWM input signal of a multiphase controller Controller, a TMON / FLT pin used for temperature fault monitoring in normal control and reporting after the count of POCP events and / or HOCP events reaches a set value, and a current monitoring pin IMON, a reference input pin REFIN, a logic ground pin LGND, a driving power supply pin VDRV, a pin GL, an input voltage end VIN, a bootstrap pin BOOT (for constructing a driving circuit in cooperation with a bootstrap capacitor, etc.), a phase node PHASE, an output node SW (a switching node connected to an external inductor LOUT), a power ground pin PGND, etc. Resistors RTMON and CTMON are used for temperature monitoring, resistor RIMON is used for current monitoring, bootstrap capacitor CBOOT and bootstrap resistor RBOOT are used for assisting in constructing a circuit for driving a high-voltage side MOSFET, inductor LOUT is used for transferring and smoothing output current when the switching device is turned on and turned off, input capacitor CVIN is used for filtering to reduce input voltage fluctuation, output capacitor CVOUT is used for reducing output voltage ripple to make the voltage output to the CPU more stable, bleeder resistor RBLEEDER can assist in stabilizing the output voltage under certain conditions (such as light load, etc.), and the working state of the CPU at the load end can be fed back to the controller through SVID and PMBus, etc. to form closed-loop regulation.

[0139] Briefly, the above voltage reduction overcurrent protection circuit coordinates multiple groups of phase modules (SPS) through the multiphase controller Controller, uses the switching power supply principle, stores energy and filters through inductors, capacitors and other elements, realizes efficient and low-ripple voltage output, accurately supplies power to the CPU load and dynamically adapts to the load change of the CPU load; in this process, the SPS circuit has the protection function of POCP and HOCP interlocking with blanking time and can count and report two kinds of OCP events, which can ensure stable operation of the load.

[0140] Through one or more embodiments of the present disclosure, the present disclosure has the following beneficial effects or advantages.

[0141] 1) The SPS circuit provided by the present disclosure has a peak over current protection (POCP) with a blanking time. When the upper switch HS is on, the first fitting current is used for protection before the on time reaches the first blanking time (POCP BT) to avoid the influence of switching noise. After the on time of the upper switch reaches the first blanking time, the first measured current is used for detection and protection to improve the protection accuracy of the POCP. The protection mechanisms in the two cases are the same, that is, the upper switch is turned off when the current is greater than the POCP threshold, even if the PWM is still high at this time.

[0142] 2) The SPS circuit also has a hysteresis over current protection (HOCP) with a blanking time. After the lower switch LS is on, the second fitting current is used for protection before the on time reaches the second blanking time (HOCP BT) to avoid the influence of switching noise. After the on time reaches the second blanking time, the second measured current is used for detection and protection to improve the protection accuracy of the HOCP. The protection mechanisms in the two cases are the same, that is, the upper switch is not allowed to be turned on when the current is greater than or equal to the HOCP threshold (even if the PWM is high at this time), and the upper switch is allowed to be turned on only when the inductor current is less than the HOCP threshold.

[0143] 3) The SPS circuit also has an OCP event counting and error reporting function. When the number of POCP event / HOCP event triggers reaches a preset value, the TMON signal is pulled high to a defined level Vup. At this time, the multiphase controller Controller can know that the SPS circuit has occurred protection, and can execute the internal action set by it, thereby improving the safety of the SPS circuit.

[0144] Although the preferred embodiments of the present disclosure have been described, those skilled in the art can make additional changes and modifications to the embodiments once they know the basic inventive concept. Therefore, the appended claims are intended to be interpreted as including all changes and modifications falling within the scope of the present disclosure.

[0145] Obviously, those skilled in the art can make various modifications and variations to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure also intends to include these modifications and variations.

Claims

1. An intelligent power stage circuit, characterized by, The drive unit, the first switch device, the second switch device, the detection unit, the PWM input terminal, the direct current input terminal and the output node are included; the input terminal of the drive unit is used for connecting the PWM input terminal to obtain a PWM input signal, the output terminal of the drive unit is connected to the control terminals of the first switch device and the second switch device, the first terminal of the first switch device is connected to the direct current input terminal, the second terminal and the first terminal of the second switch device are connected to the output node, and the second terminal of the second switch device is grounded; The input terminals of the detection unit are respectively connected to the control terminals of the first switch device and the second switch device and the output node, and the output terminal is connected to the drive unit; the detection unit is used for obtaining a first fitting current of the output node before the first switch device is turned on and lasts for a first blanking time, sending a first control signal to the drive unit when the first fitting current is higher than a POCP threshold value, so that the drive unit controls the first switch device to be turned off and the second switch device to be turned on, and obtaining a first measured current of the output node after the first switch device is turned on and lasts for the first blanking time, and sending the first control signal to the drive unit when the first measured current is higher than the POCP threshold value; The first fitting current is determined according to a measured current of the second switch device in a previous conduction period.

2. The intelligent power stage circuit of claim 1, wherein, The detection unit is further used for: obtaining a second fitting current of the output node before the second switch device is turned on and lasts for a second blanking time, continuously sending the first control signal to the drive unit when the second fitting current is higher than a HOCP threshold value, and sending a second control signal to the drive unit when the second fitting current is lower than the HOCP threshold value, so that the drive unit controls the first switch device and the second switch device according to the PWM input signal; obtaining a second measured current of the output node after the second switch device is turned on and lasts for the second blanking time, and sending the first control signal to the drive unit when the second measured current is higher than the HOCP threshold value, and sending the second control signal to the drive unit when the second measured current is lower than the HOCP threshold value; The HOCP threshold value is lower than the POCP threshold value, and the second fitting current is determined according to a measured current of the second switch device in a previous conduction period.

3. The intelligent power stage circuit of claim 2, wherein, The driving unit comprises a comparison circuit, a first logic circuit and a driving control circuit; an input end of the comparison circuit is connected with the PWM input end, and an output end is connected with an input end of the first logic circuit; an input end of the first logic circuit is also connected with an output end of the detection unit, an output end of the first logic circuit is connected with an input end of the driving control circuit, and an output end of the driving control circuit is connected with a control end of the first switch device and a control end of the second switch device; The comparison circuit is used for outputting a VH high level signal when the level of the PWM input signal is higher than a first reference level, outputting a VH low level signal when the level of the PWM input signal is lower than the first reference level, outputting a VL low level signal when the level of the PWM input signal is higher than a second reference level, and outputting a VL high level signal when the level of the PWM input signal is lower than the second reference level; the first reference level is higher than the second reference level; The first logic circuit is used for outputting a VH1 high level signal to the driving control circuit when the second control signal and the VH high level signal are detected, otherwise outputting a VH1 low level signal to the driving control circuit; and outputting a VL1 low level signal to the driving control circuit when the second control signal and the VL low level signal are detected, otherwise outputting a VL1 high level signal to the driving control circuit; The driving control circuit is used for outputting a GH high level signal to make the first switch device conductive according to the VH1 high level signal, outputting a GH low level signal to make the first switch device cut off according to the VH1 low level signal, and outputting a GL high level signal to make the second switch device conductive according to the VL1 high level signal, and outputting a GL low level signal to make the second switch device cut off according to the VL1 low level signal.

4. The intelligent power stage circuit of claim 3, wherein, The comparison circuit comprises a first comparator and a second comparator; a non-inverting input end of the first comparator is connected with the PWM input end, and an inverting input end is connected with the first reference level, and is used for outputting the VH high level signal when the level of the PWM input signal is higher than the first reference level, and outputting the VH low level signal when the level of the PWM input signal is lower than the first reference level; An inverting input end of the second comparator is connected with the PWM input end, and a non-inverting input end is connected with the second reference level, and is used for outputting the VL low level signal when the level of the PWM input signal is higher than the second reference level, and outputting the VL high level signal when the level of the PWM input signal is lower than the second reference level.

5. The intelligent power stage circuit of claim 4, wherein, The first control signal is a high-level signal, and the second control signal is a low-level signal; the first logic circuit comprises an AND gate and a first OR gate, the AND gate comprises an input end and an inverting input end, the input end of the AND gate is connected to the output end of the first comparator, and the inverting input end is connected to the output end of the detection unit, so as to input the level of the first control signal or the second control signal after being flipped into the first comparator; and the output end of the AND gate is connected to the drive control circuit; the input end of the first OR gate is connected to the output end of the detection unit and the output end of the second comparator, and the output end of the first OR gate is connected to the drive control circuit.

6. The smart power stage circuit of claim 2, wherein, The detection unit comprises a first detection circuit, a second detection circuit and a second logic circuit; the input end of the first detection circuit is connected to the control end, the first end and the second end of the first switch device, the output end is connected to the first input end of the second logic circuit, the input end of the second detection circuit is connected to the control end, the first end and the second end of the second switch device, and the output end is connected to the second input end of the second logic circuit; and the output end of the second logic circuit is connected to the drive unit. The first detection circuit is configured to, before the first switch device is turned on and lasts for the first blanking time, acquire a first fitting current of the output node, output a F_POCP high-level signal when the first fitting current is higher than the POCP threshold, and output a F_POCP low-level signal when the first fitting current is lower than the POCP threshold; and after the first switch device is turned on and lasts for the first blanking time, acquire a current of the first switch device as a first measured current, output the F_POCP high-level signal when the first measured current is higher than the POCP threshold, and output the F_POCP low-level signal when the first measured current is lower than the POCP threshold; The second detection circuit is configured to, before the second switch device is turned on and lasts for the second blanking time, acquire a second fitting current of the output node, output a F_HOCP low-level signal when the second fitting current is higher than the HOCP threshold, and output a F_HOCP high-level signal when the second fitting current is lower than the HOCP threshold; and after the second switch device is turned on and lasts for the second blanking time, acquire a current of the second switch device as a second measured current, output the F_HOCP low-level signal when the second measured current is higher than the HOCP threshold, and output the F_HOCP high-level signal when the second measured current is lower than the HOCP threshold; The second logic circuit outputs the first control signal when receiving the F_POCP high-level signal and the F_HOCP low-level signal, maintains outputting the first control signal when the F_POCP high-level signal changes to the F_POCP low-level signal and the F_HOCP low-level signal is received, and outputs the second control signal otherwise.

7. The intelligent power stage circuit of claim 6, wherein, The first detection circuit comprises a first delay analog sub-circuit, a first switch, a second switch, a third comparator and a second OR gate; a non-inverting input terminal of the third comparator is connected to a first terminal of the first switch device through the first switch, a first inverting input terminal of the third comparator is connected to a second terminal of the first switch device through the second switch, a second inverting input terminal is connected to the POCP threshold value, and an output terminal of the third comparator is connected to a first input terminal of the second OR gate; an input terminal of the first delay analog sub-circuit is connected to a control terminal of the first switch device, a first output terminal of the first delay analog sub-circuit is connected to an enable terminal of the third comparator, the first switch and the second switch, and a second output terminal is connected to a second input terminal of the second OR gate; The first delay analog sub-circuit is configured to calculate the first fitting current according to a measured current of the second switch device in a last conduction period before the first switch device is turned on and lasts for the first blanking time, output an E_POCP high-level signal to the second OR gate when the first fitting current is higher than the POCP threshold value, and output an E_POCP low-level signal to the second OR gate when the first fitting current is lower than the POCP threshold value; and after the first switch device is turned on and lasts for the first blanking time, control the first switch and the second switch to be turned on and enable the third comparator, and when the first switch device is detected to be turned off, control the first switch and the second switch to be turned off and disable the third comparator; The third comparator is configured to acquire the current of the first switch device when enabled, output a CP3 high-level signal when the current of the first switch device is detected to be higher than the POCP threshold value, and output a CP3 low-level signal when disabled and when the current of the first switch device is detected to be lower than the POCP threshold value; An enable terminal of the second OR gate is connected to a control terminal of the first switch device, and the second OR gate is enabled when the first switch device is turned on and disabled when the first switch device is turned off; the second OR gate outputs the F_POCP low-level signal when disabled, outputs the F_POCP low-level signal when enabled and when the E_POCP low-level signal and the CP3 low-level signal are received, and otherwise outputs the F_POCP high-level signal.

8. The smart power stage circuit of claim 6, wherein, The second detection circuit comprises a second delay analog sub-circuit, a third switch, a fourth switch, a fourth comparator and a third OR gate; a first non-inverting input terminal of the fourth comparator is connected to a second terminal of the second switch device through the fourth switch, a second non-inverting input terminal is connected to the HOCP threshold value, and an inverting input terminal of the fourth comparator is connected to a first terminal of the second switch device through the third switch; an input terminal of the second delay analog sub-circuit is connected to a control terminal of the second switch device, a first output terminal of the second delay analog sub-circuit is connected to the third switch, the fourth switch and an enable terminal of the fourth comparator, and a second output terminal is connected to the third OR gate; The second delay analog sub-circuit is configured to calculate a second fitting current according to a measured current of the second switch device in a last conduction period before the second switch device is turned on and lasts for the second blanking time, output an E_HOCP low-level signal to the third OR gate when the second fitting current is higher than the HOCP threshold, and output an E_HOCP high-level signal to the third OR gate when the second fitting current is lower than the HOCP threshold; and control the third switch and the fourth switch to be turned on and enable the fourth comparator after the second switch device is turned on and lasts for the second blanking time, and control the third switch and the fourth switch to be turned off and disable the fourth comparator when the second switch device is detected to be turned off; The fourth comparator is configured to acquire a current of the second switch device when enabled, and output a CP4 high-level signal when the current of the second switch device is detected to be lower than the HOCP threshold, and output a CP4 low-level signal when the current of the second switch device is higher than the HOCP threshold when disabled; An enable end of the third OR gate is connected to a control end of the second switch device, and the third OR gate is enabled when the second switch device is turned on and disabled when the second switch device is turned off; the third OR gate outputs the F_HOCP low-level signal when disabled, outputs the F_HOCP low-level signal when enabled and receives the E_HOCP low-level signal and the CP4 low-level signal, and otherwise outputs the F_HOCP high-level signal.

9. The smart power stage circuit of claim 6, wherein, The second logic circuit comprises an RS flip-flop, an inverter and a fourth OR gate; An S input end of the RS flip-flop is connected to an output end of the first detection circuit, an R input end is connected to an output end of the second detection circuit, and an output end is connected to a first input end of the fourth OR gate, configured to output an F_POCP1 high-level signal when the S input end inputs the F_POCP high-level signal, the R input end inputs the F_HOCP low-level signal, and the S input end changes from the F_POCP high-level signal to the F_POCP low-level signal and the R input end inputs the F_HOCP low-level signal; and output an F_POCP1 low-level signal when the R input end changes from the F_HOCP low-level signal to the F_HOCP high-level signal; An input end of the inverter is connected to an output end of the second detection circuit, an output end is connected to an input end of the fourth OR gate, and an enable end is connected to a control end of the second switch device, configured to be enabled when the second switch device is turned on and disabled when the second switch device is turned off; the inverter is configured to output an F_HOCP1 low-level signal when disabled, output the F_HOCP1 low-level signal when enabled and receives the F_HOCP high-level signal, and output an F_HOCP1 high-level signal when enabled and receives the F_HOCP low-level signal. The fourth OR gate outputs a high level signal as the first control signal when receiving the F_POCP1 high level signal or the F_HOCP1 high level signal, and outputs a low level signal as the second control signal when receiving the F_POCP1 low level signal and the F_HOCP1 low level signal.

10. The smart power stage circuit of claim 6, wherein, The event detection unit is connected to the PWM input end, the output end of the first detection circuit and the output end of the second logic circuit, and the output end of the event detection unit is connected to the input end of the counting unit, for generating and outputting a POCP event signal when the F_POCP high level signal is detected, and generating and outputting an HOCP event signal when the first control signal is detected and the level of the PWM input signal changes from low to high; The intelligent power stage circuit further comprises a monitoring node for connecting an external controller, and the output end of the counting unit is connected to the monitoring node, for counting the POCP event signal and the HOCP event signal, and sending a report signal to the monitoring node when the count reaches a preset value.

11. The smart power stage circuit of claim 10, wherein, The counting unit comprises a counter and a third switching device, the input end of the counter is connected to the output end of the event detection unit, the output end of the counter is connected to the control end of the third switching device, and the first end of the third switching device is connected to a set voltage end and the second end is connected to the monitoring node. The counter is used to count up when the POCP event signal or the HOCP event signal is obtained, and the counter controls the third switching device to be turned on when the count reaches the preset value, so that the voltage of the monitoring node rises and the voltage signal of the set voltage end is taken as the report signal.

12. A brownout and overcurrent protection circuit, comprising: The multi-phase controller comprises a plurality of PWM output ends, and the intelligent power stage circuit comprises a PWM input end, a direct current input end and an output node, one of the PWM output ends being connected to the PWM input end of one of the intelligent power stage circuits. The multi-phase controller is used to send a PWM input signal to the intelligent power stage circuit, and the intelligent power stage circuit is used to output an input voltage signal of the direct current input end to a load through the output node after voltage reduction according to the PWM input signal, and the load comprises at least one of a CPU, a GPU, an NPU and a TPU.

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