Motor control method and system and vehicle

Abstract

The invention provides a motor control method and system and a vehicle, and belongs to the technical field of vehicles. According to the embodiment of the invention, task processing sequences of a plurality of kernels are determined, and a first interrupt request is sequentially and circularly sent to the plurality of kernels according to a preset period based on a processing sequence indicated by the task processing sequences; therefore, under the condition that any kernel receives the first interruption request, the motor control signal can be determined based on the current motor operation parameter in the preset period, and the target motor is controlled based on the motor control signal. According to the embodiment of the invention, by accurately setting the interrupt cooperation mechanism among the plurality of kernels, the multi-kernel parallel computing capability of the motor controller can be fully utilized, and rapid and accurate control of the target motor can be realized. Therefore, the problem that the processing speed and the load rate of the single-nuclear motor controller are limited when the switching frequency is increased can be effectively solved, and the system response speed and the motor control precision are further improved.

Description

Technical Field

[0001] The present application relates to the field of vehicle technology, and in particular to a motor control method, system and vehicle. Background Art

[0002] To meet the precise current control, stable torque output, and high-efficiency energy conversion requirements of high-speed motors during operation, third-generation semiconductor materials such as silicon carbide (SiC) and gallium nitride (GaN) are gradually replacing traditional silicon-based IGBTs (Insulated Gate Bipolar Transistors), greatly promoting the increase in the switching frequency of power devices.

[0003] However, current motor drive systems generally use single-core MCUs (Microcontroller Units). In single-core task systems, the increase in the switching frequency of power devices requires the MCU to complete motor control within a shorter computing time window, which may cause a sharp increase in the core load rate and limited processing speed, thereby affecting system stability and motor control accuracy. Summary of the Invention

[0004] The present application provides a motor control method, system and vehicle to solve the problem that current MCUs are difficult to meet motor control requirements under high switching frequencies.

[0005] In order to solve the above problems, this application adopts the following technical solutions:

[0006] In a first aspect, an embodiment of the present application provides a motor control method, which is applied to a motor controller, wherein the motor controller includes multiple cores, and the method includes:

[0007] determining a task processing sequence of the plurality of said cores;

[0008] Based on the processing order indicated by the task processing sequence, the first interrupt request is cyclically sent to the plurality of cores in sequence according to a preset period, so that any core performs the following interrupt processing steps when receiving the first interrupt request:

[0009] Acquiring current motor operating parameters of the target motor, and determining a motor control signal based on the current motor operating parameters within the preset period;

[0010] The target motor is controlled based on the motor control signal.

[0011] In one embodiment of the present application, before the step of determining the task processing sequence of the plurality of cores, the method further includes:

[0012] When it is detected that the clock sources of the multiple cores are inconsistent, time synchronization is performed on the clock sources of the multiple cores.

[0013] In one embodiment of the present application, the step of determining the task processing sequence of the plurality of cores includes:

[0014] The task processing sequence of the plurality of cores is determined based on the core priorities and / or load states corresponding to the plurality of cores.

[0015] In one embodiment of the present application, the plurality of cores are configured with a computing model constructed based on a magnetic field orientation algorithm;

[0016] The step of determining a motor control signal based on the current motor operating parameters includes:

[0017] The current motor operating parameters are input into the calculation model, and the motor control signal is output.

[0018] In one embodiment of the present application, the motor control signal includes a duty cycle;

[0019] The step of controlling the target motor based on the motor control signal includes:

[0020] The duty cycle is updated into a shared register, so that the pulse width modulation unit generates a pulse width modulation signal based on the duty cycle in the shared register, and controls the power driving unit to drive the target motor to operate based on the pulse width modulation signal.

[0021] In one embodiment of the present application, the method further includes:

[0022] When the first interrupt request is sent to any core, an interrupt flag is added to the core, and context information of unfinished tasks of the core is retained.

[0023] In one embodiment of the present application, the method further includes:

[0024] When any of the cores completes the interrupt processing step, the interrupt flag of the core is cleared, and the unfinished tasks of the core are restored based on the context information of the unfinished tasks of the core.

[0025] In one embodiment of the present application, the method further includes:

[0026] If a second interrupt request is received during the execution of the interrupt processing step by any of the cores, the second interrupt request is suspended until the core completes the interrupt processing step, and then the second interrupt request is sent to the core so that the core executes an operation corresponding to the second interrupt request;

[0027] The interrupt priority of the second interrupt request is less than or equal to the interrupt priority of the first interrupt request.

[0028] In a second aspect, based on the same inventive concept, an embodiment of the present application provides a motor control device, which is applied to a motor controller. The motor controller includes multiple cores. The motor control device includes:

[0029] a sequence determination module, configured to determine a task processing sequence of the plurality of cores;

[0030] an interrupt triggering module, configured to cyclically send a first interrupt request to the plurality of cores in sequence according to a preset period based on a processing order indicated by the task processing sequence, so that any core executes an interrupt processing step when receiving the first interrupt request;

[0031] Any of the above-mentioned cores includes an interrupt processing device, wherein the interrupt processing device includes:

[0032] The signal determination module is configured to obtain current motor operating parameters of the target motor upon receiving the first interrupt request, and determine a motor control signal based on the current motor operating parameters within the preset period;

[0033] The motor control module is configured to control the target motor based on the motor control signal.

[0034] In one embodiment of the present application, the motor control device further includes:

[0035] The clock synchronization module is used to synchronize the clock sources of the multiple cores when it is detected that the clock sources of the multiple cores are inconsistent.

[0036] In one embodiment of the present application, the sequence determination module includes:

[0037] A kernel status acquisition submodule, configured to acquire kernel priorities and / or load status corresponding to each of the plurality of kernels;

[0038] The core sequence determination submodule determines the task processing sequence of the plurality of cores based on the core priorities and / or the load status.

[0039] In one embodiment of the present application, the plurality of cores are configured with a computing model based on a magnetic field orientation algorithm; the signal determination module includes:

[0040] The operation submodule is used to input the current motor operating parameters into the operation model and output the motor control signal.

[0041] In one embodiment of the present application, the motor control signal includes a duty cycle; and the motor control module includes:

[0042] The duty cycle update submodule is used to update the duty cycle to the shared register so that the pulse width modulation unit generates a pulse width modulation signal based on the duty cycle in the shared register, and controls the power drive unit to drive the target motor to operate based on the pulse width modulation signal.

[0043] In one embodiment of the present application, the motor control device further includes:

[0044] A flag adding module is used to add an interrupt flag to any core and retain context information of unfinished tasks of the core when the first interrupt request is sent to the core.

[0045] In one embodiment of the present application, the motor control device further includes:

[0046] A flag clearing module is used to clear the interrupt flag of any of the cores when the interrupt processing step is completed, and to resume the unfinished tasks of the core based on the context information of the unfinished tasks of the core.

[0047] In one embodiment of the present application, the motor control device further includes:

[0048] an interrupt request suspending module, configured to, if a second interrupt request is received during the process of any of the cores executing the interrupt processing step, suspend the second interrupt request until the core completes the interrupt processing step, and then send the second interrupt request to the core so that the core executes an operation corresponding to the second interrupt request;

[0049] The interrupt priority of the second interrupt request is less than or equal to the interrupt priority of the first interrupt request.

[0050] In a third aspect, based on the same inventive concept, an embodiment of the present application provides a motor control system, including a motor controller, a sampling unit, and a pulse width modulation unit, wherein the motor controller includes multiple cores; wherein,

[0051] The motor controller is configured to determine a task processing sequence of the plurality of cores; and based on a processing order indicated by the task processing sequence, cyclically send the first interrupt request to the plurality of cores in sequence according to a preset period;

[0052] The motor controller is further configured to send a sampling instruction to the sampling unit when the first interrupt request is sent to any one of the cores;

[0053] The sampling unit is configured to collect current motor operating parameters of the target motor in response to the sampling instruction, and send the current motor operating parameters to the motor controller;

[0054] The motor controller is further configured to send the current motor operating parameters to the kernel;

[0055] Any of the cores is configured to, upon receiving the first interrupt request, execute the following interrupt processing steps: obtaining the current motor operating parameters, and determining a motor control signal based on the current motor operating parameters within the preset period, and sending the motor control signal to the pulse width modulation unit;

[0056] The pulse width modulation unit is configured to generate a pulse width modulation signal based on the motor control signal; and control the target motor based on the pulse width modulation signal.

[0057] In a fourth aspect, based on the same inventive concept, an embodiment of the present application provides a vehicle, including the motor control system proposed in the third aspect of the present application.

[0058] Compared with the prior art, this application has the following advantages:

[0059] An embodiment of the present application provides a motor control method, which determines the task processing sequence of multiple cores and, based on the processing order indicated by the task processing sequence, cyclically sends the first interrupt request to the multiple cores in sequence according to a preset period, so that any core can obtain the current motor operating parameters of the target motor when receiving the first interrupt request, and determine the motor control signal based on the current motor operating parameters within the preset period, and then control the target motor based on the motor control signal. By accurately setting the interrupt coordination mechanism between multiple cores, the embodiment of the present application can fully utilize the multi-core parallel computing capability of the motor controller to achieve fast and accurate control of the target motor. In this way, it can effectively solve the problem of limited processing speed and load rate of the single-core motor controller when the switching frequency is increased, thereby improving the system response speed and motor control accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0061] Figure 1 This is a flowchart of the steps of a motor control method in one embodiment of the present application.

[0062] Figure 2 This is a flowchart of an interrupt processing step in an embodiment of the present application.

[0063] Figure 3 This is a working principle diagram of a dual-core motor controller in one embodiment of the present application.

[0064] Figure 4 This is a schematic diagram of the functional modules of a motor control device in one embodiment of the present application.

[0065] Figure 5 This is a functional module diagram of an interrupt processing device in one embodiment of the present application.

[0066] Figure 6 It is a structural diagram of a motor control system in one embodiment of the present application.

[0067] Figure 7 This is a structural diagram of another motor control system in an embodiment of the present application.

[0068] Figure 8 It is a structural schematic diagram of a vehicle in one embodiment of the present application. DETAILED DESCRIPTION

[0069] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0070] It should be noted that there is an increasing demand for high-frequency, high-efficiency, and miniaturized power electronic equipment, especially in new energy vehicles. This places higher requirements on the switching frequency of power semiconductors, enabling them to play a key role in switching power supplies, inverters, and other motor drive applications, becoming an important technical support for increasing switching frequency.

[0071] On the other hand, the role of the microcontroller unit (MCU) in motor control systems cannot be ignored, especially in processing complex control algorithms to achieve precise control of power semiconductor devices. As switching frequencies increase, the MCU must complete various digital signal sampling, complex control logic calculations, and PWM (Pulse Width Modulation) signal generation within a shorter time window to ensure real-time and efficient motor control response. This requires the MCU to have higher computing power and faster response speed.

[0072] However, the computing power of the MCU itself is limited by the advancement of chip technology. As the overall system load increases, the challenges faced by the MCU also increase accordingly. Not only must it handle basic control tasks, especially under high-frequency switching conditions, but it must also complete the tasks required to execute various control algorithms within a shorter time window, resulting in significantly increased MCU utilization. If the MCU performance is insufficient or task scheduling is inappropriate, it will not be able to meet the real-time requirements of high-frequency switching frequencies and may even introduce additional delays and errors, affecting the control accuracy and efficiency of the drive motor.

[0073] Therefore, MCU performance bottlenecks may become a key factor restricting further increases in switching frequency. Increasing PWM switching frequency by increasing single-core processing speed or optimizing algorithms will lead to increased power consumption of power devices, heat dissipation difficulties, and limited computing resources. This may not meet the requirements of efficient energy conservation and fast dynamic response, especially in certain high-performance applications.

[0074] Currently, permanent magnet synchronous motors (PMSMs) are widely used in electric drive systems for new energy vehicles, and their main drive control programs usually run on single-core microcontroller units (MCUs). Single-core MCUs need to complete multiple tasks required by the control system within a fixed, fast task cycle, including sampling, digital-to-analog conversion, algorithm calculation, PWM duty cycle output, fault diagnosis, and bus communication. They control power devices through gate-level signals to achieve variable frequency speed regulation and precise power output control while ensuring smooth communication operation of the system. However, in single-core task systems, increasing the PWM switching frequency means a shorter calculation time window, which can lead to a sharp increase in the core load rate and limited processing speed. This makes it difficult to simultaneously achieve high-speed response and stability, especially when processing complex and real-time motor control algorithms.

[0075] The inventors also discovered that in traditional MCU dual-core or multi-core system implementation schemes, the dual-core or multi-core architecture is usually utilized in the form of a serial task allocation mechanism. For example, the two or more independent cores integrated in the MCU are clearly divided into functions: for example, one core is dedicated to handling real-time management and control of peripheral interfaces or bus communications to ensure effective data interaction; the other core is focused on executing complex algorithm calculations for motor control or similar applications. Although this conventional design can optimize the task scheduling within the system through the parallel use of multi-core resources, its limitation is that it does not significantly improve the generation rate of the gate-level control signal ultimately output by the control algorithm, that is, the update frequency of the gate signal is not effectively improved, and the program running configuration between the two cores is a typical serial mode, which does not involve parallel collaborative work across cores.

[0076] In response to the problem that current MCUs are unable to meet the motor control requirements under high switching frequencies, this application aims to provide a motor control method that can fully utilize the multi-core parallel computing capabilities of the motor controller by accurately setting the interrupt coordination mechanism between multiple cores to achieve fast and precise control of the target motor, thereby effectively solving the problem of limited processing speed and load rate of single-core MCUs when the switching frequency is increased, and improving system response speed and motor control accuracy.

[0077] Reference Figure 1 , shows a motor control method of the present application, which is applied to a motor controller. The motor controller includes multiple cores. The method includes:

[0078] S101: Determine a task processing sequence for multiple cores.

[0079] In this embodiment, after powering on, the motor controller performs initialization, enables interrupts, and initializes motor control-related system parameters to default values, such as the interrupt flags and register states of each core. After initialization is complete, the motor controller determines the task processing sequence for the multiple cores.

[0080] It should be noted that the task processing sequence is a cyclic sequence, that is, the next core of the last core in the task processing sequence is the first core in the task processing sequence. In this way, the motor controller can sequentially and orderly control multiple cores to perform motor control operations according to the task processing sequence.

[0081] S102: Based on the processing order indicated by the task processing sequence, the first interrupt request is cyclically sent to the multiple cores in sequence according to a preset period, so that any core executes the interrupt processing step when receiving the first interrupt request.

[0082] In this embodiment, after determining the task processing sequence, the motor controller enters an interrupt processing loop phase. During this phase, the motor controller may determine a preset period for sending a first interrupt request to the multiple cores based on the required switching frequency of the power devices. The motor controller then cyclically sends the first interrupt request to the multiple cores in accordance with the preset period and the processing order indicated by the task processing sequence.

[0083] It should be noted that the first interrupt request is an interrupt request for motor control. For any core, if it receives the first interrupt request sent by the motor controller, it will respond immediately and execute the preset interrupt processing steps.

[0084] In this embodiment, by controlling multiple cores to perform parallel calculations and controlling the calculation time interval between two adjacent cores to a preset period, the switching frequency of the power device can be increased exponentially while ensuring that the control period of each core remains unchanged, thereby improving the dynamic response speed and control accuracy of the motor.

[0085] In one example, when a motor controller is configured with two cores, compared to a single-core motor controller and a traditional multi-core motor controller's serial control scheme, the switching frequency of the power device can be increased to twice the original frequency while keeping the control period of the two cores unchanged.

[0086] In this embodiment, referring to Figure 2 , the interrupt processing step may specifically include the following steps:

[0087] S201: Acquire current motor operating parameters of a target motor, and determine a motor control signal based on the current motor operating parameters within a preset period.

[0088] In this embodiment, when the motor controller sends the first interrupt request to any core, it also triggers the sampling unit to perform corresponding data collection operations. Specifically, the motor controller sends a sampling instruction to the sampling unit, which responds to the sampling instruction, collects the current motor operating parameters of the target motor, and sends the current motor operating parameters to the motor controller. The motor controller then transmits the current motor operating parameters to the core.

[0089] In a specific implementation, the current motor operating parameters may include parameters such as the current, voltage, position, and speed of the target motor. After receiving the first interrupt request, any core will execute a preset motor control algorithm based on the current motor operating parameters within a preset period to calculate a motor control signal. The motor control signal may be a duty cycle.

[0090] S202: Control the target motor based on the motor control signal.

[0091] In this embodiment, after calculating the motor control signal, any core can send the motor control signal to the pulse width modulation unit, which generates a PWM signal based on the duty cycle. Based on the PWM signal, the pulse width modulation unit controls the power drive unit to drive the target motor. The power drive unit can be a drive module made of SiC devices, which can achieve higher switching frequency and power density while reducing the size and weight of the heat sink.

[0092] In this embodiment, by precisely setting the interrupt coordination mechanism between multiple cores and fully utilizing the multi-core parallel computing capability of the motor controller, the target motor is controlled in a sequential cycle, which can achieve the following beneficial effects:

[0093] (1) Improve control efficiency and motor performance. By allocating resources and scheduling tasks across multiple cores of the MCU, the switching frequency of the semiconductor can be increased to twice or more of the original frequency while maintaining the control cycle of a single core, thereby improving the dynamic response speed and control accuracy of the motor.

[0094] (2) Reduce core load and improve system stability. By collaborating with multiple cores in parallel, the computing burden can be effectively dispersed, effectively avoiding the problem of excessive core load and decreased system stability caused by increasing the switching frequency in a single-core system.

[0095] (3) Energy saving and efficiency improvement. Compared with solutions such as replacing a high-performance single-core MCU or using FPGA (Field Programmable Gate Array) / DSP (Digital Signal Processing), this implementation can better balance performance and energy consumption without increasing costs, and has better cost-effectiveness and applicability.

[0096] (4) Simplified design. By utilizing the built-in hardware synchronization mechanism of the multi-core MCU, the design complexity of high-frequency gate-level signal generation is simplified, making it easier to implement and maintain.

[0097] This implementation effectively addresses the current challenges single-core MCUs face when increasing switching frequency, such as reduced motor dynamic response, increased time delays, load rate limitations, limited processing speed, and increased power consumption. Furthermore, it addresses the inability of multi-core MCUs' serial operating mode to effectively increase the update frequency of gate control signals. By increasing switching frequency, optimizing energy efficiency, and maintaining system stability, it can significantly advance the development of motor drive control systems for new energy vehicles toward higher speeds and higher power levels.

[0098] In a feasible implementation manner, before S101, the motor control method may further include the following steps:

[0099] S301: When it is detected that the clock sources of multiple cores are inconsistent, time synchronization is performed on the clock sources of the multiple cores.

[0100] In this embodiment, some cores of the motor controller may be configured with independent clock sources, potentially leading to clock source inconsistencies. Therefore, during the initialization phase, the motor controller obtains the clock sources of multiple cores to determine whether they share a common clock source. If inconsistencies are detected among the cores, the clock sources of the multiple cores are synchronized.

[0101] In a specific implementation, the core with the highest core priority among multiple cores can be determined as the reference core, and the clock source of the reference core can be determined as the reference clock source. Then, based on the reference clock source, the clock sources of other cores except the reference core can be synchronized.

[0102] In this embodiment, by selecting and configuring the clock sources of multiple cores, it is possible to ensure that each core operates on the same time base, so that each core can not only independently execute interrupt processing steps, but also flexibly cooperate according to needs, thereby ensuring system stability.

[0103] In a feasible implementation, S101 may specifically include the following sub-steps:

[0104] S101 - 1 : Obtain core priorities and / or load states corresponding to each of the plurality of cores.

[0105] In this embodiment, in order to quickly control the target motor after the motor controller is powered on, the motor controller will obtain the core priority and / or load status corresponding to each core.

[0106] It should be noted that the kernel priority represents the processing priority of each kernel, which determines the priority order of multiple kernels when processing system tasks and requests.

[0107] It should be noted that the load status indicates the load on the core when processing the current task. Specific load statuses include no load, light load, medium load, and high load. Higher load indicates that the core's processing capacity is nearing saturation, and response speed may be reduced accordingly.

[0108] S101 - 2 : Determine a task processing sequence for multiple cores based on core priorities and / or load states.

[0109] In the specific implementation, kernel priority and load status are comprehensively considered, and corresponding weight scores are assigned to each kernel priority and each load status. For each kernel, an evaluation score is calculated based on the first weight score corresponding to the kernel priority and the second weight score corresponding to the kernel load status. Then, based on the evaluation scores corresponding to each kernel, multiple kernels are sorted in descending order to obtain a task processing sequence for the multiple kernels.

[0110] In this embodiment, by comprehensively considering the priority load of each core, the computing resources of multiple cores can be reasonably allocated and effectively utilized after the controller is powered on, thereby improving the execution efficiency of the system and reducing the response time.

[0111] In one feasible implementation, the step of determining the motor control signal based on the current motor operating parameters in S201 may specifically include the following sub-steps:

[0112] S201-1: Input the current motor operating parameters into the calculation model, and output the motor control signal.

[0113] In this embodiment, to enable each core to independently and quickly control the motor, each core is configured with a computational model, wherein the computational model includes but is not limited to one constructed based on a Field-Oriented Control (FOC) algorithm.

[0114] It should be noted that the field-oriented algorithm is an advanced control technology used for AC motor control. The algorithm has the characteristics of accuracy, high performance, high efficiency and high protection, and is suitable for precise control of permanent magnet synchronous motors.

[0115] In the specific implementation, after receiving the current motor operating parameters of the target motor, the kernel can use the calculation model to calculate and analyze the current motor operating parameters within a preset period, and then quickly calculate the appropriate duty cycle based on the operating conditions and performance requirements of the target motor.

[0116] In this embodiment, by configuring a calculation model for each core, each core can execute an independent magnetic field orientation algorithm after receiving the first interrupt request, and calculate the duty cycle quickly and accurately.

[0117] In a feasible implementation, the motor control signal includes a duty cycle, and S202 may specifically include the following sub-steps:

[0118] S202 - 1 : updating the duty cycle to the shared register so that the pulse width modulation unit generates a pulse width modulation signal based on the duty cycle in the shared register, and controls the power drive unit to drive the target motor to operate based on the pulse width modulation signal.

[0119] In this embodiment, the motor controller is provided with a globally shared storage area, and the storage area is configured with shared registers for storing the latest duty cycle calculated by each core.

[0120] It should be noted that the PWM unit and multiple cores all have access to and read and write permissions to the storage area. That is, after calculating the duty cycle, any core can update it in the shared register, allowing any core to update the duty cycle in the shared register. The PWM unit can then generate a corresponding PWM signal based on the latest duty cycle stored in the shared register and send this PWM signal to the power drive unit. This allows the power drive unit to precisely control the on and off states of the power devices within the power drive unit based on the PWM signal, thereby achieving precise control of the motor power.

[0121] In a specific implementation, register updates for multiple cores can occur before or after a core interrupt is processed, and this can be configured based on actual needs. For example, before an interrupt is processed, multiple cores can choose to update their registers to ensure that the latest data is used when processing the interrupt; or after an interrupt is processed, multiple cores can choose to update their registers to ensure that the latest data is used when continuing to execute other tasks.

[0122] It should be noted that no matter whether the register update occurs before or after the interrupt processing, the data in the register can be ensured to be the latest, thereby ensuring that the pulse width modulation unit can generate the corresponding pulse width modulation signal according to the preset period to achieve rapid control of the target motor.

[0123] In a feasible implementation manner, the motor control method may further include the following steps:

[0124] S401: When a first interrupt request is sent to any core, an interrupt flag is added to the core, and context information of unfinished tasks of the core is retained.

[0125] In this embodiment, since any core will immediately process the corresponding interrupt event after receiving the first interrupt request, an interrupt flag will be added to the core to ensure that the core can successfully process the current interrupt event.

[0126] It should be noted that the interrupt event refers to an event to which the motor controller requests the kernel to respond. When the kernel receives the first interrupt request, the kernel responds to the first interrupt request, and the interrupt event processed is an event for controlling the target motor.

[0127] It should be noted that the interrupt flag is a flag or identifier used to identify an interrupt event. In this embodiment, the interrupt flag is used to indicate that the kernel is executing an interrupt processing step.

[0128] In this embodiment, since the interrupt event for controlling the motor belongs to the category with the highest interrupt priority, if the kernel receives the first interrupt request, it will retain the context information of its unfinished tasks to avoid the loss of unfinished tasks during the kernel's execution of the interrupt processing step.

[0129] S402: When any core completes the interrupt processing step, the interrupt flag of the core is cleared, and the unfinished tasks of the core are restored based on the context information of the unfinished tasks of the core.

[0130] In this embodiment, after the kernel processes the interrupt event indicated by the first interrupt request, the interrupt flag of the kernel will be cleared to indicate that the kernel has completed processing the interrupt event; at the same time, the kernel can restore the unfinished tasks that were previously interrupted based on the retained context information of the unfinished tasks, so that the unfinished tasks can continue to run, thereby ensuring system stability.

[0131] In a feasible implementation manner, the motor control method may further include the following steps:

[0132] S501: When any core is executing an interrupt processing step, if a second interrupt request is received, the second interrupt request is suspended until the core completes the interrupt processing step, and then the second interrupt request is sent to the core so that the core executes the operation corresponding to the second interrupt request.

[0133] In this embodiment, the interrupt priority of the second interrupt request is less than or equal to the interrupt priority of the first interrupt request.

[0134] It should be noted that interrupt priority refers to the processing priority set for different types of interrupt events. Based on interrupt priority, the system can respond and handle interrupts appropriately based on their urgency and importance. Interrupt requests with higher interrupt priorities are processed first, while lower priority interrupt requests may be processed only after higher priority interrupts are responded to.

[0135] In this embodiment, a specific interrupt priority can be assigned to each interrupt event in advance. Specifically, the interrupt priority of the first interrupt request can be configured according to actual needs, for example, configured to the highest level of priority to meet motor control requirements.

[0136] In one example, a motor controller is configured with two cores, namely core 1 and core 2. When core 1 responds to a first interrupt request and executes an interrupt processing step, if core 2 triggers a second interrupt request for core 1, core 1 is required to execute the operation corresponding to the second interrupt request. However, since the interrupt priority of the second interrupt request is lower than the interrupt priority of the first interrupt request, core 2 will suspend the second interrupt request until core 1 completes the interrupt processing step, and then send the second interrupt request to core 1. After completing the interrupt processing step, core 1 will also check whether there are other interrupt requests that need to be processed. If it is detected that multiple interrupt requests including the second interrupt request need to be processed, the interrupt event with the highest interrupt priority will be processed first until the interrupt priority of the second interrupt request is the highest, and then the operation corresponding to the second interrupt request will be executed.

[0137] In this embodiment, by setting a corresponding interrupt priority for each interrupt event, it is possible to effectively prevent the core from being interrupted by other interrupt events during the execution of the interrupt processing steps, thereby ensuring that each core can smoothly execute the interrupt processing steps corresponding to the first interrupt request; at the same time, when each core receives multiple interrupt requests, it can process the corresponding interrupt events in sequence and in an orderly manner, thereby ensuring the stable operation of the core.

[0138] In this embodiment, the computing resources of the motor controller can be allocated accurately and timely to ensure that no matter which core receives the first interrupt request, it can respond quickly; at the same time, in order to meet the accuracy requirements of the magnetic field oriented control algorithm, the sampling rate of the sampling unit and the switching frequency of the power drive unit can be set at a sufficiently high level. Through the fine adjustment of the PWM signal, the performance of the motor can be optimized under different working conditions, thereby improving the system response speed and motor control accuracy.

[0139] As an example, see Figure 3 , shows the working principle diagram of a dual-core motor controller. The following is a detailed description of the content in the figure:

[0140] Time axis: The horizontal line in the figure represents the time axis. The time axis does not mark specific time intervals, and this embodiment does not impose any specific restrictions on the selection of time intervals. As an example, the time interval can refer to the triangular wave carrier in the figure. That is, the time interval between two adjacent triangular wave carrier peaks is used as the preset period, and the first interrupt request is cyclically sent to core 1 and core 2 in sequence.

[0141] Core 1 update point: This is the time point indicated by the first row of arrows in the figure. This is the time point when Core 1 updates the duty cycle to the shared register after calculating the duty cycle.

[0142] Core 2 update point: This is the time point indicated by the second arrow in the figure. This is the time point when Core 2 updates the duty cycle to the shared register after calculating the duty cycle.

[0143] Sampling point: The time point pointed by the arrow in the third row of the diagram. This is the time point at which the sampling unit collects the current motor operating parameters of the target motor.

[0144] Interrupt transition flags: The solid and dashed pulse waveforms in the figure represent interrupt transition flags between cores 1 and 2, respectively. At the interrupt time points corresponding to the solid or dashed pulse waveforms, an interrupt transition occurs between cores 1 and 2 of the motor controller. In other words, at any given interrupt time point, one core is processing the interrupt while the other is waiting for it.

[0145] It can be seen that when the motor controller is configured with two cores, by performing resource allocation and task scheduling on the two cores of the motor controller, compared with the serial control scheme of the single-core motor controller and the traditional multi-core motor controller, the switching frequency of the semiconductor can be increased to twice the original frequency while keeping the control cycle of a single core unchanged, thereby improving the dynamic response speed and control accuracy of the motor.

[0146] Secondly, refer to Figure 4 Based on the same inventive concept, an embodiment of the present application provides a motor control device 400, which is applied to a motor controller. The motor controller includes multiple cores. The motor control device 400 includes:

[0147] A sequence determination module 401 is used to determine the task processing sequence of multiple cores;

[0148] An interrupt triggering module 402 is configured to cyclically send the first interrupt request to the plurality of cores in sequence according to a predetermined period based on a processing order indicated by the task processing sequence, so that any core executes an interrupt processing step when receiving the first interrupt request;

[0149] Reference Figure 5 , for any core, an interrupt processing device 500 is configured, and the interrupt processing device 500 includes:

[0150] The signal determination module 501 is configured to obtain current motor operating parameters of the target motor upon receiving the first interrupt request, and determine a motor control signal based on the current motor operating parameters within a preset period;

[0151] The motor control module 502 is configured to control the target motor based on the motor control signal.

[0152] In one embodiment of the present application, the motor control device 400 further includes:

[0153] The clock synchronization module is used to synchronize the clock sources of multiple cores when it is detected that the clock sources of multiple cores are inconsistent.

[0154] In one embodiment of the present application, the sequence determination module 401 includes:

[0155] A kernel status acquisition submodule is used to obtain kernel priorities and / or load status corresponding to each of the multiple kernels;

[0156] The core sequence determination submodule determines the task processing sequence of multiple cores based on the core priority and / or load status.

[0157] In one embodiment of the present application, multiple cores are configured with a computing model based on a magnetic field orientation algorithm; the signal determination module 501 includes:

[0158] The operation submodule is used to input the current motor operating parameters into the operation model and output the motor control signal.

[0159] In one embodiment of the present application, the motor control signal includes a duty cycle; the motor control module 502 includes:

[0160] The duty cycle update submodule is used to update the duty cycle to the shared register so that the pulse width modulation unit generates a pulse width modulation signal based on the duty cycle in the shared register, and controls the power drive unit to drive the target motor to operate based on the pulse width modulation signal.

[0161] In one embodiment of the present application, the motor control device 400 further includes:

[0162] The flag adding module is used to add an interrupt flag to any core and retain context information of unfinished tasks of the core when the first interrupt request is sent to any core.

[0163] In one embodiment of the present application, the motor control device 400 further includes:

[0164] The flag clearing module is used to clear the interrupt flag of the kernel when any kernel completes the interrupt processing step, and resume the unfinished tasks of the kernel based on the context information of the unfinished tasks of the kernel.

[0165] In one embodiment of the present application, the motor control device 400 further includes:

[0166] an interrupt request suspending module, configured to suspend, if a second interrupt request is received during the execution of an interrupt processing step by any core, the second interrupt request until the core completes the interrupt processing step, and then send the second interrupt request to the core so that the core executes an operation corresponding to the second interrupt request;

[0167] The interrupt priority of the second interrupt request is less than or equal to the interrupt priority of the first interrupt request.

[0168] It should be noted that the specific implementation of the motor control device 400 and the interrupt processing device 500 in the embodiment of the present application refers to the specific implementation of the motor control method proposed in the first aspect of the embodiment of the present application, and will not be repeated here.

[0169] Thirdly, refer to Figure 6 Based on the same inventive concept, the embodiment of the present application provides a motor control system 600, including a motor controller 601, a sampling unit 602 and a pulse width modulation unit 603. The motor controller 601 includes multiple cores; wherein,

[0170] The motor controller 601 is configured to determine a task processing sequence for the plurality of cores; and based on a processing order indicated by the task processing sequence, cyclically send the first interrupt request to the plurality of cores in sequence according to a preset period;

[0171] The motor controller 601 is further configured to send a sampling instruction to the sampling unit 602 when sending the first interrupt request to any core;

[0172] The sampling unit 602 is used to collect the current motor operating parameters of the target motor 605 in response to the sampling instruction, and send the current motor operating parameters to the motor controller 601;

[0173] The motor controller 601 is also used to send the current motor operating parameters to the kernel;

[0174] Any core is configured to, upon receiving the first interrupt request, execute the following interrupt processing steps: obtaining current motor operating parameters, and determining a motor control signal based on the current motor operating parameters within a preset period, and sending the motor control signal to the pulse width modulation unit 603;

[0175] The pulse width modulation unit 603 is configured to generate a pulse width modulation signal based on the motor control signal, and control the target motor 605 based on the pulse width modulation signal.

[0176] In this embodiment, by precisely configuring the interrupt coordination mechanism between multiple cores, the multi-core parallel computing capabilities of motor controller 601 can be fully utilized to achieve fast and precise control of target motor 605. This effectively solves the problem of limited processing speed and load rate of a single-core motor controller when the switching frequency is increased, thereby improving system response speed and motor control accuracy.

[0177] In the specific implementation, refer to Figure 7 , which shows a schematic structural diagram of another motor control system. The motor control system 600 further includes a power drive unit 604 and a target motor 605 . The pulse width modulation unit 603 is connected to the target motor 605 via the power drive unit 604 , and the sampling unit 602 is connected to the output terminals of the target motor 605 and the power drive unit 604 , respectively.

[0178] In a specific implementation, the sampling unit 602 may include an A / D sampling subunit and an SPI communication subunit. The A / D sampling subunit may be connected to the output end of the power drive unit 604 via a Hall current sensor and a voltage sensor to collect the three-phase current and bus voltage of the target motor 605, and convert the analog signal (Analog signal) including the three-phase current and bus voltage into a digital signal (Digital signal) before sending it to the motor controller 601. The SPI communication subunit may be connected to the target motor 605 via a rotary encoder. The SPI communication subunit adopts the SPI (Serial Peripheral Interface) protocol to collect the position and speed of the target motor 605 via the rotary encoder, and send the collected position and speed of the target motor 605 to the motor controller 601. After obtaining the above-mentioned current motor operating parameters, the motor controller 601 may pass the current motor operating parameters to the core currently processing the interrupt event for data calculation and processing to obtain a motor control signal.

[0179] In this embodiment, the pulse width modulation unit 603 is used to generate a PWM signal based on the motor control signal (i.e., the duty cycle) sent by any core, and send the PWM signal to the power drive unit 604, so that the power drive unit 604 drives the target motor 605 according to the PWM signal. The target motor 605 includes, but is not limited to, a permanent magnet synchronous motor.

[0180] In this embodiment, the power driving unit 604 may be a driving module made of SiC devices, which can achieve higher switching frequency and power density and reduce the volume and mass of the heat sink.

[0181] In this embodiment, since the motor controller 601 can increase the switching frequency of the power drive unit 604 exponentially while keeping the control period of a single core unchanged, the sampling rate of the sampling unit 602 and the switching frequency of the power drive unit 604 can be set at a sufficiently high level. By fine-tuning the PWM signal, the performance of the target motor 605 can be optimized under different working conditions, thereby improving the system response speed and motor control accuracy.

[0182] In this embodiment, the motor control system may further include a diagnostic protection unit, a controller power supply, a power supply unit, and a CAN communication unit. The diagnostic protection unit is responsible for monitoring and protecting the software and hardware signals of the entire motor control system to ensure its safe and reliable operation. The controller power supply is used to provide power for the motor controller 601. The power supply unit is connected to the positive terminal of the battery to provide power to various components of the motor control system. The CAN communication unit is used to exchange data with other vehicle systems and communicates using the CAN (Controller Area Network) bus.

[0183] It should be noted that the specific implementation of a motor control system 500 in an embodiment of the present application refers to the specific implementation of the motor control method proposed in the first aspect of the aforementioned embodiment of the present application, and will not be repeated here.

[0184] Fourthly, refer to Figure 8 Based on the same inventive concept, an embodiment of the present application provides a vehicle 800, including the motor control system proposed in the third aspect of the present application.

[0185] It should be noted that the specific implementation of the vehicle 800 in the embodiment of the present application refers to the specific implementation of the motor control system 600 proposed in the third aspect of the embodiment of the present application, and will not be repeated here.

[0186] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, apparatuses, or computer program products. Thus, embodiments of the present invention may take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROMs, optical storage, etc.) containing computer-usable program code.

[0187] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the process in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0188] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0189] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0190] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they become aware of the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0191] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or terminal device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or terminal device that includes the element.

[0192] The above is a detailed introduction to the motor control method, system and vehicle provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core ideas. At the same time, for those skilled in the art, according to the ideas of the present invention, there may be changes in the specific implementation methods and application scopes. In summary, the contents of this specification should not be understood as limiting the present invention.

Claims

1. A motor control method, characterized in that: Applied to a motor controller, the motor controller including multiple cores, the method comprising: determining a task processing sequence of the plurality of said cores; Based on the processing order indicated by the task processing sequence, the first interrupt request is cyclically sent to the plurality of cores in sequence according to a preset period, so that any core performs the following interrupt processing steps when receiving the first interrupt request: Acquiring current motor operating parameters of the target motor, and determining a motor control signal based on the current motor operating parameters within the preset period; The target motor is controlled based on the motor control signal.

2. The motor control method according to claim 1, wherein: Before the step of determining the task processing sequence of the plurality of cores, the method further comprises: When it is detected that the clock sources of the multiple cores are inconsistent, time synchronization is performed on the clock sources of the multiple cores.

3. The motor control method according to claim 1, wherein: The step of determining a task processing sequence of the plurality of cores comprises: Obtaining kernel priorities and / or load states corresponding to each of the plurality of kernels; Based on the core priorities and / or the load status, a task processing sequence of the plurality of cores is determined.

4. The motor control method according to claim 1, wherein: A plurality of the cores are each configured with a computational model; The step of determining a motor control signal based on the current motor operating parameters includes: The current motor operating parameters are input into the calculation model, and the motor control signal is output.

5. The motor control method according to claim 1, wherein: The motor control signal includes a duty cycle; The step of controlling the target motor based on the motor control signal includes: The duty cycle is updated into a shared register, so that the pulse width modulation unit generates a pulse width modulation signal based on the duty cycle in the shared register, and controls the power driving unit to drive the target motor to operate based on the pulse width modulation signal. The motor control method according to claim 1 , wherein: The method further comprises: When the first interrupt request is sent to any core, an interrupt flag is added to the core, and context information of unfinished tasks of the core is retained.

7. The motor control method according to claim 6, wherein: The method further comprises: When any core completes the interrupt processing step, the interrupt flag of the core is cleared, and the unfinished task of the core is restored based on the context information of the unfinished task of the core.

8. The motor control method according to claim 1, wherein: The method further comprises: If a second interrupt request is received during the execution of the interrupt processing step by any of the cores, the second interrupt request is suspended until the core completes the interrupt processing step, and then the second interrupt request is sent to the core so that the core executes an operation corresponding to the second interrupt request; The interrupt priority of the second interrupt request is less than or equal to the interrupt priority of the first interrupt request.

9. A motor control system, characterized in that: It includes a motor controller, a sampling unit and a pulse width modulation unit, wherein the motor controller includes multiple cores; wherein, The motor controller is configured to determine a task processing sequence of the plurality of cores; and based on a processing order indicated by the task processing sequence, cyclically send the first interrupt request to the plurality of cores in sequence according to a preset period; The motor controller is further configured to send a sampling instruction to the sampling unit when the first interrupt request is sent to any one of the cores; The sampling unit is configured to collect current motor operating parameters of the target motor in response to the sampling instruction, and send the current motor operating parameters to the motor controller; The motor controller is further configured to send the current motor operating parameters to the kernel; Any of the cores is configured to, upon receiving the first interrupt request, execute the following interrupt processing steps: obtaining the current motor operating parameters, and determining a motor control signal based on the current motor operating parameters within the preset period, and sending the motor control signal to the pulse width modulation unit; The pulse width modulation unit is configured to generate a pulse width modulation signal based on the motor control signal; and control the target motor based on the pulse width modulation signal.

10. A vehicle, characterized in that: Comprising the motor control system as claimed in claim 9.

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