Gate driver and power device

Abstract

The invention relates to the technical field of power semiconductors, and discloses a gate driver and a power device.The gate driver is connected to a power tube and comprises a comparator, a pull-down switch tube, a first path and a second path; the source electrode of the pull-down switch tube is grounded, and the drain electrode of the pull-down switch tube is connected to the grid electrode of the power tube; the first path is provided with an inverter and an MOS (Metal Oxide Semiconductor) tube and is suitable for responding to the high-level signal, and the first path provides charging current for a grid electrode of the pull-down switch tube through the inverter and the MOS tube; the second path is provided with an MOS tube and a diode. The second path directly transfers part of charges stored on the grid electrode of the power tube to the grid electrode of the pull-down switch tube. Therefore, the gate driver realizes charge transfer based on the first path and the second path by controlling the gate of the pull-down switch tube, so that rapid pull-down of the gate voltage is realized on the premise of not increasing static power consumption.

Description

Technical Field

[0001] The present invention relates to the technical field of power semiconductors, and in particular to a gate driver and a power device. Background Art

[0002] In power electronics systems, gate drivers for power devices such as Si-based MOSFETs (silicon-based metal-oxide-semiconductor field-effect transistors), IGBTs (insulated-gate bipolar transistors), and wide-bandgap semiconductors like GaN and SiC are core modules for efficient and reliable switching. Pull-down capability directly determines device shutdown speed, interference immunity, and safety.

[0003] However, in the pursuit of energy efficiency optimization, traditional low-power drive architectures often reduce static losses by reducing drive current or simplifying negative voltage circuits, resulting in significant degradation of pull-down capability, which is manifested in increased shutdown delay, intensified gate voltage oscillation, and even the risk of false turn-on. Summary of the Invention

[0004] The object of the present invention is to overcome the deficiencies of the prior art and provide a gate driver having low power consumption and good pull-down capability.

[0005] In a first aspect, the present application discloses a gate driver connected to a power tube, comprising: a comparator, a pull-down switch tube, a first path, and a second path; the comparator is used to respond to a shutdown signal and output a high-level signal; the source of the pull-down switch tube is grounded, and the drain is connected to the gate of the power tube; the first path is provided with an inverter and a MOS tube M2, and is suitable for responding to the high-level signal, and the first path provides a charging current to the gate of the pull-down switch tube through the inverter and the MOS tube M2; the second path is provided with a MOS tube M1 and a diode, and the second path directly transfers part of the charge stored on the gate of the power tube to the gate of the pull-down switch tube.

[0006] The beneficial effect is that the gate driver of the present application controls the gate of the pull-down switch tube and realizes charge transfer based on the first path and the second path, thereby realizing rapid pull-down of the gate voltage without the need for connecting multiple inverters in series and without increasing static power consumption, so as to achieve high pull-down capability while maintaining low power consumption.

[0007] Furthermore, the inverter includes: a first inverter and a second inverter consisting of a MOS transistor M2 and a MOS transistor M3, and is adapted to charge and discharge the gate of the pull-down transistor after receiving the output signal of the first inverter; one end of the first resistor is connected to the drain of the MOS transistor M3, and the other end is connected to the gate of the pull-down switch transistor; when the high-level signal is received, the MOS transistor M2 is turned on and the MOS transistor M3 is turned off, forming a charging loop for the gate-source capacitance of the pull-down switch transistor through the second inverter.

[0008] Furthermore, the gate of the MOS tube M1 directly receives the high-level signal, and the source is connected to the gate of the pull-down switch tube; the anode of the diode is connected to the gate of the power tube, and the cathode is connected to the drain of the MOS tube M1; when the high-level signal is received, the MOS tube M1 is turned on, and a low-resistance channel is formed between the gate of the power tube and the gate of the pull-down switch tube. The diode is in a forward biased state, so that part of the charge on the gate of the power tube is directly injected into the gate of the pull-down switch tube through the MOS tube M1.

[0009] Furthermore, a second resistor is included, which is connected between the gate of the pull-down switch tube and the ground. The second resistor is used to maintain the gate of the pull-down switch tube close to the ground potential in an inactive state.

[0010] Furthermore, the pull-down switch tube is an N-channel MOS tube.

[0011] Furthermore, when the gate voltage of the power tube is higher than the sum of the gate-source voltage of the pull-down switch tube and the forward voltage drop of the diode, the diode remains forward biased, and the second path continues to transfer the charge of the power tube gate to the gate of the pull-down switch tube.

[0012] In a second aspect, the present application discloses a power device, comprising: the gate driver and the power tube, wherein the gate driver is connected to the gate of the power tube to control the on and off of the power tube. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a schematic diagram of a gate driver circuit according to some embodiments of the present application; Figure 2 is a schematic diagram of a partial circuit of a power device according to some embodiments of the present application; In the figure: 100-gate driver, 11-first inverter, 12-comparator. DETAILED DESCRIPTION

[0014] The following will clearly and completely describe the technical solutions of the present invention in conjunction with the embodiments. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work shall fall within the scope of protection of the present invention.

[0015] First, some professional terms are explained.

[0016] Pull-down capability: The ability to quickly and stably reduce the gate voltage of a power device from above the operating threshold to below the cut-off threshold through an internal discharge loop or an external auxiliary circuit.

[0017] Comparator: A circuit or device that can compare two or more data items to determine whether they are equal. Its output control signals include high-level signals and low-level signals.

[0018] ‌ Figure 1 Where VDD2 represents the power supply voltage.

[0019] Next, see Figure 1-Figure 2 , understand the gate driver 100 and power device disclosed in the embodiments of the present application.

[0020] In high-speed power conversion systems, such as server power supplies, motor drives, or high-frequency DC-DC converters, the switching speed of power MOSFETs directly impacts system efficiency and reliability. Switching losses are proportional to the switching time, especially during the shutdown process. If the gate charge of the power transistor cannot be quickly removed, the slow shutdown process will not only generate significant crossover losses but may also lead to bridge arm shoot-through.

[0021] Traditional solutions rely on a series inverter chain to increase pull-down drive capability, but each inverter stage introduces additional delay and static power consumption; if low power consumption is to be maintained, it is difficult to achieve good pull-down capability.

[0022] To this end, the embodiment of the present application discloses a gate driver 100 connected to a power tube (such as M5), referring to Figure 1-Figure 2 As shown, it includes: a comparator 12, a pull-down switch tube, a first path and a second path. Figure 2 In the figure, VDD1 and VDD2 are both power supplies, GATE is the gate signal, and POWER is an intuitive indication that the power tube M5 can be used as an energy source.

[0023] The comparator 12 is used to output a high level signal in response to the shutdown signal, such as Figure 1The output of the high-level signal V1; the source of the pull-down switch is grounded, and the drain is connected to the gate of the power tube (such as M5). Here, the shutdown signal is a signal that needs to shut down the driver, which can be any signal form.

[0024] The first path is adapted to provide a charging current to the gate of the pull-down switch (e.g., M4) via a second inverter composed of MOS transistors M2 and M3 in response to a high-level signal output by the comparator 12; in some examples, the first path is provided with only two inverters, namely, a first inverter 11 and a second inverter composed of MOS transistors M2 and M3; it is understandable that the provision of MOS transistors M2 and M3 actually realizes the function of an inverter, which is different from the prior art of providing multiple inverters in series. Figure 1 The following examples will be used for illustration.

[0025] The second path is adapted to directly transfer a portion of the charge stored on the gate of the power transistor (e.g., M5) to the gate of the pull-down switch transistor (e.g., M4) via a MOS transistor (e.g., M1) and a diode (e.g., D1) in response to the high-level signal output by comparator 12. Thus, the first path and the second path work together to accelerate the increase in the gate voltage of the pull-down switch transistor (e.g., M4), thereby enhancing its ability to pull down the gate of the power transistor (e.g., M5).

[0026] It can be understood that the gate driver 100 of the embodiment of the present application controls the gate of the pull-down switch tube and realizes charge transfer based on the first path and the second path, thereby realizing rapid pull-down of the gate voltage without the need for connecting multiple inverters in series and without increasing static power consumption, thereby achieving high pull-down capability while maintaining low power consumption.

[0027] Next, Figure 2 Taking the corresponding local circuit of the power device as an example, when the comparator 12 detects a signal that needs to turn off the power tube M5 (outputs a high-level signal), the drive circuit is activated, and its goal is to charge the gate capacitance of the power tube M5.

[0028] For example, it is described by taking M4 as an N-channel MOS transistor, MOS transistors M2 and M3 forming a second inverter, MOS transistor M2 as a P-channel MOS transistor, MOS transistor M3 as an N-channel MOS transistor, and MOS transistor M1 as an N-channel MOS transistor as an example.

[0029] like Figure 1One end of resistor R1 is connected to the drain of MOS transistor M3, and the other end is connected to the gate of M4. One end of resistor R2 is connected to the gate of M4, and the other end is connected to ground. The drain of MOS transistor M1 is connected to the gate of power transistor M5 via diode D1. The source of MOS transistor M1 is connected to the gate of M4. MOS transistors M2 and M3 form a second inverter connected to the gate of M4. The driver input is connected to the gate of MOS transistor M1 and to the gates of MOS transistors M2 and M3 via first inverter 11. Therefore, this example only has two inverters, eliminating the problem of increased power and delay caused by multiple inverters.

[0030] When the comparator 12 outputs a high level, it means that the gate of the power transistor M5 needs to be pulled down to ground. When the comparator 12 outputs a low level, the drive circuit does not operate. Resistor R2 acts as a pull-down resistor to ensure that the gate of the MOS transistor M4 is at a low level, preventing the drive circuit from malfunctioning due to interference.

[0031] Specifically, during operation, the pull-down transistor M4 is turned on, and the gate of the pull-down MOS transistor M4 is charged through two paths. The first path includes the first inverter 11, the MOS transistor M2, and the MOS transistor M3 (the two constitute a second inverter), and the second path is composed of the diode D1 and the MOS transistor M1. Thus, by directly extracting the charge stored in the gate of the power transistor M5, the gate of the pull-down MOS transistor M4 is charged simultaneously by the two paths, thereby increasing the pull-down capability of the pull-down MOS transistor M4.

[0032] Specifically, when the comparator 12 outputs a high level, the comparator 12 outputs a high level signal to the first path, in which: A high-level signal acts on the gates of MOS transistors M2 and M3. This signal undergoes logic level conversion via the first inverter 11, generating a low-level signal that is applied to the gates of MOS transistors M2 and M3. Consequently, MOS transistor M2 enters a conductive state due to the low-level signal received by its gate, with the conductive path connecting the power supply voltage VDD2 to the gate of M4. Simultaneously, MOS transistor M3 remains in a cutoff state due to the same low-level signal received by its gate. This circuit configuration, through the conduction of MOS transistor M2, enables a charging path from VDD2 to the gate capacitance of M4, thereby establishing a gate bias voltage for M4.

[0033] Accordingly, the high level output by comparator 12 directly acts on the gate of MOS transistor M1, transferring charge through the second path and immediately turning on MOS transistor M1. In the second path, the source of MOS transistor M1 is connected to the gate of M4, and the drain is connected to the gate of power transistor M5 via diode D1. Thus, when MOS transistor M1 is turned on, the gate of power transistor M5 stores a high charge (corresponding to its on-state) and has a high voltage. The initial voltage of M4's gate is close to ground (maintained by R2). When MOS transistor M1 is turned on, a low-resistance channel is formed between its drain and source. Diode D1 points from the gate of M5 to the drain of MOS transistor M1 and is in a forward biased state at that moment.

[0034] As a result, the circuit directly uses the charge to be released stored on the gate of power tube M5 as an energy source to accelerate the opening of switch M4, which is responsible for pulling it down. As a result, part of the charge on the gate of M5 is not slowly released to ground first, but is directly extracted and injected into the gate capacitance of M4. In this way, the directly injected charge raises the gate voltage of M4 at a speed far exceeding that of charging through MOS tube M2 alone, causing M4 to reach a strong on state more quickly. Before M4 is fully turned on, part of the charge on the gate of M5 has been transferred and consumed.

[0035] Furthermore, the first path and the second path cooperate to form positive feedback, that is, as described in the above embodiment, in the initial stage, the first path and the second path simultaneously inject charge into the gate capacitance of M4, and the gate voltage of M4 begins to rise.

[0036] When M4 starts to pull down the gate voltage of M5, its gate voltage begins to drop; however, as long as the gate voltage of M5 is still significantly higher than the sum of the gate-source voltage of M4 and the forward voltage drop of diode D1, diode D1 remains forward biased. Therefore, the drop in the gate voltage of M5 will continue to transfer charge to the gate capacitance of M4 through the second path to continue to increase the gate voltage of M4. The higher gate voltage means that M4 has a smaller on-resistance and a stronger pull-down capability, thereby being able to pull down the gate voltage of M5 at a faster rate.

[0037] A power device according to an embodiment of the present application includes the gate driver 100 and the power tube described in the above embodiment, wherein the gate driver 100 is connected to the gate of the power tube to control its on and off; for example Figure 2 The power device shown may be any component or device used to configure the gate driver 100 .

[0038] The foregoing description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the form disclosed herein and should not be construed as excluding other embodiments. Rather, the present invention can be used in various other combinations, modifications, and environments and can be modified within the scope of the concept described herein through the above teachings or techniques or knowledge in the relevant field. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention are intended to be protected by the appended claims.

Claims

1. A gate driver connected to a power tube, characterized in that: include: a comparator configured to respond to a shutdown signal and output a high-level signal; a pull-down switch tube, wherein the source of the pull-down switch tube is grounded, and the drain is connected to the gate of the power tube; a first path, wherein the first path is provided with an inverter and a MOS transistor and is adapted to respond to the high-level signal, and the first path provides a charging current to the gate of the pull-down switch transistor through the inverter and the MOS transistor; and a second path, wherein the second path is provided with a MOS tube and a diode, and the second path directly transfers part of the charge stored on the gate of the power tube to the gate of the pull-down switch tube.

2. The gate driver according to claim 1, wherein: The inverter comprises: a first inverter; and a second inverter composed of a MOS transistor M2 and a MOS transistor M3, wherein at least one of the MOS transistor M2 and the MOS transistor M3 has an output end of the first inverter and is adapted to charge and discharge the gate of the pull-down transistor after receiving an output signal of the first inverter; a first resistor, one end of which is connected to the drain of the MOS transistor M3, and the other end of which is connected to the gate of the pull-down switch transistor; When receiving the high level signal, the MOS transistor M2 is turned on and the MOS transistor M3 is turned off, forming a charging loop for the gate-source capacitance of the pull-down switch transistor through the second inverter.

3. The gate driver according to claim 1 or 2, wherein: The MOS transistor provided in the second path is a MOS transistor M1, the gate of the MOS transistor M1 directly receives the high-level signal, and the source is connected to the gate of the pull-down switch transistor; The anode of the diode is connected to the gate of the power tube, and the cathode is connected to the drain of the MOS tube M1; When receiving the high-level signal, the MOS tube M1 is turned on and a low-resistance channel is formed between the gate of the power tube and the gate of the pull-down switch tube. The diode is in a forward biased state, so that part of the charge on the gate of the power tube is directly injected into the gate of the pull-down switch tube through the MOS tube M1.

4. The gate driver according to claim 1, wherein: The device further includes a second resistor connected between the gate of the pull-down switch tube and the ground. The second resistor is used to maintain the gate of the pull-down switch tube close to the ground potential in an inactive state.

5. The gate driver according to claim 1, wherein: The pull-down switch tube is an N-channel MOS tube.

6. The gate driver according to claim 1, wherein: When the gate voltage of the power tube is higher than the sum of the gate-source voltage of the pull-down switch tube and the forward voltage drop of the diode, the diode remains forward biased, and the second path continues to transfer the charge of the power tube gate to the gate of the pull-down switch tube.

7. A power device, characterized in that: include: The gate driver and the power tube according to any one of claims 1 to 6, wherein the gate driver is connected to the gate of the power tube to control its on and off.

Images