Central node-free distributed clock phase synchronization method

Abstract

The application discloses a center node-free distributed clock phase reference synchronization method and belongs to the technical field of clock synchronization. The method comprises the following steps: step 1, clock phase reference synchronization; step 2, time system synchronization; and step 3, multi-node synchronization. According to the application, the clock phase reference synchronization and the relative time system synchronization of multiple stations are simultaneously performed, high-precision clock frequency synchronization between stations is realized, a stable and accurate clock source is provided between devices, errors caused by different clock oscillators of the transmitting and receiving parties are reduced, the transmission and reception of information between unmanned aerial vehicles are guaranteed, and the problem that a clock cannot be synchronized when a satellite navigation signal is interfered with in the prior art is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of clock synchronization, in particular to a centerless node distributed clock phase synchronization method. BACKGROUND

[0002] In recent years, the development of war form has a clear trend of changing from "humanization" to "unmanned", and unmanned aerial vehicle combat as an important part of "unmanned" combat is particularly important.

[0003] The development of swarm intelligence technology inspired by bees, ants and other organisms promotes the research of new organizational architecture of unmanned aerial vehicles, and proposes a distributed control formation mechanism of centerless node composed of multiple small unmanned aerial vehicles, based on information sharing calculation decision, individual task planning and realization of individual and cluster target cooperation. This control and decision mechanism based on cluster and distribution has good redundancy and linkage. Whether it is a traditional formation mode or a cluster distribution mode, the clock synchronization accuracy is an important prerequisite for realizing real-time and accurate cluster control.

[0004] The time system, also known as the time-frequency system or the time-unified system, is a system that can provide standardized time and frequency signals to make the entire system coordinated and unified in time and frequency. With the wide application of distributed systems in radar detection, Internet of Things, industrial automation and other fields, high-precision clock synchronization between multiple nodes has become a key technology for data consistency, signal level phase synchronization fusion and system performance improvement. At present, time-unification between devices is generally achieved through satellite navigation. The synchronization accuracy of GPS is generally 100-150ns, which is not high and is easily affected by the ionosphere at high altitudes, resulting in further decrease in accuracy.

[0005] At present, time-unification between devices is generally achieved through satellite navigation, which has the following problems. 1) Strong dependence, clock synchronization depends on satellite navigation system, and it is difficult to maintain clock synchronization if satellite navigation signal is disturbed; 2) Low accuracy, satellite navigation clock synchronization accuracy is generally 100-150ns, which is low and easily affected by complex environment; 3) Greatly affected by environment, time synchronization must be performed in open outdoor sites. SUMMARY

[0006] The centerless node distributed clock phase synchronization method provided by the embodiments of the present application solves the problem that the clock synchronization is difficult to maintain if the satellite navigation signal is disturbed in the prior art, and reduces the error caused by the difference between the clock oscillators of the transmitting and receiving parties.

[0007] The embodiment of the present application provides a centerless node distributed clock phase synchronization method, comprising the following steps: step 1, clock phase synchronization: a receiving end generates a synchronization carrier according to a received original carrier and takes the synchronization carrier as a local clock reference of the receiving end, so that the receiving end is synchronized with a transmitting end clock; step 2, time synchronization: the transmitting end modulates a synchronization carrier to obtain a linear frequency modulation second pulse signal and broadcasts the linear frequency modulation second pulse signal, when the receiving end receives the linear frequency modulation second pulse signal, the receiving end performs frequency down conversion on the linear frequency modulation second pulse signal according to the synchronization carrier to obtain a baseband time domain signal, performs matched filtering on the baseband time domain signal, generates a time domain narrow pulse, extracts a second pulse moment from the time domain narrow pulse, and synchronizes the receiving end with the transmitting end time system; step 3, multi-node synchronization: time of signal transceiving moments of each node is marked, transmission time delay and inherent time delay are deducted, and initial clock deviation between nodes is calculated, so that the distributed nodes are synchronized in the time system.

[0008] Further, the transmitting end is a dynamic reference node; the dynamic reference node is obtained through the following steps: each node periodically broadcasts a clock stability evaluation parameter of the node, and the clock stability evaluation parameter is received by a neighbor node; a stability score of each node is obtained, and a node with the highest stability score is recorded as the dynamic reference node.

[0009] Further, the stability score is obtained according to the following formula: ; wherein S is the stability score, and is a weight, is a crystal oscillator temperature drift rate, is a crystal oscillator frequency deviation, is a crystal oscillator temperature change amount, is a phase noise power spectral density. Further, the update period of the dynamic reference node satisfies: ; wherein is a maximum frequency drift rate, is a maximum phase jitter frequency.

[0010] Further, the generating the synchronous carrier wave and taking it as the local clock reference of the receiving end comprises the following steps: when the receiving end receives the original carrier wave modulated by BPSK through the channel of the data link, performing double frequency processing on the original carrier wave modulated by BPSK to obtain a single carrier wave signal converted by the BPSK modulated signal, and inputting the single carrier wave signal into a Costas phase-locked loop to obtain an output signal; the receiving end divides the output signal by two to recover the carrier wave to obtain the synchronous carrier wave; by detecting the phase difference between the synchronous carrier wave and the original carrier wave of the transmitting end, if the phase difference is constant for a long time, it is determined that the two are the same frequency and in phase; and the receiving end takes the recovered synchronous carrier wave as the local clock reference. Further, the step of inputting the single carrier wave signal into the Costas phase-locked loop to obtain the output signal comprises: generating a phase error signal by comparing the phase of the double frequency signal with the output signal of the voltage-controlled oscillator through a phase detector; filtering high-frequency noise in the phase error signal through a low-pass filter to output a smooth control voltage; adjusting the voltage-controlled oscillator according to the smooth control voltage, so that the real-time output frequency of the voltage-controlled oscillator gradually approaches the double frequency target value of the original carrier wave; and obtaining the output signal from the voltage-controlled oscillator.

[0011] Further, the generating the time domain narrow pulse comprises the following steps: performing Fourier transform on the baseband time domain signal to obtain a baseband frequency domain signal ; multiplying the baseband frequency domain signal with a matched filter function to obtain a compressed signal spectrum ; ; performing inverse Fourier transform on the compressed signal spectrum to generate the time domain narrow pulse.

[0012] Further, the matched filter function is: ; wherein, rect is a rectangular window function, f is a signal frequency domain variable, k is a frequency modulation rate of the linear frequency modulation second pulse signal, T is a transmitting pulse width, j is an imaginary unit, π is a circular constant, is a windowing function used for suppressing the edge mutation of the spectrum.

[0013] Further, the deducting the transmission delay and the inherent delay and calculating the initial clock deviation between the nodes comprises the following steps: sending a probe signal by node A at a first local time, and receiving the probe signal by node B at a second local time; calculating the clock deviation according to the second local time marked by the second pulse extracted by node B, in combination with the signal propagation delay and the inherent delay.

[0014] Further, the formula for calculating the clock deviation is: ; wherein, is the clock deviation, is the first local time, is the second local time, is the signal propagation delay, For the inherent time delay.

[0015] The one or more technical solutions provided in the embodiments of the application have at least the following technical effects or advantages:

[0016] 1. By using the multi-station cooperative clock phase synchronization technology, high-precision clock frequency synchronization between stations is achieved, a stable and accurate clock source is provided between devices, errors caused by different clock oscillators of the transmitting and receiving parties are reduced, and the transmission and reception of information between unmanned aerial vehicles are ensured, effectively solving the problem that the clock synchronization is difficult to maintain when the existing technology is disturbed by a satellite navigation signal.

[0017] 2. By using the multi-station cooperative clock synchronization technology, high-precision clock synchronization is achieved, all nodes in the system are managed and distributed in the same clock domain, and the clock synchronization precision is high and the anti-interference ability is strong.

[0018] 3. By using a centerless distributed multi-node, it is not necessary to rely on a specific device, and the system robustness is improved. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 Flow chart of the centerless node distributed clock phase synchronization method

[0020] Figure 2 Schematic diagram of node active time service

[0021] Figure 3 Block diagram of clock phase synchronization implementation principle

[0022] Figure 4 Block diagram of time synchronization implementation

[0023] Figure 5 Matching filter principle diagram

[0024] Figure 6 Time domain spectrum of the baseband modulated signal of embodiment 1

[0025] Figure 7 Spectrum diagram of the modulated signal with added noise of embodiment 1

[0026] Figure 8 Phase-locked loop carrier extraction of embodiment 1

[0027] Figure 9 Signal spectrum after frequency division of embodiment 1

[0028] Figure 10 Comparison of the carrier of the transmitting end and the extracted carrier of the receiving end of embodiment 1

[0029] Figure 11 Phase difference output of embodiment 1

[0030] Figure 12 Transmit-receive carrier error standard deviation for example 1;

[0031] Figure 13 Linear frequency modulation signal generation for the transmit end of example 2;

[0032] Figure 14 Down-converted baseband signal for example 2;

[0033] Figure 15 Frequency domain filtering of correlation peaks for example 2. DETAILED DESCRIPTION

[0034] The embodiments of the present application provide a centerless node distributed clock phase reference synchronization method, which solves the problem that in the prior art, when a satellite navigation signal is interfered, it is difficult to maintain clock synchronization. Through multi-station coordinated clock phase reference and relative time system synchronization, the clock synchronization accuracy of each device in the system is effectively improved, the hardware complexity is reduced, and the system work efficiency is improved.

[0035] In order to better understand the above technical solutions, the above technical solutions will be described in detail below in combination with the drawings of the specification and specific embodiments.

[0036] As shown in Figure 1 The embodiments of the present application provide a centerless node distributed clock phase reference synchronization method, which includes the following steps: step 1, clock phase reference synchronization: the receiving end generates a synchronization carrier according to the received original carrier and uses it as a local clock reference of the receiving end, so that the receiving end is synchronized with the transmitting end clock; step 2, time system synchronization: the transmitting end modulates to obtain a linear frequency modulation second pulse signal based on the synchronization carrier and broadcasts it, when the receiving end receives the second linear frequency modulation second pulse signal, it performs down-conversion to obtain a baseband time domain signal according to the synchronization carrier, performs matched filtering on the baseband time domain signal, generates a time domain narrow pulse, extracts the second pulse moment from the time domain narrow pulse, and makes the receiving end and the transmitting end time system synchronization; step 3, multi-node synchronization: mark the time of the signal transmission and reception time of each node, deduct the transmission delay and inherent delay, and calculate the initial clock deviation between nodes, so that the distributed nodes are time system synchronized.

[0037] Further, the transmitting end is a dynamic reference node; the dynamic reference node is obtained by the following steps: each node periodically broadcasts its clock stability evaluation parameter, and the clock stability evaluation parameter is received by the neighbor node; the stability score of each node is obtained, and the node with the highest stability score is recorded as the dynamic reference node.

[0038] Further, the formula for obtaining the stability score is: ; wherein S is the stability score, and is the weight. is the temperature drift rate of the crystal oscillator, is the frequency deviation of the crystal oscillator, is the temperature variation of the crystal oscillator, is the phase noise power spectral density.

[0039] Further, the update period of the dynamic reference node satisfies: ; wherein is the maximum frequency drift rate, is the maximum phase jitter frequency.

[0040] In the embodiment, the dynamic reference node is taken as the center node, and the clock synchronization between nodes can be realized by the way that the center node actively provides time service and the sub-nodes passively receive, as shown in Figure 2 , and the clock deviation is finally solved as , and the number of supported nodes is greater than or equal to 32.

[0041] Further, as shown in Figure 3 , the step of generating the synchronization carrier and taking it as the local clock reference of the receiving end comprises the following steps: when the receiving end receives the original carrier modulated by BPSK through the channel of the data link, the original carrier modulated by BPSK is subjected to a frequency doubling process to obtain a single carrier signal converted from the BPSK modulated signal, and then the single carrier signal is input into a Costas phase-locked loop to obtain an output signal; the receiving end divides the output signal by two to recover the carrier and obtain the synchronization carrier; by detecting the phase difference between the synchronization carrier and the original carrier of the transmitting end, if the phase difference is constant for a long time, it is determined that the two are the same frequency and in phase; and the receiving end takes the recovered synchronization carrier as the local clock reference.

[0042] Further, the step of inputting the single carrier signal into the Costas phase-locked loop to obtain the output signal comprises the following steps: a phase detector compares the phase of the frequency-doubled signal with the output signal of the voltage-controlled oscillator to generate a phase error signal; a low-pass filter filters out high-frequency noise in the phase error signal to output a smooth control voltage; the voltage-controlled oscillator is regulated according to the smooth control voltage, so that the real-time output frequency of the voltage-controlled oscillator gradually approaches the target value of the frequency-doubled original carrier; and the output signal is obtained from the voltage-controlled oscillator.

[0043] In the embodiment, the receiving end first extracts the local oscillator of the received signal by frequency multiplication and Costas phase-locked loop after removing the direct current component, and judges whether the extracted carrier is in phase with the carrier of the transmitting end by judging whether the phase difference between the extracted carrier and the carrier of the transmitting end is constant, i.e. and whether the same frequency and constant phase difference.

[0044] Further, the step of generating the time-domain narrow pulse comprises the following steps: the baseband time-domain signal is subjected to Fourier transform to obtain a baseband frequency-domain signal ; match the baseband frequency domain signal with a matched filter function ; multiply by frequency component, get compressed signal spectrum ; at this time, the exponential term imposes a differentiated phase delay on the frequency components of the signal, that is, low frequency components (fsmall) accumulate phase slowly, corresponding to long time domain delay; high frequency components (fbig) accumulate phase quickly, corresponding to short time domain delay. ; on the compressed signal spectrum ; perform inverse Fourier transform, on the time domain, the originally dispersed frequency components are precisely aligned due to the delay difference, making the wide pulse of T at the transmitting end compressed into a narrow pulse of u, the compression ratio D = T / u, the time accuracy is improved to the original D times, generating a time domain narrow pulse. In this embodiment, the transmitting end performs linear frequency modulation on the second pulse signal based on the synchronous carrier, so that the signal carrier frequency changes linearly within the pulse width, generating a linear frequency modulation second pulse signal, which uses large bandwidth-time product to improve transmission distance and subsequent analysis accuracy, and is broadcast through the data link.

[0045] When the receiving end receives the broadcast signal, it is converted into a baseband time domain signal by relying on the synchronous carrier in phase with the transmitting end; the baseband time domain signal is subjected to matched filtering. Matched filtering refers to using the characteristics of linear frequency modulation signal "low frequency component delay long, high frequency component delay short" to align different frequency components in time, compressing the originally wide pulse of T into a narrow pulse of u, the compression ratio D = T / u, the time accuracy is improved to the original D times; finally, the second pulse moment is extracted from the narrow pulse, realizing the time synchronization between the transmitting end and the receiving end.

[0046] As shown in Figure 4 , the implementation principle of time synchronization is as follows:

[0047] At the transmitting end, a stable reference clock is output by a high-precision clock source, which is calibrated by a precise synchronization module to eliminate clock drift, and drives a pulse generation unit to generate a synchronization pulse, which is the time reference of the time synchronization signal. The synchronization pulse is input into the linear frequency modulation module to make the signal carrier frequency change linearly within the pulse width, forming a linear frequency modulation signal, which uses the "large bandwidth-time product" characteristics to improve the data link transmission distance and enhance the time resolution; the frequency control unit fine tunes the signal parameters to optimize the spectral characteristics. The linear frequency modulation signal is converted into an analog signal by DA conversion, amplified in power by the power amplifier unit, and injected into the data link channel for external transmission.

[0048] At the receiving end, the receiving end radio frequency front end captures the linear frequency modulation signal from the data link, sends it to the mixing component to down-convert to intermediate frequency, and reduces the signal frequency. The intermediate frequency processing component filters the intermediate frequency signal to filter out the clutter and enhance the weak signal, and then generates a digital signal through AD conversion, which enters the synchronization processing link. The digital signal is correlated with the preset linear frequency modulation matching filter template in the frequency domain. The essence of matching filtering: use the "linear phase change" characteristic of linear frequency modulation signal to compress the wide pulse of the transmitting end into a narrow pulse, greatly improve the time resolution, and make it easier to capture the signal arrival time. Extract the correlation peak with the most concentrated energy in the correlation operation, and the position of the peak corresponds to the arrival time of the transmitted signal. Because the signal energy is highly aggregated after pulse compression, the peak shape is sharp, supporting high-precision detection. Through the capture module, the frequency, phase, and time characteristics of the signal are locked according to the correlation peak. Because the transmitting end has realized clock phase correlation, the receiving end can more accurately match the signal parameters and reduce synchronization errors. The tracking module dynamically tracks signal changes, deals with channel fading and frequency drift, and continuously calibrates the local time system; finally, a high-precision PPS is output, so that the receiving end time system is completely aligned with the transmitting end clock frequency, phase, and time reference, and time synchronization is completed.

[0049] Further, as shown in Figure 5 , the matching filter function is: ; wherein rect is a rectangular window function, f is a signal frequency domain variable, k is a frequency modulation rate of the linear frequency modulation pulse signal, T is a transmission pulse width, j is an imaginary unit, and π is a circular constant, is a windowing function used to suppress the edge discontinuity of the spectrum.

[0050] In this embodiment, the rectangular window limits the effective bandwidth of the signal, and the exponential term introduces a quadratic phase conjugate to the frequency modulation slope of the transmitting end.

[0051] The windowing function includes Taylor window, Chebyshev window, Hanning window, Hamming window, and Kaiser window, etc., and the window function parameters satisfy: the main lobe width and the side lobe attenuation ratio ≥ 25 dB; the spectrum transition band slope ≥ 40 dB / dec. The matching filter is processed by the windowing function to weaken the discontinuity at the edge of the spectrum and reduce the main lobe energy leakage in the compressed pulse, but the resolution will be lost.

[0052] Further, the deducting the transmission delay and the inherent delay and calculating the initial clock deviation between nodes specifically includes the following steps: sending a probe signal at a first local time by node A, and receiving the probe signal at a second local time by node B; according to the second local time marked by the second node B extracting the second local time, combining the signal propagation delay and the inherent delay, and calculating the clock deviation.

[0053] Further, the formula for calculating the clock deviation is: ; wherein, is a clock bias, is a first local time, is a second local time, is a signal propagation delay, is an inherent delay. Embodiment 1

[0054] Clock synchronization: for the BPSK modulated signal sent by the sending end, the local oscillator frequency of the receiving end can be extracted to obtain a signal with the same frequency as the carrier of the sending end, so as to realize the clock synchronization of the sending end and the receiving end.

[0055] Parameter setting: sampling frequency fs: 30MHz; symbol rate : 30k; carrier frequency fc: 0.5MHz; signal-to-noise ratio snr: 12dB.

[0056] A random sequence is generated at the sending end and is BPSK modulated to obtain a waveform after BPSK modulation as shown in Figure 6 . The sending signal of the sending end is added with noise by a Gaussian channel, and the signal spectrum diagram after adding noise is as shown in Figure 7 . The local oscillator frequency of the received signal is extracted by a phase-locked loop at the receiving end, the noise-added signal is processed by a frequency multiplication method, and the direct current component is filtered out to obtain a double-frequency single carrier signal as shown in Figure 8 . The carrier extracted by the phase-locked loop is divided by two, and its spectrum diagram is as shown in Figure 9 . It can be observed that the carrier frequency is the same as that of the sending end. The carrier of the sending end and the receiving end is as shown in Figure 10 , and the phase difference is calculated by Hilbert transform as shown in Figure 11 . The phase error fluctuates around a fixed value and is relatively stable. Therefore, the signal with the same frequency and constant phase difference as the carrier of the sending end can be recovered at the receiving end through the process. The standard deviation of the phase error of the extracted carrier and the carrier of the sending end is as shown in Figure 12 under the simulation output result of the signal-to-noise ratio of 12dB. The final standard deviation is stable at about 3°, which meets the design index requirements. Embodiment 2

[0057] Time synchronization: a wide time-interval linear frequency modulation second pulse signal is transmitted by the sending end, and a correlation filter is used at the receiving end to receive the second pulse signal to obtain a high-gain correlation peak, so as to realize the time synchronization of the sending end and the receiving end, and has the advantages of high precision and strong anti-interference ability.

[0058] Parameter setting: 300MHz.

[0059] A linear frequency modulation signal is generated at the sending end as shown in Figure 13 . The baseband signal is obtained by down-conversion of the received signal at the receiving end asFigure 14 The correlation peak of the baseband signal is extracted by matched filtering, and a high-precision correlation peak is obtained as shown in FIG. 4. Figure 15 As shown in FIG. 4, when the system clock is 300 MHz, the precision of the obtained correlation peak can reach 3.3 ns.

[0060] In summary, the multi-station cooperative clock synchronization technology is used in the embodiments of the present application to realize high-precision clock synchronization between stations, to provide a stable and accurate clock source for devices, to reduce the error caused by the difference between the clock oscillators of the transmitting and receiving parties, and to provide a guarantee for the transmission and reception of information between unmanned aerial vehicles. The multi-station cooperative clock synchronization technology lays a foundation for realizing high-precision relative ranging, has the advantages of high synchronization precision and strong anti-interference capability. Meanwhile, by using a suitable ranging method, the ranging error can be greatly reduced, and the ranging precision can be improved.

[0061] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can adopt a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer usable storage media containing computer usable program code (including but not limited to disk storage, CD-ROM, optical storage, etc.).

[0062] The present application is described with reference to flowcharts and / or block diagrams of the method, device (system), and computer program product according to the embodiments of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and the combination of the flows and / or blocks in the flowcharts and / or block diagrams can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device that implements the functions specified in the flowcharts and / or block diagrams. Figure 1 The functions specified in one or more flows and / or blocks. Figure 1 The devices that implement the functions specified in one or more flows and / or blocks.

[0063] These computer program instructions can also be stored in a computer readable memory that can guide the computer or other programmable data processing device to work in a specific way, so that the instructions stored in the computer readable memory produce a product including instruction devices that implement the functions specified in the flowcharts and / or block diagrams. Figure 1 The functions specified in one or more flows and / or blocks. Figure 1 The devices that implement the functions specified in one or more flows and / or blocks.

[0064] These computer program instructions can also be loaded into a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 one or more flowcharts and / or blocks Figure 1 one or more flowcharts and / or blocks

[0065] Although preferred embodiments of the application have been described herein, substitutions and modifications of these preferred embodiments made by those skilled in the art are to be considered within the scope of the application. Therefore, it is intended that the appended claims be construed to include all such substitutions and modifications as fall within the true spirit and scope of the application.

[0066] Obviously, numerous modifications and variations of the present application are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims and their equivalents, the application can be practiced otherwise than as specifically described.

Claims

1. A method for phase coherent synchronization of distributed clocks without a central node, characterized in that, The method comprises the following steps: Step 1, clock phase synchronization: a receiving end generates a synchronization carrier according to a received original carrier and takes the synchronization carrier as a local clock reference of the receiving end, so that the receiving end is synchronized with a transmitting end clock; The transmitting end is a dynamic reference node; The dynamic reference node is obtained through the following steps: Each node periodically broadcasts a clock stability evaluation parameter of itself, and the clock stability evaluation parameter is received by a neighbor node; A stability score of each node is obtained, and a node with the highest stability score is recorded as a dynamic reference node; The step of generating a synchronization carrier and taking the synchronization carrier as a local clock reference of the receiving end comprises the following steps: When the receiving end receives a BPSK modulated original carrier through a channel of a data link, a single carrier signal converted from the BPSK modulated signal is obtained through double frequency processing of the BPSK modulated original carrier, and the single carrier signal is input into a Costas phase-locked loop to obtain an output signal; The receiving end divides the output signal by two to recover the carrier and obtain a synchronization carrier; The phase difference between the synchronization carrier and the original carrier of the transmitting end is detected, and if the phase difference is constant for a long time, it is determined that the two are the same frequency and in phase; The receiving end takes the recovered synchronization carrier as a local clock reference; The step of inputting the single carrier signal into the Costas phase-locked loop to obtain an output signal comprises: A phase error signal is generated by comparing the phase of the double frequency signal with the output signal of the voltage controlled oscillator through a phase detector; High frequency noise in the phase error signal is filtered out through a low pass filter to output a smooth control voltage; The voltage controlled oscillator is adjusted according to the smooth control voltage, so that the real-time output frequency of the voltage controlled oscillator gradually approaches the double frequency target value of the original carrier; An output signal is obtained from the voltage controlled oscillator; Step 2, time system synchronization: the transmitting end modulates to obtain a linear frequency modulation second pulse signal based on the synchronization carrier and broadcasts, when the receiving end receives the linear frequency modulation second pulse signal, the synchronization carrier is used for frequency conversion to obtain a baseband time domain signal, the baseband time domain signal is matched filtered to generate a time domain narrow pulse, and a second pulse moment is extracted from the time domain narrow pulse, so that the receiving end is synchronized with the transmitting end time system; Step 3, multi-node synchronization: the time of signal transmission and reception time of each node is marked, the transmission delay and inherent delay are deducted, and the initial clock deviation between nodes is calculated, so that the distributed nodes are time system synchronized; The step of deducting the transmission delay and inherent delay and calculating the initial clock deviation between nodes comprises the following steps: A node A sends a probe signal at a first local time, and a node B receives the probe signal at a second local time; The second local time is marked by the second pulse extracted by the node B, and the clock deviation is calculated combined with the signal propagation delay and inherent delay.

2. The method of claim 1, wherein the step of synchronizing the distributed clocks of the plurality of nodes comprises the steps of: transmitting a synchronization message from the first node to the second node; and transmitting a synchronization message from the second node to the first node. The formula for obtaining the stability score is: ； wherein S is a stability score, and is a weight, , is a crystal oscillator temperature drift rate, is a crystal oscillator frequency deviation, is a crystal oscillator temperature variation, is a phase noise power spectral density.

3. The method of claim 1, wherein: The update period of the dynamic reference node satisfies: ​ ； wherein is the maximum frequency drift rate, is the maximum phase jitter frequency.

4. The method of claim 1, wherein the step of synchronizing the distributed clocks of the plurality of nodes comprises the steps of: transmitting a synchronization message from the first node to the second node; and transmitting a synchronization message from the second node to the first node. The step of generating a time domain narrow pulse comprises the following steps: transforming a baseband time domain signal into a baseband frequency domain signal ; Multiplying the baseband frequency domain signal with a matched filter function to obtain a compressed signal spectrum ; ； Compressing signal spectrum Performing an inverse Fourier transform generates a time-domain narrow pulse.

5. The method of claim 4, wherein the step of synchronizing the distributed clocks of the plurality of nodes comprises the steps of: transmitting a synchronization message from the first node to the second node; and transmitting a synchronization message from the second node to the first node. The matched filter function is: ； where rect is a rectangular window function, f is a signal frequency domain variable, k is a frequency modulation rate of the linear frequency modulation pulse signal, T is a transmitting pulse width, j is an imaginary unit, and π is a constant of a circular ratio, is a windowing function used to suppress spectrum edge mutation.

6. The distributed clock coherent synchronization method without a central node as described in claim 1, characterized in that, The formula for calculating the clock deviation is: ； wherein is a clock offset, is a first local time, is a second local time, is a signal propagation delay, is an inherent delay.

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