Circuit packaging module and manufacturing method thereof

Abstract

The embodiment of the invention provides a circuit packaging module and a manufacturing method thereof, and the module comprises a substrate which is provided with a cavity; the embedded device is arranged in the cavity, and the first surface of the embedded device is provided with a bonding pad; the first outer layer plate is arranged on the side, located on the first surface, of the substrate, a via hole is formed in the first outer layer plate, the via hole is opposite to the bonding pad, a conductive layer is formed in the via hole, the conductive layer is connected with the bonding pad, and the via hole is formed through plasma etching. According to the circuit packaging module, the device can be directly embedded into the substrate, the overall size of the circuit packaging module is reduced, the via holes are formed in the first outer layer plate through plasma etching, the processing precision of the via holes is high, the etching depth and precision are easy to control, poor hole patterns caused by high temperature and high heat of laser processing can be avoided, and the reliability of the circuit packaging module is improved. The circuit packaging module is simple in structure, free of environmental pollution risks, capable of improving the machining precision of the via holes in the circuit packaging module, capable of effectively increasing the wiring density of the circuit packaging module and capable of improving the performance of the module.

Description

Technical Field

[0001] The present application relates to the technical field of circuit board packaging, and in particular to a circuit packaging module and a manufacturing method thereof. Background Art

[0002] With the rapid development of integrated circuit technology, chip integration continues to increase. During chip manufacturing, blind vias are required to achieve electrical connections. To effectively increase chip wiring density and improve chip performance, it is necessary to reduce the diameter of the blind vias, the width of the wall between the blind vias, and the spacing between the blind vias.

[0003] Traditionally, laser processing or chemical etching is used to create blind vias in chips. However, laser processing suffers from large alignment errors, complex processes, and is prone to thermal damage that can lead to material degradation and hole shape changes that affect electrical performance. Chemical etching carries the risk of environmental pollution, and etching depth and precision are difficult to control. Summary of the Invention

[0004] The embodiments of the present application provide a circuit packaging module and a manufacturing method thereof, which can improve the processing accuracy of vias on the circuit packaging module, effectively increase the wiring density, and improve the module performance.

[0005] An embodiment of the present application provides a circuit packaging module, comprising: a substrate having a cavity formed therein; An embedded device is disposed in the cavity, wherein a first surface of the embedded device has a pad; A first outer layer board is arranged on a side of the substrate located on the first surface. The first outer layer board is formed with a via hole, the via hole is opposite to the pad, a conductive layer is formed in the via hole, the conductive layer is connected to the pad, and the via hole is formed by plasma etching.

[0006] In some embodiments, the first outer layer includes a first insulating layer and a first conductor layer sequentially stacked on the substrate, the via is formed in the first insulating layer, the first conductor layer has a circuit pattern and a window, and the window is opposite to the via.

[0007] In some embodiments, the embedded device further includes a second surface opposite to the first surface; The circuit packaging module further includes a second outer layer board, which is arranged on a side of the substrate located on the second surface.

[0008] In some embodiments, the second outer layer includes a second insulating layer and a second conductive layer sequentially stacked on the substrate, and the second conductive layer has a circuit pattern.

[0009] In some embodiments, the substrate includes a third outer layer board, a core board, and a fourth outer layer board stacked in sequence, the cavity passes through the third outer layer board, the core board, and the fourth outer layer board, and the third outer layer board, the core board, and the fourth outer layer board are all provided with at least one layer of circuit pattern.

[0010] In some embodiments, the embedded device is a chip.

[0011] The present invention also provides a method for manufacturing a circuit packaging module, including: providing a substrate, and cutting the substrate to form a cavity; An embedded device is arranged in the cavity, wherein a first surface of the embedded device has a pad; Disposing a first outer plate on a side of the substrate located on the first surface; performing plasma etching on the first outer layer board to form a via hole, wherein the via hole is opposite to the pad; A conductive layer is formed in the via hole, and the conductive layer is connected to the pad.

[0012] In some embodiments, the step of disposing a first outer plate on a side of the substrate located on the first surface includes: Laminating a first insulating layer on a side of the substrate located on the first surface; Laminating a first conductor layer on the first insulating layer; The first conductor layer is patterned to form a circuit pattern and a window, wherein the window is opposite to the pad.

[0013] In some embodiments, the plasma etching the first outer layer plate to form a via hole comprises: Plasma etching is performed on the first insulating layer at the position of the window to form a via hole.

[0014] In some embodiments, the embedded device further includes a second surface opposite to the first surface; Before plasma etching the first outer layer plate to form the via hole, the method further includes: arranging a second outer layer plate on a side of the substrate located on the second surface.

[0015] The circuit packaging module of the embodiment of the present application is provided with an embedded device in the substrate, which can directly bury the device inside the substrate, reduce the overall volume of the circuit packaging module, and realize the miniaturization of the packaging module. Vias are formed on the first outer layer board by plasma etching, and the conductive layer in the via is connected to the solder pad of the embedded device. Compared with laser processing or chemical etching, the via processing accuracy of the embodiment of the present application is high, and it is easy to control the etching depth and accuracy. It can avoid the poor hole shape caused by the high temperature and heat of laser processing, and there is no risk of environmental pollution. It can improve the processing accuracy of the vias on the circuit packaging module, effectively increase the wiring density of the circuit packaging module, and improve the module performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] To more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. Those skilled in the art can also derive other drawings based on these drawings without inventive effort.

[0017] Figure 1 This is a schematic diagram of the first structure of the circuit packaging module according to an embodiment of the present application.

[0018] Figure 2 This is a second structural diagram of the circuit packaging module according to an embodiment of the present application.

[0019] Figure 3 This is a third structural schematic diagram of the circuit packaging module according to an embodiment of the present application.

[0020] Figure 4 Schematic diagram of the manufacturing process of the circuit packaging module according to an embodiment of the present application.

[0021] Figure 5 A schematic structural diagram of a core plate formed by the manufacturing method of an embodiment of the present application.

[0022] Figure 6 Schematic diagram of the structure of a substrate formed by the manufacturing method of an embodiment of the present application.

[0023] Figure 7 Schematic diagram of the structure of forming a cavity on a substrate according to the manufacturing method of an embodiment of the present application.

[0024] Figure 8 This is a structural diagram of a manufacturing method according to an embodiment of the present application in which an embedded device is disposed in a substrate.

[0025] Figure 9 This is a structural schematic diagram of the manufacturing method of an embodiment of the present application, in which a first outer layer plate is arranged on a substrate.

[0026] Figure 10 This is a structural schematic diagram of forming a via hole on the first outer layer board according to the manufacturing method of an embodiment of the present application.

[0027] Figure 11 This is a structural schematic diagram of forming a second outer layer plate on a substrate according to the manufacturing method of an embodiment of the present application. DETAILED DESCRIPTION

[0028] The following will be combined with the accompanying drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making any creative work are within the scope of protection of this application.

[0029] The present invention provides a circuit packaging module that can improve the machining accuracy of vias on the circuit packaging module, effectively increase wiring density, and improve module performance. The circuit packaging module can be applied to devices or systems such as power supplies, control systems, and inverters.

[0030] refer to Figure 1 , Figure 1 FIG. 1 is a schematic diagram of a first structure of a circuit packaging module 100 according to an embodiment of the present application. The circuit packaging module 100 includes a substrate 10 , an embedded device 20 , and a first outer layer board 30 .

[0031] The substrate 10 may be a single-layer circuit board or a multi-layer circuit board. The substrate 10 includes at least one conductor layer, and the conductor layer is formed with a circuit pattern. One or more cavities 11 are formed on the substrate 10. When there are multiple cavities 11, the multiple cavities 11 are spaced apart, such as Figure 1 As shown. The cavity 11 can be formed by laser cutting or mechanical cutting. The shape, size, and depth of the cavity 11 can be set according to requirements. In practical applications, the cavity 11 can be a square cavity and pass through the substrate 10.

[0032] The embedded device 20 is arranged in the cavity 11. The number of embedded devices 20 is the same as the number of cavities 11, and one embedded device 20 is arranged in each cavity 11. The embedded device 20 can be a functional module such as a chip, an antenna, or an electronic component such as a resistor, a capacitor, or an inductor. For example, in one example, the embedded device 20 is a chip. The embedded device 20 includes a first surface 201, and the first surface 201 has a pad 21. The pad 21 can be used to achieve electrical connection between other electronic components or circuits and the chip 20. It can be understood that in actual applications, the number of the pads 21 is multiple, and the multiple pads 21 are spaced apart from each other.

[0033] The first outer layer board 30 is arranged on the side of the first surface 201 of the embedded device 20 of the substrate 10. The first outer layer board 30 can be a single-layer circuit board or a multi-layer circuit board. The first outer layer board 30 is formed with a via 31. There are multiple vias 31, and each via 31 is opposite to a pad 21. A conductive layer is formed in the via 31, and the conductive layer is connected to the pad 21. For example, a conductive layer can be formed in the via 31 by sputtering, electroplating, etc., and the conductive layer can be formed of a metal with good conductive properties, such as copper, silver, etc., so the via 31 can also be understood as a metallized hole. Thereby, other electronic components or circuits can be electrically connected to the embedded device 20 through the via 31.

[0034] Among them, the via 31 is formed by plasma etching. In a specific application, a plasma etching machine can be used to perform plasma etching on the first outer layer plate 30 to form the via 31. Plasma etching can produce a dual effect through the physical bombardment and chemical reaction of high-energy plasma, gradually removing the material to form the via 31. During the etching process, the etching power, the chamber pressure of the plasma etching machine, the gas flow rate, and the etching time can be controlled to control the etching rate and etching depth to achieve the desired via size. For example, the etching power can be 200W~1000W, the chamber pressure can be 0.1Pa~10Pa, the gas flow rate can be 10sccm~200sccm, and the etching time can be in the range of seconds to minutes.

[0035] Take the example of a plasma etching machine using gas CF4 to etch the ABF (Ajinomoto Build-up Film, epoxy resin insulating film) material of the first outer plate 30. On the one hand, CF4 is ionized to form high-energy charged particles. The positive ions CF3+ in the high-energy charged particles collide with the surface of the ABF material at high speed under the action of the electric field. The energy of the high-energy charged particles can reach hundreds to thousands of electron volts. The physical bombardment of the ions destroys the chemical bonds on the surface of the material (such as CC and CO chemical bonds), causing the atoms or molecules of the material to separate from the substrate, forming sputtered fragments, and gradually removing the material. On the other hand, CF4 decomposes into active free radicals CF3· and F· in the plasma. The decomposition reaction formula is: CF4+ e- → CF3· + F· + e-. The active free radical F· reacts chemically with the organic matter in the material to form volatile products CO2, HF, and CF4, which are gradually removed. The chemical reaction formula is: C x H y O z + F· → CO2↑ + HF↑ + CF4↑. Where x, y, and z represent the number of C, H, and O atoms in the organic compound's molecular formula, respectively, and are all positive integers.

[0036] In practical applications, a passivation gas (such as O2, C4F8, etc.) can also be added to the plasma gas. The passivation gas decomposes into active groups in the plasma. The active groups are deposited on the sidewalls of the hole through physical adsorption and chemical bonding, forming a non-volatile polymer layer. This resists lateral erosion of the sidewalls during subsequent etching and improves the smoothness of the etched via sidewalls.

[0037] The circuit packaging module 100 of the embodiment of the present application is provided with an embedded device 20 in the substrate 10, which can directly bury the device inside the substrate 10, reduce the overall volume of the circuit packaging module 100, and realize the miniaturization of the packaging module, and form a via 31 on the first outer layer board 30 by plasma etching, and the conductive layer in the via 31 is connected to the solder pad of the embedded device 20. Compared with laser processing or chemical etching processing, the via 31 of the embodiment of the present application has high processing accuracy, is easy to control the etching depth and accuracy, can avoid the poor hole shape caused by the high temperature and heat of laser processing, and does not have the risk of environmental pollution. It can improve the processing accuracy of the via 31 on the circuit packaging module, effectively increase the wiring density of the circuit packaging module 100, and improve the module performance.

[0038] In some embodiments, reference Figure 2 , Figure 2 This is a second structural diagram of the circuit packaging module 100 according to an embodiment of the present application.

[0039] The embedded device 20 further includes a second surface 202. The second surface 202 is opposite the first surface 201. The circuit packaging module 100 further includes a second outer layer board 40. The second outer layer board 40 is disposed on the side of the substrate 10 located on the second surface 202 of the embedded device 20. The second outer layer board 40 can be a single-layer circuit board or a multi-layer circuit board.

[0040] It can be understood that providing the second outer layer board 40 can increase the number of circuit layers of the circuit packaging module 100 , thereby further increasing the wiring density and improving the module performance.

[0041] In some embodiments, reference Figure 3 , Figure 3 This is a third structural diagram of the circuit packaging module 100 according to an embodiment of the present application.

[0042] The substrate 10 includes a third outer layer board 12, a core board 13, and a fourth outer layer board 14, which are stacked in this order. A cavity 11 extends through the third outer layer board 12, the core board 13, and the fourth outer layer board 14. Each of the third outer layer board 12, the core board 13, and the fourth outer layer board 14 is provided with at least one layer of circuit pattern.

[0043] In some embodiments, core board 13 may be a copper-clad laminate (CCL), which includes a substrate and copper layers covering both sides of the substrate. For example, the substrate may be FR4 (fiberglass epoxy) or other high-frequency substrates, which provide mechanical support. Both sides of the substrate are covered with copper foil having a thickness of 18 μm to 35 μm. The copper foil can be chemically etched to form the desired circuit pattern.

[0044] Both the third outer layer 12 and the fourth outer layer 14 can include an insulating layer and a conductive layer attached to the insulating layer. Taking the third outer layer 12 as an example, it includes an insulating layer disposed on the core substrate 13 and a conductive layer attached to the insulating layer. The conductive layer can be copper foil. For example, the insulating layer can be an epoxy insulating film (ABF) with a thickness of 20μm to 50μm, and the copper foil can be an electrolytic copper foil with a thickness of 5μm to 12μm. The copper foil can be chemically etched to form the desired circuit pattern. In practical applications, the copper foil can be roughened to enhance adhesion to the ABF. Thus, a substrate 10 with a multi-layer circuit pattern can be formed.

[0045] In some embodiments, continue to refer to Figure 3 The first outer layer 30 includes a first insulating layer 32 and a first conductive layer 33 stacked in sequence on the substrate 10. For example, the first insulating layer 32 may be an epoxy resin insulating film (ABF) with a thickness of 20μm to 50μm, and the first conductive layer 33 may be an electrolytic copper foil with a thickness of 5μm to 12μm. The via 31 is formed in the first insulating layer 32. The first conductive layer 33 has a circuit pattern and a window. For example, the desired circuit pattern and window can be formed by chemical etching, and the window is opposite to the via 31. The window can be understood as a through hole formed on the first conductive layer 33 to expose the first insulating layer 32 below the first conductive layer 33. In practical applications, the desired circuit pattern and window can be first formed on the first conductive layer 33 by chemical etching, and then the first insulating layer 32 (such as ABF) exposed at the window position can be plasma etched to form the via 31.

[0046] In some embodiments, continue to refer to Figure 3 The second outer layer 40 includes a second insulating layer 41 and a second conductive layer 42 sequentially stacked on the substrate 10. For example, the second insulating layer 41 may be an epoxy resin insulating film (ABF) having a thickness of 20 μm to 50 μm, and the second conductive layer 42 may be an electrolytic copper foil having a thickness of 5 μm to 12 μm. The second conductive layer 42 has a circuit pattern, for example, which can be formed on the second conductive layer 42 by chemical etching.

[0047] The present invention also provides a method for manufacturing a circuit packaging module to form the circuit packaging module 100. Figure 4 , Figure 4Schematic diagram of a manufacturing method of a circuit packaging module according to an embodiment of the present application. The manufacturing method includes the following steps: 210, providing a substrate, and cutting the substrate to form a cavity; 220, disposing an embedded device in the cavity, wherein a first surface of the embedded device has a pad; 230, disposing a first outer plate on a side of the substrate located on the first surface; 240 , plasma etching the first outer layer board to form a via hole, where the via hole is opposite to the pad; 250, forming a conductive layer in the via hole, and connecting the conductive layer to the pad.

[0048] For reference Figures 5 to 10 , Figure 5 This is a schematic diagram of the structure of the core plate formed by the manufacturing method of an embodiment of the present application. Figure 6 This is a schematic diagram of the structure of a substrate formed by the manufacturing method of an embodiment of the present application. Figure 7 This is a schematic structural diagram of a manufacturing method according to an embodiment of the present application for forming a cavity on a substrate. Figure 8 This is a schematic structural diagram of a manufacturing method according to an embodiment of the present application in which an embedded device is provided in a substrate. Figure 9 This is a structural diagram of a manufacturing method according to an embodiment of the present application in which a first outer layer plate is arranged on a substrate. Figure 10 This is a structural schematic diagram of forming a via hole on the first outer layer board according to the manufacturing method of an embodiment of the present application.

[0049] Among them, Figure 5 As shown, first, a core board 13 is provided. The core board 13 may be a copper clad board, which includes a substrate and copper layers covering both sides of the substrate.

[0050] Subsequently, the third outer plate 12 and the fourth outer plate 14 are arranged on the base plate 13, as shown in FIG. Figure 6 As shown, the third outer layer 12 includes an insulating layer 121 and a conductive layer 122, and the fourth outer layer 14 includes an insulating layer 141 and a conductive layer 142. Specifically, insulating layers 121 and 141 can be laminated on both sides of the core substrate 13. Insulating layers 121 and 141 can be made of epoxy resin insulating film (ABF). Then, conductive layer 122 is formed on insulating layer 121, and conductive layer 142 is formed on insulating layer 141. Conductive layers 122 and 142 can be formed of electrolytic copper foil. This completes the substrate 10.

[0051] Subsequently, the substrate 10 is cut to form one or more cavities 11, such as Figure 7 For example, the cavity 11 can be formed by laser cutting or mechanical cutting.

[0052] Then, an embedded device 20 is provided in the cavity 11, such as Figure 8 When there are multiple cavities 11, an embedded device 20 is disposed in each cavity 11. It should be noted that when there are multiple cavities 11, the embedded devices 20 disposed in different cavities can be the same device or different devices, and can be configured according to actual needs. The embedded device 20 includes a first surface 201 having a pad 21.

[0053] Then, a first outer layer plate 30 is provided on the side of the substrate 10 located on the first surface 201 of the embedded device 20, such as Figure 9 As shown, the first outer layer board 30 includes a first insulating layer 32 and a first conductor layer 33 .

[0054] In some embodiments, providing the first outer layer 30 may specifically include laminating a first insulating layer 32 on the side of the substrate 10 located on the first surface 201. The first insulating layer 32 may be an epoxy insulating film (ABF). Laminating a first conductive layer 33 on the first insulating layer 32. The first conductive layer 33 may be a copper foil, such as an electrolytic copper foil. Patterning the first conductive layer 33 to form a circuit pattern and a window. The window is opposite to the pad 21 of the embedded device 20. The window in the first conductive layer 33 may expose the underlying first insulating layer 32.

[0055] In some embodiments, the first conductor layer 33 can be patterned as follows: After pre-treating the copper foil surface (e.g., cleaning with an abrasive brush and chemical cleaning), photoresist is applied to the copper foil surface using a dry film process or a wet film process. UV light is then irradiated (exposed) to portions of the photoresist, causing a photochemical reaction to form a basic pattern. A chemical solution is then used to dissolve the photoresist in the exposed areas (i.e., the areas irradiated by UV light), exposing the copper surface to be etched. An acidic or alkaline etching solution is then used to dissolve the exposed copper surface, forming the desired circuit pattern and openings. A dedicated stripping solution is then used to remove any remaining photoresist.

[0056] Subsequently, the first outer layer board 30 is plasma etched to form a via hole 31, wherein the via hole 31 is opposite to the pad 21 of the embedded device 20, as shown in FIG. Figure 10 Specifically, plasma etching can be performed on the exposed first insulating layer 32 (eg, epoxy resin insulating film) at the window position of the first conductive layer 33 to form the via hole 31 .

[0057] Subsequently, a conductive layer is formed in the via hole 31, and the conductive layer is connected to the pad 21 of the embedded device 20. For example, a uniform metal seed layer can be deposited on the inner wall of the via hole 31 through a sputtering process. The metal seed layer can be a thin layer of copper or titanium copper. Then, a copper layer of a certain thickness is formed on the metal seed layer through an electroplating process, thereby forming a conductive layer in the via hole 31.

[0058] In some embodiments, before step 240 , plasma etching the first outer plate to form the via hole, the method further includes: disposing a second outer plate on a side of the substrate located on the second surface of the embedded device.

[0059] refer to Figure 11 , Figure 11 This is a schematic diagram of the structure of forming a second outer layer plate on a substrate according to the manufacturing method of an embodiment of the present application. The embedded device 20 includes a first surface 201 and a second surface 202, with the second surface 202 opposing the first surface 201. After the first outer layer plate 30 is disposed on the side of the substrate 10 located on the first surface 201, a second outer layer plate 40 can be disposed on the side of the substrate 10 located on the second surface 202. The second outer layer plate 40 includes a second insulating layer 41 and a second conductive layer 42.

[0060] In some embodiments, providing the second outer layer 40 may specifically include laminating a second insulating layer 41 on the side of the substrate 10 located on the second surface 202. The second insulating layer 41 may be an epoxy insulating film (ABF). Subsequently, laminating a second conductive layer 42 on the second insulating layer 41. The second conductive layer 42 may be a copper foil, such as an electrolytic copper foil. The second conductive layer 42 may be patterned, for example, by exposure, etching, or other processes, to form a circuit pattern.

[0061] In the description of this application, it should be understood that terms such as "first" and "second" are only used to distinguish similar objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.

[0062] It should be noted that in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.

[0063] The circuit packaging module and its manufacturing method provided in the embodiments of the present application are described in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only intended to help understand the present application. At the same time, those skilled in the art may vary in the specific implementation methods and application scope based on the concepts of the present application. In summary, the contents of this specification should not be construed as limiting the present application.

Claims

1. A circuit packaging module, characterized in that: include: a substrate having a cavity formed therein; An embedded device is disposed in the cavity, wherein a first surface of the embedded device has a pad; A first outer layer board is arranged on a side of the substrate located on the first surface. The first outer layer board is formed with a via hole, the via hole is opposite to the pad, a conductive layer is formed in the via hole, the conductive layer is connected to the pad, and the via hole is formed by plasma etching.

2. The circuit packaging module according to claim 1, wherein: The first outer layer includes a first insulating layer and a first conductive layer sequentially stacked on the substrate. The via hole is formed in the first insulating layer. The first conductive layer has a circuit pattern and a window. The window is opposite to the via hole.

3. The circuit packaging module according to claim 1, wherein: The embedded device further includes a second surface opposite to the first surface; The circuit packaging module further includes a second outer layer board, which is arranged on a side of the substrate located on the second surface.

4. The circuit packaging module according to claim 3, wherein: The second outer layer board includes a second insulating layer and a second conductive layer sequentially stacked on the substrate, and the second conductive layer has a circuit pattern.

5. The circuit packaging module according to any one of claims 1 to 4, characterized in that: The substrate includes a third outer layer board, a core board, and a fourth outer layer board stacked in sequence. The cavity runs through the third outer layer board, the core board, and the fourth outer layer board. The third outer layer board, the core board, and the fourth outer layer board are all provided with at least one layer of circuit pattern.

6. The circuit packaging module according to any one of claims 1 to 4, characterized in that: The embedded device is a chip.

7. A method for manufacturing a circuit packaging module, characterized in that: include: providing a substrate, and cutting the substrate to form a cavity; An embedded device is arranged in the cavity, wherein a first surface of the embedded device has a pad; Disposing a first outer plate on a side of the substrate located on the first surface; performing plasma etching on the first outer layer board to form a via hole, wherein the via hole is opposite to the pad; A conductive layer is formed in the via hole, and the conductive layer is connected to the pad.

8. The manufacturing method according to claim 7, characterized in that The first outer layer plate is provided on the side of the substrate located on the first surface, comprising: Laminating a first insulating layer on a side of the substrate located on the first surface; Laminating a first conductor layer on the first insulating layer; The first conductor layer is patterned to form a circuit pattern and a window, wherein the window is opposite to the pad.

9. The manufacturing method according to claim 8, characterized in that The plasma etching of the first outer layer plate to form a via hole comprises: Plasma etching is performed on the first insulating layer at the position of the window to form a via hole.

10. The manufacturing method according to any one of claims 7 to 9, characterized in that: The embedded device further includes a second surface opposite to the first surface; Before plasma etching the first outer layer plate to form the via hole, the method further includes: arranging a second outer layer plate on a side of the substrate located on the second surface.

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