Method for preparing printed circuit board

Abstract

This application discloses a method for fabricating a printed circuit board (PCB), relating to the field of electronic equipment technology. The PCB includes multiple sublayers stacked together, each sublayer including a core region for connection to a ball grid array (BGA), i.e., the core region is the area where the BGA is located. The fabrication method includes, before laminating the multiple sublayers, performing expansion and contraction compensation on the core region of each sublayer using the center point of the core region as the expansion and contraction center point. This avoids the problem in related technologies where expansion and contraction compensation is performed on the entire sublayer using the center point as the expansion and contraction center point, which cannot accurately control the expansion and contraction degree of local BGA areas within the sublayer, leading to severe alignment deviations in the BGA areas. This application improves the alignment accuracy of the BGA area structure, such as signal lines, by performing localized and refined expansion and contraction compensation on the BGA areas of the sublayers, thereby optimizing the reliability of signal transmission in the BGA area.

Description

Technical Field

[0001] This application relates to the field of electronic equipment technology, and in particular to a method for preparing a printed circuit board. Background Technology

[0002] Printed circuit boards (PCBs), as the core structure of electronic devices, are facing increasingly stringent requirements for high-density interconnection and ultra-high-speed signal transmission. Ball grid array (BGA) packaging is widely used in the packaging connection between PCBs and chips due to its high I / O density and short path advantages.

[0003] With the rapid development of fifth-generation communication (5G), artificial intelligence computing, and high-performance computing (HPC) technologies, electronic devices are placing increasingly higher demands on impedance consistency and signal integrity in signal transmission. However, in related technologies, significant misalignment exists in the signal line positions, via positions, or other structural positions within the PCB area used to connect BGAs. This can easily lead to problems such as sudden impedance changes, signal reflection, or electromagnetic interference in signal lines, especially high-speed signal lines, affecting the reliability of signal transmission, particularly high-speed and ultra-high-speed signals. Summary of the Invention

[0004] This application provides a method for manufacturing a printed circuit board, which aims to improve the alignment accuracy of the structure in the area of ​​the printed circuit board used to connect BGAs, thereby reducing the probability of problems such as impedance abrupt changes, signal reflection or electromagnetic interference in the printed circuit board, and improving the reliability of signal transmission in the printed circuit board and even electronic devices.

[0005] This application provides a method for manufacturing a printed circuit board, which includes multiple sub-layers stacked together, each sub-layer including a core region for connection with a ball grid array.

[0006] The preparation method includes: compensating for the expansion and contraction of the core area of ​​each sublayer using the center point of the core area as the expansion and contraction center point; stacking and pressing multiple sublayers together to obtain a printed circuit board.

[0007] In the fabrication method provided in this application embodiment, before the lamination process of multiple sublayers, the core area of ​​each sublayer is first compensated for expansion and contraction using the center point of the core area (the area of ​​the PCB used to connect BGAs) as the expansion and contraction center point. This avoids the problem of inaccurate control of the expansion and contraction degree of the local core area in the sublayer when the expansion and contraction compensation of the entire sublayer is performed using the center point of the sublayer as the expansion and contraction center point in related technologies. This can lead to alignment deviations in the structure of the core area. In other words, the fabrication method provided in this application embodiment improves the alignment accuracy of the structure of the core area, such as signal lines, vias or other structures, by performing local and refined expansion and contraction compensation on the core area of ​​the sublayer (the area of ​​the PCB used to connect BGAs). This reduces the probability of impedance abrupt changes, signal reflections or electromagnetic interference in the structure of the core area and optimizes the reliability of signal transmission in the core area. Attached Figure Description

[0008] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 A top view of a printed circuit board provided in an embodiment of this application;

[0010] Figure 2 A cross-sectional view of a printed circuit board provided in an embodiment of this application;

[0011] Figure 3 This is a partial enlarged view of the core area of ​​a printed circuit board provided in an embodiment of this application;

[0012] Figure 4 A flowchart illustrating the fabrication process of a printed circuit board provided in this application embodiment;

[0013] Figure 5 This is a top view of a printed circuit board in related technologies;

[0014] Figure 6 Another top view of the printed circuit board provided in the embodiments of this application;

[0015] Figure 7 Another top view of the printed circuit board provided in the embodiments of this application;

[0016] Figure 8 Another top view of the printed circuit board provided in the embodiments of this application;

[0017] Figure 9 Another top view of the printed circuit board provided in the embodiments of this application;

[0018] Figure 10 Another manufacturing process diagram of the printed circuit board provided in the embodiments of this application;

[0019] Figure 11 Other fabrication flowcharts of the printed circuit board provided in the embodiments of this application;

[0020] Figure 12 Another top view of the printed circuit board provided in the embodiments of this application;

[0021] Figure 13 for Figure 12 A magnified view of a structure corresponding to region B in the image;

[0022] Figure 14 A cross-sectional view of a sublayer provided in an embodiment of this application;

[0023] Figure 15 Other fabrication flowcharts of the printed circuit board provided in the embodiments of this application;

[0024] Figure 16 for Figure 12 Another enlarged view of the structure corresponding to region B in the image;

[0025] Figure 17 A schematic diagram of the computer processing preparation method provided in the embodiments of this application;

[0026] Figure 18 Another top view of the printed circuit board provided in the embodiments of this application;

[0027] Figure 19 Other fabrication flowcharts of the printed circuit board provided in the embodiments of this application;

[0028] Figure 20 Another top view of the printed circuit board provided in the embodiments of this application. Detailed Implementation

[0029] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0030] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0031] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0032] The embodiments of this application provide a method for preparing a printed circuit board.

[0033] Figure 1 This is a top view of a printed circuit board provided in an embodiment of this application. Figure 2 For along Figure 1 The cross-sectional view of section line A-A' in the diagram.

[0034] The printed circuit board 100 (e.g., PCB) can serve as a mounting substrate for electronic devices, enabling electrical connections between chips, electrical components, and conductive structures, while also providing mechanical support.

[0035] See Figure 2 The printed circuit board 100 (e.g., PCB) includes multiple sublayers 10 stacked together.

[0036] It is understandable that Figure 1 It can represent the top view of the printed circuit board 100, or the top view of a sublayer 10 in the printed circuit board 100.

[0037] Sublayer 10 may include a wiring layer in the printed circuit board 100 for wiring design. Multiple sublayers 10 are stacked to utilize the wiring layers in sublayer 10 to achieve complex electrical connection requirements, thereby enabling functions such as high-speed signal transmission or complex power supply.

[0038] For example, the printed circuit board 100 may also include an outer layer structure covering the upper and lower surfaces of the multilayer sublayer 10. The outer layer structure may include a solder mask layer, or it may also include a trace layer for implementing surface traces. That is, the multilayer sublayer 10 can be understood as the inner layer structure of the printed circuit board 100. After the inner layer structure is prepared, the outer layer structure is then covered. The embodiments of this application mainly explain the preparation method of the inner layer structure.

[0039] See Figure 2Each sublayer 10 includes a core region 1, which is used to connect to a ball grid array (BGA). That is, the core region 1 is the actual part of the printed circuit board 100 (or sublayer 10) used to connect to the BGA.

[0040] For example, see Figure 2 After the multi-layer sub-layers 10 are stacked together to form the printed circuit board 100, the core area 1 of the multi-layer sub-layers 10 is overlapped so that the printed circuit board 100 can be connected to the BGA at the location of the core area 1.

[0041] For example, see Figure 1 The core region 1 can be used to open multiple vias with high density distribution, so as to form multiple pads in the core region 1 that are connected to the solder balls of the BGA.

[0042] For example, see Figure 1 The planar shape of the core area 1 can be rectangular, and the size and position of the rectangle are such that it can surround multiple through holes.

[0043] For example, a printed circuit board 100 (or a sublayer 10) may include multiple core regions 1. Figure 1 The structure of the printed circuit board 100 is explained using only one core area 1 as an example, and is not intended to limit the number of core areas 1.

[0044] Figure 3 This is a partial enlarged view of the core area 1 of the printed circuit board 100 provided in the embodiments of this application.

[0045] For example, see Figure 3 In the multi-layer sublayer 10, some sublayers 10 may include a routing layer L3 for signal line routing design, and some sublayers 10 may include a reference layer L4 (i.e., a ground layer or power layer, which is a full-surface metal layer, such as a full-surface copper layer). See [reference]. Figure 3 The copper layer stacked adjacent to the wiring layer L3 can serve as the reference layer L4 for the signal lines in the wiring layer L3, providing a return path for the signal lines, shielding them from external noise interference, and controlling the characteristic impedance of the transmission line formed between the reference layer L4 and the signal lines.

[0046] For example, see Figure 3 Multiple through holes can be formed in the core area 1 of sublayer 10. Conductive material is provided in the through holes. The conductive material is used to electrically connect with the signal line. Insulating material is also provided between the conductive material and the inner wall of the through hole to prevent the conductive material and the signal line connected to it from having an unexpected electrical connection.

[0047] When designing the wiring for sublayer 10, the alignment accuracy of signal line placement and via drilling placement in sublayer 10 have a significant impact on the electrical performance of the printed circuit board 100. For example, the drilling placement (i.e., ...) Figure 3 The location of the through hole should at least avoid the routing location of the signal line to prevent the signal line from being disconnected during drilling and causing the signal line to malfunction. Alternatively, the routing location of the signal line should be within the range of reference layer L4 to avoid impedance changes in the signal transmitted by the signal line (especially high-speed signals).

[0048] For example, see Figure 3 The spacing Li between the signal line and the boundary of the reference layer (e.g., the boundary of the insulating material near the via of the reference layer) can be designed to be greater than or equal to 2mil to ensure that the reference layer L4 can cover the signal line. If the alignment of the wiring layer L3 and the reference layer L4 is off, it is easy for part of the material of the signal line stack to become insulating material, that is, the reference layer L4 will be discontinuous, which will lead to impedance change and affect the reliability of the signal transmitted by the printed circuit board 100.

[0049] To address the aforementioned technical problems, this application provides the following method for preparing a printed circuit board 100.

[0050] Figure 4 This is a flowchart illustrating the fabrication process of the printed circuit board 100 provided in this embodiment of the application. Figure 5 , Figure 6 , Figure 7 , Figure 8 and Figure 9 These are some other top views of the printed circuit board 100 provided in the embodiments of this application.

[0051] See Figure 4 The preparation method may include steps S1 and S2:

[0052] S1: See Figure 6 , Figure 7 , Figure 8 and Figure 9 The expansion and contraction compensation is performed on the core area 1 of each sub-layer 10 with the center point 1a of the core area 1 as the expansion and contraction center point.

[0053] For example, the center point 1a of the core area 1 can be the intersection of its diagonals.

[0054] For example, when compensating for expansion and contraction in the core area 1, the expansion and contraction can be started from the center point and moved outward to make the expansion and contraction degree at different locations in the core area 1 roughly the same.

[0055] S2: Stack and press 10 layers of multiple sub-layers together into one piece (see reference). Figure 2), thus obtaining printed circuit board 100.

[0056] When the multilayer sublayer 10 is laminated, the sublayer 10 will undergo a certain degree of expansion and contraction (deformation such as expansion or contraction in shape and size). This phenomenon can easily cause the wiring position of the signal lines in the sublayer 10 to shift, which is not conducive to the alignment of the structure (such as signal lines or vias) between different sublayers 10.

[0057] By performing pre-expansion and contraction compensation on sublayer 10 before lamination, the expansion and contraction deviation of sublayer 10 during subsequent wiring or lamination processes can be reduced or even eliminated, thereby helping to reduce alignment errors caused by expansion and contraction.

[0058] Figure 5 A top view of a printed circuit board 100 provided for related technologies.

[0059] See Figure 5 In related technologies, the intersection of the diagonals of the entire sublayer 10 (i.e., the center point) is usually used as the expansion and contraction compensation center to compensate for the expansion and contraction of the entire sublayer 10. However, due to the different physical characteristics (such as copper density, insulation layer thickness, etc.) between the core area 1 and other areas (conventional area 2), the local expansion and contraction of the core area 1 cannot be precisely controlled in this related technology. This results in poor alignment accuracy of structures in the core area 1, such as high-speed signal lines, which affects the reliability of signals transmitted by the printed circuit board 100. For example, the impedance stability of signal lines in the core area 1 with poor alignment accuracy is difficult to guarantee, resulting in poor stability and reliability of signal transmission.

[0060] In the preparation method provided in this application embodiment, by taking the center point of the core region 1 as the expansion and contraction compensation center, local and fine expansion and contraction compensation is performed on the core region 1, thereby improving the accuracy of expansion and contraction control of the core region 1, ensuring the alignment accuracy of the structure in the core region 1, thereby reducing the impedance deviation of the signal lines in the core region 1, reducing signal reflection and crosstalk problems, and improving the stability and reliability of signal transmission.

[0061] In some embodiments, see Figure 6 The aforementioned step S1 may include:

[0062] The expansion and contraction compensation of sub-layer 10 is performed with the center point 1a of core area 1 as the expansion and contraction center point.

[0063] That is, the expansion and contraction compensation of the sub-layer 10 is still performed as a whole. This ensures that the expansion and contraction center point is located at the center point of the core area 1 while the expansion and contraction compensation is easy and efficient. This ensures the expansion and contraction compensation accuracy of the key component in the sub-layer 10 - the core area 1, and thus prioritizes the alignment accuracy of the structure of the core area 1.

[0064] In some embodiments, see Figure 7 and Figure 8 Sub-layer 10 also includes a regular area 2, which is set around the core area 1. That is, the regular area 2 is the part of sub-layer 2 other than the core area 1, and the regular area is not used to connect with the ball grid array.

[0065] The aforementioned step S1 may also include:

[0066] The expansion and contraction compensation of the conventional region 2 is performed with the center point 2a of sublayer 10 as the expansion and contraction center point.

[0067] That is, in this embodiment, expansion and contraction compensation can be performed on the core area 1 and the regular area 2 respectively, so as to perform fine and local expansion and contraction compensation on the core area 1 without affecting the expansion and contraction of the regular area 2 in the sub-layer 10, thereby ensuring the alignment accuracy of the structure of the core area 1.

[0068] For example, a first expansion / contraction coefficient can be used to compensate for expansion / contraction in the core area 1, and a second expansion / contraction coefficient can be used to compensate for expansion / contraction in the regular area 2, wherein the first expansion / contraction coefficient and the second expansion / contraction coefficient are different.

[0069] That is, different expansion and contraction coefficients can be designed according to the different physical structural characteristics of core area 1 and conventional area 2, so that the expansion and contraction compensation of core area 1 and conventional area 2 is decoupled, avoiding the problem that the expansion and contraction compensation of the two need to be taken into account, which leads to the loss of expansion and contraction accuracy. In other words, expansion and contraction compensation can be carried out in a targeted manner for core area 1 and conventional area 2, thereby improving the alignment accuracy of the overall structure of sub-layer 10.

[0070] For example, see Figure 8 In the case that sub-layer 10 includes multiple core areas 1, multiple expansion and contraction compensations can be performed. That is, each core area 1 corresponds to an expansion and contraction center point and performs local fine-grained expansion and contraction compensation.

[0071] In some embodiments, see Figure 9 Sub-layer 10 also includes a transition zone 3, which is set around the core zone 1 and is located between the core zone 1 and the regular zone 2.

[0072] The aforementioned step S1 may also include:

[0073] The third expansion / contraction coefficient is used to compensate for the expansion / contraction of the transition zone 3.

[0074] The third expansion / contraction coefficient lies between the first and second expansion / contraction coefficients.

[0075] That is, the transition zone 3 is used to transition the expansion and contraction compensation of the core zone 1 and the regular zone 2, so as to avoid the problem that the compensation coefficient of the core zone 1 and the regular zone 2 is large due to the large difference in physical structure, and that there is still mutual influence during expansion and contraction compensation. This further improves the precision control of the expansion and contraction compensation of the core zone 1, thereby improving the alignment accuracy of the structure therein.

[0076] For example, the transition zone 3 can be further divided into multiple sequentially surrounding sub-zones, and the multiple sub-zones are compensated for by a gradient-varying expansion and contraction coefficient. This further reduces the impact of the expansion and contraction compensation of the conventional zone 2 on the expansion and contraction degree of the core zone 1, thereby further improving the alignment accuracy of the structure in the core zone 1.

[0077] For example, the transition zone 3 can be compensated for expansion and contraction by taking the center point 1a of the core zone 1 as the expansion and contraction center point.

[0078] The above embodiments improve the control over the expansion and contraction of the core area 1 by performing local expansion and contraction compensation, thereby optimizing the alignment accuracy of the structure in the core area 1. The following embodiments further improve the alignment accuracy of the core area 1 in subsequent batches of printed circuit boards 100 by dynamically feeding back the expansion and contraction of the previous batch of printed circuit boards 100.

[0079] Figure 10 Another manufacturing process diagram of the printed circuit board 100 provided in this application embodiment.

[0080] In some embodiments, see Figure 10 The method for preparing the printed circuit board 100 further includes:

[0081] S3: Measure the expansion and contraction differences between the core areas 1 of the multilayer sublayer 10 in the printed circuit board 100 (i.e., after step S2).

[0082] The aforementioned step S1 includes:

[0083] S11: Based on the difference in expansion and contraction, determine the expansion and contraction coefficient of the core area 1 of each sub-layer 10.

[0084] S12: Use the expansion / contraction coefficient to compensate for expansion / contraction in core area 1.

[0085] Step S12 can reduce the difference in expansion and contraction between different sub-layers 10 after the printed circuit board 100 is laminated.

[0086] For example, if there is a large difference in expansion and contraction between two adjacent sub-layers 10, the expansion and contraction coefficient of the sub-layer 10 that is prone to larger expansion and contraction will be set to a smaller value when performing expansion and contraction compensation, while the expansion and contraction coefficient of the sub-layer 10 that is prone to smaller expansion and contraction will be set to a larger value when performing expansion and contraction compensation. In this way, the deformation difference that occurs after subsequent compression expansion and contraction can be reduced by using different degrees of expansion and contraction compensation, thereby reducing the alignment error between the two.

[0087] That is, by utilizing the expansion and contraction differences between different sub-layers 10 of the printed circuit board 100 after lamination due to lamination and other processes, the results are fed back to the preparation steps of subsequent batches of printed circuit boards 100. This allows subsequent batches of printed circuit boards 100 to dynamically adjust the expansion and contraction coefficient during the preparation process, thereby further improving the control accuracy of expansion and contraction compensation in the core area 1, and further improving the alignment accuracy of the structure in the core area 1.

[0088] For example, a detection device (such as an optical detection device, such as a high-precision CCD) can be used to scan the core region 1 after the bad step S2 in real time to obtain the actual deformation and expansion / contraction data of the core region 1 in each sub-layer 10, thereby obtaining the expansion / contraction differences between different sub-layers 10.

[0089] Exemplarily, the preparation step may further include:

[0090] The data during the preparation process is transmitted to the processor, which analyzes and calculates the expansion and contraction coefficients of different sublayers 10, thereby further improving the accuracy of expansion and contraction control of the core region 1.

[0091] For example, the actual deformation and expansion / contraction data of the core area 1 in each sub-layer 10 detected by the detection equipment can be uploaded to the processor (e.g., a computer system). The processor calculates the expansion / contraction differences between different sub-layers 10 and obtains the expansion / contraction coefficient that each sub-layer 10 needs to adjust for expansion / contraction compensation based on these differences.

[0092] For example, the processor may be equipped with AI algorithms to perform intelligent calculations and data optimization on the data involved in the embodiments of this application, thereby improving the preparation accuracy.

[0093] For example, an automated expansion and contraction optimization program can be written and integrated into the processor. Actual expansion and contraction data, expansion and contraction differences, and processor-predicted expansion and contraction data can be imported into the program for automatic comparison and optimization. This ensures more accurate expansion and contraction data in subsequent batches, guaranteeing the alignment of the core area 1 in the printed circuit board 100 after lamination. Simultaneously, processing data from previous batches can be recorded to form a database, facilitating data retrieval or reference for subsequent similar fabrication processes.

[0094] Figure 11Here are some other manufacturing process diagrams for the printed circuit board 100 provided in the embodiments of this application. Figure 12 This is another top view of the printed circuit board 100 provided in an embodiment of this application. Figure 13 for Figure 12 The enlarged view of the structure corresponding to region B in the image.

[0095] In some embodiments, see Figure 11 The aforementioned step S3 may include steps S31 to S33:

[0096] S31: See also Figure 13 Before performing expansion and contraction compensation (before step S1), four first targets M1 are set in the core area 1 of sublayer 10.

[0097] The target can be a Mark, so that it can be identified and detected by the detection device. The same applies to the subsequent second target, third target, etc.

[0098] For example, the diameter of the first target M1 can be 0.5mm to 1mm.

[0099] See Figure 12 and Figure 13 The four first targets M1 are respectively set near the four corners of the core area 1.

[0100] It should be noted that the "four corners of core area 1" refers to the fact that the overall planar shape of core area 1 can be rectangular, and the four corners of the rectangle are the four corners of core area 1. In addition, when multiple through holes in core area 1 are arranged in a ring, the part of the rectangle that can at least completely cover the multiple through holes is divided into core area 1, and the four corners of core area 1 are still the four corners of the rectangle.

[0101] Among them, "set at the four corners near the core area 1" means that the first target M1 set at a certain corner is relatively close to that corner.

[0102] For example, the first target M1 can be set outside the rectangular area where the core area 1 is located (outside the corner), and the distance between it and the nearest corner is small, for example, the distance can be less than or equal to 2mm.

[0103] Alternatively, for example, the first target M1 can be set inside the rectangular area where the core area 1 is located (inside the corner), and the distance between it and the nearest corner is small, for example, the distance can be less than or equal to 2mm.

[0104] In summary, the first target M1 provided in this application embodiment only needs to be set in one of the four directions of the core area 1 and be close to the core area 1, rather than restricting the specific structural or shape settings in the core area 1.

[0105] S32: Measure the spacing between the four first targets M1 in each sublayer 10 of the printed circuit board 100 to obtain the first spacing parameter.

[0106] For example, the first spacing parameter may include Figure 12 The four spacing values ​​are: the spacing between the two leftmost first targets M1, the spacing between the two rightmost first targets M1, the spacing between the two topmost first targets M1, and the spacing between the two bottommost first targets M1. These four spacing values ​​can ensure the expansion and contraction states that occur in different orientations of the core region 1 in this sub-layer 10.

[0107] Figure 13 In the diagram, the first target M1 shown by the solid line is the first target M1 of this sublayer 10, and the first target M1 shown by the dashed line is the first target M1 in other sublayers that are superimposed on this sublayer 10.

[0108] See Figure 13 In the printed circuit board 100, the first target M1 in the multilayer sublayer 10 is staggered in the stacking direction of the multilayer sublayer 10 so that after the multilayer sublayer 10 is stacked and pressed, the first target M1 in each sublayer 10 can still be detected individually, so that the expansion and contraction of the multilayer sublayer 10 can be detected after pressing.

[0109] For example, see Figure 13 Multiple first targets M1 located in the same direction can be arranged along the circumference to achieve staggered positioning.

[0110] For example, the order in which the plurality of first targets M1 are arranged along the circumference can be set according to the arrangement order of the sub-layers.

[0111] For example, multiple first targets M1 located in the same direction can be set within a range of 0.6 mm so that the first targets M1 can be removed when the positioning holes are formed later, so as to avoid the first targets M1 remaining and interfering with the identification and measurement of other targets.

[0112] S33: Based on the first spacing parameter of each sub-layer 10, obtain the difference between the first spacing parameters in the multiple sub-layers 10.

[0113] The difference between the first spacing parameters characterizes the expansion and contraction differences between the core regions 1 of the multilayer sublayer 10.

[0114] For example, the difference between the spacing between the two leftmost first targets M1 of one sub-layer 10 and the spacing between the two leftmost first targets M1 of the other sub-layer 10 can indicate the magnitude of the difference in expansion and contraction between the two sub-layers 10.

[0115] For example, steps S32 and S33 can be performed using a processor to perform analysis and calculation.

[0116] In this embodiment, multiple first targets M1 that are staggered are used to measure the expansion and contraction of the core area 1 in each sub-layer 10, thereby obtaining the expansion and contraction differences between the core areas 1 in different sub-layers 10. This achieves parameterization of the expansion and contraction differences, thereby improving the accuracy of the expansion and contraction difference measurement. This improves the accuracy of the expansion and contraction coefficient when calculating the expansion and contraction compensation based on the expansion and contraction differences, and facilitates further improvement of the alignment accuracy of the structure in the core area 1.

[0117] Figure 14 This is a cross-sectional view of sublayer 10 provided in an embodiment of this application.

[0118] In some embodiments, see Figure 14 Sublayer 10 may include a first wiring layer 11, a second wiring layer 12, and an insulating layer 13 sandwiched between the first wiring layer 11 and the second wiring layer 12.

[0119] For example, the aforementioned step S31 may include:

[0120] A first target M1 is set on the first wiring layer 11 or the second wiring layer 12 of each sublayer 10.

[0121] That is, when the design space is insufficient, four first targets M1 can be set on only one of the wiring layers of sub-layer 10, so as to balance the design space and the control of the expansion and contraction of each sub-layer 10.

[0122] Alternatively, as an example, the aforementioned step S31 may include:

[0123] A first target M1 is set on the first wiring layer 11 and the second wiring layer 12 of each sub-layer 10, thereby further refining the expansion and contraction control of each wiring layer in the sub-layer 10 and further improving the alignment accuracy of the core area 1 of the printed circuit board 100.

[0124] For example, the fabrication method further includes: performing wiring design (i.e. patterning, for example, using LDI exposure method to design and shape the wiring pattern) on the wiring layers (including the first wiring layer 11 and the second wiring layer 12) of the sublayer 10.

[0125] For example, during routing, routing design can be performed on the first routing layer 11 first, and a positioning target can be formed at the position of the corresponding core area 1 of the second routing layer 12. Then, the positioning target is used as the positioning reference to design routing on the second routing layer 12, so that the core areas 1 of the upper and lower routing layers in the same sub-layer 10 have better alignment accuracy, further improving the overall alignment accuracy of the core area 1 of the printed circuit board 100.

[0126] For example, the positioning target can reuse the aforementioned first target M1, or it can reuse the second target M2 in a subsequent embodiment.

[0127] The aforementioned embodiments improve the alignment accuracy of the structures in the core area 1 of different sub-layers 10 by locally and precisely controlling the expansion and contraction of the core area 1 in each sub-layer 10, thereby optimizing the electrical performance of the printed circuit board 100 (e.g., the reliability of the transmitted signals). In addition, the accuracy of the drilling position on the printed circuit board 100 also affects the reliability of the transmitted signals. The following embodiments will explain the drilling process of the printed circuit board 100.

[0128] Figure 15 Here are some other manufacturing process diagrams for the printed circuit board 100 provided in the embodiments of this application. Figure 16 For pressing Figure 12 Another enlarged view of the structure corresponding to region B in the image.

[0129] In some embodiments, see Figure 15 The method for preparing the printed circuit board 100 also includes the following steps S4 to S6:

[0130] S4: Before performing expansion and contraction compensation (i.e. before step S1), set at least two second targets M2 on each sub-layer 10.

[0131] For example, see Figure 12 and Figure 13 This step S4 can be performed simultaneously with the aforementioned step S31.

[0132] Among them, see Figure 12 and Figure 13 The at least two second targets M2 are respectively set near the four corners of the core area 1, and two of the second targets M2 are respectively set near the two corners of the core area 1 arranged diagonally.

[0133] The design of the second target M2 provided in this application embodiment can refer to the description of the first target M1 in the foregoing embodiment, and will not be repeated here. That is, as long as the second target M2 can be set in the four directions of the core area 1 and is relatively close to the core area 1, it is acceptable.

[0134] For example, two second targets M2 can be set on each sub-layer 10. In this case, the two second targets M2 are set on the diagonal of the core area 1 (that is, set on the two corners arranged along the diagonal of the core area 1 respectively), so that the core area 1 can still be located with the minimum number of second targets M2, which is convenient for subsequent drilling based on the location.

[0135] Alternatively, for example, four second targets M2 can be set on each sub-layer 10, which can be used to further improve the positioning accuracy of the core area 1, thereby improving the drilling accuracy when drilling is performed based on the positioning.

[0136] See Figure 13 The second target M2 in different sublayers 10 is positioned in the same location within its respective sublayer 10. Figure 13 The illustration is based on the example of the complete overlap of the second target M2 in multiple sub-layers 10.

[0137] That is, before the multi-layer sub-layer 10 is pressed together and before the sub-layer 10 undergoes expansion and contraction deformation, the second target M2 in different sub-layers 10 is set in the same position. For example, when multiple sub-layers 10 are stacked at this time (without pressing, only simple stacking), multiple second targets M2 in multiple sub-layers 10 located in the same position of the core region 1 can overlap. That is, the second targets M2 in different sub-layers 10 can represent the same position information of the core region 1, so as to use whether the second targets M2 in different sub-layers 10 overlap to represent whether the core region 1 in different sub-layers 10 overlaps, that is, to represent the alignment after the sub-layers 10 are stacked and pressed together.

[0138] Figure 17 This is a schematic diagram illustrating the execution of step S5 using a computer, as provided in an embodiment of this application.

[0139] S5: See Figure 16 and Figure 17 In the printed circuit board 100 (i.e. after step S2), the multiple overlapping second targets M2 of the multilayer sublayers 10 are fitted into a target circle N1.

[0140] Wherein, the target circle N1 is a circle that minimizes the sum of the squared distances from multiple second targets M2 to the center of the circle.

[0141] That is, the target circle N1 is the optimal circle after the position fitting of multiple second targets M2, and its position can characterize the optimal overlap position of the multiple second targets M2.

[0142] Figure 18 Another top view of the printed circuit board 100 provided in an embodiment of this application.

[0143] S6: See also Figure 18 Based on the position of the target circle N1, the printed circuit board 100 is drilled to obtain the positioning hole H1.

[0144] For example, it can be understood that the number of positioning holes H1 is the same as the number of second targets M2 in a sublayer 10, that is, there are at least two positioning holes H1, and two of the positioning holes H1 are arranged along the diagonal of the core area 1.

[0145] The positioning hole H1 is used to position the core area 1 of the printed circuit board 100. For example, the positioning hole H1 can be used as a physical fixing hole to physically fix the processing equipment (such as a drilling machine), thereby ensuring the alignment accuracy of the multiple through holes drilled by the drilling machine in the core area 1 for connection with the ball grid array, and avoiding the through holes from shifting or misaligning.

[0146] After step S2, the multi-layer sub-layer 10 expands and contracts to varying degrees. The multiple second targets M2, which should ideally overlap completely, overlap due to the expansion and contraction (i.e., partially overlap, but not completely overlap). At this time, the positioning hole H1 is obtained by drilling a hole using the position of the fitted target circle N1. This can make the alignment error of the positioning hole H1 in each sub-layer 10 smaller, thereby improving the alignment accuracy of the multiple through holes formed in the core area 1 using the positioning hole H1.

[0147] Figure 19 Some other manufacturing process diagrams for the printed circuit board 100 provided in the embodiments of this application.

[0148] In some embodiments, see Figure 19 The aforementioned step S6 may include:

[0149] S61: Measure the spacing change of the four first targets M1 of each sublayer 10 in the printed circuit board 100 (i.e. after step S2) to obtain the expansion and contraction state of the core area 1 of the printed circuit board 100 (i.e. the core area 1 after the multilayer sublayer 10 is pressed together).

[0150] The spacing change value is the difference between the spacing of the four first targets M1 before the expansion and contraction compensation step (step S1) and the spacing of the four first targets M1 after the pressing step (step S2).

[0151] The spacing variation value of a sublayer 10 can characterize the expansion and contraction state of the core area 1 of the sublayer 10. By fitting the spacing variation values ​​of multiple sublayers 10, the overall expansion and contraction state of the core area 1 of the printed circuit board 100 can be obtained.

[0152] S62: See also Figure 16 The position of the target circle N1 is adjusted based on the expansion and contraction state to obtain the final positioning point N2.

[0153] See Figure 17 The position of the target circle N1 can be adjusted using a computer / processor to obtain the final positioning point N2.

[0154] S63: Based on the position of the final positioning point N2, drill holes in the printed circuit board 100 to obtain positioning holes H1.

[0155] That is, in this embodiment of the application, the expansion and contraction of the core area 1 as a whole (that is, not the core area 1 of a single sub-layer 10, but the whole of the core areas 1 of all sub-layers 10) can also be obtained by using the first target M1 after the multi-layer sub-layers 10 are stacked and pressed together. Based on the expansion and contraction of the core area 1 of the printed circuit board 100, the position of the aforementioned target circle N1 is dynamically adjusted in real time, thereby taking into account the influence of the overall expansion and contraction of the core area 1 on the position of the target circle N1, fitting a better drilling path, eliminating the interference of the mark offset of the second target M2 of the single sub-layer 10 on the drilling positioning, and further improving the alignment accuracy of the positioning hole H1.

[0156] For example, a detection device (such as a CCD device) can be used to collect the deformation (i.e., expansion and contraction) of the core area 1, and the drilling position can be automatically calculated and updated based on the deformation (i.e., the coordinates of the target circle N1 are updated to the coordinates of the final positioning point N2).

[0157] Figure 20 Another top view of the printed circuit board 100 provided in an embodiment of this application.

[0158] In some embodiments, see Figure 20 After step S6, the preparation method may further include:

[0159] S7: Based on the positioning of the positioning hole H1, multiple through holes H2 are opened in the core area 1 of the printed circuit board 100.

[0160] These multiple through-holes H2 are used for connection to a ball grid array (BGA).

[0161] For example, the diameter of the aforementioned positioning hole H1 can be 0.6 mm, and the diameter of the through hole H2 can be 2 mm.

[0162] For example, see Figure 13 The first target M1 and the second target M2, located in the same direction (near the same corner) in the core area 1, are spaced apart to avoid mutual interference when they are measured.

[0163] For example, the first target M1 and the second target M2 located in the same direction (near the same corner) of the core area 1 can be within a 0.6mm area, so that when drilling the positioning hole N1, the first target M1 and the second target M2 can be removed to avoid the first target M1 and the second target M2 affecting the identification and positioning of other positions of the printed circuit board 100.

[0164] For example, the position of the positioning hole H1 (that is, the setting position of the first target M1 and the second target M2) can be the position where the printed circuit board 100 needs to form an opening (including a through hole H2 or a second through hole H4), so that the positioning hole H1 can be covered after the opening is formed, thereby maximizing the utilization of the design space in the printed circuit board 100.

[0165] In some embodiments, the preparation method may further include:

[0166] S8: See Figure 12 Third targets M3 are set at the four corners of sublayer 10.

[0167] S9: See Figure 18 After step S2, the second positioning hole H3 is obtained using the third target M3.

[0168] S10: See Figure 20 Based on the positioning of the second positioning hole H3, a plurality of second through holes H4 are opened in the regular area 2 of the printed circuit board 100. These plurality of second through holes H4 are used to realize some connections in the regular area 2 of the printed circuit board 100 other than those before the BGA.

[0169] For example, step S8 can be performed simultaneously with step S4.

[0170] For example, step S10 can be performed separately from step S7, and there is no restriction on the order in which they are performed.

[0171] In summary, the embodiments of this application can improve the alignment accuracy of the core area 1 by performing local expansion and contraction compensation on the core area 1. Furthermore, the synergistic innovation of real-time dynamic compensation (adjusting the expansion and contraction coefficient during compensation based on the difference in expansion and contraction) technology and intelligent detection technology can achieve fine control of the expansion and contraction coefficient during local expansion and contraction compensation of the core area 1, thereby further improving the alignment accuracy of the core area 1. In addition, the second target M2 is used to achieve high-precision positioning of the drilling position, and the drilling position is dynamically adjusted and refined by real-time monitoring of expansion and contraction, further improving the alignment accuracy of the core area 1. This overcomes the reliability bottleneck of BGA interconnection in high-frequency scenarios and reduces the difficulty of mass production yield control in the core area 1 of the printed circuit board 100 due to material thermal expansion coefficient mismatch, lamination alignment error and drilling accuracy fluctuation.

[0172] The foregoing has provided a detailed description of a method for manufacturing a printed circuit board according to this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and its core ideas. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A method for preparing a printed circuit board, characterized in that, The printed circuit board includes multiple sub-layers stacked together, each sub-layer including a core area, which is used to connect with a ball grid array; The preparation method includes: Measure the expansion and contraction differences between the core areas of multiple sublayers in the printed circuit board; Using the center point of the core area as the expansion and contraction center point, expansion and contraction compensation is performed on the core area of ​​each sub-layer: based on the expansion and contraction difference, the expansion and contraction coefficient of the core area of ​​each sub-layer is determined; using the expansion and contraction coefficient, expansion and contraction compensation is performed on the core area to reduce the expansion and contraction difference; The multilayer sub-layers are stacked and pressed together to obtain the printed circuit board; The measurement of the expansion and contraction differences between the core areas of multiple sublayers in the printed circuit board includes: Before performing expansion and contraction compensation, four first targets are set in the core area of ​​the sub-layer; the four first targets are respectively set near the four corners of the core area; The spacing between the four first targets in each sublayer of the printed circuit board is measured to obtain a first spacing parameter; in the printed circuit board, the first targets in the multilayer sublayers are staggered with each other in the stacking direction of the multilayer sublayers. Based on the first spacing parameter of each sub-layer, the difference between the first spacing parameters in the multiple sub-layers is obtained; the difference between the first spacing parameters represents the expansion and contraction difference between the core areas of the multiple sub-layers.

2. The preparation method according to claim 1, characterized in that, The expansion and contraction compensation of the core area of ​​each sub-layer using the center point of the core area as the expansion and contraction center point includes: The sub-layer is subjected to expansion and contraction compensation with the center point of the core area as the expansion and contraction center point.

3. The preparation method according to claim 1, characterized in that, The sub-layer also includes a regular area, which is arranged around the core area; The method of compensating for the expansion and contraction of the core area of ​​each sub-layer using the center point of the core area as the expansion and contraction center point also includes: The expansion and contraction compensation of the conventional area is performed with the center point of the sub-layer as the expansion and contraction center point.

4. The preparation method according to claim 3, characterized in that, The core area is compensated for by a first expansion / contraction coefficient, and the regular area is compensated for by a second expansion / contraction coefficient; the first expansion / contraction coefficient and the second expansion / contraction coefficient are different.

5. The preparation method according to claim 4, characterized in that, The sub-layer further includes a transition area, which is disposed around the core area and is located between the core area and the regular area; The method of compensating for the expansion and contraction of the core area of ​​each sub-layer using the center point of the core area as the expansion and contraction center point also includes: A third expansion / contraction coefficient is used to compensate for the expansion / contraction of the transition region; the third expansion / contraction coefficient is between the first expansion / contraction coefficient and the second expansion / contraction coefficient.

6. The preparation method according to claim 1, characterized in that The sublayer includes a first wiring layer, a second wiring layer, and an insulating layer sandwiched between the first wiring layer and the second wiring layer; The provision of setting four first targets in the core region of the sub-layer includes: The first target is set on the first wiring layer and / or the second wiring layer of each sub-layer.

7. The preparation method according to any one of claims 1 to 5, characterized in that, Also includes: Before performing expansion and contraction compensation, at least two second targets are set on each sub-layer; the at least two second targets are respectively set near the four corners of the core area, and two of the second targets are respectively set near the two corners of the core area arranged diagonally; the second targets in different sub-layers are set in the same position in their respective sub-layers; In the printed circuit board, the multiple overlapping second targets of the multi-layer sub-layers are fitted into a target circle; the target circle is the circle that minimizes the sum of the squared distances from the multiple second targets to the center of the circle. Based on the position of the target circle, the printed circuit board is drilled to obtain positioning holes.

8. The preparation method according to claim 7, characterized in that, Each sub-layer's core area has four primary targets; The step of drilling positioning holes in the printed circuit board based on the position of the target circle includes: The spacing change value of the four first targets in each sub-layer of the printed circuit board is measured to obtain the expansion and contraction state of the core area of ​​the printed circuit board; the spacing change value is the difference between the spacing of the four first targets before the expansion and contraction compensation step and the spacing of the four first targets after the pressing step. The position of the target circle is adjusted based on the expansion and contraction state to obtain the final positioning point; Based on the location of the final positioning point, the printed circuit board is drilled to obtain positioning holes.

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