Semiconductor structure and method of fabricating the same

Abstract

Disclosed are a semiconductor structure and a manufacturing method thereof. The technical problem of how to improve the uniformity of multiple gaps formed by lateral etching is solved. The manufacturing method comprises: forming a laminated structure comprising multiple sacrificial layers and multiple semiconductor layers alternately stacked on a substrate; the multiple sacrificial layers comprise multiple first sacrificial layers and multiple second sacrificial layers, the distance between any one of the second sacrificial layers and the substrate is greater than the distance between any one of the first sacrificial layers and the substrate; the thickness of any one of the second sacrificial layers in the vertical direction is greater than the thickness of any one of the first sacrificial layers in the vertical direction; forming a groove extending along a first horizontal direction and penetrating through the laminated structure; laterally etching each sacrificial layer through the groove to form a gap between two adjacent semiconductor layers; and the width of any two gaps in a second horizontal direction is the same. In this way, the precise side etching of the sacrificial layers in the upper and lower laminated structures can be realized, and the width uniformity of each gap formed is improved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of semiconductor technology, and relate to but are not limited to a semiconductor structure and a manufacturing method thereof. BACKGROUND

[0002] Each memory cell of a dynamic random access memory (DRAM) usually includes a transistor and a capacitor. The gate of the transistor is coupled to a word line (also referred to as a word line structure), one of the source and the drain of the transistor is coupled to a bit line (also referred to as a bit line structure), and the other of the source and the drain of the transistor is coupled to the capacitor (also referred to as a capacitor structure or a capacitor).

[0003] With the continuous development of semiconductor technology, DRAM is developing in the direction of higher integration and smaller size in three dimensions. DRAM with a three-dimensional architecture is usually referred to as three-dimensional DRAM (3D DRAM for short). At present, 3D DRAM still needs to be further improved. SUMMARY

[0004] According to a first aspect of embodiments of the present disclosure, a manufacturing method of a semiconductor structure is provided, including: providing a substrate; forming a stack structure on the substrate, the stack structure including a plurality of sacrificial layers and a plurality of semiconductor layers alternately stacked; wherein the plurality of sacrificial layers includes a plurality of first sacrificial layers and a plurality of second sacrificial layers, a distance between any one of the second sacrificial layers and the substrate is greater than a distance between any one of the first sacrificial layers and the substrate; a thickness of any one of the second sacrificial layers in a vertical direction is greater than a thickness of any one of the first sacrificial layers in the vertical direction, the vertical direction being perpendicular to a main surface of the substrate; forming a trench extending along a first horizontal direction and penetrating through the stack structure, the first horizontal direction being parallel to the main surface of the substrate; and laterally etching each of the sacrificial layers through the trench to form a gap between two adjacent semiconductor layers; wherein a width of any two of the gaps in a second horizontal direction is the same, the second horizontal direction being parallel to the main surface of the substrate and perpendicular to the first horizontal direction.

[0005] In some embodiments, the manufacturing method further includes: thinning each of the semiconductor layers through the gap to form a plurality of semiconductor patterns arranged along the vertical direction; and forming a plurality of transistors stacked along the vertical direction based on the plurality of semiconductor patterns; wherein the plurality of transistors includes a plurality of first transistors and a plurality of second transistors, a distance between any one of the second transistors and the substrate is greater than a distance between any one of the first transistors and the substrate; and a spacing between the semiconductor patterns of any two adjacent second transistors in the vertical direction is greater than a spacing between the semiconductor patterns of any two adjacent first transistors in the vertical direction.

[0006] In some embodiments, a thickness of any two of the second sacrificial layers in the vertical direction is the same.

[0007] In some embodiments, a thickness of the plurality of second sacrificial layers in the vertical direction increases in a direction away from the substrate.

[0008] In some embodiments, a material of each of the semiconductor layers includes silicon, and a material of each of the sacrificial layers includes silicon germanium; wherein a germanium content of any one of the second sacrificial layers is greater than a germanium content of any one of the first sacrificial layers.

[0009] According to a second aspect of embodiments of the present disclosure, a semiconductor structure is provided, including: a substrate and a plurality of transistors stacked along a vertical direction on the substrate; wherein the plurality of transistors includes a plurality of first transistors and a plurality of second transistors, a distance between any one of the second transistors and the substrate is greater than a distance between any one of the first transistors and the substrate; and each of the transistors includes a semiconductor pattern extending along a horizontal direction, a spacing between the semiconductor patterns of any two adjacent second transistors in the vertical direction is greater than a spacing between the semiconductor patterns of any two adjacent first transistors in the vertical direction, the vertical direction is perpendicular to a main surface of the substrate, and the horizontal direction is parallel to the main surface of the substrate.

[0010] In some embodiments, a width of the semiconductor pattern of any two of the transistors in the horizontal direction is the same.

[0011] In some embodiments, a spacing between the semiconductor patterns of each of any two adjacent second transistors of the plurality of second transistors in the vertical direction is the same.

[0012] In some embodiments, a spacing between the semiconductor patterns of each of any two adjacent second transistors of the plurality of second transistors in the vertical direction increases in a direction away from the substrate.

[0013] In some embodiments, the semiconductor structure further comprises: a plurality of capacitors stacked, the plurality of capacitors comprising a plurality of first capacitors and a plurality of second capacitors, a first lower electrode of the first capacitors connected to the first transistor, a second lower electrode of the second capacitors connected to the second transistor; wherein a distance between any two adjacent second lower electrodes is greater than a distance between any two adjacent first lower electrodes.

[0014] According to a third aspect of embodiments of the present disclosure, a method for manufacturing a semiconductor structure is provided, comprising: providing a substrate; forming a stack structure on the substrate, the stack structure comprising a plurality of sacrificial layers and a plurality of semiconductor layers stacked alternately; wherein the plurality of sacrificial layers comprises a plurality of first sacrificial layers and a plurality of second sacrificial layers, a distance between any one of the second sacrificial layers and the substrate is greater than a distance between any one of the first sacrificial layers and the substrate; a material of each of the sacrificial layers comprises silicon germanium, a germanium content of any one of the second sacrificial layers is greater than a germanium content of any one of the first sacrificial layers; forming a trench extending along a first horizontal direction and penetrating through the stack structure, the first horizontal direction being parallel to a main surface of the substrate; laterally etching each of the sacrificial layers through the trench to form a gap between two adjacent semiconductor layers; wherein a width of any two of the gaps in a second horizontal direction is the same, the second horizontal direction being parallel to the main surface of the substrate and perpendicular to the first horizontal direction.

[0015] In some embodiments, the germanium content of any two of the second sacrificial layers is the same.

[0016] In some embodiments, in a direction away from the substrate, the germanium content of the plurality of second sacrificial layers increases in a gradient.

[0017] In embodiments of the present disclosure, since the thickness of any one of the second sacrificial layers is greater than the thickness of any one of the first sacrificial layers or the germanium content of any one of the second sacrificial layers is greater than the germanium content of any one of the first sacrificial layers, the lateral etching amount of each sacrificial layer can be better controlled, thereby solving the problem of slow side etching of the upper stack layer (i.e., the second sacrificial layer) in the lateral etching process, so that each gap formed has the same width. In this way, precise side etching of the sacrificial layers in the upper and lower stack layers can be achieved, thereby improving the uniformity of the width of each gap formed. BRIEF DESCRIPTION OF DRAWINGS

[0018] In the drawings, like reference numerals refer to same or similar functionalities throughout the several views. The drawings are not necessarily to scale. It is to be understood that the drawings only depict several embodiments of the disclosure and should not be considered to limit the scope of the disclosure.

[0019] Figure 1 is a schematic diagram of wafer warpage as a function of the number of layers of a stack;

[0020] Figure 2 is a schematic diagram of wafer warpage for wafers having silicon germanium layers with different germanium fractions;

[0021] Figure 3 is a schematic diagram of wafer cross-sectional etching for wafers having silicon germanium layers with different germanium fractions;

[0022] Figure 4 is a flowchart of a method of fabricating a semiconductor structure according to an embodiment of the present disclosure;

[0023] Figure 5 is a partial cross-sectional view after trench formation according to an embodiment of the present disclosure;

[0024] Figure 6 is a partial cross-sectional view after gap formation according to an embodiment of the present disclosure;

[0025] Figure 7 is a partial cross-sectional view after semiconductor pattern formation according to an embodiment of the present disclosure;

[0026] Figure 8 is a partial cross-sectional view after transistor formation according to an embodiment of the present disclosure;

[0027] Figure 9 is a partial cross-sectional view after bit line formation according to an embodiment of the present disclosure;

[0028] Figure 10 is a partial cross-sectional view after capacitor formation according to an embodiment of the present disclosure;

[0029] Figure 11 is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure;

[0030] Figure 12 is a flowchart of a method of fabricating a semiconductor structure according to another embodiment of the present disclosure;

[0031] Figure 13 is a partial cross-sectional view after trench formation according to another embodiment of the present disclosure;

[0032] Figure 14 is a schematic diagram of etch rate of silicon germanium as a function of germanium fraction according to an embodiment of the present disclosure;

[0033] Figure 15 is a schematic diagram of etch rate of silicon germanium as a function of silicon germanium layer thickness according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] In order to facilitate the understanding of the present disclosure, exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it is understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure can be more thoroughly understood, and so that the scope of the present disclosure can be conveyed to those skilled in the art.

[0035] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure can be practiced without one or more of these specific details. In some embodiments, in order to avoid obscuring the present disclosure, some well-known features are not described; that is, actual implementation of the embodiments can not include all the features described herein, and well-known functions or constructions can not be described in detail.

[0036] Generally, terminology can be understood at least in part from usage in context. For example, terms, as used herein, can be used in a singular sense or in a plural sense depending upon the context in which the terms are used. Similarly, terms, such as "one" or "said" can be read to convey a singular or plural usage, depending upon the context. Further, terms, such as "based on" can be understood as not necessarily requiring explicitly-cited factors but instead can also include other factors that are not expressly recited, as understood by those having ordinary skill in the art. Additionally, terms, such as "based on" can be understood as not necessarily requiring exclusive factors but instead can also allow for additional factors that are not necessarily explicitly recited, again as understood by those having ordinary skill in the art.

[0037] Unless otherwise defined, terms used herein are for descriptive purposes only and do not limit the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0038] For a thorough understanding of the present disclosure, detailed steps and detailed structures will be set forth in the following description below with reference to the following drawings. The preferred embodiments of the present disclosure are described in detail below, however, the present disclosure can have other embodiments in addition to those described.

[0039] Before introducing the embodiments of this disclosure, the various directions that may be involved below are defined. The direction perpendicular to the main surface of the substrate is defined as the vertical direction (represented as the Z direction in the figure). In a plane parallel to the main surface of the substrate, a first horizontal direction (represented as the X direction in the figure) and a second horizontal direction (represented as the Y direction in the figure) that are perpendicular to each other are defined, that is, the X direction and the Y direction are perpendicular to and parallel to the main surface of the substrate, and the Z direction is perpendicular to the main surface of the substrate.

[0040] Traditional processes typically rely on the periodic superlattice growth of silicon (Si) / silicon germanium (SiGe) to achieve the structure of 3D DRAM. Specifically, the lengths of capacitors and transistors within the memory cells can be precisely defined by laterally etching the silicon germanium in the stack.

[0041] Figure 1 This is a schematic diagram illustrating how the warpage of a wafer varies with the number of layers in a stack. (Refer to...) Figure 1 As shown, with the increase in the number of Si / SiGe layers, the wafer warpage also increases, even exceeding the limits of existing memory devices. To reduce wafer warpage, the Ge composition (also known as Ge content) in the SiGe layer can be reduced.

[0042] Figure 2 This is a schematic diagram showing the warpage of wafers corresponding to silicon-germanium layers with different germanium compositions. Figure 2 In Figures (a), (b), and (c), the Ge composition increases sequentially, for example, from 15% to 20% to 25%. Correspondingly, the wafer warpage also increases sequentially, meaning that reducing the Ge composition in the SiGe layer can reduce wafer warpage. However, reducing the Ge composition in the SiGe layer also leads to a decrease in the uniformity of lateral etching (also known as side-cutting).

[0043] Figure 3 These are cross-sectional views of wafers after lateral etching for silicon-germanium layers with different germanium compositions. (Refer to...) Figure 3 As shown, lateral etching can create gaps between two adjacent Si layers. Because... Figure 3 In Figure (b), the Ge composition (e.g., 15%) of the SiGe layer is less than... Figure 3 In Figure (a), the Ge composition of the SiGe layer (e.g., 25%) leads to Figure 3 In Figure (b), the uniformity of the upper SiGe layer after lateral etching is significantly worse. For example, the uniformity of the width of each gap is worse, which will affect the uniformity of the capacitors and transistors formed subsequently, and thus affect the uniformity of each memory cell.

[0044] Based on one or more of the above-mentioned technical problems, this disclosure provides a method for fabricating a semiconductor structure.

[0045] Figure 4 is a flowchart of a method for manufacturing a semiconductor structure. Referring to Figure 4 , the method comprises at least the following steps:

[0046] Step S110: providing a substrate;

[0047] Step S120: forming a stack structure on the substrate, the stack structure comprising a plurality of sacrificial layers and a plurality of semiconductor layers stacked alternately; wherein the plurality of sacrificial layers comprises a plurality of first sacrificial layers and a plurality of second sacrificial layers, a distance between any one of the second sacrificial layers and the substrate is greater than a distance between any one of the first sacrificial layers and the substrate; a thickness of any one of the second sacrificial layers in a vertical direction is greater than a thickness of any one of the first sacrificial layers in the vertical direction, the vertical direction being perpendicular to a main surface of the substrate;

[0048] Step S130: forming a trench extending along a first horizontal direction and penetrating through the stack structure, the first horizontal direction being parallel to the main surface of the substrate;

[0049] Step S140: laterally etching each of the sacrificial layers through the trench to form a gap between two adjacent semiconductor layers; wherein a width of any two of the gaps in a second horizontal direction is the same, the second horizontal direction being parallel to the main surface of the substrate and perpendicular to the first horizontal direction.

[0050] Figures 5 to 10 is a schematic diagram of a structure in a process of manufacturing a semiconductor structure, which will be described below in combination with Figure 4 , Figures 5 to 10 The method for manufacturing a semiconductor structure provided by the embodiments of the present disclosure will be described exemplarily.

[0051] In step S110, referring to Figure 5 , a substrate 202 is provided. The substrate 202 has a front surface and a back surface opposite to each other along a Z direction, Figure 5 The stack structure 204 in the substrate 202 can be formed on the front surface of the substrate 202. In some embodiments, the main surface of the substrate 202 can be the front surface of the substrate 202.

[0052] The material of the substrate 202 can include elemental semiconductor materials (e.g., silicon (Si) or germanium (Ge), etc.), III-V compound semiconductor materials (e.g., gallium nitride (GaN), gallium arsenide (GaAs) or indium phosphide (InP), etc.), II-VI compound semiconductor materials (e.g., zinc sulfide (ZnS), cadmium sulfide (CdS) or cadmium telluride (CdTe), etc.), organic semiconductor materials, or other semiconductor materials known in the art.

[0053] In step S120, referring to Figure 5As shown, a stack structure 204 is formed on the substrate 202, the stack structure 204 includes a plurality of sacrificial layers and a plurality of semiconductor layers 206 which are alternately stacked; wherein the plurality of sacrificial layers includes a plurality of first sacrificial layers 208 and a plurality of second sacrificial layers 210, a distance between any one of the second sacrificial layers 210 and the substrate 202 is greater than a distance between any one of the first sacrificial layers 208 and the substrate 202; a thickness of any one of the second sacrificial layers 210 in a Z direction is greater than a thickness of any one of the first sacrificial layers 208 in the Z direction, the Z direction is perpendicular to a main surface of the substrate 202.

[0054] The forming process of the sacrificial layers and the semiconductor layers 206 includes, but is not limited to, epitaxial growth process, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD) or any combination thereof.

[0055] The material of each semiconductor layer 206 includes silicon, and the material of each sacrificial layer includes silicon germanium. As an example, the silicon germanium can be epitaxially grown on a monocrystalline silicon surface, and the silicon germanium can be selectively oriented and grown on the monocrystalline silicon surface, and the process flow is simple and controllable. Of course, the semiconductor layer 206 can also select other semiconductor materials, and the sacrificial layer can also select other sacrificial materials which have an etching selectivity with the semiconductor layer 206, and the present disclosure has no special limitation thereon.

[0056] The stack structure 204 can include a lower stack 204A and an upper stack 204B, and the plurality of sacrificial layers in the lower stack 204A can be referred to as the first sacrificial layers 208, and the plurality of sacrificial layers in the upper stack 204B can be referred to as the second sacrificial layers 210. Since the lower stack 204A is located between the substrate 202 and the upper stack 204B, the distance between any one of the second sacrificial layers 210 and the substrate 202 is greater than the distance between any one of the first sacrificial layers 208 and the substrate 202.

[0057] In some embodiments, the thickness of any one of the sacrificial layers in the upper stack 204B is greater than the thickness of any one of the sacrificial layers in the lower stack 204A, i.e., the thickness of any one of the second sacrificial layers 210 is greater than the thickness of any one of the first sacrificial layers 208. Figure 5 The thickness of the second sacrificial layer 210 is H2, the thickness of the first sacrificial layer 208 is H1, and H2>H1. In actual applications, the thickness of each sacrificial layer can be controlled by controlling the process parameters for forming each sacrificial layer. For example, the thickness of the SiGe layer can be controlled by controlling the growth time of epitaxy on a monocrystalline silicon surface.

[0058] In some embodiments, the thickness of any two of the plurality of second sacrificial layers 210 in the Z direction is the same, i.e., the thickness of each of the second sacrificial layers 210 in the upper stack 204B is the same, and the thickness of each of the second sacrificial layers 210 is greater than the thickness of any one of the first sacrificial layers 208.

[0059] In other embodiments, the thickness of the plurality of second sacrificial layers 210 in the Z direction increases in a direction away from the substrate 202. Here, the thickness of the plurality of second sacrificial layers 210 can increase with the same or different gradient increments.

[0060] As an example, the thickness of the plurality of second sacrificial layers 210 increases in a direction away from the substrate 202 sequentially, and the thickness of the lowermost second sacrificial layer 210 in the upper stack 204B is greater than the thickness of any one of the first sacrificial layers 208.

[0061] As another example, the thickness of the plurality of second sacrificial layer groups increases in a direction away from the substrate 202 sequentially, and the thickness of each of the second sacrificial layers 210 in a second sacrificial layer group is the same, and a second sacrificial layer group can include at least two second sacrificial layers 210.

[0062] In the above two embodiments, the thickness of the plurality of second sacrificial layers 210 varies regularly. However, in other examples, the thickness of the plurality of second sacrificial layers 210 can vary irregularly, as long as the thickness of any one of the second sacrificial layers 210 is greater than the thickness of any one of the first sacrificial layers 208, and the present disclosure does not have special restrictions thereon.

[0063] It should be noted that the number of sacrificial layers and semiconductor layers 206 in the present embodiment is not limited. In actual applications, it can be reasonably set according to the needs. The thickness in the present embodiment and hereinafter refers to the size of a structure or a film layer in the Z direction, which will not be described again.

[0064] In some embodiments, the thickness of any two of the plurality of first sacrificial layers 208 in the Z direction is the same, i.e., the thickness of each of the first sacrificial layers 208 in the lower stack 204A is the same. Of course, in other embodiments, the thickness of any two of the first sacrificial layers 208 in the lower stack 204A can be different.

[0065] In some embodiments, the thickness of any two of the plurality of semiconductor layers 206 in the Z direction is the same, i.e., the thickness of each of the semiconductor layers 206 in the upper stack 204B and the lower stack 204A is the same.

[0066] In some embodiments, the Ge content of any one of the sacrificial layers in the upper stack 204B is greater than the Ge content of any one of the sacrificial layers in the lower stack 204A, i.e., the Ge content of any one of the second sacrificial layers 210 is greater than the Ge content of any one of the first sacrificial layers 208. In practical applications, the Ge content of each sacrificial layer can be controlled by controlling the process parameters for forming each sacrificial layer. For example, the Ge content of a SiGe layer can be controlled by controlling the flow rate of a Ge source gas for epitaxial growth on a single-crystal silicon surface. The Ge source gas can include GeH4gas, Ge solid, or other Ge-containing reactants.

[0067] In step S130, referring to Figure 5 , a trench 214 is formed extending along the X direction and penetrating through the stack structure 204, the X direction being parallel to the main surface of the substrate 202.

[0068] The forming process of the trench 214 includes but is not limited to a dry etching process. For example, a patterned mask layer 212 is formed on the stack structure 204; a dry etching process is used to etch down the stack structure 204 until the substrate 202 is exposed, thereby forming a trench 214 penetrating through the stack structure 204, the trench 214 can extend along the X direction. Of course, the substrate 202 can be further etched down so that the bottom of the trench 214 extends into the substrate 202, as shown in Figure 5 .

[0069] In step S140, referring to Figure 5 and Figure 6 , each sacrificial layer is laterally etched through the trench 214 to form a gap 216 between two adjacent semiconductor layers 206; wherein the width of any two gaps 216 in the Y direction is the same, the Y direction being parallel to the main surface of the substrate 202 and perpendicular to the X direction.

[0070] The forming process of the gap 216 includes but is not limited to a wet etching process. For example, a wet etching process is used to selectively etch each first sacrificial layer 208 and each second sacrificial layer 210 exposed by the trench 214, thereby forming a gap 216 at the position where each first sacrificial layer 208 and each second sacrificial layer 210 is removed, and a plurality of gaps 216 can be arranged at intervals along the Z direction, and the width of each gap 216 is W.

[0071] In some embodiments, the plurality of gaps 216 includes a plurality of first gaps and a plurality of second gaps, the first gap is formed between two adjacent semiconductor layers 206 in the lower stack 204A, and the second gap is formed between two adjacent semiconductor layers 206 in the upper stack 204B, the size of the second gap in the Z direction is greater than the size of the first gap in the Z direction. In this embodiment, the first gap is formed at the position where the first sacrificial layer 208 is removed, and the second gap is formed at the position where the second sacrificial layer 210 is removed.

[0072] In some embodiments, the lateral etching rate of the second sacrificial layer 210 is the same as that of the first sacrificial layer 208. This allows the lateral etching amount of the second sacrificial layer 210 to be the same as that of the first sacrificial layer 208.

[0073] In this embodiment, since the thickness of any second sacrificial layer 210 is greater than the thickness of any first sacrificial layer 208, the lateral etching amount of each sacrificial layer can be better controlled. This solves the problem of slow side-cutting of the sacrificial layer (i.e., the second sacrificial layer 210) in the upper stack 204B during lateral etching, resulting in all gaps 216 having the same width. Thus, precise side-cutting of the sacrificial layers in the upper and lower stacks 204A can be achieved, thereby improving the uniformity of the width of each gap 216.

[0074] In some embodiments, refer to Figure 6 and Figure 7 As shown, the above manufacturing method further includes: thinning each semiconductor layer 206 through gap 216 to form a plurality of semiconductor patterns 218 spaced apart along the Z direction.

[0075] The process for thinning the semiconductor layer 206 can include, but is not limited to, dry etching. The structure after thinning the semiconductor layer 206 is as follows: Figure 7 As shown, the thinned semiconductor layer 206 forms a semiconductor pattern 218, and the thickness of the semiconductor pattern 218 is less than the thickness of the semiconductor layer 206.

[0076] Thinning the semiconductor layer 206 can increase the size of the gap 216 in the Z direction. It should be noted that some word lines will be formed within the gap 216. By thinning the semiconductor layer 206, the space for forming word lines can be increased, which helps to reduce the coupling between adjacent word lines.

[0077] In some embodiments, refer to Figure 7 As shown, the semiconductor pattern 218 may include a first portion, a second portion, and a third portion arranged sequentially along the Y direction, with the first portion contacting the unthinned semiconductor layer 206; wherein, along the direction from the first portion to the third portion, the thickness of the semiconductor pattern 218 gradually decreases in the Z direction. The first portion may be either a source or a drain, the second portion may be a channel, and the third portion may be either a source or a drain.

[0078] In some embodiments, refer to Figure 7 and Figure 8As shown, the manufacturing method further includes: based on the plurality of semiconductor patterns 218, forming a plurality of transistors stacked along the Z direction; wherein the plurality of transistors includes a plurality of first transistors Tr1 and a plurality of second transistors Tr2, a distance between any one of the second transistors Tr2 and the substrate 202 is greater than a distance between any one of the first transistors Tr1 and the substrate 202; and a spacing between semiconductor patterns 218 of any two adjacent second transistors Tr2 in the Z direction is greater than a spacing between semiconductor patterns 218 of any two adjacent first transistors Tr1 in the Z direction.

[0079] In this embodiment, the first transistors Tr1 can be formed based on the semiconductor patterns 218 exposed by the increased first gaps, and the spacing between semiconductor patterns 218 of any two adjacent first transistors Tr1 in the Z direction is the increased first gap. The second transistors Tr2 can be formed based on the semiconductor patterns 218 exposed by the increased second gaps, and the spacing between semiconductor patterns 218 of any two adjacent second transistors Tr2 in the Z direction is the increased second gap. Since the size of the increased second gap in the Z direction is greater than the size of the increased first gap in the Z direction, the spacing between semiconductor patterns 218 of any two adjacent second transistors Tr2 in the Z direction is greater than the spacing between semiconductor patterns 218 of any two adjacent first transistors Tr1 in the Z direction.

[0080] It should be noted that the spacing between the two adjacent semiconductor patterns 218 can be the distance between the top surface of the semiconductor pattern 218 located at the lower layer and the bottom surface of the semiconductor pattern 218 located at the upper layer of the two adjacent semiconductor patterns 218.

[0081] In some embodiments, referring to Figure 7 and Figure 8 As shown, the manufacturing method further includes: based on the plurality of semiconductor patterns 218, forming a plurality of transistors stacked along the Z direction; wherein the plurality of transistors includes a plurality of first transistors Tr1 and a plurality of second transistors Tr2, a distance between any one of the second transistors Tr2 and the substrate 202 is greater than a distance between any one of the first transistors Tr1 and the substrate 202; and a spacing between semiconductor patterns 218 of any two adjacent second transistors Tr2 in the Z direction is greater than a spacing between semiconductor patterns 218 of any two adjacent first transistors Tr1 in the Z direction.

[0082] The formation processes of the first dielectric layer 220, the initial word line structure, and the initial second dielectric layer include, but are not limited to, CVD, PVD, ALD, or any combination thereof. The material of the first dielectric layer 220 includes, but is not limited to, silicon nitride, and the material of the initial second dielectric layer includes, but is not limited to, silicon oxide. The formation process of the word line isolation trench includes, but is not limited to, dry etching.

[0083] The word line isolation structure can divide the initial word line structure into two word line structures 222 and the initial second dielectric layer into two second dielectric layers 224. Each word line structure 222 may include a gate dielectric layer and a gate structure, with the gate dielectric layer located between the channel and the gate structure. Multiple gate structures arranged along the X direction are coupled to each other to form a word line. The gate structure and the word line can refer to the same structure. A portion of the word line located on the channel sidewall can serve as the gate structure in a transistor. That is, multiple transistors arranged along the X direction can be coupled to the same word line, and multiple transistors arranged along the Z direction can be coupled to different word lines.

[0084] It should be noted that, based on the amount of gate structure covering the channel sidewalls, transistors can be classified as single-gate transistors, dual-gate transistors, or gate all-around (GAA) transistors. In practical applications, the type of transistor can be appropriately selected according to requirements.

[0085] In some embodiments, refer to Figure 8 and Figure 9 As shown, the above manufacturing method further includes: forming a bit line 228 in the trench 214, the bit line 228 connecting multiple transistors arranged along the Z direction, for example, the bit line connecting the third part.

[0086] It should be noted that multiple transistors arranged along the Z direction are coupled to the same bit line 228, while multiple transistors arranged along the X direction are coupled to different bit lines 228. Furthermore, Figure 9 The diagram shows transistors located on opposite sides of trench 214 along the Y direction connected to different bit lines 228. Figure 10 The diagram illustrates a bit line isolation structure 238 that physically isolates two bit lines 228 arranged along the Y direction in trench 214 from each other. However, in other embodiments, transistors located on opposite sides of trench 214 along the Y direction may share a bit line 228 (i.e., be connected to the same bit line 228). The material of the bit line isolation structure 238 includes, but is not limited to, silicon oxide.

[0087] In some embodiments, refer to Figure 9 and Figure 10As shown, the manufacturing method further includes: removing the remaining semiconductor layer to form a cavity; sequentially forming a lower electrode 230, a capacitor dielectric layer 232 and an upper electrode 234 in the cavity; wherein the lower electrode 230 is connected to the first part of the transistor. The lower electrode 230, the capacitor dielectric layer 232 and the upper electrode 234 can constitute a capacitor.

[0088] The forming process of the capacitor can include: forming a capacitor hole penetrating through the stack structure 204; removing the remaining semiconductor layer through the capacitor hole to form a cavity in communication with the capacitor hole, the cavity exposing the first part of the transistor; forming a lower electrode 230 covering the capacitor hole and the cavity in a common type; forming a capacitor dielectric layer 232 covering the lower electrode 230 in a common type; forming an upper electrode 234 covering the capacitor dielectric layer 232 in a common type. It should be noted that the upper electrodes 234 of multiple capacitors can be connected in the capacitor hole to constitute a common terminal.

[0089] In some embodiments, referring to Figure 10 As shown, the manufacturing method further includes: removing part of the sacrificial layer, and forming an insulating layer 236 at the position where part of the sacrificial layer is removed. The material of the insulating layer 236 includes but is not limited to silicon oxide.

[0090] Based on the manufacturing method of the semiconductor structure, the embodiments of the present disclosure provide a semiconductor structure which can be formed by using the manufacturing method of any one of the above embodiments.

[0091] Figure 11 is a structural schematic diagram of a semiconductor structure provided by the embodiments of the present disclosure. The semiconductor structure includes but is not limited to 3D DRAM.

[0092] Referring to Figure 11 As shown, the semiconductor structure 300 includes: a substrate 302 and a plurality of transistors stacked along a Z direction on the substrate 302; wherein the plurality of transistors includes a plurality of first transistors Tr1 and a plurality of second transistors Tr2, the distance between any one of the second transistors Tr2 and the substrate 302 is greater than the distance between any one of the first transistors Tr1 and the substrate 302; each transistor includes a semiconductor pattern 318 extending along a Y direction, the pitch of the semiconductor patterns 318 of any two adjacent second transistors Tr2 in the Z direction is greater than the pitch of the semiconductor patterns 318 of any two adjacent first transistors Tr1 in the Z direction, the Z direction is perpendicular to the main surface of the substrate 302, and the Y direction is parallel to the main surface of the substrate 302. For the substrate 302, the first transistor Tr1, the second transistor Tr2 and the semiconductor pattern 318, refer to the related descriptions of the substrate 202, the first transistor Tr1, the second transistor Tr2 and the semiconductor pattern 218 in Figures 5 to 10 The substrate 302, the first transistor Tr1, the second transistor Tr2 and the semiconductor pattern 318 can be referred to the related descriptions of the substrate 202, the first transistor Tr1, the second transistor Tr2 and the semiconductor pattern 218 in

[0093] In some embodiments, the width of the semiconductor pattern 318 of any two transistors in the Y direction is the same.

[0094] In the present embodiment, the width of each of the second gaps formed by the lateral etching is the same. Figure 6 In the present embodiment, the width of each of the second gaps formed by the lateral etching is the same. Figure 7 In the present embodiment, the width of each of the semiconductor patterns 218 formed by the thinning of the semiconductor layer is the same, i.e., the width of the semiconductor pattern of any two transistors in the Y direction is the same.

[0095] In some embodiments, the pitch of the semiconductor pattern 318 of any two adjacent second transistors Tr2 in the Z direction is the same.

[0096] In the present embodiment, the width of each of the second gaps formed by the lateral etching is the same. Figure 5 In the present embodiment, the width of each of the second gaps formed by the lateral etching is the same.

[0097] In other embodiments, the pitch of the semiconductor pattern 318 of each of the adjacent second transistors Tr2 in the Z direction increases in a direction away from the substrate 302.

[0098] In the present embodiment, the width of each of the second gaps formed by the lateral etching is the same. Figure 5 In the present embodiment, the width of each of the second gaps formed by the lateral etching is the same.

[0099] In some embodiments, the semiconductor structure 300 further comprises a first dielectric layer 320 covering a first portion of the semiconductor pattern 318. For the first dielectric layer 320, reference can be made to the related description of the first dielectric layer 220 in the above embodiments, which will not be repeated here. Figure 8 In some embodiments, the semiconductor structure 300 further comprises a first dielectric layer 320 covering a first portion of the semiconductor pattern 318. For the first dielectric layer 320, reference can be made to the related description of the first dielectric layer 220 in the above embodiments, which will not be repeated here. In some embodiments, the semiconductor structure 300 further comprises a first dielectric layer 320 covering a first portion of the semiconductor pattern 318. For the first dielectric layer 320, reference can be made to the related description of the first dielectric layer 220 in the above embodiments, which will not be repeated here.

[0100] In some embodiments, the semiconductor structure 300 further comprises word line structures 322 covering the second portions of the semiconductor patterns 318. For the word line structures 322, reference can be made to the related description of the word line structures 222, which will not be repeated here. Figure 8

[0101] In some embodiments, the semiconductor structure 300 further comprises a second dielectric layer 324 covering the third portions of the semiconductor patterns 318. For the second dielectric layer 324, reference can be made to the related description of the second dielectric layer 224, which will not be repeated here. Figure 8

[0102] In some embodiments, the semiconductor structure 300 further comprises word line isolation structures 326 between any two adjacent word line structures 322 and any two adjacent second dielectric layers 324. For the word line isolation structures 326, reference can be made to the related description of the word line isolation structures 226, which will not be repeated here. Figure 8

[0103] In some embodiments, the semiconductor structure 300 further comprises a bit line 328 extending along the Z direction and connecting a plurality of transistors arranged along the Z direction. For the bit line 328, reference can be made to the related description of the bit line 228, which will not be repeated here. Figure 9

[0104] In some embodiments, the semiconductor structure 300 further comprises a plurality of stacked capacitors, each of which comprises a lower electrode 330, a capacitor dielectric layer 332 and an upper electrode 334. For the lower electrode 330, the capacitor dielectric layer 332 and the upper electrode 334, reference can be made to the related description of the lower electrode 230, the capacitor dielectric layer 232 and the upper electrode 234, respectively, which will not be repeated here. Figure 10

[0105] In some embodiments, the plurality of capacitors comprises a plurality of first capacitors Cap1 and a plurality of second capacitors Cap2, a first lower electrode of the first capacitor Cap1 is connected to the first transistor Tr1, and a second lower electrode of the second capacitor Cap2 is connected to the second transistor Tr2; wherein a spacing between any two adjacent second lower electrodes is greater than a spacing between any two adjacent first lower electrodes.

[0106] In the present embodiment, the spacing between any two adjacent second lower electrodes is the thickness of the second sacrificial layer 210, and the spacing between any two adjacent first lower electrodes is the thickness of the first sacrificial layer 208. Since the thickness of any one second sacrificial layer 210 is greater than the thickness of any one first sacrificial layer 208, the spacing between any two adjacent second lower electrodes is greater than the spacing between any two adjacent first lower electrodes. ​​​​​

[0107] In some embodiments, the semiconductor structure 300 further comprises an insulating layer 336 between any two adjacent lower electrodes 330. For the insulating layer 336, refer to the related description of the insulating layer 236, which will not be repeated here. Figure 10 In some embodiments, the semiconductor structure 300 further comprises an insulating layer 336 between any two adjacent lower electrodes 330. For the insulating layer 336, refer to the related description of the insulating layer 236, which will not be repeated here.

[0108] Based on the above technical problems, the disclosure further provides another method for manufacturing a semiconductor structure.

[0109] Figure 12 is a flowchart of another method for manufacturing a semiconductor structure provided by the disclosure, Figure 13 is a partial cross-sectional view after forming a trench provided by another embodiment of the disclosure, referring to Figure 12 , the manufacturing method comprises at least steps S410 to S440.

[0110] In step S410, referring to Figure 12 and Figure 13 , a substrate 402 is provided. For step S410, refer to the related description of step S110, which will not be repeated here.

[0111] In step S420, referring to Figure 12 and Figure 13 , a stack structure 404 is formed on the substrate 402, the stack structure 404 comprises a plurality of sacrificial layers and a plurality of semiconductor layers 406 stacked alternately; wherein the plurality of sacrificial layers comprises a plurality of first sacrificial layers 408 and a plurality of second sacrificial layers 410, the distance between any one of the second sacrificial layers 410 and the substrate 402 is greater than the distance between any one of the first sacrificial layers 408 and the substrate 402; the material of each sacrificial layer comprises silicon germanium, and the germanium content of any one of the second sacrificial layers 410 is greater than the germanium content of any one of the first sacrificial layers 408.

[0112] The stack structure 404 can comprise a lower stack 404A and an upper stack 404B, and the plurality of sacrificial layers in the lower stack 404A can be referred to as the first sacrificial layers 408, and the plurality of sacrificial layers in the upper stack 404B can be referred to as the second sacrificial layers 410. Since the lower stack 404A is located between the substrate 402 and the upper stack 404B, the distance between any one of the second sacrificial layers 410 and the substrate 402 is greater than the distance between any one of the first sacrificial layers 408 and the substrate 402.

[0113] In some embodiments, the germanium content of any one of the sacrificial layers in the upper stack 404B is greater than the germanium content of any one of the sacrificial layers in the lower stack 404A, i.e. the germanium content of any one of the second sacrificial layers 410 is greater than the germanium content of any one of the first sacrificial layers 408.

[0114] In practical applications, the Ge content of each sacrificial layer can be controlled by controlling the process parameters for forming each sacrificial layer. For example, the Ge content of a SiGe layer can be controlled by controlling the flow rate of a Ge source gas for epitaxial growth on a monocrystalline silicon surface. The Ge source gas can include GeH4gas, Ge solid, or other Ge-containing reaction sources.

[0115] In some embodiments, the Ge content of any two of the plurality of second sacrificial layers 410 is the same, i.e., the Ge content of each second sacrificial layer 410 in the upper stack 404B is the same, and the Ge content of each second sacrificial layer 410 is greater than the Ge content of any first sacrificial layer 408.

[0116] In some embodiments, the Ge content of the plurality of second sacrificial layers 410 increases in a direction away from the substrate 402. Here, the Ge content of the plurality of second sacrificial layers 410 can increase by the same or different gradient increments.

[0117] As an example, the Ge content of the plurality of second sacrificial layers 410 increases in a direction away from the substrate 402 in sequence, and the Ge content of the lowermost second sacrificial layer 410 in the upper stack 404B is greater than the Ge content of any first sacrificial layer 408.

[0118] As another example, the Ge content of the plurality of second sacrificial layer groups increases in a direction away from the substrate 402 in sequence, and the Ge content of each second sacrificial layer 410 in a second sacrificial layer group is the same, and a second sacrificial layer group can include at least two second sacrificial layers 410.

[0119] In the above two embodiments, the Ge content of the plurality of second sacrificial layers 410 varies regularly. However, in other examples, the Ge content of the plurality of second sacrificial layers 410 can vary irregularly, as long as the Ge content of any second sacrificial layer 410 is greater than the Ge content of any first sacrificial layer 408, and the present disclosure does not have special limitations in this regard.

[0120] It should be noted that the number of sacrificial layers and the semiconductor layer 406 in the present embodiment is not limited. In practical applications, it can be reasonably set according to the needs. The Ge content in the present embodiment and hereinafter refers to the atomic percentage of Ge elements in a SiGe layer, and will not be described again.

[0121] In some embodiments, the Ge content of any two of the plurality of first sacrificial layers 408 is the same, i.e., the Ge content of each first sacrificial layer 408 in the lower stack 404A is the same. Of course, in other embodiments, the Ge content of any two of the plurality of first sacrificial layers 408 in the lower stack 404A can be different.

[0122] In some embodiments, the thickness of any one of the sacrificial layers in the upper stack 404B is the same as the thickness of any one of the sacrificial layers in the lower stack 404A, i.e., the thickness of any one of the second sacrificial layers 410 is the same as the thickness of any one of the first sacrificial layers 408, i.e., the thickness of each of the sacrificial layers is the same.

[0123] In some embodiments, the thickness of any two of the semiconductor layers 406 in the Z direction is the same, i.e., the thickness of each of the semiconductor layers 406 in the upper stack 404B and the lower stack 404A is the same.

[0124] In step S430, a trench 414 extending along a first horizontal direction and penetrating the stack structure 404 is formed, the first horizontal direction being parallel to the main surface of the substrate 402. For step S430, refer to the related description of step S130, which will not be repeated here. Figure 12 Figure 13 As shown in FIG. 4B and FIG. 4C, the trench 414 extends along the first horizontal direction and penetrates the stack structure 404.

[0125] In step S440, each of the sacrificial layers is laterally etched through the trench 414 to form a gap between two adjacent semiconductor layers 406; wherein the width of any two of the gaps in a second horizontal direction is the same, the second horizontal direction being parallel to the main surface of the substrate 402 and perpendicular to the first horizontal direction. For step S440, refer to the related description of step S140, which will not be repeated here. Figure 12 Figure 13 As shown in FIG. 4D and FIG. 4E, each of the semiconductor layers 406 is laterally etched through the trench 414 to form a gap between two adjacent semiconductor layers 406.

[0126] In some embodiments, the plurality of gaps comprises a plurality of first gaps and a plurality of second gaps, the first gap being formed between two adjacent semiconductor layers 406 in the lower stack 404A, the second gap being formed between two adjacent semiconductor layers 406 in the upper stack 404B, the size of the second gap in the Z direction being equal to the size of the first gap in the Z direction.

[0127] In the present embodiment, the first gap is formed at the position where the first sacrificial layer 408 is removed, and the second gap is formed at the position where the second sacrificial layer 410 is removed. Since the thickness of the second sacrificial layer 410 is the same as the thickness of the first sacrificial layer 408, the size of the second gap in the Z direction is also the same as the size of the first gap in the Z direction.

[0128] In some embodiments, the lateral etching rate of the second sacrificial layer 410 is the same as the lateral etching rate of the first sacrificial layer 408. In this way, the lateral etching amount of the second sacrificial layer 410 is the same as the lateral etching amount of the first sacrificial layer 408.

[0129] ​​In the embodiments of the present disclosure, since the germanium content of any one of the second sacrificial layers 410 is greater than the germanium content of any one of the first sacrificial layers 408, the lateral etching amount of each sacrificial layer can be better controlled, and the problem of slow side etching of the sacrificial layer (i.e., the second sacrificial layer 410) of the upper layer 404B in the lateral etching process can be solved, so that each gap formed has the same width. In this way, in a first aspect, the precise side etching of the sacrificial layer in the upper and lower layers 404A can be achieved, and the uniformity of the width of each gap formed can be improved; in a second aspect, the decrease of the germanium content of the partial silicon germanium layer can alleviate the wafer warping, which is conducive to reducing the warping degree of the wafer.

[0130] In some embodiments, the manufacturing method further includes: thinning each semiconductor layer 406 through the gap to form a plurality of semiconductor patterns arranged at intervals along the Z direction.

[0131] In some embodiments, the manufacturing method further includes: based on the plurality of semiconductor patterns, forming a plurality of transistors stacked along the Z direction; wherein the plurality of transistors includes a plurality of first transistors and a plurality of second transistors, the distance between any one of the second transistors and the substrate 402 is greater than the distance between any one of the first transistors and the substrate 402; and the interval of the semiconductor patterns of any two adjacent second transistors in the Z direction is equal to the interval of the semiconductor patterns of any two adjacent first transistors in the Z direction. For the forming process of the transistors, refer to the related description of Figure 10 , which will not be repeated here.

[0132] In some embodiments, the manufacturing method further includes: forming a bit line in the trench 414, the bit line connecting the plurality of transistors arranged along the Z direction.

[0133] In some embodiments, the manufacturing method further includes: removing the remaining semiconductor layer 406 to form a cavity; sequentially forming a lower electrode, a capacitor dielectric layer and an upper electrode in the cavity; wherein the lower electrode connects the first part of the transistor. The lower electrode, the capacitor dielectric layer and the upper electrode can constitute a capacitor. For the forming process of the capacitor, refer to the related description of Figure 10 , which will not be repeated here.

[0134] In some embodiments, the manufacturing method further includes: removing part of the sacrificial layer, and forming an insulating layer at the position where the part of the sacrificial layer is removed. For the insulating layer, refer to the related description of the insulating layer 236 in Figure 10 , which will not be repeated here.

[0135] Figure 14 is a schematic diagram of the variation of the etching rate of silicon germanium with the germanium content. For the etching rate of silicon germanium, refer to the related description of Figure 14As shown, the etching rate of the silicon germanium increases with the increase of the germanium content in the silicon germanium layer. Therefore, by adjusting the germanium content of the silicon germanium layer in the upper stack and the lower stack, for example, increasing the germanium content of each sacrificial layer in the upper stack, that is, the germanium content of any one second sacrificial layer is greater than the germanium content of any one first sacrificial layer, the lateral etching amount of the silicon germanium layer in the upper stack and the lower stack in the lateral etching process can be controlled to be consistent, so as to ensure the uniformity of the plurality of gaps formed.

[0136] Figure 15 is a schematic diagram of the change of the etching rate of the silicon germanium with the change of the thickness of the silicon germanium layer provided by the embodiment of the present disclosure. Referring to Figure 15 As shown, the etching rate of the silicon germanium increases with the increase of the thickness of the silicon germanium layer. Therefore, by adjusting the thickness of the silicon germanium layer in the upper stack and the lower stack, for example, increasing the thickness of each sacrificial layer in the upper stack, that is, the thickness of any one second sacrificial layer is greater than the thickness of any one first sacrificial layer, the lateral etching amount of the silicon germanium layer in the upper stack and the lower stack in the lateral etching process can be controlled to be consistent, so as to ensure the uniformity of the plurality of gaps formed.

[0137] The features disclosed in the several product embodiments of the present disclosure can be combined arbitrarily without conflict, to obtain new product embodiments.

[0138] The methods disclosed in the several method embodiments of the present disclosure can be combined arbitrarily without conflict, to obtain new method embodiments.

[0139] It should be understood that the "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that the size of the sequence number of each process in various embodiments of the present disclosure does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The sequence number of the above embodiments of the present disclosure is only for description, not representing the advantages and disadvantages of the embodiments.

[0140] It should be noted that, in the present document, the terms "comprising", "comprising" or any other variant thereof are intended to cover non-exclusive inclusions, so that a process, method, article, or apparatus that comprises a list of elements not only includes those elements, but also includes other elements not expressly listed or inherent to such process, method, article, or apparatus. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0141] The above description is only an embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered by the protection scope of the present disclosure.

Claims

1. A method of fabricating a semiconductor structure, the method comprising: The method comprises: providing a substrate; forming a stack structure on the substrate, the stack structure comprising a plurality of sacrificial layers and a plurality of semiconductor layers stacked alternately; wherein the plurality of sacrificial layers comprises a plurality of first sacrificial layers and a plurality of second sacrificial layers, a distance between any one of the second sacrificial layers and the substrate is greater than a distance between any one of the first sacrificial layers and the substrate; a thickness of any one of the second sacrificial layers in a vertical direction is greater than a thickness of any one of the first sacrificial layers in the vertical direction, the vertical direction being perpendicular to a main surface of the substrate; forming a trench extending along a first horizontal direction and penetrating through the stack structure, the first horizontal direction being parallel to the main surface of the substrate; laterally etching each of the sacrificial layers through the trench to form a gap between two adjacent semiconductor layers; wherein a width of any two of the gaps in a second horizontal direction is the same, the second horizontal direction being parallel to the main surface of the substrate and perpendicular to the first horizontal direction.

2. The method of fabricating a semiconductor structure of claim 1, wherein, The method further comprises: thinning each of the semiconductor layers through the gap to form a plurality of semiconductor patterns spaced along the vertical direction; forming a plurality of transistors stacked along the vertical direction based on the plurality of semiconductor patterns; wherein the plurality of transistors comprises a plurality of first transistors and a plurality of second transistors, a distance between any one of the second transistors and the substrate is greater than a distance between any one of the first transistors and the substrate; a spacing of the semiconductor patterns of any two adjacent second transistors in the vertical direction is greater than a spacing of the semiconductor patterns of any two adjacent first transistors in the vertical direction.

3. The method of fabricating a semiconductor structure according to claim 1 or 2, wherein The thickness of any two of the second sacrificial layers in the vertical direction is the same.

4. The method of fabricating a semiconductor structure according to claim 1 or 2, wherein The thickness of the plurality of second sacrificial layers in the vertical direction increases in a direction away from the substrate.

5. The method of fabricating a semiconductor structure of claim 1, wherein, The material of each of the semiconductor layers comprises silicon, and the material of each of the sacrificial layers comprises silicon germanium; wherein a germanium content of any one of the second sacrificial layers is greater than a germanium content of any one of the first sacrificial layers.

6. A semiconductor structure, characterized by The semiconductor structure is formed by the method of any one of claims 1 to 5; the semiconductor structure comprises: a substrate; a plurality of transistors stacked along a vertical direction on the substrate; wherein the plurality of transistors comprises a plurality of first transistors and a plurality of second transistors, a distance between any one of the second transistors and the substrate is greater than a distance between any one of the first transistors and the substrate; each of the transistors comprises a semiconductor pattern extending along a horizontal direction, a spacing of the semiconductor patterns of any two adjacent second transistors in the vertical direction is greater than a spacing of the semiconductor patterns of any two adjacent first transistors in the vertical direction, the vertical direction being perpendicular to a main surface of the substrate, and the horizontal direction being parallel to the main surface of the substrate.

7. The semiconductor structure of claim 6, wherein, The width of the semiconductor pattern of any two of the transistors in the horizontal direction is the same.

8. The semiconductor structure of claim 6 or 7, wherein, The interval of the semiconductor patterns of any two adjacent second transistors in the plurality of second transistors in the vertical direction is the same.

9. The semiconductor structure of claim 6 or 7, wherein, The interval of the semiconductor patterns of any two adjacent second transistors in the plurality of second transistors in the vertical direction increases in a direction away from the substrate.

10. The semiconductor structure of claim 6, wherein, The semiconductor structure further comprises: a plurality of stacked capacitors comprising a plurality of first capacitors and a plurality of second capacitors, a first lower electrode of the first capacitors being connected to the first transistors, a second lower electrode of the second capacitors being connected to the second transistors; wherein the interval between any two adjacent second lower electrodes is greater than the interval between any two adjacent first lower electrodes.

11. A method of fabricating a semiconductor structure, the method comprising: comprising: providing a substrate; forming a stack structure on the substrate, the stack structure comprising a plurality of sacrificial layers and a plurality of semiconductor layers stacked alternately; wherein the plurality of sacrificial layers comprises a plurality of first sacrificial layers and a plurality of second sacrificial layers, the distance between any one of the second sacrificial layers and the substrate being greater than the distance between any one of the first sacrificial layers and the substrate; the material of each of the sacrificial layers comprising silicon germanium, the germanium content of any one of the second sacrificial layers being greater than the germanium content of any one of the first sacrificial layers; forming a trench extending along a first horizontal direction and penetrating through the stack structure, the first horizontal direction being parallel to the main surface of the substrate; laterally etching each of the sacrificial layers through the trench to form a gap between two adjacent semiconductor layers; wherein the width of any two of the gaps in a second horizontal direction is the same, the second horizontal direction being parallel to the main surface of the substrate and perpendicular to the first horizontal direction.

12. The method of fabricating a semiconductor structure of claim 11, wherein, The germanium content of any two of the plurality of second sacrificial layers is the same.

13. The method of fabricating a semiconductor structure of claim 11, wherein, The germanium content of the plurality of second sacrificial layers increases in a direction away from the substrate.

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