Inductor device and manufacturing method

Abstract

Some aspects relate to an inductor device comprising: a first metal layer comprising a plurality of first interconnects; a second metal including a plurality of second interconnects; a first dielectric layer between the first metal layer and the second metal layer; and an inductor. The inductor includes a plurality of vias, wherein the plurality of vias is configured to couple the plurality of first interconnects to the plurality of second interconnects. The inductor includes a plurality of inductor loops formed by a plurality of vias, a plurality of first interconnects, and a plurality of second interconnects. The inductor also includes a first magnetic layer and a second magnetic layer between the first interconnect and the second interconnect, and a third magnetic layer and optionally a fourth magnetic layer external to the plurality of inductor loops.

Description

[0001] This application is a divisional application of the invention patent with an application date of November 8, 2018, application number 201880076899.1, and invention name “Inductor device and manufacturing method”.

[0002] Priority claim

[0003] This patent application claims priority to patent application No. 15 / 826,735, filed on November 30, 2017, entitled “INDUCTOR APPARATUS AND METHOD OF FABRICATING,” which is assigned to the assignee of this patent application and is hereby expressly incorporated herein by reference. Technical Field

[0004] Various aspects relate to an inductor device embedded in a substrate. Background Art

[0005] Integrated circuits, integrated circuit packages, and electronic devices are continually being driven to smaller form factors. There is also a need for inductors with high inductance density that meet the demand for smaller form factors.

[0006] Figure 1 An example of an inductor in a packaged system is shown. Specifically, Figure 1 1 , a package system 100 is shown that includes a die 102, a plurality of first interconnects 104, a substrate 106, a plurality of second interconnects 108, an inductor 110, and a printed circuit board (PCB) 112. The inductor 110 is coupled to the PCB 112. The inductor 110 requires additional space on the PCB. One disadvantage of the inductor 110 is that it creates a device or package system 100 with a surface area that is larger than that required. For example, for a mobile computing device or a wearable computing device, the package system 100 may be too large. Another disadvantage of the inductor 110 is that it is located far from the die 102. In applications such as radio frequency and voltage regulators, the inductor should be close to the die 102.

[0007] In another embodiment (not shown), inductor 110 can be embedded within PCB 112. A disadvantage of this embodiment is that space is required to route the inductor to other components. In another embodiment (not shown), inductor 110 can be mounted on the back side (i.e., the opposite side) of PCB 112. The back side of PCB 112 can have solder balls (not shown) for coupling to other components. A disadvantage of this embodiment is that it requires reducing the solder balls to make room for inductor 110.

[0008] Figure 2 An example of a solenoid inductor embedded in a substrate is shown in cross-sectional view. Specifically, Figure 2 A substrate 200 is shown, comprising a first metal layer 202, a first dielectric layer 204, a second metal layer 206, a second dielectric layer 210, a third metal layer 212, a third dielectric layer 214, a fourth metal layer 216, and a plurality of vias 218. In one aspect, if substrate 200 is a conventional substrate having a core, second dielectric layer 210 may be in the form of a prepreg material. In another aspect, if substrate 200 is a coreless substrate, second dielectric layer 210 may be any commonly used dielectric. If substrate 200 is a conventional substrate having a core, second dielectric layer 210 will have a greater thickness than in aspects where substrate 200 is a coreless substrate.

[0009] The first metal layer 202 and the fourth metal layer 216 may be ground planes or power planes. Figure 2 Also shown is a first inductor 208 including a plurality of vias 218, as well as a second metal layer 206 and a third metal layer 212. First inductor 208 is embedded in substrate 200. First inductor 208 may be a three-dimensional solenoidal inductor. The inductor loop of first inductor 208 is formed by the plurality of vias 218, the second metal layer 206, and the third metal layer 212. The second metal layer 206 and the third metal layer 212 lie in the X and Y planes and form a portion of the inductor loop. The plurality of vias 218 lie in the Z plane and form a portion of the inductor loop.

[0010] When current is applied through embedded inductor 208, embedded inductor 208 generates a magnetic field. The magnetic field surrounding embedded inductor 208 can interact with the nearby first metal layer 202 and fourth metal layer 216, significantly reducing the effective inductance of embedded inductor 208. To avoid this problem, first metal layer 202 and fourth metal layer 216 are placed farther apart (in the z-direction), or open space is created in the X, Y plane, and first metal layer 202 and fourth metal layer 216 are not allowed to be above or below inductor 208. The problem is that this makes the entire substrate 200 larger, and therefore makes it more difficult to manufacture small devices for mobile computing devices or wearable computing devices.

[0011] Therefore, there is a need for an improved inductor that can be placed very close to a die (eg, die 102 ) to enable a smaller, compact substrate (eg, substrate 200 ). Summary of the Invention

[0012] Various aspects relate to an inductor apparatus.

[0013] A first example provides an inductor device comprising: a first metal layer comprising a plurality of first interconnects; a second metal layer comprising a plurality of second interconnects; a first dielectric layer between the first metal layer and the second metal layer; and an inductor. The inductor comprises: a plurality of vias configured to couple the plurality of first interconnects to the plurality of second interconnects; a plurality of inductor loops formed by the plurality of vias, the plurality of first interconnects, and the plurality of second interconnects; a first magnetic layer and a second magnetic layer between the plurality of first interconnects and the plurality of second interconnects; and a third magnetic layer external to the plurality of inductor loops. Optionally, the inductor device may include a fourth magnetic layer external to the plurality of inductor loops.

[0014] A second example provides a method for manufacturing an inductor device, the method comprising: depositing a first magnetic layer and a second magnetic layer inside a first dielectric layer; forming a plurality of through-holes in the first dielectric layer; patterning a plurality of first interconnects and a plurality of second interconnects coupled together through the plurality of through-holes, wherein the plurality of through-holes, the plurality of first interconnects, and the plurality of second interconnects form a plurality of inductor loops; and depositing a third magnetic layer outside the plurality of inductor loops, wherein the first magnetic layer and the second magnetic layer are located between the plurality of first interconnects and the plurality of second interconnects. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The various aspects, properties and advantages will become apparent from the detailed description set forth below when taken in conjunction with the accompanying drawings, in which like reference numerals identify correspondingly throughout.

[0016] Figure 1 A conventional inductor in a packaged system is shown.

[0017] Figure 2 A conventional solenoidal inductor is shown embedded in a substrate.

[0018] Figure 3 (including Figures 3A-3E ) shows an inductor device in multiple cross-sectional views on the X, Y and Z axes.

[0019] Figure 4 An inductor arrangement comprising two inductors is shown.

[0020] Figure 5 A substrate including an inductor arrangement is shown.

[0021] Figure 6 (including Figures 6A-6F ) shows an example of a sequence for manufacturing an inductor device embedded in a substrate.

[0022] Figure 7 An exemplary flow chart illustrating a high-level method for manufacturing an inductor device is shown.

[0023] Figure 8A system including a voltage regulator and a packaging substrate including an inductor device is shown.

[0024] Figure 9 Various electronic devices are shown that may include the various substrates, integrated devices, integrated device packages, semiconductor devices, dies, integrated circuits, packages, or inductors described herein. DETAILED DESCRIPTION

[0025] In the following description, specific details are given to provide a thorough understanding of various aspects of the present disclosure. However, those skilled in the art will understand that various aspects can be practiced without these specific details. For example, circuits may be shown as block diagrams to avoid obscuring various aspects due to unnecessary detail. In other cases, well-known circuits, structures, and techniques may not be shown in detail to avoid obscuring various aspects of the present disclosure.

[0026] Overview

[0027] Some aspects relate to an inductor device. The inductor device is three-dimensional. The inductor device includes: a first metal layer including a plurality of first interconnects, a second metal layer including a plurality of second interconnects, and a first dielectric between the first and second metal layers. The inductor device also includes an inductor including a plurality of first through-vias and a plurality of second through-vias configured to couple the plurality of first interconnects to the plurality of second interconnects. An inductor loop is formed by the plurality of first through-vias, the plurality of second through-vias, the plurality of first interconnects, and the plurality of second interconnects. The inductor has a first magnetic layer and a second magnetic layer located within the inductor loop. In other words, the first and second magnetic layers are located between the first and second interconnects. The inductor also has a third magnetic layer located outside the inductor loop. The third magnetic layer is parallel to and at least partially aligned with the plurality of first interconnects. The inductor has an optional fourth magnetic layer located outside the inductor loop. The fourth magnetic layer is parallel to and at least partially aligned with the plurality of second interconnects. The first magnetic layer, the second magnetic layer, the third magnetic layer, and the optional fourth magnetic layer provide a path with higher magnetic permeability than the surrounding dielectric material, thereby confining and guiding the magnetic field lines and increasing the inductance density.

[0028] In one aspect, the inductor device can be a stand-alone component configured to be placed together with another component that utilizes the inductor. On the other hand, the inductor device can be integrated or embedded in a substrate that includes the inductor device (i.e., an inductor included in a first metal layer and a second metal layer) and other components or structures, such as other interconnects (e.g., interconnects for electrical coupling) (such as metal layers, pads, traces, through-holes) or passive devices (e.g., inductors, capacitors, resistors) or active devices (e.g., die, transistors). On the other hand, the substrate can include a package substrate (including cored or coreless), an interposer (e.g., silicon or glass), a ceramic package, or a printed circuit board. In one aspect, the inductor device can include a core. On the other hand, the inductor device can be coreless.

[0029] It should be understood that terms such as above, over, below, and under are relative. For example, a device having component X may be described as being "above" component Y. However, if the device is turned over, component X may appear to be "below" component Y. Therefore, such terms (e.g., above, below, and under) are relative to the figures provided.

[0030] Exemplary Inductor Devices

[0031] Figure 3A 、 3B , 3C, 3D, and 3E illustrate an exemplary inductor device 300 in multiple cross-sectional views in the X, Y, and Z axes. Inductor device 300 can be three-dimensional in that it can have aspects in the X, Y, and Z planes. Inductor device 300 can include inductor 301. Inductor 301 can be a magnetic inductor. Inductor 301 can be a solenoid inductor. In one aspect, inductor device 300 can include a standalone component configured to be placed with another component that utilizes magnetic inductor 300. In another aspect, inductor device 300 can be embedded in or integrated into a substrate, as discussed later in this disclosure with respect to Figure 5 discussed.

[0032] Figure 3A The exemplary inductor device 300 is shown from a side view in the X, Y, and Z planes. Specifically, Figure 3A The inductor device 300 is shown to include a first metal layer 330 including a plurality of first interconnects 302a, 302b, 302c, 302d. The plurality of first interconnects 302a-d are formed in the first metal layer 330. The inductor device 300 also includes a second metal layer 332 including a plurality of second interconnects 306a, 306b, 306c. The plurality of second interconnects are formed in the second metal layer 332. The first dielectric layer 360 ( Figure 5) is located between the first metal layer 330 and the second metal layer 332, including between the plurality of first interconnects 302a-d and the plurality of second interconnects 306a-c. Figure 3A -E does not show the first dielectric layer 360, but will be Figure 5 and Figure 6A The first dielectric layer 360 is further shown and discussed.

[0033] The plurality of first vias 308a, 308b, 308c and the plurality of second vias 310a, 310b, 310c are configured to couple the plurality of first interconnects 302a-d to the plurality of second interconnects 306a-c.

[0034] The inductor arrangement 300 is coupled as follows. One of the plurality of first interconnects 302a is coupled to one of the plurality of second vias 310a, one of the plurality of second vias 310a is coupled to one of the plurality of second interconnects 306a, one of the plurality of second interconnects 306a is coupled to one of the plurality of first vias 308a, one of the plurality of first vias 308a is coupled to one of the plurality of first interconnects 302b, one of the plurality of first interconnects 302b is coupled to one of the plurality of second vias 310b, one of the plurality of second vias 310b is coupled to one of the plurality of second interconnects 306b, one of the plurality of second interconnects 306b is coupled to one of the plurality of first vias 308b, one of the plurality of first vias 308b is coupled to one of the plurality of first interconnects 302c, one of the plurality of first interconnects 302c is coupled to one of the plurality of second vias 310c, one of the plurality of second vias 310c is coupled to one of the plurality of second interconnects 306c, one of the plurality of second interconnects 306c is coupled to one of the plurality of first vias 308c, and one of the plurality of first vias 308c is coupled to one of the plurality of first interconnects 302d.

[0035] Inductor device 300 includes an inductor 301. Inductor 301 includes a plurality of first vias 308a-c, a plurality of second vias 310a-c, a plurality of first interconnects 302a-d, and a plurality of second interconnects 306a-c. A plurality of inductor loops are formed by the plurality of first vias 308a-c, the plurality of second vias 310a-c, the plurality of first interconnects 302a-d, and the plurality of second interconnects 306a-c.

[0036] The inductor 301 may have Figure 3E The width shown (eg, the width may be measured across one of the plurality of first interconnects, such as 302b), and may have Figure 3E The inductor 301 may have a length Figure 3EThe thickness shown (eg, the thickness may be the height of the plurality of first vias 308a-c plus the thickness of the first metal layer 330 and the second metal layer 332). In other words, the inductor 301 has dimensions including a length, a width, and a thickness.

[0037] Inductor 301 also includes a first magnetic layer 320 and a second magnetic layer 322 positioned between and parallel to first interconnects 302a-d and second interconnects 306a-c (e.g., wherein first magnetic layer 322 and second magnetic layer 322 are parallel to first interconnects 302a-d and second interconnects 306a-c because they are juxtaposed with, but not in the same plane as, first interconnects 302a-d and second interconnects 306a-c). In other words, first magnetic layer 320 and second magnetic layer 322 are positioned between first metal layer 330 and second metal layer 332. First magnetic layer 320 and second magnetic layer 322 are positioned at least partially within the plurality of inductor loops. First magnetic layer 320 and second magnetic layer 322 are positioned at least partially within the plurality of first through-vias 308a-c and the plurality of second through-vias 310a-c.

[0038] exist Figure 3A In the example of FIG. 3 , the first magnetic layer 320 and the second magnetic layer 322 may be located on the first dielectric layer 360 ( Figure 3A Not shown in -E, but see Figure 5 ) inside, wherein the first dielectric layer 360 is located between the first metal layer 330 and the second metal layer 332. Figure 5 The first dielectric layer 360 is discussed further.

[0039] Figure 3E The dimensions, i.e., length, width, and thickness, of any of the first magnetic layer 320, the second magnetic layer 322, the third magnetic layer 324, or the fourth magnetic layer 326 are shown. The lengths of the first magnetic layer 320 and the second magnetic layer 322 can each be less than, equal to, or greater than the length of the inductor 301. For example, the lengths of the first magnetic layer 320 and the second magnetic layer 322 can each range from approximately half the length of the inductor 301 to approximately twice the length of the inductor 301. The first magnetic layer 320 and the second magnetic layer 322 have widths such that the first magnetic layer 320 and the second magnetic layer 322 are each located within the inductor loop of the inductor 310. In other words, the widths of the first magnetic layer 320 and the second magnetic layer 322 are each located between the plurality of first through-holes 308a-c and the plurality of second through-holes 310a-d. The thicknesses of the first magnetic layer 320 and the second magnetic layer 322 can each be approximately 1-4 μm.

[0040] Inductor 301 also includes a third magnetic layer 324. Third magnetic layer 324 is located outside the plurality of inductor loops. Third magnetic layer 324 is parallel to, and at least partially aligned with, the plurality of first interconnects 302a-d. In other words, third magnetic layer 324 is in a plane below (i.e., parallel to) the plurality of first interconnects 302a-d. Third magnetic layer 324 is perpendicular to the plurality of first through-holes 308a-c. Third magnetic layer 324 is perpendicular to the plurality of second through-holes 310a-c.

[0041] Inductor 301 also includes a fourth magnetic layer 326. Fourth magnetic layer 326 is optional. It is located outside the plurality of inductor loops. Fourth magnetic layer 326 is parallel to, and at least partially aligned with, the plurality of second interconnects 306a-c. In other words, fourth magnetic layer 326 is in a plane above (i.e., parallel to) the plurality of second interconnects 306a-c. Fourth magnetic layer 326 is perpendicular to the plurality of first through-holes 308a-c. Fourth magnetic layer 326 is perpendicular to the plurality of second through-holes 310a-c.

[0042] The lengths of the third magnetic layer 324 and the optional fourth magnetic layer 326 can each be less than, equal to, or greater than the length of the inductor 301. For example, the lengths of the first magnetic layer 324 and the second magnetic layer 326 can each range from approximately half the length of the inductor 301 to approximately twice the length of the inductor 301. The widths of the second magnetic layer 324 and the third magnetic layer 326 can each be less than, equal to, or greater than the width of the inductor 301. For example, the widths of the first magnetic layer 324 and the second magnetic layer 326 can each range from approximately half the width of the inductor 301 to approximately twice the width of the inductor 301. The widths of the third magnetic layer 324 and the fourth magnetic layer 326 are not limited to within the first plurality of through-holes 302a-d and the second plurality of through-holes 310a-d, respectively. The thicknesses of the third magnetic layer 324 and the fourth magnetic layer 326 can each be approximately 1-4 μm.

[0043] The first magnetic layer 320, the second magnetic layer 322, the third magnetic layer 324, and the fourth magnetic layer 326 can be formed of a material having high magnetic permeability and low coercivity. Examples of such materials include, but are not limited to, iron alloys (such as NiFe) or cobalt alloys (such as CoTaZr). In one aspect, the first magnetic layer 320, the second magnetic layer 322, the third magnetic layer 324, and the fourth magnetic layer 326 can be formed of one or more layers of magnetic material. In another aspect, any one or more of the first magnetic layer 320, the second magnetic layer 322, the third magnetic layer 324, and the fourth magnetic layer 326 can be formed of a first magnetic material and a second magnetic material, and a thin oxide layer between the first magnetic material and the second magnetic material. Each or more of the first magnetic layer 320, the second magnetic layer 322, the third magnetic layer 324, and the fourth magnetic layer 326 may be composed of the same material or a different material, or some combination, than any other layer of magnetic material (e.g., the first magnetic layer 320 and the second magnetic layer 322 may be composed of a first material or composite material, and the third magnetic layer 324 and the fourth magnetic layer may be composed of a second material or composite material that is different from the first material).

[0044] Each or more of the first magnetic layer 320, the second magnetic layer 322, the third magnetic layer 324, and the fourth magnetic layer 326 may have a different size or the same size (length, width, or thickness) or shape as any other magnetic layer. Figure 3A and Figure 3B The illustrated inductor 301 shows the first magnetic layer 320, the second magnetic layer 322, the third magnetic layer 324, and the fourth magnetic layer 326 as having specific sizes and shapes. However, this is not limited to this. In one aspect, the first magnetic layer 320, the second magnetic layer 322, the third magnetic layer 324, and the fourth magnetic layer 326 can be square, or they can be rectangular, but oriented so that the long side of the rectangle is along the X-axis rather than along the Y-axis as shown. In another aspect, the first magnetic layer 320, the second magnetic layer 322, the third magnetic layer 324, and the fourth magnetic layer 326 can be polygonal. Figure 3AThe first, second, third, and fourth magnetic layers (i.e., 320, 322, 324, 326, respectively) are shown as a single sheet (i.e., a single magnetic layer sheet). However, in another aspect, the first, second, third, and fourth magnetic layers 320, 322, 324, and 326 can be comprised of multiple magnetic layer portions, where the magnetic layer portions can have a variety of shapes, including, but not limited to, square, rectangular, or polygonal. In another aspect, the multiple magnetic layer portions can mirror the shape or size, or both, of the plurality of first interconnects 302a-d or the plurality of second interconnects 306a-c. In each of the above examples, each magnetic layer (i.e., first magnetic layer 320, second magnetic layer 322, third magnetic layer 324, fourth magnetic layer 326) can have a different size or shape than each other magnetic layer (i.e., first magnetic layer 320, second magnetic layer 322, third magnetic layer 324, fourth magnetic layer 326), can have the same size or shape, or can have some combination of different and the same size, shape, or orientation.

[0045] When current is applied to the inductor 301, the inductor 301 generates a first magnetic field. The first magnetic layer 320 and the second magnetic layer 322 increase the inductance of the inductor 301 by, for example, confining and guiding the first magnetic field through a low permeability material. However, the inductor device 300 including the inductor 301 can be placed or integrated into other conductive metal layers (e.g., see Figure 5 This can also reduce inductance in devices (e.g., substrates) near the third metal layer 534 in the inductor 301. These other conductive metal layers generate a second magnetic field when current flows through them. In this case, the third magnetic layer 324 and the fourth magnetic layer 326 confine the second magnetic field to the low permeability material and reduce the effect of the second magnetic field on the inductor 301. For example, the third magnetic layer 324 and the fourth magnetic layer 326 limit eddy currents (e.g., eddy currents from surrounding conductors including the third metal layer 534), which would otherwise cause energy loss and inductance loss in the inductor 301.

[0046] Figure 3B An exemplary inductor device 300 is shown from a top view. In the top view, the inductor device 300 is shown in the XY plane, with the positive Z axis pointing out of the page. This view also shows that a plurality of first through-vias 308a-c and a plurality of second through-vias 310a-c couple together a plurality of first interconnects 302a-d and a plurality of second interconnects 306a-c. Inductor 301 can form a solenoid. For simplicity, the first, second, third, and fourth magnetic layers (320, 322, 324, and 326, respectively) are shown as a shaded area.

[0047] Figure 3CAn exemplary inductor device 300 is shown from a cross-sectional view. In the cross-sectional view, the inductor device 300 is shown in the XZ plane, with the positive Y axis pointing out of the page. Figure 3C The width of the inductor 301 is shown, where the width of the inductor 301 may be a measurement of one of the plurality of first interconnects (eg, 302b), or a measurement of one of the plurality of second interconnects (eg, 306a). Figure 3C Also shown are one of the first plurality of through-holes (eg, 308a) and one of the second plurality of through-holes (eg, 310a). Figure 3C Also shown in cross-sectional view are a first magnetic layer 320 , a second magnetic layer 322 , a third magnetic layer 324 , and an optional fourth magnetic layer 326 .

[0048] Figure 3D Another cross-sectional view shows an exemplary inductor device 300. In this cross-sectional view, the inductor device 300 is shown in the Y, Z plane, with the positive X axis pointing out of the page. Figure 3D Shown are views of each of the plurality of first interconnects 302a-d, views of each of the plurality of second interconnects 306a-c, and views of the plurality of first vias 308a-c. Figure 3D Also shown in cross-sectional view are a first magnetic layer 320, a second magnetic layer 322, a third magnetic layer 324, and an optional fourth magnetic layer 326. The length of the inductor 301 is also shown.

[0049] although Figure 3A The diagram of FIG-E shows an example of a single inductor (eg, inductor 301), but it should be understood that the previous discussion also applies to one or more inductors. In addition, inductor 301 may be formed with a ratio Figure 3A -E, depending on the desired inductance. In addition, the number of inductor loops can be an integer or a half integer (e.g., 1, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 1 / 2, 2, 2 1 / 2, etc.).

[0050] Example inductor arrangement comprising two inductors

[0051] Figure 4 Shows something like Figure 3A A three-dimensional inductor arrangement 400 is the same as the inductor arrangement 300 of FIG. 1 , but with two inductors. Figure 4 An exemplary first inductor 450 and an exemplary second inductor 455 are shown. Either or both of the first inductor 450 and the second inductor 455 may be connected to Figure 3A -E inductor 301 is the same.

[0052] First inductor 450 includes a plurality of first interconnects 402a, 402b, and 402c, a plurality of second interconnects 406a, 406b, 406c, a plurality of first vias 410a, 410b, 410c, and a plurality of second vias 410d, 410e, 410f. The plurality of first interconnects 402a-c, the plurality of second interconnects 406a-c, the plurality of first vias 410a-c, and the plurality of second vias 410d-f together form a plurality of inductor loops of first inductor 450 and are coupled as described in the discussion of inductor device 300. The plurality of first interconnects 402a-c are formed in first metal layer 430, and the plurality of second interconnects 406a-c are formed in second metal layer 432.

[0053] Second inductor 455 includes a plurality of third interconnects 404a, 404b, 404c, a plurality of fourth interconnects 408a, 408b, a plurality of third vias 412a, 412b, and a plurality of fourth vias 412c, d. The plurality of third interconnects 404a-c, the plurality of fourth interconnects 408a, b, the plurality of third vias 412a, b, and the plurality of fourth vias 412c, d together form a plurality of inductor loops of second inductor 455 and are coupled as described in the discussion of inductor device 300. The plurality of third interconnects 404a-c are formed in first metal layer 430, and the plurality of fourth interconnects 408a, b are formed in second metal layer 432.

[0054] Dielectric layer 460 (for simplicity, dielectric layer 460 is not shown here, but see Figure 5 ) is located between the first metal layer 430 and the second metal layer 432 , including between the multiple inductor loops of the first inductor 450 and the multiple inductor loops of the magnetic inductor 455 .

[0055] Similar to inductor 301, first magnetic layer 420 and second magnetic layer 422 are at least partially located within the multiple inductor loops of first inductor 450 and at least partially located within the multiple inductor loops of second inductor 455. It should be understood that although first magnetic layer 420 and second magnetic layer 422 are at least partially located within the inductor loops (of first inductor 450 and second inductor 455, respectively), the lengths of first magnetic layer 420 and second magnetic layer 422 can extend beyond first inductor 450 and second inductor 455. Similarly, third magnetic layer 424 and optional fourth magnetic layer 426 are located outside the multiple inductor loops of first inductor 450 and outside the multiple inductor loops of second inductor 455. The lengths or widths of third magnetic layer 424 and optional fourth magnetic layer 426 can be less than or greater than those of first inductor 450 and second inductor 455. The first magnetic layer 420, the second magnetic layer 422, the third magnetic layer 424 and the fourth magnetic layer 426 are Figure 3ASame as described in the discussion of -E.

[0056] although Figure 4 An example of two inductors (e.g., a first inductor 450 and a second inductor 455) is shown, but one skilled in the art may include more or fewer inductors with more or fewer inductor loops, depending on the needs of the design. The first inductor 450 and the second inductor 455 may have the same number of inductor loops as each other, or may have a different number of inductor loops than each other. In other words, one of the first inductor 450 or the second inductor 455 may have more inductor loops than the other. For example, the second inductor 455 may have more additional inductor loops (not shown) than the third interconnect 404c, and these additional inductor loops are not interleaved with the inductor loops of the first inductor 450. The number of inductor loops of the first inductor 450 and the second inductor 455 may be an integer or a half-integer.

[0057] Exemplary substrate including an inductor device

[0058] Figure 5 The diagram shows the structure of the substrate 500 embedded or integrated in the X and Z planes. Figure 3A -E inductor device 300, where the positive Y axis points out of the page (e.g. Figure 3C shown).

[0059] In one aspect, substrate 500 may be a device that includes inductor device 300 and other components or structures such as other interconnects (e.g., interconnects for electrical coupling, such as metal layers, pads, traces, vias) or passive devices (e.g., inductors, capacitors, resistors) or active devices (e.g., chips, transistors). In one aspect, substrate 500 may include a package substrate (including a core or coreless), an interposer (e.g., silicon or glass), a ceramic package, or a PCB.

[0060] Figure 5 A substrate 500 is shown, which includes: the aforementioned inductor device 300 (including the first magnetic layer 320, the second magnetic layer 322, the third magnetic layer 324, and the optional fourth magnetic layer 326), the first metal layer 330 further including a plurality of third interconnects 570 (e.g., pads, traces), the second metal layer 332 further including a plurality of fourth interconnects 572, the third metal layer 534 including a plurality of fourth interconnects 574 (e.g., pads, traces), the fourth metal layer 536 including a plurality of fifth interconnects 576 (e.g., pads, traces), the fifth metal layer 538 including a plurality of sixth interconnects 578 (e.g., pads, traces, redistribution layer), and the sixth metal layer 540 including a plurality of seventh interconnects 580 (e.g., pads, traces, redistribution layer).

[0061] Furthermore, substrate 500 includes a first dielectric layer 360 located between first metal layer 330 and second metal layer 332, between the plurality of first interconnects 302a-d and the plurality of second interconnects 306a-c, between first magnetic layer 320 and second magnetic layer 326, between the first plurality of first interconnects 302a-d and first magnetic layer 320, and between the plurality of second interconnects 306a-c and second magnetic layer 326. In other words, first magnetic layer 320 and second magnetic layer 322 may be located within first dielectric layer 360. In one aspect, first dielectric layer 360 is a prepreg material. In this aspect, first dielectric layer 360 comprises the core of substrate 500 (e.g., substrate 500 is a conventional substrate having a core). In another aspect, first dielectric layer 360 may be a dielectric layer of a coreless substrate (e.g., substrate 500 is a coreless substrate).

[0062] Second dielectric layer 562 is located between first metal layer 330 and third metal layer 534, between the plurality of first interconnects 302a-d and third metal layer 534, between the plurality of first interconnects 302a-d and third magnetic layer 324, and between third magnetic layer 324 and third metal layer 534. In other words, third magnetic layer 324 can be located inside second dielectric layer 562. Third dielectric layer 564 is located between third metal layer 534 and fifth metal layer 538, between the plurality of second interconnects 306a-c and fifth metal layer 562, between the plurality of second interconnects 306a-c and optional fourth magnetic layer 326, and between optional fourth magnetic layer 326 and fifth metal layer 538. In other words, fourth magnetic layer 326 can be located inside third dielectric layer 564.

[0063] Fourth dielectric layer 566 is located between second metal layer 332 and fourth metal layer 536, including between plurality of second interconnects 306a-c and fourth metal layer 536. Fifth dielectric layer 568 is located between sixth metal layer 540 and fourth metal layer 536. The first through sixth dielectric layers (i.e., 360, 562, 564, 566, and 568, respectively) are configured to isolate the first through sixth metal layers (i.e., 330, 332, 534, 536, 538, and 540, respectively).

[0064] Each or more of the first dielectric layer 360, the second dielectric layer 562, the third dielectric layer 564, the fourth dielectric layer 566 and the fifth dielectric layer 568 can have the same material, different materials or a combination of materials, such as but not limited to prepreg, an insulating film (e.g., Ajinomoto build-up film) or a laminate film.

[0065] A plurality of first vias 554 (although only one via is shown in this view, it should be understood that there are multiple vias) couple the plurality of sixth interconnects 578 to the plurality of fourth interconnects 574, the plurality of second vias 552 couple the plurality of fourth interconnects 574 to the plurality of third interconnects 570, the plurality of third vias 550 couple the plurality of third interconnects 570 to the plurality of fourth interconnects 574, the plurality of fourth vias 556 couple the plurality of fourth interconnects 574 to the plurality of fifth interconnects 576, and the plurality of fifth vias 558 couple the plurality of fifth interconnects 576 to the plurality of seventh interconnects 580.

[0066] As described above, the substrate 500 may include a packaging substrate (including a core or coreless), an interposer (e.g., silicon or glass), a ceramic package, or a printed circuit board. In one aspect, where the substrate 500 includes a packaging substrate, other components not shown may be included, such as interconnects for coupling to the die and the PCB, solder balls, solder paste, copper pillars. On the other hand, where the substrate 500 includes an interposer, other components not shown may be included, such as interconnects for coupling to the die or packaging substrate. On the other hand, where the substrate 500 includes a PCB, other components not shown may be included, such as interconnects for coupling to the packaging substrate or passive devices.

[0067] although Figure 5 A single inductor device 300 (i.e., a single inductor 301) is shown embedded or integrated into substrate 500, but it should be understood that the foregoing discussion also applies to one or more inductor devices. In one aspect, inductor device 400 can be embedded or integrated into substrate 500 (instead of inductor device 300). In another aspect, substrate 500 can have multiple inductors (such as multiple inductor devices 300). In any of these aspects, inductor 301 can be formed with a plurality of inductors. Figure 3A -E or Figure 4 More or fewer inductor loops as shown.

[0068] Exemplary sequence for fabricating an inductor device embedded in a substrate

[0069] In some implementations, manufacturing the inductor device includes several processes. Figures 6A-6F ) shows an exemplary sequence for fabricating an inductor device 699 including an inductor 698 embedded in a substrate 600. The inductor device 699 can be three-dimensional in that it can have aspects in the X, Y, and Z axes. The inductor device 699 and the substrate 600 are shown in a cross-sectional view in the X, Z plane. In some implementations, Figures 6A-6F The sequence of can be used to manufacture the inductor device 300, the inductor 301 and the substrate 500. It should be noted that Figures 6A-6FThe sequence shown may combine one or more stages to simplify and clarify the sequence.In some implementations, the sequence of the processes may be changed or modified.

[0070] Figure 6A A first dielectric layer 660 is shown including first dielectric portions 660a, 660b, and 660c. The first dielectric layer 660 (including first dielectric portions 660a, 660b, and 660c) may be the same as the first dielectric layer 360. A first dielectric portion 660a is provided.

[0071] A first magnetic layer 620 is deposited onto a first side of the first dielectric portion 660a, and a second magnetic layer 622 is deposited onto a second side of the first dielectric portion 660a. The first magnetic layer 620 can be identical to the first magnetic layer 320, and the second magnetic layer 622 can be identical to the second magnetic layer 322 (including size, shape, and orientation). The first dielectric portion 660b is deposited to at least partially cover the first side of the dielectric portion 660a and cover the first magnetic layer 620. The first dielectric portion 660c is deposited to at least partially cover the second side of the first dielectric portion 660a and cover the second magnetic layer 622. It should be noted that the first dielectric portion 660c can be deposited before the first dielectric portion 660b.

[0072] It is important to note that substrate 600 can be a substrate with a core or a coreless substrate. In one aspect where substrate 600 is a coreless substrate, first dielectric layer 660 can comprise the same material (i.e., first dielectric layer portions 660a, 660b, and 660c can all comprise the same material). In another aspect where substrate 600 is a substrate with a core, first dielectric portion 660a can comprise a prepreg material. In this aspect, the thickness of prepreg first dielectric portion 660a is greater than the thickness in the previous aspect where first dielectric portion 660a is any dielectric material (i.e., the substrate is coreless). Regardless of whether substrate 600 is a cored or coreless substrate, the first magnetic layer and the second magnetic layer are surrounded by first dielectric layer 660.

[0073] Figure 6B 6. The plurality of through holes 601 are formed through the first dielectric layer 660. The plurality of through holes 601 are formed by drilling or laser drilling. As can be seen from the X and Z planes, for simplicity, Figure 6B The plurality of through holes 601 is shown as including two through holes. However, the plurality of through holes 601 may correspond to Figure 3A A plurality of first vias 302a-d and a plurality of second vias 306a-c are shown. Furthermore, it should be understood that additional vias may be formed to achieve a desired inductance.

[0074] Figure 6C The seed layer 603 is shown optionally deposited on any portion of the first dielectric layer 660, which will subsequently be patterned with a metal. Depositing the seed layer 603 may be beneficial in cases where copper is used for patterning of a metal layer such as the first metal layer 630 (this will be relevant to Figure 6D ). In one aspect, the seed layer 603 is deposited so that it covers all exposed areas (i.e., the exterior areas and the plurality of vias) of the first dielectric layer 660. In this aspect, the seed layer 603 is deposited so that it covers at least the sides of the first dielectric portion 660c, the sides of the first dielectric portion 660b, and the sidewalls of the plurality of vias 601.

[0075] Figure 6D The patterning of the first metal layer 630 including the patterning of the plurality of first interconnects 602, the patterning of the second metal layer 632 including the patterning of the plurality of second interconnects 606, and the formation of the plurality of first vias 608 are shown. Figure 6D Not shown, but formation of a plurality of second vias (eg, 310a-c) may also be performed. Patterning occurs such that the plurality of first interconnects 602 and the plurality of second interconnects 602 are coupled together by the plurality of first vias 608 and the plurality of second vias (eg, 310a-c).

[0076] The plurality of first through holes 608 may be Figure 3A The plurality of first through holes 308a-c are the same. The plurality of second through holes may be the same as Figure 3A The plurality of second vias 310a-c shown are the same. The plurality of first interconnects 602 can be the same as the plurality of first interconnects 302a-d, and the plurality of second interconnects 606 can be the same as the plurality of interconnects 306a-c. Patterning of the plurality of first interconnects 302a-d, the plurality of second interconnects 606, and the plurality of first vias 608 and the plurality of second vias (e.g., 310a-c) can include providing a photoresist layer (not shown) on areas where metal patterning is not required, then depositing metal to enable formation of the desired pattern (e.g., interconnects, traces, vias), and finally stripping the photoresist layer.

[0077] Figure 6E The deposition of a third magnetic layer 624, an optional fourth magnetic layer 626, a second dielectric layer 662, and a third dielectric layer 666 is shown. The third magnetic layer 624 is surrounded by the second dielectric layer 662, and the optional fourth magnetic layer is surrounded by the third dielectric layer 666. The third magnetic layer 624 can be the same as the third magnetic layer 324, and the optional fourth magnetic layer 626 can be the same as the optional fourth magnetic layer 326. The second dielectric material 662 and the third dielectric material 666 can be the same as the third magnetic layer 324, respectively. Figure 5The second dielectric material 562 and the fourth dielectric material 566 are the same.

[0078] Figure 6E Inductor device 699 (corresponding to inductor device 300) and inductor 698 (and its inductor loop) are shown. Inductor 698 includes a plurality of first vias 608 (corresponding to 308a-c), a plurality of second vias (not shown in FIG6 , but see 310a-c), a plurality of first interconnects 602 and a plurality of second interconnects 606, a first magnetic layer 620, a second magnetic layer 622, a third magnetic layer 624, and an optional fourth magnetic layer 626. It is important to note that inductor device 699 can include a standalone component configured to be placed with another component that utilizes magnetic inductor 300. In another aspect, inductor device 699 (or 300) can be embedded in or integrated into a substrate (e.g., 600).

[0079] Figure 6F The inductor device 699 is shown after the third metal layer 634 and the fourth metal layer 636 have been patterned, after the vias 607 have been formed, and after the solder resist 610 has been deposited. In one aspect, Figure 6F The device may include a substrate 500 (see Figure 5 ) or the like. On the other hand, Figure 6F The device may include a package substrate (including a core or coreless), an interposer (e.g., silicon or glass), a ceramic package, or a printed circuit board. In one aspect, Figure 6F An inductor device 699 is shown embedded or integrated into the substrate 600 .

[0080] Exemplary Flowchart of a Method for Manufacturing an Inductor Device

[0081] Figure 7 An exemplary flow chart of a high-level method for manufacturing an inductor device is shown. It should be noted that for clarity and simplicity, Figure 7 The flowcharts shown do not necessarily include all steps for making an inductor device. Furthermore, in some cases, several steps may have been combined into one step to simplify the description of the sequence.

[0082] like Figure 7 As shown, the method includes depositing (at step 705) a first magnetic layer and a second magnetic layer within the first dielectric layer. Different implementations may deposit the first magnetic layer and the second magnetic layer differently. Figure 6A An example of depositing the first magnetic layer 620 and the second magnetic layer 622 inside the first dielectric layer 660 is shown.

[0083] The method shows (at step 710 ) forming a plurality of vias in a first dielectric. Figure 6B The formation of a through hole 601 is shown. Figure 6D A plurality of vias, such as a first plurality of vias 608, are shown formed in a first dielectric layer 660 (and forming a second plurality of vias 610, not shown, is discussed).

[0084] The method (at step 715) illustrates patterning a plurality of first interconnects and a plurality of second interconnects coupled together by a plurality of vias, wherein the plurality of vias, the plurality of first interconnects, and the plurality of second interconnects form a plurality of inductor loops. For example, Figure 6D The patterning of the plurality of first interconnects 602 and the plurality of second interconnects 606 is shown, and the first interconnects 602 and the second interconnects 606 are shown coupled together by a first plurality of vias 608 (and a second plurality of vias 610 , not shown), respectively.

[0085] The method (at step 720) shows depositing a third magnetic layer outside the plurality of inductor loops, wherein the first magnetic layer and the second magnetic layer are located between the plurality of first interconnects and the plurality of second interconnects. For example, Figure 6E Depositing the third magnetic layer 624 outside the plurality of inductor loops is shown. In one aspect, depositing the third magnetic layer 624 outside the plurality of inductor loops includes depositing the third magnetic layer 624 in a plane below another plane where the plurality of first interconnects 602a-d are located. Figure 6D A first magnetic layer 620 and a second magnetic layer 622 are shown between the first plurality of interconnects 602 and the second plurality of interconnects 606 .

[0086] An optional method (at step 725) shows depositing a fourth magnetic layer outside the plurality of inductor loops. For example, Figure 6E Depositing the fourth magnetic layer 626 outside the plurality of inductor loops is shown. In one aspect, depositing the fourth magnetic layer 626 outside the plurality of inductor loops includes depositing the fourth magnetic layer 626 in a plane above another (second) plane where the plurality of second interconnects 606a-c are located.

[0087] Exemplary system including a voltage regulator, and package substrate including an inductor device

[0088] Figure 8 An exemplary system including a voltage regulator including an inductor device is shown. For simplicity, Figure 8 The various components are shown coupled together by simple lines (ie, interconnects). However, it should be understood that a variety of interconnects may be used, including fine lines, traces, embedded traces, vias, or redistribution layers (not shown).

[0089] Specifically, Figure 8802, a packaging substrate 804, a PCB 806, a power management integrated circuit (PMIC) 818, and surface-mounted passive components 820 are shown. SoC 802 includes one or more voltage regulators 810 and one or more loads 812. Although SoC 802 is shown as a single device, in another aspect, voltage regulator 810 can be located in a separate die (i.e., separate from load 812). Package substrate 804 includes inductor device 814. Inductor device 814 can be inductor device 300, or can be inductor device 400 (including first inductor 450 and second inductor 455). Package substrate 804 can be substrate 500, but with additional components.

[0090] The PMIC 818 is coupled to a surface mounted passive device 820 , which is coupled to a PCB 806 , which is coupled to a package substrate 804 , which is coupled to a voltage regulator 810 , which is coupled to an inductor device 814 , which may be coupled to a capacitor and may also be coupled to a load 812 .

[0091] In one aspect, the voltage regulator 810 is configured to receive a first voltage, such as 1.8 volts, from a voltage source (not shown). The voltage regulator 810 can be configured to step down the received 1.8 volts to a second voltage, such as approximately 0.6-1.0 volts. The second voltage is provided to a load 812 via an inductor device 814. In another aspect, the voltage regulator 810 can be a buck regulator configured to step down the received first voltage to a second voltage.

[0092] Exemplary electronic devices

[0093] Figure 9 Various electronic devices are shown that can be integrated with any of the aforementioned substrates, integrated devices, semiconductor devices, integrated circuits, dies, interposers, packages, or inductor devices. For example, mobile phone device 902, laptop device 904, fixed location terminal device 906, and wearable device 908 can include an integrated device 900 as described herein. Integrated device 900 can be, for example, any of the substrates, integrated circuits, dies, integrated devices, integrated device packages, integrated circuit devices, device packages, integrated circuit (IC) packages, and package-on-package devices described herein. Figure 9The devices 902, 904, 906, and 908 shown are exemplary only. Other electronic devices may also have features of the integrated device 900, including but not limited to a group of devices (e.g., electronic devices) including mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), devices supporting global positioning systems (GPS), navigation devices, set-top boxes, music players, video players, entertainment devices, fixed location data units (such as meter reading devices), communication devices, smart phones, tablets, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in automobiles (e.g., self-driving cars), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0094] Figure 3A -E to Figure 8 One or more of the components, processes, features, and / or functions shown may be rearranged and / or combined into a single component, process, feature, or function, or embodied as multiple components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from the present disclosure. It should also be noted that the present disclosure Figure 3A -E to Figure 8 The present disclosure and its corresponding description are not limited to substrates. In some implementations, the present disclosure and its corresponding description can be used to manufacture, create, provide, and / or produce an integrated device. In some implementations, the device can include a die, an integrated device, a die package, an integrated circuit (IC), a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, and / or an interposer.

[0095] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the discussed feature, advantage, or mode of operation. The term "coupled" is used herein to refer to a direct or indirect coupling between two objects. For example, if object A physically contacts object B, and object B contacts object C, then objects A and C may still be considered coupled to each other even though they are not in direct physical contact with each other. As used herein, the term "traverse" means through and includes all the way through an object or partially through an object.

[0096] In addition, it should be noted that the various disclosures included herein can be described as processes depicted as flow charts, flow diagrams, structure diagrams, or block diagrams. Although flow charts can describe operations as sequential processes, many operations can be performed in parallel or simultaneously. In addition, the order of operations can be rearranged. After the operations are completed, the process will terminate.

[0097] The various aspects of the present disclosure described herein can be implemented in different systems without departing from the present disclosure. It should be noted that the foregoing aspects of the present disclosure are merely examples and should not be construed as limiting the present disclosure. The description of the various aspects of the present disclosure is intended to be illustrative, not limiting, of the scope of the claims. Thus, the present teachings can be readily applied to other types of devices, and many alternatives, modifications, and variations will be readily apparent to those skilled in the art.

Claims

1. An inductor device comprising: a first metal layer comprising a plurality of first interconnects; a second metal layer comprising a plurality of second interconnects; a first dielectric layer between the first metal layer and the second metal layer; as well as A first inductor, the first inductor comprising: a plurality of vias configured to couple the plurality of first interconnects to the plurality of second interconnects; a plurality of inductor loops formed by the plurality of through-vias, the plurality of first interconnects, and the plurality of second interconnects; a first magnetic layer, a second magnetic layer, and a third magnetic layer stacked one on top of another, wherein the first magnetic layer and the second magnetic layer are spaced apart from each other and completely located within the first dielectric layer between the plurality of first interconnects and the plurality of second interconnects; and wherein the third magnetic layer is located outside the plurality of inductor loops, and wherein the inductor device is embedded in a substrate, The inductor device further includes: a second inductor having the same configuration as the first inductor, wherein the plurality of through-holes, the plurality of first interconnects, and the plurality of second interconnects of the plurality of inductor loops included in the first inductor are formed to be interwoven with another plurality of through-holes, another plurality of first interconnects, and another plurality of second interconnects of another plurality of inductor loops included in the second inductor, respectively.

2. The inductor device according to claim 1, wherein The third magnetic layer is parallel to the plurality of first interconnects and is at least partially aligned with the first interconnects.

3. The inductor device according to claim 2, wherein The third magnetic layer includes a single sheet.

4. The inductor device according to claim 2, wherein The third magnetic layer includes a plurality of magnetic layer portions.

5. The inductor device of claim 1 , further comprising: The length of the third magnetic layer is greater than or equal to the length of the inductor.

6. The inductor device of claim 1 , further comprising: The length of the third magnetic layer is less than or equal to the length of the inductor.

7. The inductor device of claim 1 , further comprising: The width of the third magnetic layer is greater than or equal to the width of the inductor.

8. The inductor device of claim 1 , further comprising: The width of the third magnetic layer is smaller than or equal to the width of the inductor.

9. The inductor device of claim 1 , further comprising: a second dielectric layer, wherein the third magnetic layer is surrounded by the second dielectric layer.

10. The inductor device according to claim 1, wherein The first magnetic layer and the second magnetic layer are at least partially within the plurality of inductor loops, and wherein the first magnetic layer and the second magnetic layer are surrounded by the first dielectric layer.

11. The inductor device according to claim 1, wherein The first magnetic layer and the second magnetic layer are between the plurality of through holes.

12. The inductor device of claim 1 , further comprising: The fourth magnetic layer is outside the plurality of inductor loops.

13. The inductor device according to claim 12, wherein The fourth magnetic layer is parallel to and at least partially aligned with the plurality of second interconnects.

14. The inductor device according to claim 12, wherein The third magnetic layer and the fourth magnetic layer are perpendicular to the plurality of through holes.

15. The inductor device according to claim 12, wherein The fourth magnetic layer includes a single sheet parallel to the plurality of second interconnects.

16. The inductor device of claim 12, further comprising: The fourth magnetic layer has a width greater than or equal to a width of the inductor.

17. The inductor device of claim 12, further comprising: The fourth magnetic layer has a width smaller than or equal to a width of the inductor.

18. The inductor device of claim 12, further comprising: The length of the fourth magnetic layer is greater than or equal to the length of the inductor.

19. The inductor device of claim 12, further comprising: The length of the fourth magnetic layer is less than or equal to the length of the inductor.

20. The inductor device of claim 12, wherein The fourth magnetic layer includes a plurality of magnetic layer portions.

21. The inductor device of claim 12, further comprising: A third dielectric layer, wherein the fourth magnetic layer is surrounded by the third dielectric layer.

22. The inductor device of claim 1, further comprising: A third metal layer is below the first metal layer, wherein the third magnetic layer is between the third metal layer and the first metal layer.

23. The inductor device of claim 22, further comprising: A fourth metal layer is above the second metal layer, wherein a fourth magnetic layer is between the fourth metal layer and the second metal layer, and wherein the fourth magnetic layer is parallel to the plurality of second interconnects.

24. The inductor device of claim 23, wherein The third magnetic layer and the fourth magnetic layer are configured to confine magnetic flux of the third metal layer and the fourth metal layer.

25. The inductor device of claim 1, wherein The inductor device further includes a device selected from the group consisting of a package substrate, an interposer, a ceramic package, and a printed circuit board.

26. The inductor device of claim 1, wherein The inductor is configured to be coupled to a voltage regulator.

27. The inductor device of claim 1, wherein The thickness of the third magnetic layer is about 0.1 to 6 microns.

28. The inductor device according to claim 1, in, The third magnetic layer is outside the other plurality of inductor loops of the second inductor; and A fourth magnetic layer, wherein the fourth magnetic layer is outside the plurality of inductor loops of the first inductor and outside the additional plurality of inductor loops of the second inductor.

29. The inductor device of claim 1, wherein The inductor device is incorporated into a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal or server, a tablet computer, a wearable computing device and a laptop computer.

30. A method of manufacturing an inductor device embedded in a substrate, comprising: depositing a first magnetic layer and a second magnetic layer of the substrate inside the first dielectric layer; as well as forming a plurality of through holes in the first dielectric layer; patterning a plurality of first interconnects and a plurality of second interconnects coupled together through the plurality of vias, wherein the plurality of vias, the plurality of first interconnects, and the plurality of second interconnects form a plurality of inductor loops of a first inductor; and depositing a third magnetic layer outside the plurality of inductor loops, wherein the first magnetic layer and the second magnetic layer are located between the plurality of first interconnects and the plurality of second interconnects and are separated from each other by the first dielectric layer, wherein the first magnetic layer, the second magnetic layer and the third magnetic layer are stacked on each other, The third magnetic layer is located outside the plurality of inductor loops. wherein the plurality of inductor loops of the second inductor are formed in the same manner, wherein the plurality of through-holes, the plurality of first interconnections, and the plurality of second interconnections of the plurality of inductor loops included in the first inductor are formed to be interwoven with another plurality of through-holes, another plurality of first interconnections, and another plurality of second interconnections of another plurality of inductor loops included in the second inductor, respectively.

31. The method according to claim 30, wherein The third magnetic layer is parallel to and at least partially aligned with the plurality of first interconnects.

32. The method according to claim 30, wherein Depositing the third magnetic layer includes depositing a magnetic layer sheet or depositing a plurality of magnetic portions.

33. The method of claim 30, further comprising: A fourth magnetic layer is deposited outside the plurality of inductor loops.

34. The method according to claim 33, wherein Depositing the fourth magnetic layer further includes depositing the fourth magnetic layer parallel to and at least partially aligned with the plurality of second interconnects.

35. The method of claim 33, wherein: Depositing the fourth magnetic layer includes depositing a single magnetic layer piece or depositing a plurality of magnetic portions.

36. The method of claim 33, further comprising: depositing a second dielectric layer such that the second dielectric layer at least partially surrounds the plurality of first interconnects and the plurality of second interconnects; forming a plurality of holes through the second dielectric layer; Patterning another metal layer, wherein patterning the another metal layer comprises: filling the plurality of holes, forming a plurality of third interconnects parallel to and at least partially aligned with the third magnetic layer, and A plurality of fourth interconnects are formed parallel to and at least partially aligned with the fourth magnetic layer; wherein the plurality of third interconnects and the plurality of fourth interconnects are configured to conduct a ground signal or a power signal or a signal.

37. The method of claim 30, wherein: Depositing the first magnetic layer and the second magnetic layer includes: depositing a first portion of the first dielectric layer, the first portion comprising a first side and a second side, depositing a second portion of the first dielectric layer to at least partially cover the first side of the first dielectric layer and cover the first magnetic layer, A third portion of the first dielectric layer is deposited to at least partially cover the second side of the first dielectric layer and cover the second magnetic layer, wherein depositing the second and third portions occurs after depositing the first and second magnetic layers within the first dielectric layer.

38. The method of claim 30, wherein: Depositing the first magnetic layer and the second magnetic layer includes depositing the first magnetic layer and the second magnetic layer inside the plurality of inductor loops.

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