Integrated passive device and preparation method thereof, chip and electronic equipment

Abstract

The invention provides an integrated passive device, a preparation method thereof, a chip and electronic equipment, relates to the technical field of semiconductors, and can avoid the situation that the number of layers of a three-dimensional capacitor is limited due to the fact that a first conductive layer and a second conductive layer are damaged. The integrated passive device comprises a substrate, a three-dimensional capacitor, a spacing layer, and a first conductive layer and a second conductive layer which are arranged at an interval. The three-dimensional capacitor comprises a plurality of electrode layers and a plurality of dielectric layers which are alternately stacked on the surface of a substrate, and a pyramid structure with multiple steps is formed. In the direction from the substrate to the three-dimensional capacitor, the multiple electrode layers comprise first electrodes and second electrodes which are isolated from each other and alternate. The multi-stage step is covered by a spacer layer. The surface of the first side step of the pyramid structure is covered with a first conductive layer, and the first conductive layer is electrically connected with the first electrode through a first through hole in the spacing layer. The surface of a second side step of the pyramid structure is covered with a second conductive layer, and the second conductive layer is electrically connected with the second electrode through a second through hole in the spacing layer.

Description

Integrated passive device and preparation method thereof, chip, and electronic device Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to an integrated passive device and a preparation method thereof, a chip, and an electronic device. Background Art

[0002] With the continuous evolution of communication technology, smartphones need to support more and more frequency bands. For example, fifth-generation mobile communication technology (5G) mobile phones need to include new 5G frequency bands and be backward compatible with 4G frequency bands, which has led to a significant increase in the number of passive components assembled on circuit boards. As a result, the resulting high-frequency transmission loss and heat dissipation problems have become increasingly apparent. Integrated passive devices (IPDs), due to their excellent high capacitance density and miniaturization, play an important role in higher-integration packaging compared to traditional passive devices set on circuit boards through welding technology. They are one of the key components for smartphones to meet their high-frequency communication needs.

[0003] Taking a three-dimensional capacitor as an example, the existing technology forms a three-dimensional capacitor by sequentially forming an etch stop layer, an oxide layer, and a conductive layer. In order to allow the conductive layer to contact the electrode layer in the three-dimensional capacitor, the etch stop layer and the oxide layer include through holes. However, since the depths of the through holes vary and the difference in the etching selectivity between the etch stop layer and the oxide layer has an upper limit, the number of layers of the three-dimensional capacitor will be limited.

[0004] Summary of the Invention

[0005] The present application provides an integrated passive device and a preparation method thereof, a chip, and an electronic device, which can avoid limiting the number of layers of a three-dimensional capacitor due to damage to the first conductive layer and the second conductive layer.

[0006] In a first aspect, the present application provides an integrated passive device, which includes a substrate, a three-dimensional capacitor, a spacer layer, and a first conductive layer and a second conductive layer spaced apart. The three-dimensional capacitor includes multiple electrode layers and multiple dielectric layers alternately stacked on the surface of the substrate to form a pyramid structure with multiple steps; along the direction of the substrate pointing to the three-dimensional capacitor, the multiple electrode layers include first electrodes and second electrodes that are isolated from each other and alternate; the multiple steps are covered by a spacer layer composed of a dielectric material. The surface of the first step of the pyramid structure is covered with a first conductive layer, and a first through hole connected to the first electrode is provided on the spacer layer, and the first conductive layer is electrically connected to the first electrode through the first through hole. The surface of the second step of the pyramid structure is covered with a second conductive layer, and a second through hole connected to the second electrode is also provided on the spacer layer, and the second conductive layer is electrically connected to the second electrode through the second through hole.

[0007] In the present application, a three-dimensional capacitor is fabricated into a pyramid structure comprising multiple steps, so that the steps farther from the substrate can expose the surface of the steps closer to the substrate. On the first side of the pyramid structure, a first through-hole connected to the first electrode is provided on the spacer layer, so that the first conductive layer covering the first side of the pyramid structure is electrically connected to the first electrode through the first through-hole, and the second electrode is electrically isolated from the first conductive layer by the spacer layer. On the second side of the pyramid structure, a second through-hole connected to the second electrode is provided on the spacer layer, so that the second conductive layer covering the second side of the pyramid structure is electrically connected to the second electrode through the second through-hole, and the second electrode is electrically isolated from the second conductive layer by the spacer layer. There is no need to form a thicker oxide layer on the side of the three-dimensional capacitor facing away from the substrate and to flatten the oxide layer as in the solution provided in the related art, thus saving manufacturing costs. There is also no need to form multiple through-holes of varying depths in the oxide layer, and thus there is no problem of the electrode layer being damaged when etching multiple through-holes of varying depths, which in turn limits the number of layers of the three-dimensional capacitor.

[0008] In some possible implementations, a step on a first side of the plurality of steps is disposed opposite a step on a second side of the plurality of steps. Thus, a step on the first side includes a portion of the first electrode, and a step on the second side that faces the step also includes a portion of the first electrode. A step on the first side includes a portion of the second electrode, and a step on the second side that faces the step also includes a portion of the second electrode.

[0009] In some possible implementations, the multiple steps include a first step, a surface of the dielectric layer facing away from the substrate includes a step surface of the first step, and a surface of the electrode layer facing the substrate includes a surface of the first step facing the substrate. At the first step, a third through-hole is defined in the dielectric layer, the third through-hole being disposed opposite the first through-hole and the second through-hole; the first conductive layer is electrically connected to the first electrode via the third through-hole and the first through-hole, and the second conductive layer is electrically connected to the second electrode via the third through-hole and the second through-hole.

[0010] The sidewall of the first electrode on the second side is covered by a spacer layer, and the upper surface of the first electrode on the second side is covered by a dielectric layer that forms the same first step as the first electrode, thereby electrically isolating the second conductive layer from the first electrode. The sidewall of the second electrode on the first side is covered by a spacer layer, and the upper surface of the second electrode on the first side is covered by a dielectric layer that forms the same first step as the first electrode, thereby electrically isolating the first conductive layer from the second electrode. The upper surface of the first electrode is the surface of the first electrode facing away from the substrate, and the upper surface of the second electrode is the surface of the second electrode facing away from the substrate.

[0011] Because the three-dimensional capacitor has a multi-step pyramid structure, the depth of each first and second through-hole, along the direction from the substrate toward the spacer layer, is equal to the thickness of the same spacer layer, and the depth of each third through-hole is equal to the thickness of one dielectric layer. This ensures that the depths of the multiple first and second through-holes are the same, and the depths of the multiple third through-holes are the same or similar. This prevents the problem of varying depths of through-holes formed during the same etching process, which could damage the electrode layer and limit the number of layers in the three-dimensional capacitor.

[0012] Furthermore, there is no need to provide a thick oxide layer between the first conductive layer, the second conductive layer and the spacer layer, and the oxide layer needs to be planarized, which can save preparation costs.

[0013] In some possible implementations, the multiple steps further include a second step, and the first step is disposed between the substrate and the second step. At the second step, the surface of an electrode layer facing the substrate comprises the surface of the second step facing the substrate, and the surface of the electrode layer facing away from the substrate comprises the step surface of the second step. That is, the second step consists of a portion of the electrode layer and does not include the dielectric layer. Therefore, at the second step, there is no need to open a through hole in the dielectric layer.

[0014] If the second step is composed of a portion of the first electrode, the first conductive layer is directly electrically connected to the first electrode through the first through-hole, and the sidewall of the first electrode on the second side and the step surface are covered by the spacer layer, thereby achieving electrical isolation between the second conductive layer and the first electrode.

[0015] If the second step is composed of a portion of the second electrode, the second conductive layer is directly electrically connected to the second electrode through the second through hole, and the sidewall of the second electrode on the first side and the step surface are covered by the spacer layer, thereby achieving electrical isolation between the first conductive layer and the second electrode.

[0016] In some possible implementations, a surface of the electrode layer facing away from the substrate includes a stepped surface, and a surface of the dielectric layer facing the substrate includes a stepped surface facing the substrate. The first conductive layer is electrically connected to the first electrode via a first through-hole, and the second conductive layer is electrically connected to the second electrode via a second through-hole.

[0017] The sidewall and upper surface of the first electrode on the second side are covered by the spacer layer, thereby electrically isolating the second conductive layer from the first electrode. The sidewall and upper surface of the second electrode on the first side are covered by the spacer layer, thereby electrically isolating the first conductive layer from the second electrode.

[0018] Because the three-dimensional capacitor has a multi-step pyramidal structure, the depth of each first and second through-hole, along the direction from the substrate toward the spacer layer, is the same thickness as the spacer layer. This ensures that the depths of multiple first and second through-holes are uniform, eliminating the problem of varying depths of through-holes formed during the same etching process, which could damage the electrode layer and limit the number of layers in the three-dimensional capacitor. Furthermore, there's no need to planarize the oxide layer between the first and second conductive layers and the spacer layer, saving manufacturing costs.

[0019] In some possible implementations, the integrated passive device further includes a passivation layer, a first conductive lead, and a second conductive lead, wherein the passivation layer covers the first conductive layer, the second conductive layer, and the three-dimensional capacitor. The first conductive lead can be electrically connected to the first conductive layer via a fourth through-hole, and the second conductive lead can be electrically connected to the second conductive layer via a fifth through-hole. In this way, the first electrode transmits a signal via the first conductive layer and the first conductive lead, and the second electrode transmits a signal via the second conductive layer and the second conductive lead.

[0020] Furthermore, the first and second conductive layers of the embodiments of the present application correspond to the oxide layers of the related art, and both are disposed on the side of the stepped three-dimensional capacitor facing away from the substrate. By setting the first and second conductive layers to a greater thickness, the sides of the first and second conductive layers facing away from the substrate are nearly flat, thereby making the thickness of the passivation layer disposed on the sides of the first and second conductive layers facing away from the substrate much less than the thickness of the oxide layer of the related art. Therefore, even though the passivation layer also includes fourth and fifth through holes, the aspect ratio of the fourth and fifth through holes is much greater than the aspect ratio of the through holes in the oxide layer. For example, the aspect ratio of the through holes in the oxide layer of the related art is approximately 1:3, and the aperture size of the through holes is approximately several hundred nanometers; whereas the aspect ratio of the fourth and fifth through holes of the present application is approximately 1:2, and the aperture size of the fourth and fifth through holes is approximately several tens of nanometers.

[0021] In the related art, the size of the through-holes in the oxide layer is relatively small in the direction of the interface between the electrode layer and the dielectric layer (for example, the size of the through-holes is 0.18 μm), which makes the contact area between the conductive material filling the through-holes and the electrode layer in contact with them relatively small, resulting in a large contact resistance between the two, affecting the electrical properties such as ESL and ESR of the integrated passive device.

[0022] Furthermore, the width-to-depth ratio of each via in the oxide layer is relatively large, so the vias cannot be etched using the same machine as the conductive layer. In other words, etching the vias in the oxide layer requires a dedicated machine.

[0023] Compared to related technologies, the fourth and fifth vias of this application are larger in size, reducing the contact area and contact resistance between the first conductive lead and the first conductive layer, and the contact area and contact resistance between the second conductive lead and the second conductive layer, thereby improving the electrical performance of the integrated passive device, such as ESL and ESR. Furthermore, due to the increased aspect ratio of the fourth and fifth vias, the process for etching the fourth and fifth vias in the passivation layer can share the same machine as the process for forming the first and second conductive layers, saving production costs.

[0024] In some possible implementations, the integrated passive device further includes an etch stop layer disposed between a step distal from the substrate and the spacer layer, with the etch stop layer exposed in the gap between the first conductive layer and the second conductive layer. The etch stop layer protects the electrode layer of the three-dimensional capacitor during subsequent etching to form patterns in the first and second conductive layers.

[0025] Here, in order not to affect the electrical connection between the first conductive layer and the electrode layer farthest from the substrate, the etch stop layer may also include a through hole.

[0026] In a second aspect, the present application provides an integrated passive device, which includes: a substrate, a three-dimensional capacitor, a first spacer layer, a first connected conductive layer, a second spacer layer, a first conductive layer, a conductive bridge, an insulating layer, and a second conductive layer. The three-dimensional capacitor includes multiple electrode layers and multiple dielectric layers stacked alternately on the surface of the substrate to form a pyramid structure with multiple steps; along the direction of the substrate pointing to the three-dimensional capacitor, the multiple electrode layers include first electrodes and second electrodes that are isolated from each other and alternate with each other. The pyramid structure is sequentially covered with a first spacer layer, a first connected conductive layer, a second spacer layer, and a first conductive layer; the first connected conductive layer is located on the second side of the pyramid structure. On the first side of the pyramid structure, a first through hole connected to the first electrode is opened on the second spacer layer, and the first conductive layer is electrically connected to the first electrode through the first through hole. On the second side of the pyramid structure, a first spacer layer is used to electrically isolate the first electrode from the first connected conductive layer, and the first connected conductive layer is electrically connected to the second electrode; a conductive bridge and an insulating layer are provided between the substrate and the three-dimensional capacitor, and the insulating layer is used to electrically isolate the first conductive layer from the conductive bridge; the conductive bridge is electrically connected to the first connected conductive layer through a second through hole opened in the insulating layer, and extends to the outside of the pyramid structure and is electrically connected to the second conductive layer outside the pyramid structure.

[0027] In this application, a three-dimensional capacitor is fabricated into a pyramid structure with multiple steps. This allows steps farther from the substrate to expose the surface of steps closer to the substrate. On the first side of the pyramid structure, a second spacer layer is provided with a first through-hole connected to the first electrode, allowing the first conductive layer overlying the pyramid structure to be electrically connected to the first electrode via the first through-hole. By placing the second spacer layer between the pyramid structure and the first conductive layer, the second spacer layer can be used to electrically isolate the second electrode from the first conductive layer. On the second side of the pyramid structure, a first interconnected conductive layer is placed over the pyramid structure, allowing the first interconnected conductive layer to be electrically connected to the second conductive layer on the second side of the pyramid structure. The first interconnected conductive layer is then electrically connected to the second conductive layer disposed outside the pyramid structure via a conductive bridge. Furthermore, on the second side of the pyramid structure, a first spacer layer is placed between the pyramid structure and the first interconnected conductive layer, allowing the first spacer layer to electrically isolate the first interconnected conductive layer from the first electrode. By placing the second spacer layer between the first conductive layer and the first interconnected conductive layer, the second spacer layer can be used to electrically isolate the first conductive layer from the first interconnected conductive layer. There is no need to form a thick oxide layer on the side of the three-dimensional capacitor facing away from the substrate and then flatten the oxide layer, as in the related art, thus saving manufacturing costs. There is also no need to form multiple through holes of varying depths in the oxide layer, and thus there is no problem of damaging the electrode layer when etching multiple through holes of varying depths, which would limit the number of layers in the three-dimensional capacitor.

[0028] In some possible implementations, a step on a first side of the plurality of steps is disposed opposite a step on a second side of the plurality of steps. Thus, a step on the first side includes a portion of the first electrode, and a step on the second side that faces the step also includes a portion of the first electrode. A step on the first side includes a portion of the second electrode, and a step on the second side that faces the step also includes a portion of the second electrode.

[0029] In some possible implementations, the multi-step step includes a first step. At the first step, the surface of the dielectric layer facing away from the substrate comprises the surface of the first step facing away from the substrate, and the surface of the electrode layer facing the substrate comprises the surface of the first step facing the substrate. On a first side of the first step, the dielectric layer includes a third through-hole connected to the first electrode, and the first conductive layer is electrically connected to the first electrode via the third through-hole and the first through-hole. By disposing a second spacer layer between the pyramid structure and the first conductive layer, the second electrode can be electrically isolated from the first conductive layer. On a second side of the first step, the first spacer layer is located lateral to the first step, the dielectric layer includes a fourth through-hole connected to the second electrode, and the first conductive layer is electrically connected to the second electrode via the fourth through-hole. By disposing the first spacer layer between the pyramid structure and the first conductive layer, the first conductive layer can be electrically isolated from the first electrode. By disposing the second spacer layer between the first conductive layer and the first conductive layer, the first conductive layer can be electrically isolated from the first conductive layer.

[0030] According to this structure, on the first side of the pyramid structure, the first electrode is electrically connected to the first conductive layer via a first through-hole in the second spacer layer and a third through-hole in the dielectric layer. On the second side of the pyramid structure, the second electrode is electrically connected to the first connected conductive layer via a fourth through-hole in the dielectric layer. The first connected conductive layer is then electrically connected to the conductive bridge via a second through-hole in the insulating layer. The conductive bridge is then electrically connected to the second conductive layer.

[0031] Because the three-dimensional capacitor has a pyramid structure with multiple steps, the depth of each first through-hole along the direction of the substrate pointing to the first spacer layer is the thickness of the same second spacer layer, and the depth of each third through-hole and each fourth through-hole is the thickness of a dielectric layer. Therefore, the depths of the multiple first through-holes are the same, and the depths of the multiple third through-holes and the multiple fourth through-holes are the same or have little difference. This prevents the electrode layer from being damaged due to the different depths of the through-holes formed by the same etching process, which in turn leads to the problem of limiting the number of layers of the three-dimensional capacitor. In addition, there is no need to set a thick oxide layer between the first conductive layer, the second conductive layer, and the second spacer layer, and to flatten the oxide layer, which can save manufacturing costs.

[0032] In some possible implementations, the integrated passive device further includes a second interconnected conductive layer, the second interconnected conductive layer being co-layered with and spaced apart from the first interconnected conductive layer. A first spacer layer is located on a side of the first step on a first side of the first step, electrically isolating the second electrode from the second interconnected conductive layer. The second interconnected conductive layer is electrically connected to the first electrode via a third through-hole in the dielectric layer. There is at least one first through-hole, and the first conductive layer is electrically connected to the second interconnected conductive layer via the first through-hole in the second spacer layer.

[0033] According to this structure, on the first side of the pyramid structure, the multi-layer first electrode is electrically connected to the second connected conductive layer via a third through-hole in the multi-layer dielectric layer. The second connected conductive layer is further electrically connected to the first conductive layer via at least one first through-hole in the second spacer layer. On the second side of the pyramid structure, the second electrode is electrically connected to the first connected conductive layer via a fourth through-hole in the dielectric layer. The first connected conductive layer is further electrically connected to the conductive bridge via a second through-hole in the insulating layer. The conductive bridge is electrically connected to the second conductive layer.

[0034] In some possible implementations, the multiple steps further include a second step, with the first step disposed between the substrate and the second step. At the second step, the surface of the electrode layer facing the substrate includes the surface of the second step facing the substrate, and the surface of the electrode layer facing away from the substrate includes the step surface of the second step. That is, the second step consists of a portion of the electrode layer and does not include the dielectric layer. Therefore, at the second step, there is no need to provide a through hole in the dielectric layer. On the first side of the second step, the first conductive layer is electrically connected to the electrode layer via the first through hole; alternatively, on the second side of the second step, the first connected conductive layer is electrically connected to the electrode layer.

[0035] If the electrode layer of the second step is the first electrode, then on the first side of the second step, the first conductive layer is electrically connected to the first electrode via the first through-hole in the second spacer layer. Alternatively, the first conductive layer is electrically connected to the second connected conductive layer via the first through-hole in the second spacer layer, and the second connected conductive layer is directly electrically connected to the first electrode. Of course, the first spacer layer can also extend from the sidewall of the second step to the step surface of the second step. In this way, the second connected conductive layer can be electrically connected to the first electrode via the through-hole in the first spacer layer.

[0036] If the electrode layer of the second step is a second electrode, then the second electrode is directly electrically connected to the first connected conductive layer on the second side of the second step. Alternatively, the first spacer layer may extend from the sidewall of the second step to the surface of the second step. In this way, the first connected conductive layer may be electrically connected to the second electrode via a through hole in the first spacer layer. The first connected conductive layer is then electrically connected to the conductive bridge via a second through hole in the insulating layer, and the conductive bridge is electrically connected to the second conductive layer.

[0037] In some possible implementations, in any one step, a surface of the electrode layer facing away from the substrate comprises a surface of the step facing away from the substrate, and a surface of the electrode layer facing the substrate comprises a surface of the step facing the substrate. On a second side of the multi-step step, a first spacer layer covers the multi-step step, the first spacer layer includes a fifth through hole connected to the second electrode, and the first conductive layer is electrically connected to the second electrode via the fifth through hole.

[0038] According to this structure, on the first side of the pyramid structure, the first electrode is electrically connected to the first conductive layer via a first through-hole in the second spacer layer. On the second side of the pyramid structure, the second electrode is electrically connected to the first connected conductive layer via a fifth through-hole in the first spacer layer. The first connected conductive layer is then electrically connected to the conductive bridge via a second through-hole in the insulating layer. The conductive bridge is then electrically connected to the second conductive layer.

[0039] Because the three-dimensional capacitor has a multi-step pyramid structure, the depth of each first through-hole along the direction from the substrate to the first spacer layer is the thickness of the same second spacer layer, and the depth of each fifth through-hole is the thickness of the same first spacer layer. Therefore, the depths of the multiple first through-holes are the same, and the depths of the multiple fifth through-holes are the same. This prevents the problem of the electrode layer being damaged due to the different depths of the through-holes formed by the same etching process, which in turn limits the number of layers in the three-dimensional capacitor. Furthermore, there is no need to provide a thick oxide layer between the first conductive layer, the second conductive layer, and the second spacer layer, and to flatten the oxide layer, which can save manufacturing costs.

[0040] In some possible implementations, the integrated passive device further includes a second interconnected conductive layer, the second interconnected conductive layer being co-layered with and spaced apart from the first interconnected conductive layer. A first spacer layer covers the first step on a first side of the first step, electrically isolating the second electrode from the second interconnected conductive layer. The first spacer layer includes a fifth through-hole connected to the first electrode, and the second interconnected conductive layer is electrically connected to the first electrode via the fifth through-hole. There is at least one first through-hole, and the first conductive layer is electrically connected to the second interconnected conductive layer via the first through-hole.

[0041] According to this structure, on the first side of the pyramid structure, the multi-layer first electrodes are electrically connected to the second connected conductive layer via the fifth through-hole in the first spacer layer, and the second connected conductive layer is further electrically connected to the first conductive layer via at least one first through-hole in the second spacer layer. On the second side of the pyramid structure, the second electrodes are electrically connected to the first connected conductive layer via the fifth through-hole in the first spacer layer, and the first connected conductive layer is further electrically connected to the conductive bridge via the second through-hole in the insulating layer, and the conductive bridge is electrically connected to the second conductive layer.

[0042] In some possible implementations, the integrated passive device further includes a third conductive layer disposed between the second spacer layer and the first conductive layer, wherein the material of the third conductive layer includes TiN; the third conductive layer covers the three-dimensional capacitor, and the third conductive layer is prepared by an atomic layer deposition process.

[0043] Since the dielectric layer can be a single layer or a stacked layer structure including materials such as Si3N4, HfO2, ZrO2, Al2O3, etc., where HfO2 and ZrO2 are high dielectric constant materials, the materials of the first spacer layer and the second spacer layer can also include high dielectric constant materials.

[0044] After the dielectric and spacer layers are formed, the Hf or Zr elements in the high-k dielectric material diffuse within the tool, contaminating the tool. Subsequent use of the tool for fabricating integrated passive devices will contaminate other layers already formed or to be formed, impacting the performance of the integrated passive devices. To address this issue, the related technology requires the use of dedicated tools to form layers containing high-k dielectric materials, increasing both equipment investment and device fabrication costs.

[0045] In the present application, although the materials of the dielectric layer, the first spacer layer, and the second spacer layer also include high dielectric constant materials, since the third conductive layer completely covers the dielectric layer, the first spacer layer, and the second spacer layer, the third conductive layer can be used to prevent the Hf element or the Zr element from diffusing into other film layers that have been formed or are to be formed, thereby eliminating the need to use a dedicated machine to form a film layer containing a high dielectric constant material, greatly reducing equipment investment costs and device preparation costs.

[0046] On this basis, since the third conductive layer completely covers the three-dimensional capacitor, when forming the patterns of the first conductive layer and the second conductive layer, the third conductive layer can be used to protect the electrode layer of the three-dimensional capacitor. Therefore, after the three-dimensional capacitor is formed and before the third conductive layer is formed, there is no need to form an etching barrier layer on the side of the third conductive layer facing away from the substrate.

[0047] In some possible implementations, the integrated passive device further includes a passivation layer, a first conductive lead, and a second conductive lead, wherein the first conductive lead and the second conductive lead are disposed on a side of the passivation layer facing away from the substrate. The passivation layer may include a sixth through-hole and a seventh through-hole, wherein the first conductive lead may be electrically connected to the first conductive layer via the sixth through-hole, and the second conductive lead may be electrically connected to the second conductive layer via the seventh through-hole. In this manner, the first electrode transmits a signal via the first conductive layer and the first conductive lead, and the second electrode transmits a signal via the second conductive layer and the second conductive lead.

[0048] Furthermore, the first and second conductive layers of the embodiments of the present application correspond to the oxide layers of the related art, and both are disposed on the side of the stepped three-dimensional capacitor facing away from the substrate. By setting the first and second conductive layers to a greater thickness, the sides of the first and second conductive layers facing away from the substrate are nearly flat, thereby making the thickness of the passivation layer disposed on the sides of the first and second conductive layers facing away from the substrate much less than the thickness of the oxide layer of the related art. Therefore, even though the passivation layer also includes the sixth and seventh through holes, the aspect ratio of the sixth and seventh through holes is much greater than the aspect ratio of the through holes in the oxide layer. For example, the aspect ratio of the through holes in the oxide layer of the related art is approximately 1:3, and the aperture size of the through holes is approximately several hundred nanometers; whereas the aspect ratio of the sixth and seventh through holes of the present application is approximately 1:2, and the aperture size of the sixth and seventh through holes is approximately several tens of nanometers.

[0049] In the related art, the size of the through-holes in the oxide layer is relatively small in the direction of the interface between the electrode layer and the dielectric layer (for example, the size of the through-holes is 0.18 μm), which makes the contact area between the conductive material filling the through-holes and the electrode layer in contact with them relatively small, resulting in a large contact resistance between the two, affecting the electrical properties such as ESL and ESR of the integrated passive device.

[0050] Furthermore, the width-to-depth ratio of each via in the oxide layer is relatively large, so the vias cannot be etched on the same machine as the conductive layer. In other words, etching the vias in the oxide layer requires a dedicated machine.

[0051] Compared to related art, the sixth and seventh through-holes of the present application are larger in size, which can reduce the contact area and contact resistance between the first conductive lead and the first conductive layer, and reduce the contact area and contact resistance between the second conductive lead and the second conductive layer, thereby improving the electrical performance of the integrated passive device, such as ESL and ESR. Furthermore, due to the increased aspect ratio of the sixth and seventh through-holes, the process for etching the sixth and seventh through-holes in the passivation layer can share the same machine as the process for forming the first and second conductive layers, saving production costs.

[0052] In a third aspect, the present application provides an integrated passive device, which includes a substrate, a three-dimensional capacitor, a spacer layer composed of a dielectric material, and a first conductive layer and a second conductive layer arranged at intervals. The three-dimensional capacitor includes multiple electrode layers and multiple dielectric layers stacked alternately on the surface of the substrate to form a pyramid structure with multiple steps; along the direction of the substrate pointing to the three-dimensional capacitor, the multiple electrode layers include first electrodes and second electrodes that are isolated from each other and alternate. On the first side of the pyramid structure, the spacer layer is used to electrically isolate the second electrode from the first conductive layer; the step surface of the multiple steps is the surface of the first electrode facing away from the substrate, and the first conductive layer is electrically connected to the first electrode at the step surface. On the second side of the pyramid structure, the spacer layer is used to electrically isolate the first electrode from the second conductive layer; the step surface of the multiple steps is the surface of the second electrode facing away from the substrate, and the second conductive layer is electrically connected to the second electrode at the step surface.

[0053] In the present application, a three-dimensional capacitor is fabricated into a pyramid structure comprising multiple steps. This allows steps farther from the substrate to expose step surfaces closer to the substrate. On the first side of the pyramid structure, by making the step surfaces of the multiple steps the surface of the first electrode facing away from the substrate, the first conductive layer covering the step surface on the first side of the pyramid structure can be electrically connected to the first electrode at the step surface simply by using a spacer layer to electrically isolate the second electrode from the first conductive layer. On the second side of the pyramid structure, by making the step surfaces of the multiple steps the surface of the second electrode facing away from the substrate, the first conductive layer covering the second side of the pyramid structure can be electrically connected to the second electrode at the step surface simply by using a spacer layer to electrically isolate the first electrode from the second conductive layer. This eliminates the need to form a thick oxide layer on the side of the three-dimensional capacitor facing away from the substrate and then flatten the oxide layer, as in the solutions provided in the related art, thus reducing manufacturing costs. It also eliminates the need to form multiple through-holes of varying depths in the oxide layer, eliminating the problem of electrode layer damage caused by etching multiple through-holes of varying depths, which in turn limits the number of layers in the three-dimensional capacitor.

[0054] In some possible implementations, on the first side of the pyramid structure, because the stepped surfaces of the multiple steps are the surfaces of the first electrode facing away from the substrate, only the side surfaces of the second electrode are exposed. On the second side of the pyramid structure, because the stepped surfaces of the multiple steps are the surfaces of the second electrode facing away from the substrate, only the side surfaces of the first electrode are exposed.

[0055] Furthermore, by simply setting the spacer layer on the side of the multiple steps, it can be achieved that on the first side of the pyramid structure, the spacer layer is used to electrically isolate the second electrode from the first conductive layer; on the second side of the pyramid structure, the spacer layer is used to electrically isolate the first electrode from the second conductive layer.

[0056] For the step farthest from the substrate, if the step surface is the surface of the first electrode facing away from the substrate, the spacer layer is also on the second side of the pyramid structure, covering the surface of the first electrode facing away from the substrate. If the step surface is the surface of the second electrode facing away from the substrate, the spacer layer is also on the first side of the pyramid structure, covering the surface of the second electrode facing away from the substrate.

[0057] In some possible implementations, the integrated passive device further includes a third conductive layer and a fourth conductive layer. The third conductive layer is disposed between the three-dimensional capacitor and the first conductive layer, and the fourth conductive layer is disposed between the three-dimensional capacitor and the second conductive layer. The third conductive layer and the fourth conductive layer are fabricated using an ALD process.

[0058] Because the first and second conductive layers are produced using processes such as PVD, their coverage is poor, and holes may exist in the film layers, causing defects in the integrated passive devices and affecting the service life of the integrated passive devices. However, since the ALD process has better coverage, the embodiments of the present application use the ALD process to form a third conductive layer between the three-dimensional capacitor and the first conductive layer, and a fourth conductive layer between the three-dimensional capacitor and the second conductive layer before forming the first and second conductive layers, thereby avoiding the above-mentioned defects.

[0059] In some possible implementations, the integrated passive device further includes a passivation layer, a first conductive lead, and a second conductive lead, wherein the passivation layer covers the first conductive layer, the second conductive layer, and the three-dimensional capacitor. The first conductive lead can be electrically connected to the first conductive layer via a first through-hole, and the second conductive lead can be electrically connected to the second conductive layer via a second through-hole. In this way, the first electrode transmits a signal through the first conductive layer and the first conductive lead, and the second electrode transmits a signal through the second conductive layer and the second conductive lead.

[0060] Furthermore, the first and second conductive layers of the embodiments of the present application correspond to the oxide layers of the related art, and both are disposed on the side of the stepped three-dimensional capacitor facing away from the substrate. By setting the first and second conductive layers to a greater thickness, the sides of the first and second conductive layers facing away from the substrate can be made nearly flat, thereby making the thickness of the passivation layer disposed on the sides of the first and second conductive layers facing away from the substrate much less than the thickness of the oxide layer of the related art. Therefore, even if through-holes are provided in the passivation layer, the aspect ratio of the through-holes in the passivation layer is much greater than the aspect ratio of the through-holes in the oxide layer. For example, the aspect ratio of the through-holes in the oxide layer of the related art is approximately 1:3, and the aperture size of the through-holes is approximately several hundred nanometers; whereas, in the present application, the aspect ratio of the first and second through-holes is approximately 1:2, and the aperture size of the first and second through-holes is approximately several tens of nanometers.

[0061] Compared to related technologies, the through-holes in the passivation layer of the present application are larger in size, which can reduce the contact area and contact resistance between the first conductive lead and the first conductive layer, and reduce the contact area and contact resistance between the second conductive lead and the second conductive layer, thereby improving the electrical performance of the integrated passive device, such as ESL and ESR. In addition, due to the increased aspect ratio of the first through-hole and the second through-hole, the process of etching the first through-hole and the second through-hole in the passivation layer can share the same machine as the process of forming the first conductive layer and the second conductive layer.

[0062] In some possible implementations, the integrated passive device further includes an etch stop layer, which is disposed between a step away from the substrate and the spacer layer, and the etch stop layer is exposed in a gap between the first conductive layer and the second conductive layer.

[0063] In a fourth aspect, the present application provides a chip comprising the integrated passive device described in the first aspect, the second aspect, or the third aspect.

[0064] The fourth aspect and any implementation of the fourth aspect correspond to the first aspect and any implementation of the first aspect, respectively. The technical effects corresponding to the fourth aspect and any implementation of the fourth aspect can be referred to the technical effects corresponding to the first aspect and any implementation of the first aspect, and will not be repeated here.

[0065] In a fifth aspect, the present application provides an electronic device, characterized in that it includes a circuit board and the chip described in the fourth aspect, and the chip is arranged on the circuit board.

[0066] The fifth aspect and any implementation of the fifth aspect correspond to the first aspect and any implementation of the first aspect, respectively. The technical effects corresponding to the fifth aspect and any implementation of the fifth aspect can be referred to the technical effects corresponding to the first aspect and any implementation of the first aspect, and will not be repeated here.

[0067] In a sixth aspect, the present application provides a method for preparing an integrated passive device, comprising: forming a three-dimensional capacitor on a substrate; the three-dimensional capacitor comprises multiple electrode layers and multiple dielectric layers alternately stacked on the surface of the substrate, forming a pyramid structure with multiple steps; along the direction of the substrate pointing toward the three-dimensional capacitor, the multiple electrode layers comprise first electrodes and second electrodes that are isolated from each other and alternate with each other. A spacer layer composed of a dielectric material is formed on the multiple steps. A first conductive layer is formed on the step surface on the first side of the pyramid structure, and a second conductive layer is formed on the step surface on the second side of the pyramid structure; on the first side of the pyramid structure, a first through hole connected to the first electrode is provided on the spacer layer, and the first conductive layer is electrically connected to the first electrode through the first through hole; on the second side of the pyramid structure, a second through hole connected to the second electrode is also provided on the spacer layer, and the second conductive layer is electrically connected to the second electrode through the second through hole.

[0068] In some possible implementations, the steps on the first side of the multiple steps are arranged opposite to the steps on the second side of the multiple steps.

[0069] In some possible implementations, a three-dimensional capacitor is formed on a substrate, including: forming a three-dimensional capacitor including multiple first steps on the substrate, the surface of the dielectric layer facing away from the substrate including the step surface of the first step, and the surface of the electrode layer facing the substrate including the surface of the first step facing the substrate; at the first step, a third through hole is opened in the dielectric layer, and the third through hole is arranged opposite to the first through hole and the second through hole; the first conductive layer is electrically connected to the first electrode through the third through hole of the spacer layer and the first through hole of the dielectric layer, and the second conductive layer is electrically connected to the second electrode through the third through hole of the spacer layer and the second through hole of the spacer layer.

[0070] In some possible implementations, after forming multiple first steps on the substrate, forming a three-dimensional capacitor on the substrate further includes: forming a second step on the first step; at the second step, a surface of an electrode layer facing the substrate includes a surface of the second step facing the substrate, and a surface of the electrode layer facing away from the substrate includes a step surface of the second step.

[0071] In some possible implementations, a three-dimensional capacitor is formed on a substrate, including: alternately forming multiple electrode layers and multiple dielectric layers on the substrate; the surface of the electrode layer facing away from the substrate includes a step surface, and the surface of the dielectric layer facing the substrate includes a step surface facing the substrate.

[0072] In some possible implementations, after forming a first conductive layer on the first side step surface of the pyramid structure and forming a second conductive layer on the second side step surface of the pyramid structure, the method for preparing an integrated passive device further includes: forming a passivation layer on the side of the first conductive layer and the second conductive layer facing away from the substrate; and providing a fourth through hole connected to the first conductive layer and a fifth through hole connected to the second conductive layer on the passivation layer.

[0073] In some possible implementations, after forming a three-dimensional capacitor on a substrate and before forming a spacer layer made of a dielectric material on multiple steps, the method for preparing an integrated passive device further includes: forming an etch stop layer on a step away from the substrate; and exposing the etch stop layer in a gap between the first conductive layer and the second conductive layer.

[0074] The sixth aspect and any implementation of the sixth aspect correspond to the first aspect and any implementation of the first aspect, respectively. The technical effects corresponding to the sixth aspect and any implementation of the sixth aspect can be referred to the technical effects corresponding to the first aspect and any implementation of the first aspect, and will not be repeated here.

[0075] In a seventh aspect, the present application provides a method for preparing an integrated passive device, comprising: sequentially forming a conductive bridge and an insulating layer on a substrate, with a second through-hole being provided on the insulating layer. A three-dimensional capacitor is formed on the substrate; the three-dimensional capacitor comprises multiple electrode layers and multiple dielectric layers alternately stacked on the surface of the substrate, forming a pyramid structure with multiple steps; along the direction of the substrate pointing to the three-dimensional capacitor, the multiple electrode layers comprise first electrodes and second electrodes that are isolated from each other and alternate with each other. A first spacer layer, a first connected conductive layer, and a second spacer layer are sequentially formed on the pyramid structure; the first connected conductive layer is located on the second side of the pyramid structure; on the first side of the pyramid structure, a first through-hole connected to the first electrode is provided on the second spacer layer, and on the second side of the pyramid structure, the first spacer layer is used to electrically isolate the first electrode from the first connected conductive layer, and the first connected conductive layer is electrically connected to the second electrode. A first conductive layer and a second conductive layer are formed; on a first side of the pyramid structure, the first conductive layer is electrically connected to the first electrode through a first through-hole; on a second side of the pyramid structure, an insulating layer is used to electrically isolate the first conductive layer from the conductive bridge, and the conductive bridge is electrically connected to the first connected conductive layer through a second through-hole opened in the insulating layer, and extends toward the outside of the pyramid structure to be electrically connected to the second conductive layer outside the pyramid structure.

[0076] In some possible implementations, the steps on the first side of the multiple steps are arranged opposite to the steps on the second side of the multiple steps.

[0077] In some possible implementations, forming a three-dimensional capacitor on a substrate includes: forming a three-dimensional capacitor on the substrate including multiple first steps; at the first step, the surface of the dielectric layer facing away from the substrate includes the surface of the first step facing away from the substrate, and the surface of the electrode layer facing the substrate includes the surface of the first step facing the substrate; wherein, on a first side of the first step, the dielectric layer includes a third through-hole connected to the first electrode, and the first conductive layer is electrically connected to the first electrode via the third through-hole and the first through-hole; on a second side of the first step, the dielectric layer includes a fourth through-hole connected to the second electrode, and the first conductive layer is electrically connected to the second electrode via the fourth through-hole. Forming a first spacer layer on the pyramid structure includes: forming the first spacer layer on the second side of the first step, the first spacer layer being located on a side of the first step.

[0078] In some possible implementations, while forming the first connected conductive layer on the pyramid structure, the method for preparing an integrated passive device also includes: forming a second connected conductive layer, the second connected conductive layer being on the same layer as the first connected conductive layer and being spaced apart; on the first side of the first step, a first spacing layer being located on the side of the first step, for electrically isolating the second electrode from the second connected conductive layer; the second connected conductive layer being electrically connected to the first electrode through a third through hole; and the number of the first through hole being at least one, and the first conductive layer being electrically connected to the second connected conductive layer through the first through hole.

[0079] In some possible implementations, after forming multiple first steps on the substrate, forming a three-dimensional capacitor on the substrate further includes: forming a second step on the first step; at the second step, the surface of the electrode layer facing the substrate includes the surface of the second step facing the substrate, and the surface of the electrode layer facing away from the substrate includes the step surface of the second step; on the first side of the second step, the first conductive layer is electrically connected to the electrode layer through the first through hole; or, on the second side of the second step, the first connecting conductive layer is electrically connected to the electrode layer.

[0080] In some possible implementations, a three-dimensional capacitor is formed on a substrate, including: forming a three-dimensional capacitor including multiple steps on the substrate; in any one step, the surface of the electrode layer facing away from the substrate includes the surface of the step facing away from the substrate, and the surface of the electrode layer facing the substrate includes the surface of the step facing the substrate; forming a first spacer layer on the pyramid structure, including: forming a first spacer layer covering the multiple steps on the second side of the multiple steps; the first spacer layer includes a fifth through hole connected to the second electrode, and the first connecting conductive layer is electrically connected to the second electrode through the fifth through hole.

[0081] In some possible implementations, while forming the first interconnected conductive layer on the pyramid structure, the method for preparing an integrated passive device further includes: forming a second interconnected conductive layer, the second interconnected conductive layer being co-layered and spaced apart from the first interconnected conductive layer; a first spacer layer covering the first step on a first side of the first step to electrically isolate the second electrode from the second interconnected conductive layer. Forming the first spacer layer on the pyramid structure further includes: forming a first spacer layer covering the multiple steps on a second side of the multiple steps; the first spacer layer including a fifth through-hole connecting to the second electrode, the second interconnected conductive layer being electrically connected to the first electrode via the fifth through-hole.

[0082] In some possible implementations, after forming the second spacer layer and before forming the first conductive layer and the second conductive layer, the method for preparing the integrated passive device further includes: using an atomic layer deposition process to form a third conductive layer covering the three-dimensional capacitor; the material of the third conductive layer includes TiN.

[0083] In some possible implementations, after the first side step surface of the pyramid structure is covered with a first conductive layer and the second side step surface of the pyramid structure is covered with a second conductive layer, the method for preparing an integrated passive device further includes: forming a passivation layer on the side of the first conductive layer and the second conductive layer facing away from the substrate; the passivation layer covers the first conductive layer, the second conductive layer, and the three-dimensional capacitor; and providing a sixth through hole connected to the first conductive layer and a seventh through hole connected to the second conductive layer on the passivation layer.

[0084] The seventh aspect and any implementation of the seventh aspect correspond to the first aspect and any implementation of the first aspect, respectively. The technical effects corresponding to the seventh aspect and any implementation of the seventh aspect can be referred to the technical effects corresponding to the first aspect and any implementation of the first aspect, and will not be repeated here.

[0085] In an eighth aspect, the present application provides a method for preparing an integrated passive device, comprising: forming a three-dimensional capacitor on a substrate; the three-dimensional capacitor comprises multiple electrode layers and multiple dielectric layers alternately stacked on the surface of the substrate, forming a pyramid structure with multiple steps; along the direction of the substrate toward the three-dimensional capacitor, the multiple electrode layers comprise first and second electrodes that are isolated from each other and alternate with each other. A spacer layer composed of a dielectric material is formed on the pyramid structure. A first conductive layer is formed on the step surface of the first side of the pyramid structure, and a second conductive layer is formed on the step surface of the second side of the pyramid structure; on the first side of the pyramid structure, the spacer layer is used to electrically isolate the second electrode from the first conductive layer, the step surface of the multiple steps is the surface of the first electrode facing away from the substrate, and the first conductive layer is electrically connected to the first electrode at the step surface; on the second side of the pyramid structure, the spacer layer is used to electrically isolate the first electrode from the second conductive layer, the step surface of the multiple steps is the surface of the second electrode facing away from the substrate, and the second conductive layer is electrically connected to the second electrode at the step surface.

[0086] In some possible implementations, the spacer layer is located on the sides of the multiple steps.

[0087] In some possible implementations, after forming a spacer layer made of a dielectric material on the pyramid structure, forming a first conductive layer on the step surface of the first side of the pyramid structure, and before forming a second conductive layer on the second side of the pyramid structure, the method for preparing an integrated passive device further includes: using an atomic layer deposition process to form a third conductive layer on the step surface of the first side of the pyramid structure, and forming a fourth conductive layer on the second side of the pyramid structure.

[0088] In some possible implementations, after forming a first conductive layer on a first side step surface of the pyramid structure and forming a second conductive layer on a second side step surface of the pyramid structure, the method for preparing an integrated passive device further includes: forming a passivation layer on the side of the first conductive layer and the second conductive layer facing away from the substrate, the passivation layer covering the three-dimensional capacitor; and providing a first through hole connected to the first conductive layer and a second through hole connected to the second conductive layer on the passivation layer.

[0089] In some possible implementations, after forming a three-dimensional capacitor on a substrate and before forming a spacer layer made of a dielectric material on a pyramid structure, the method for preparing an integrated passive device further includes: forming an etch stop layer on a step away from the substrate; and exposing the etch stop layer in a gap between the first conductive layer and the second conductive layer.

[0090] The eighth aspect and any implementation of the eighth aspect correspond to the first aspect and any implementation of the first aspect, respectively. The technical effects corresponding to the eighth aspect and any implementation of the eighth aspect can be referred to the technical effects corresponding to the first aspect and any implementation of the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0091] FIG1 is a diagram showing the connection relationship between modules in a mobile phone provided in an embodiment of the present application;

[0092] FIG2a is a diagram showing a preparation process of an integrated passive device provided in the related art;

[0093] FIG2 b is a diagram showing a preparation process of an integrated passive device provided in the related art;

[0094] FIG2c is a diagram showing the preparation process of an integrated passive device provided by the related art;

[0095] FIG2 d is a diagram showing the preparation process of an integrated passive device provided by the related art;

[0096] FIG2e is a diagram showing the preparation process of an integrated passive device provided by the related art;

[0097] FIG2f is a diagram showing the preparation process of an integrated passive device provided by the related art;

[0098] FIG2g is a diagram showing the preparation process of an integrated passive device provided by the related art;

[0099] FIG2h is a diagram showing the preparation process of an integrated passive device provided by the related art;

[0100] FIG3 a is a schematic structural diagram of an integrated passive device provided in the first embodiment of the present application;

[0101] FIG3 b is a schematic structural diagram of another integrated passive device provided in the first embodiment of the present application;

[0102] FIG3 c is a schematic structural diagram of another integrated passive device provided in the first embodiment of the present application;

[0103] FIG4 a is a schematic structural diagram of another integrated passive device provided in the first embodiment of the present application;

[0104] FIG4 b is a schematic structural diagram of another integrated passive device provided in the first embodiment of the present application;

[0105] FIG4c is a schematic structural diagram of another integrated passive device provided in the first embodiment of the present application;

[0106] FIG5a is a schematic structural diagram of another integrated passive device provided in the first embodiment of the present application;

[0107] FIG5 b is a schematic structural diagram of another integrated passive device provided in the first embodiment of the present application;

[0108] FIG5c is a schematic structural diagram of another integrated passive device provided in the first embodiment of the present application;

[0109] FIG6 a is a schematic structural diagram of an integrated passive device provided in a second embodiment of the present application;

[0110] FIG6 b is a schematic structural diagram of another integrated passive device provided in the second embodiment of the present application;

[0111] FIG6 c is a schematic structural diagram of another integrated passive device provided in the second embodiment of the present application;

[0112] FIG7 a is a schematic structural diagram of another integrated passive device provided in the second embodiment of the present application;

[0113] FIG7 b is a schematic structural diagram of another integrated passive device provided in the second embodiment of the present application;

[0114] FIG8 a is a schematic structural diagram of another integrated passive device provided in the second embodiment of the present application;

[0115] FIG8 b is a schematic structural diagram of another integrated passive device provided in the second embodiment of the present application;

[0116] FIG9 a is a schematic structural diagram of an integrated passive device provided in a third embodiment of the present application;

[0117] FIG9 b is a schematic structural diagram of another integrated passive device provided in the third embodiment of the present application;

[0118] FIG9c is a schematic structural diagram of another integrated passive device provided in the third embodiment of the present application;

[0119] FIG9 d is a schematic structural diagram of another integrated passive device provided in the third embodiment of the present application;

[0120] FIG10 is a flowchart of the preparation of an integrated passive device provided in the fourth embodiment of the present application;

[0121] FIG11a is a diagram showing a manufacturing process of an integrated passive device provided in the fourth embodiment of the present application;

[0122] FIG11b is a process diagram of an integrated passive device provided in the fourth embodiment of the present application;

[0123] FIG11c is a diagram showing a manufacturing process of an integrated passive device provided in the fourth embodiment of the present application;

[0124] FIG11d is a diagram showing a manufacturing process of an integrated passive device provided in the fourth embodiment of the present application;

[0125] FIG11e is a diagram showing a manufacturing process of an integrated passive device provided in the fourth embodiment of the present application;

[0126] FIG11f is a diagram showing a manufacturing process of an integrated passive device provided in the fourth embodiment of the present application;

[0127] FIG11g is a diagram showing a manufacturing process of an integrated passive device provided in the fourth embodiment of the present application;

[0128] FIG11h is a diagram showing a manufacturing process of an integrated passive device provided in the fourth embodiment of the present application;

[0129] FIG12 is a flowchart of the preparation of an integrated passive device provided in the fifth embodiment of the present application;

[0130] FIG13a is a diagram showing a manufacturing process of an integrated passive device provided in the fifth embodiment of the present application;

[0131] FIG13 b is a diagram showing a manufacturing process of an integrated passive device provided in the fifth embodiment of the present application;

[0132] FIG13c is a diagram showing a manufacturing process of an integrated passive device provided in the fifth embodiment of the present application;

[0133] FIG13 d is a diagram showing the preparation process of an integrated passive device provided in an embodiment of the present application;

[0134] FIG13e is a diagram showing a manufacturing process of an integrated passive device provided in the fifth embodiment of the present application;

[0135] FIG13f is a diagram showing a manufacturing process of an integrated passive device provided in the fifth embodiment of the present application;

[0136] FIG13g is a diagram showing a manufacturing process of an integrated passive device provided in the fifth embodiment of the present application;

[0137] FIG13h is a diagram showing a manufacturing process of an integrated passive device provided in the fifth embodiment of the present application;

[0138] FIG13i is a diagram showing a manufacturing process of an integrated passive device provided in the fifth embodiment of the present application;

[0139] FIG13j is a diagram showing a manufacturing process of an integrated passive device provided in the fifth embodiment of the present application;

[0140] FIG13k is a diagram illustrating a manufacturing process of an integrated passive device according to the fifth embodiment of the present application;

[0141] FIG131 is a diagram showing a manufacturing process of an integrated passive device provided in the fifth embodiment of the present application;

[0142] FIG13m is a diagram showing a manufacturing process of an integrated passive device provided in the fifth embodiment of the present application;

[0143] FIG13n is a diagram showing a manufacturing process of an integrated passive device provided in the fifth embodiment of the present application;

[0144] FIG13o is a diagram showing a manufacturing process of an integrated passive device provided in the fifth embodiment of the present application;

[0145] FIG13p is a diagram showing a manufacturing process of an integrated passive device provided in the fifth embodiment of the present application;

[0146] FIG13q is a diagram showing a manufacturing process of an integrated passive device provided in the fifth embodiment of the present application;

[0147] FIG14 is a flowchart of a preparation process of an integrated passive device provided in the sixth embodiment of the present application;

[0148] FIG15a is a diagram showing a manufacturing process of an integrated passive device provided in the sixth embodiment of the present application;

[0149] FIG15 b is a diagram showing a preparation process of an integrated passive device provided in the sixth embodiment of the present application;

[0150] FIG15c is a diagram showing a preparation process of an integrated passive device provided in the sixth embodiment of the present application;

[0151] FIG15 d is a diagram showing a preparation process of an integrated passive device provided in the sixth embodiment of the present application;

[0152] FIG15e is a diagram showing a preparation process of an integrated passive device provided in the sixth embodiment of the present application;

[0153] FIG15f is a diagram showing the preparation process of an integrated passive device provided in the sixth embodiment of the present application. DETAILED DESCRIPTION

[0154] To make the objectives, technical solutions, and advantages of this application more clear, the technical solutions of this application are described clearly and completely below in conjunction with the accompanying drawings. Obviously, the embodiments described are only some of the embodiments of this application, not all of them. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0155] The terms "first," "second," and so on in the specification, examples, claims, and drawings of this application are used solely for descriptive purposes and should not be construed as indicating or implying relative importance or order. "And / or" is used to describe an association between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can mean: only A exists, only B exists, and both A and B exist, where A and B can be singular or plural. The character " / " generally indicates that the associated objects are in an "or" relationship. "Installed," "connected," and "connected" should be broadly construed, meaning, for example, fixed, removable, or integral; directly, indirectly through an intermediary, or internally connected between two components. Furthermore, the terms "including," "having," and any variations thereof, are intended to cover non-exclusive inclusions, such as inclusion of a list of steps or elements. A method, system, product, or apparatus is not necessarily limited to the steps or elements explicitly listed and may include other steps or elements not explicitly listed or inherent to such process, method, product, or apparatus. "Up", "down", "left", "right", etc. are only used in relation to the orientation of the components in the drawings. These directional terms are relative concepts. They are used for relative description and clarification, and may change accordingly according to the change of the orientation of the components in the drawings.

[0156] An embodiment of the present application provides an electronic device, which may be a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, a communication electronic product, or the like, including integrated passive components.

[0157] Consumer electronic products include mobile phones, tablet computers, laptops, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smart watches, smart bracelets, etc.), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronic products include smart door locks, TVs, smart speakers, refrigerators, sweeping robots, etc. Car-mounted electronic products include car navigation systems and car displays, etc. Financial terminal products include automated teller machines (ATMs) and self-service terminals, etc. Communication electronic products include servers, storage devices, radars, base stations, and other communication equipment that contain integrated passive components.

[0158] For ease of explanation, the following uses a mobile phone as an example electronic device. A mobile phone may include a circuit board, a chip mounted on the circuit board, and various circuits mounted on the chip to form the necessary components within the phone. For example, components such as a processor and memory can be implemented using a variety of different circuit structures.

[0159] For ease of explanation, the following description uses a mobile phone as an example electronic device. As shown in Figure 1, the mobile phone may include a circuit board, a display screen, a battery, a camera, and the like. The circuit board may include a processor, internal memory, a charging circuit, and the like. Of course, the mobile phone may also include other components, and the circuit board may also include other circuit structures, which are not limited in this embodiment of the present application.

[0160] A processor may include one or more processing units, for example, an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a memory, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU). Different processing units may be independent devices or integrated into one or more processors.

[0161] The GPU is a microprocessor for image processing that connects the display and application processor. It performs mathematical and geometric calculations for graphics rendering. This allows the phone to achieve display functionality through the GPU, display, and application processor.

[0162] The mobile phone's charging circuitry includes a power management circuit and a charge management circuit. The power management circuit connects the battery, the charge management circuit, and the processor. The charge management circuit receives charging input from the charger to charge the battery. While the charge management circuit charges the battery, it also provides power to the mobile phone through the power management circuit. The power management circuit receives input from the battery and / or the charge management module to power the processor, internal memory, display, camera, and other components.

[0163] The internal memory in a mobile phone can be used to store computer executable program code, which includes instructions. The processor executes the instructions stored in the internal memory to perform various functions and data processing of the mobile phone.

[0164] The processor, internal memory, charging circuit, and other components integrated on the circuit board mentioned above all comprise one or more chips. The chips can be coupled to the circuit board via pins. The circuit board can also couple the chip to external circuits. For example, the circuit board can couple the chip to a power supply circuit, which can then provide a DC voltage to the chip via the circuit board to power the chip. Alternatively, taking multiple chips as an example, some of the chips can be coupled to each other via traces on the circuit board to collaborate and achieve specific functions.

[0165] On a chip, the circuits that make up various devices typically include many transistors. In addition, these circuits also include passive components such as resistors, capacitors, and inductors. By interconnecting transistors and passive components as needed, circuits with various functions can be constructed. Therefore, passive components are essential components in circuits.

[0166] With the continuous evolution of communication technology, smartphones need to support more and more frequency bands. For example, fifth-generation mobile communication technology (5G) mobile phones need to include new 5G frequency bands and be backward compatible with 4G frequency bands, which has led to a significant increase in the number of passive components assembled on circuit boards. As a result, the resulting high-frequency transmission loss and heat dissipation problems have become increasingly apparent. Integrated passive devices (IPDs), due to their excellent high capacitance density and miniaturization, play an important role in higher-integration packaging compared to traditional passive devices set on circuit boards through welding technology. They are one of the key components for smartphones to meet their high-frequency communication needs.

[0167] As mentioned above, passive components include resistors, capacitors, inductors, etc. The capacitor can be a three-dimensional capacitor. The relevant technology can prepare a three-dimensional capacitor by the following steps:

[0168] As shown in FIG2a , a receiving groove is formed on the substrate 10. As shown in FIG2b , the electrode layer 11 and the dielectric layer 12 are alternately filled in the receiving groove in sequence to form a three-dimensional capacitor. As shown in FIG2c , the opposite ends of the portion of the electrode layer 11 and the portion of the dielectric layer 12 away from the substrate 10 are etched away. After etching, the multiple electrode layers 11 and the multiple dielectric layers 12 form multiple steps to expose the electrode layer 11 to be electrically connected to the conductive layer. As shown in FIG2d , spacers 13 are formed at the opposite ends of the etched portion of the electrode layer 11 and the portion of the dielectric layer 12. As shown in FIG2e , an etch stop layer 21 is formed on the side of the electrode layer 11 and the dielectric layer 12 facing away from the substrate 10 to prevent subsequent etching processes from affecting the pattern of the electrode layer 11 and the dielectric layer 12. As shown in FIG2f , an oxide layer 22 is formed on the side of the etch stop layer 21 facing away from the substrate 10. As shown in FIG2g , multiple through holes of varying depths are formed in the oxide layer 22, each through hole exposing the surface of a different step. 2h, a conductive layer 14 is formed on the side of the oxide layer 22 facing away from the substrate 10. The conductive layer 14 contacts the exposed surfaces of the different electrode layers 11 through the conductive material in the through-holes, so that voltage is applied to the different electrode layers 11 through the conductive layer 14 when the three-dimensional capacitor is in operation.

[0169] However, the integrated passive devices prepared by the above process steps have the following problems:

[0170] First, because the oxide layer 22 and the etch stop layer 21 have different etching selectivities, when forming a through hole, the insulator 22 is etched first, and then the etch stop layer 21 is etched. However, although the oxide layer 22 and the etch stop layer 21 have different etching selectivities, the difference in their etching selectivities has an upper limit. For a deeper through hole and a shallower through hole to be formed, during the process of etching the portion of the deeper through hole located in the oxide layer 22, the portion of the shallower through hole located in the oxide layer 22 has already been completely etched, and the etching material used to etch the oxide layer 22 also etches away at least a portion of the shallower through hole located in the etch stop layer 21. Furthermore, during the process of etching the portion of the deeper through hole located in the etch stop layer 21, the portion of the shallower through hole located in the etch stop layer 21 has already been completely etched, and the etching material used to etch the stop layer 21 will also affect the surface of the electrode layer 11 exposed by the shallower through hole. In order to prevent the etching material used for etching the stop layer 21 from affecting the electrode layer 11, the depth difference of the multiple through holes cannot be too large, and thus the number of electrode layers 11 constituting the multi-step cannot be too many, resulting in a limited number of layers of the three-dimensional capacitor.

[0171] Second, because the multiple electrode layers 11 and the multiple dielectric layers 12 are stepped, the surface of the oxide layer 22 formed on the side of the multiple electrode layers 11 and the multiple dielectric layers 12 facing away from the substrate 10 is not flat. To prevent the impact of the multiple steps on the via formation process (exposure and development), chemical mechanical polishing (CMP) is typically used to planarize the oxide layer 22. However, the thickness of the oxide layer 22 at different locations is poorly controllable, which not only increases costs but also affects the yield of the integrated passive devices.

[0172] Based on this, an embodiment of the present application provides an integrated passive device, which solves the above-mentioned problem by improving the structure of the three-dimensional capacitor on the side facing away from the substrate 10.

[0173] The following is divided into three embodiments to introduce the structure of the integrated passive device respectively.

[0174] First embodiment

[0175] As shown in Figure 3a, the integrated passive device includes a substrate 10, a three-dimensional capacitor, a spacer layer 13, and a first conductive layer 141 and a second conductive layer 142 spaced apart. The three-dimensional capacitor comprises multiple electrode layers 11 and multiple dielectric layers 12 stacked alternately on the surface of substrate 10, forming a pyramidal structure with multiple steps. In the direction from substrate 10 toward the three-dimensional capacitor, the multiple electrode layers 11 include isolated and alternating first and second electrodes. The multiple steps are covered by a spacer layer 13 composed of a dielectric material.

[0176] The first step surface of the pyramid structure is covered with a first conductive layer 141. A first through-hole 31 communicating with the first electrode is defined in the spacer layer 13. The first conductive layer 141 is electrically connected to the first electrode via the first through-hole 31. The second step surface of the pyramid structure is covered with a second conductive layer 142. A second through-hole 32 communicating with the second electrode is also defined in the spacer layer 13. The second conductive layer 142 is electrically connected to the second electrode via the second through-hole 32. The term "step surface" refers to the surface of each step facing away from the substrate 10.

[0177] The first side and second side of the pyramid structure refer to two opposing sidewalls of the pyramid structure. As the name suggests, the pyramid structure gradually decreases in size in a first direction away from substrate 10 and gradually indents toward the center of the pyramid structure in the first direction. The first direction is the direction from the first side of the pyramid structure toward the second side, and vice versa.

[0178] In the embodiment of the present application, the multi-layer electrode layer 11 and the multi-layer dielectric layer 12 are stacked into a multi-step structure, and the multi-step structure is located on the first side and the second side, so that the three-dimensional capacitor has a pyramid structure including multiple steps. In the pyramid structure, the third side and the fourth side adjacent to the first side and the second side can be a plane or a stepped structure, which is not limited in the embodiment of the present application.

[0179] In a three-dimensional capacitor, a first electrode, a dielectric layer 12, and a second electrode constitute a capacitor. Furthermore, with the exception of the electrode layer 11 closest to the substrate 10 and the electrode layer 11 farthest from the substrate 10, other first electrodes can form a capacitor with either the dielectric layer 12 and the second electrode adjacent to the side facing the substrate 10 or the dielectric layer 12 and the second electrode adjacent to the side facing away from the substrate 10. Other second electrodes can form a capacitor with either the dielectric layer 12 and the first electrode adjacent to the side facing the substrate 10 or the dielectric layer 12 and the first electrode adjacent to the side facing away from the substrate 10.

[0180] When the three-dimensional capacitor is in operation, the plurality of first electrodes can transmit signals through the same first conductive layer 141 , and the plurality of second electrodes can transmit signals through the same second conductive layer 142 .

[0181] In the present application, a three-dimensional capacitor is fabricated into a pyramid structure comprising multiple steps. This allows the steps farther from the substrate 10 to expose the surface of the steps closer to the substrate 10. On the first side of the pyramid structure, a first through-hole 31 communicating with the first electrode is provided on the spacer layer 13, so that the first conductive layer 141 covering the first side of the pyramid structure is electrically connected to the first electrode via the first through-hole 31, and the second electrode is electrically isolated from the first conductive layer 141 by the spacer layer 13. On the second side of the pyramid structure, a second through-hole 32 communicating with the second electrode is provided on the spacer layer 13, so that the second conductive layer 142 covering the second side of the pyramid structure is electrically connected to the second electrode via the second through-hole 32, and the second electrode is electrically isolated from the second conductive layer 142 by the spacer layer 13. This eliminates the need to form a thicker oxide layer 22 on the side of the three-dimensional capacitor facing away from the substrate 10 and perform a planarization process on the oxide layer 22, thereby saving manufacturing costs. There is no need to form multiple through holes of varying depths in the oxide layer 22 , and there is no problem of the electrode layer 11 being damaged when etching multiple through holes of varying depths, thereby limiting the number of layers of the three-dimensional capacitor.

[0182] In some possible implementations, as shown in FIG3a , a step on the first side of the plurality of steps is disposed opposite a step on the second side of the plurality of steps. Thus, a step on the first side includes a portion of the first electrode, and a step on the second side opposite the step also includes a portion of the first electrode. A step on the first side includes a portion of the second electrode, and a step on the second side opposite the step also includes a portion of the second electrode.

[0183] On this basis, the surface of the dielectric layer 12 facing away from the substrate 10 includes a stepped surface, and the surface of the electrode layer 11 facing the substrate 10 includes a stepped surface facing the substrate 10. Alternatively, the surface of the electrode layer 11 facing away from the substrate 10 includes a stepped surface, and the surface of the dielectric layer 12 facing the substrate 10 includes a stepped surface facing the substrate 10. Several different structures of integrated passive devices are described below with reference to the accompanying drawings:

[0184] In the first case, as shown in Figure 3a, the multi-step steps include a first step. The surface of the dielectric layer 12 facing away from the substrate 10 includes the step surface of the first step, and the surface of the electrode layer 11 facing the substrate 10 includes the surface of the first step facing the substrate 10. At the first step, a third through-hole 33 is defined in the dielectric layer 12. The third through-hole 33 is disposed opposite the first through-hole 31 and the second through-hole 32. The first conductive layer 141 is electrically connected to the first electrode through the third through-hole 33 and the first through-hole 31, and the second conductive layer 142 is electrically connected to the second electrode through the third through-hole 33 and the second through-hole 32.

[0185] The sidewall of the first electrode on the second side is covered by a spacer layer 13, and the upper surface of the first electrode on the second side is covered by a dielectric layer 12 forming the same first step as the first electrode, thereby electrically isolating the second conductive layer 142 from the first electrode. The sidewall of the second electrode on the first side is covered by a spacer layer 13, and the upper surface of the second electrode on the first side is covered by a dielectric layer 12 forming the same first step as the first electrode, thereby electrically isolating the first conductive layer 141 from the second electrode. The upper surface of the first electrode is the surface of the first electrode facing away from the substrate 10, and the upper surface of the second electrode is the surface of the second electrode facing away from the substrate 10.

[0186] Because the three-dimensional capacitor has a multi-step pyramid structure, the depth of each first through-hole 31 and second through-hole 32, along the direction from substrate 10 toward spacer layer 13, is equal to the thickness of the same spacer layer 13, and the depth of each third through-hole 33 is equal to the thickness of one dielectric layer 12. As a result, the depths of the multiple first through-holes 31 and multiple second through-holes 32 are all the same, and the depths of the multiple third through-holes 33 are the same or have a small difference. This prevents the electrode layer 11 from being damaged by the varying depths of the through-holes formed during the same etching process, which would in turn limit the number of layers in the three-dimensional capacitor.

[0187] Furthermore, there is no need to provide a thick oxide layer 22 between the first conductive layer 141 , the second conductive layer 142 and the spacer layer 13 , and the oxide layer 22 can be planarized, thereby saving preparation costs.

[0188] In some embodiments, as shown in FIG3b , the integrated passive device may further include an etch stop layer 21. The etch stop layer 21 may be disposed between the first step away from the substrate 10 (or, in other words, the first step farthest from the substrate) and the spacer layer 13. The etch stop layer 21 is exposed in the gap between the first conductive layer 141 and the second conductive layer 142. During subsequent etching to form the patterns of the first conductive layer 141 and the second conductive layer 142, the etch stop layer 21 protects the electrode layer 11 of the three-dimensional capacitor.

[0189] Here, in order not to affect the electrical connection between the first conductive layer 141 and the electrode layer 11 farthest from the substrate 10 , the etch stop layer 21 may also include a through hole.

[0190] In the second case, shown in Figure 4a, the multi-step structure, based on the first case, further includes a second step, with the first step disposed between substrate 10 and the second step. At the second step, the surface of electrode layer 11 facing substrate 10 comprises the surface of the second step facing substrate 10, while the surface of the electrode layer facing away from substrate 10 comprises the surface of the second step. In other words, the second step consists of a portion of electrode layer 11 and does not include dielectric layer 12. Therefore, there is no need to provide a through-hole in dielectric layer 12 at the second step.

[0191] If the second step is composed of a portion of the first electrode, the first conductive layer 141 is directly electrically connected to the first electrode through the first through-hole 31, and the sidewall of the first electrode on the second side and the step surface are covered by the spacer layer 13, thereby achieving electrical isolation between the second conductive layer 142 and the first electrode.

[0192] As shown in Figure 4a, if the second step is composed of a portion of the second electrode, the second conductive layer 142 is directly electrically connected to the second electrode through the second through hole 32, and the sidewall of the second electrode on the first side and the step surface are covered by the spacer layer 13, thereby achieving electrical isolation between the first conductive layer 141 and the second electrode.

[0193] In some embodiments, as shown in FIG4 b , the integrated passive device may further include an etch stop layer 21. The etch stop layer 21 may be disposed between the second step and the spacer layer 13. The etch stop layer 21 is exposed in the gap between the first conductive layer 141 and the second conductive layer 142. This protects the electrode layer 11 of the three-dimensional capacitor during subsequent etching to form the pattern of the first conductive layer 141 and the second conductive layer 142.

[0194] Here, in order not to affect the electrical connection between the first conductive layer 141 and the electrode layer 11 farthest from the substrate 10 , the etch stop layer 21 may also include a through hole, and the through hole of the etch stop layer 21 is opposite to the first through hole 31 or the second through hole 32 .

[0195] In the third case, as shown in FIG5a , the step on the first side of the multiple steps is arranged opposite the step on the second side of the multiple steps, and the surface of the electrode layer 11 facing away from the substrate 10 comprises the surface of the step, and the surface of the dielectric layer 12 facing the substrate 10 comprises the surface of the step facing the substrate 10. The first conductive layer 141 is electrically connected to the first electrode through the first through-hole 31, and the second conductive layer 142 is electrically connected to the second electrode through the second through-hole 32.

[0196] The sidewalls and top surface of the first electrode on the second side are covered by the spacer layer 13, thereby electrically isolating the second conductive layer 142 from the first electrode. The sidewalls and top surface of the second electrode on the first side are covered by the spacer layer 13, thereby electrically isolating the first conductive layer 141 from the second electrode.

[0197] Because the three-dimensional capacitor has a multi-step pyramid structure, the depth of each first through-hole 31 and second through-hole 32 along the direction from substrate 10 to spacer layer 13 is the same thickness of the same spacer layer 13. As a result, the depths of the multiple first through-holes 31 and second through-holes 32 are all the same, preventing damage to the electrode layer 11 caused by varying depths of through-holes formed during the same etching process, which would in turn limit the number of layers in the three-dimensional capacitor.

[0198] Furthermore, there is no need to provide a thick oxide layer 22 between the first conductive layer 141 , the second conductive layer 142 and the spacer layer 13 , and the oxide layer 22 can be planarized, thereby saving preparation costs.

[0199] In some embodiments, as shown in FIG5b , the integrated passive device may further include an etch stop layer 21. The etch stop layer 21 may be disposed between a step away from the substrate 10 (in other words, the step farthest from the substrate) and the spacer layer 13. The etch stop layer 21 is exposed in the gap between the first conductive layer 141 and the second conductive layer 142. This protects the electrode layer 11 of the three-dimensional capacitor during subsequent etching to form the pattern of the first conductive layer 141 and the second conductive layer 142.

[0200] Here, in order not to affect the electrical connection between the first conductive layer 141 and the electrode layer 11 farthest from the substrate 10 , the etch stop layer 21 may also include a through hole.

[0201] In addition, as shown in Figures 3c, 4c, and 5c, based on the first to third cases shown in Figures 3a-3b, 4a-4b, and 5a-5b, the integrated passive device may further include a passivation layer 23, a first conductive lead, and a second conductive lead, disposed on the side of the first conductive layer 141 and the second conductive layer 142 facing away from the substrate 10. The first conductive lead and the second conductive lead are disposed on the side of the passivation layer 23 facing away from the substrate 10. The passivation layer 23 may include a fourth through-hole 34 and a fifth through-hole 35. The first conductive lead may be electrically connected to the first conductive layer 141 via the fourth through-hole 34, and the second conductive lead may be electrically connected to the second conductive layer 142 via the fifth through-hole 35. In this way, the first electrode transmits a signal through the first conductive layer 141 and the first conductive lead, and the second electrode transmits a signal through the second conductive layer 142 and the second conductive lead.

[0202] Furthermore, the first conductive layer 141 and the second conductive layer 142 of the embodiment of the present application correspond to the oxide layer 22 of the related art, and both are arranged on the side of the stepped three-dimensional capacitor away from the substrate 10. The first conductive layer 141 and the second conductive layer 142 can be set to a larger thickness so that the first conductive layer 141 and the second conductive layer 142 are close to flat on the side away from the substrate 10, so that the thickness of the passivation layer 23 arranged on the side of the first conductive layer 141 and the second conductive layer 142 away from the substrate 10 is much smaller than the thickness of the oxide layer 22 of the related art. Therefore, even if the fourth through hole 34 and the fifth through hole 35 are also provided in the passivation layer 23, the width-to-depth ratio of the fourth through hole 34 and the fifth through hole 35 is much larger than the width-to-depth ratio of the through hole in the oxide layer 22. For example, the width-to-depth ratio of the through hole in the oxide layer 22 of the related art is about 1:3, and the aperture size of the through hole is about several hundred nanometers; while the width-to-depth ratio of the fourth through hole 34 and the fifth through hole 35 of the present application is about 1:2, and the aperture size of the fourth through hole 34 and the fifth through hole 35 is about tens of nanometers.

[0203] In the related art, in the direction of the interface between the electrode layer 11 and the dielectric layer 12, the size of the through hole of the oxide layer 22 is relatively small (for example, the size of the through hole is 0.18 μm), so that the contact area between the conductive material filling the through hole and the electrode layer 11 in contact with it is relatively small, resulting in a large contact resistance between the two, affecting the electrical properties of the integrated passive device, such as the equivalent series inductance (ESL) and equivalent series resistance (ESR).

[0204] Furthermore, the width-to-depth ratio of each through hole in the oxide layer 22 is relatively large, and the through holes cannot be etched using the same machine as the conductive layer 14. In other words, etching through holes in the oxide layer requires a dedicated machine.

[0205] Compared to related art, the fourth and fifth through-holes 34 and 35 of the present application are larger in size, which can reduce the contact area and contact resistance between the first conductive lead and the first conductive layer 141, and reduce the contact area and contact resistance between the second conductive lead and the second conductive layer 142, thereby improving the electrical performance of the integrated passive device, such as ESL and ESR. Furthermore, due to the increased aspect ratio of the fourth and fifth through-holes 34 and 35, the process for etching the fourth and fifth through-holes 34 and 35 in the passivation layer 23 can share the same machine as the process for forming the first and second conductive layers 141 and 142, thus saving production costs.

[0206] Second embodiment

[0207] As shown in FIG. 6 a , the integrated passive device includes a substrate 10 , a three-dimensional capacitor, a first spacer layer 131 , a first connecting conductive layer 143 , a second spacer layer 132 , a first conductive layer 141 , and a second conductive layer 142 .

[0208] The three-dimensional capacitor comprises multiple electrode layers 11 and multiple dielectric layers 12 alternately stacked on the surface of a substrate, forming a pyramid structure with multiple steps. Along the direction of the substrate 10 toward the three-dimensional capacitor, the multiple electrode layers 11 comprise isolated and alternating first and second electrodes. The pyramid structure is sequentially covered with a first spacer layer 131, a first interconnecting conductive layer 143, a second spacer layer 132, and a first conductive layer 141. The first interconnecting conductive layer 143 is located on the second side of the pyramid structure. The explanation of the pyramid structure of the second embodiment is the same as that of the first embodiment and is not repeated here.

[0209] On the first side of the pyramid structure, a first through hole 31 communicating with the first electrode is formed on the second spacer layer 132 , and the first conductive layer 141 is electrically connected to the first electrode through the first through hole 31 .

[0210] On the second side of the pyramid structure, the first spacer layer 131 is used to electrically isolate the first electrode from the first connected conductive layer 143, and the first connected conductive layer 143 is electrically connected to the second electrode; a conductive bridge 16 and an insulating layer 17 are provided between the substrate 10 and the three-dimensional capacitor, and the insulating layer 17 is used to electrically isolate the first conductive layer 141 from the conductive bridge 16; the conductive bridge 16 is electrically connected to the first connected conductive layer 143 through a second through hole opened in the insulating layer 17, and extends to the outside of the pyramid structure and is electrically connected to the second conductive layer 142 outside the pyramid structure.

[0211] In the present application, a three-dimensional capacitor is fabricated into a pyramid structure comprising multiple steps, so that the steps farther from the substrate 10 can expose the surface of the steps closer to the substrate 10. On the first side of the pyramid structure: a first through hole 31 connected to the first electrode is provided on the second spacer layer 132, so that the first conductive layer 141 covering the pyramid structure is electrically connected to the first electrode through the first through hole 31. By arranging the second spacer layer 132 between the pyramid structure and the first conductive layer 141, the second spacer layer 132 can be used to electrically isolate the second electrode from the first conductive layer 141. On the second side of the pyramid structure: a first connecting conductive layer 143 is covered on the pyramid structure, so that the first connecting conductive layer 143 is electrically connected to the second conductive layer 142 on the second side of the pyramid structure; and the first connecting conductive layer 143 is electrically connected to the second conductive layer 142 disposed outside the pyramid structure through a conductive bridge 16. On this basis, on the second side of the pyramid structure: by arranging the first spacer layer 131 between the pyramid structure and the first connected conductive layer 143, the first spacer layer 131 can be used to electrically isolate the first connected conductive layer 143 from the first electrode. By arranging the second spacer layer 132 between the first conductive layer 141 and the first connected conductive layer 143, the second spacer layer 132 can be used to electrically isolate the first conductive layer 141 from the first connected conductive layer 143. There is no need to form a thicker oxide layer 22 on the side of the three-dimensional capacitor away from the substrate 10 as provided in the related art, and to flatten the oxide layer 22, thereby saving preparation costs. There is also no need to form multiple through holes of varying depths in the oxide layer 22, and thus there is no problem of the electrode layer 11 being damaged when etching multiple through holes of varying depths, thereby limiting the number of layers of the three-dimensional capacitor.

[0212] In some possible implementations, as shown in FIG6a , a step on the first side of the plurality of steps is disposed opposite a step on the second side of the plurality of steps. Thus, a step on the first side includes a portion of the first electrode, and a step on the second side opposite the step also includes a portion of the first electrode. A step on the first side includes a portion of the second electrode, and a step on the second side opposite the step also includes a portion of the second electrode.

[0213] On this basis, the surface of the dielectric layer 12 facing away from the substrate 10 includes a stepped surface, and the surface of the electrode layer 11 facing the substrate 10 includes a stepped surface facing the substrate 10. Alternatively, the surface of the electrode layer 11 facing away from the substrate 10 includes a stepped surface, and the surface of the dielectric layer 12 facing the substrate 10 includes a stepped surface facing the substrate 10. Several different structures of integrated passive devices are described below with reference to the accompanying drawings:

[0214] In the first case, the multiple steps include a first step. At the first step, the surface of the dielectric layer 12 facing away from the substrate 10 includes the surface of the first step facing away from the substrate 10, and the surface of the electrode layer 11 facing the substrate 10 includes the surface of the first step facing the substrate 10. On the first side of the first step, the dielectric layer 12 includes a third through-hole 33 connected to the first electrode. The first conductive layer 1422 is electrically connected to the first electrode through the third through-hole 33 and the first through-hole 31. By disposing the second spacer layer 132 between the pyramid structure and the first conductive layer 141, the second spacer layer 132 can be used to electrically isolate the second electrode from the first conductive layer 141.

[0215] On the second side of the first step, the dielectric layer 12 includes a fourth through-hole 34 connected to the second electrode. The first connected conductive layer 143 is electrically connected to the second electrode via the fourth through-hole 34. By disposing a first spacer layer 131 on the side of the first step, the first connected conductive layer 143 can be electrically isolated from the first electrode by the first spacer layer 131. By disposing a second spacer layer 132 between the first conductive layer 141 and the first connected conductive layer 143, the first conductive layer 141 and the first connected conductive layer 143 can be electrically isolated by the second spacer layer 132.

[0216] According to the structure shown in FIG6a , on the first side of the pyramid structure, the first electrode is electrically connected to the first conductive layer 141 via the first through-hole 31 in the second spacer layer 132 and the third through-hole 33 in the dielectric layer 12. On the second side of the pyramid structure, the second electrode is electrically connected to the first connected conductive layer 143 via the fourth through-hole 34 in the dielectric layer 12. The first connected conductive layer 143 is further electrically connected to the conductive bridge 16 via the second through-hole 32 in the insulating layer 17. The conductive bridge 16 is electrically connected to the second conductive layer 142.

[0217] Because the three-dimensional capacitor has a pyramid structure with multiple steps, the depth of each first through hole 31 along the direction of the substrate 10 pointing to the first spacer layer 13 is the thickness of the same second spacer layer 132, and the depth of each third through hole 33 and each fourth through hole 34 is the thickness of a dielectric layer 12. Therefore, the depths of the multiple first through holes 31 are the same, and the depths of the multiple third through holes 33 and the multiple fourth through holes 34 are the same or have little difference. This prevents the electrode layer 11 from being damaged due to the different depths of the through holes formed by the same etching process, which in turn leads to the problem of limiting the number of layers of the three-dimensional capacitor. In addition, there is no need to set a thick oxide layer 22 between the first conductive layer 141 and the second conductive layer 142 and the second spacer layer 132, and the oxide layer 22 does not need to be flattened, which can save manufacturing costs.

[0218] In some embodiments, as shown in FIG6b , the integrated passive device may further include a second connecting conductive layer 144. The second connecting conductive layer 144 is formed on the same layer as the first connecting conductive layer 143 and spaced apart from each other. The two layers may be fabricated using the same semiconductor process. On the first side of the first step, a first spacer layer 131 is located on the side of the first step to electrically isolate the second electrode from the second connecting conductive layer 144. The second connecting conductive layer 144 is electrically connected to the first electrode via a third through-hole 33 in the dielectric layer 12. There is at least one first through-hole 31, and the first conductive layer 141 is electrically connected to the second connecting conductive layer 144 via the first through-hole 31 in the second spacer layer 132.

[0219] According to the structure shown in FIG6b , on the first side of the pyramid structure, the multilayer first electrodes are electrically connected to the second connected conductive layer 144 via the third through-holes 33 in the multilayer dielectric layer 12. The second connected conductive layer 144 is further electrically connected to the first conductive layer 141 via at least one first through-hole 31 in the second spacer layer 132. On the second side of the pyramid structure, the second electrodes are electrically connected to the first connected conductive layer 143 via the fourth through-holes 34 in the dielectric layer 12. The first connected conductive layer 143 is further electrically connected to the conductive bridge 16 via the second through-holes 32 in the insulating layer 17. The conductive bridge 16 is further electrically connected to the second conductive layer 142.

[0220] In the second case, as shown in Figure 7a, the multi-step structure, based on the first case, further includes a second step, with the first step disposed between substrate 10 and the second step. At the second step, the surface of electrode layer 11 facing substrate 10 comprises the surface of the second step facing substrate 10, while the surface of electrode layer 11 facing away from substrate 10 comprises the step surface of the second step. In other words, the second step consists of a portion of electrode layer 11 and does not include dielectric layer 12. Therefore, there is no need to open a through hole in dielectric layer 12 at the second step.

[0221] If the electrode layer 11 of the second step is the first electrode, then on the first side of the second step, the first conductive layer 141 is electrically connected to the first electrode via the first through-hole 31 in the second spacer layer 132. Alternatively, the first conductive layer 141 is electrically connected to the second connected conductive layer 144 via the first through-hole 31 in the second spacer layer 132, and the second connected conductive layer 144 is directly electrically connected to the first electrode. Of course, the first spacer layer 131 can also extend from the sidewall of the second step to the surface of the second step. In this way, the second connected conductive layer 144 can be electrically connected to the first electrode via the through-hole in the first spacer layer 131.

[0222] As shown in FIG7a , if the electrode layer 11 of the second step is a second electrode, then on the second side of the second step, the second electrode is directly electrically connected to the first connecting conductive layer 143. Alternatively, the first spacer layer 131 may extend from the sidewall of the second step to the surface of the second step. In this way, the first connecting conductive layer 143 can be electrically connected to the second electrode via a through hole in the first spacer layer 131. The first connecting conductive layer 143 is then electrically connected to the conductive bridge 16 via a second through hole 32 in the insulating layer 17, and the conductive bridge 16 is electrically connected to the second conductive layer 142.

[0223] In the third case, referring to Figure 8a, in any step, the surface of the electrode layer 11 facing away from the substrate 10 includes the surface of the step facing away from the substrate 10, so no through-hole is required in the dielectric layer 12; the surface of the electrode layer 11 facing the substrate 10 includes the surface of the step facing the substrate 10. On the second side of the multi-step step, the first spacer layer 131 covers the multi-step step and is used to electrically isolate the second electrode from the first connecting conductive layer 143 on the second side of the multi-step step. The first spacer layer 131 includes a fifth through-hole 35 connecting to the second electrode, and the first connecting conductive layer 143 is electrically connected to the second electrode through the fifth through-hole 35. On the second side of the multi-step step, the second spacer layer 132 is still used to electrically isolate the second electrode from the first conductive layer 141.

[0224] According to this structure, on the first side of the pyramid structure, the first electrode is electrically connected to the first conductive layer 141 via the first through-hole 31 in the second spacer layer 132. On the second side of the pyramid structure, the second electrode is electrically connected to the first connected conductive layer 143 via the fifth through-hole 35 in the first spacer layer 131. The first connected conductive layer 143 is further electrically connected to the conductive bridge 16 via the second through-hole 32 in the insulating layer 17. The conductive bridge 16 is electrically connected to the second conductive layer 142.

[0225] Because the three-dimensional capacitor has a pyramid structure with multiple steps, the depth of each first through-hole 31 along the direction from the substrate 10 to the first spacer layer 13 is the thickness of the same second spacer layer 132, and the depth of each fifth through-hole 35 is the thickness of the same first spacer layer 131. Therefore, the depths of the multiple first through-holes 31 and the multiple fifth through-holes 35 are all the same, thus preventing the electrode layer 11 from being damaged due to the varying depths of the through-holes formed by the same etching process, which would in turn limit the number of layers in the three-dimensional capacitor. Furthermore, there is no need to provide a thicker oxide layer 22 between the first conductive layer 141, the second conductive layer 142, and the second spacer layer 132, and to perform a planarization process on the oxide layer 22, thereby saving manufacturing costs.

[0226] In some embodiments, as shown in FIG8a , the integrated passive device may further include a second interconnecting conductive layer 144. The second interconnecting conductive layer 144 is layered and spaced apart from the first interconnecting conductive layer 143, and both are fabricated using the same semiconductor process. On the first side of the multi-stepped structure, a first spacer layer 131 covers the side of the multi-stepped structure, electrically isolating the second electrode from the second interconnecting conductive layer 144. The second interconnecting conductive layer 144 is electrically connected to the first electrode via a fifth through-hole 35 in the first spacer layer 131. There is at least one first through-hole 31, and the first conductive layer 141 is electrically connected to the second interconnecting conductive layer 144 via the first through-hole 31.

[0227] According to the structure shown in FIG8a , on the first side of the pyramid structure, the multi-layer first electrodes are electrically connected to the second connected conductive layer 1421 via the fifth through-hole 35 in the first spacer layer 131. The second connected conductive layer 1421 is further electrically connected to the first conductive layer 141 via at least one first through-hole 31 in the second spacer layer 132. On the second side of the pyramid structure, the second electrodes are electrically connected to the first connected conductive layer 143 via the fifth through-hole 35 in the first spacer layer 131. The first connected conductive layer 143 is further electrically connected to the conductive bridge 16 via the second through-hole 32 in the insulating layer 17. The conductive bridge 16 is further electrically connected to the second conductive layer 142.

[0228] For the first case, the second case, and the third case, in some embodiments, as shown in Figures 6a-6b, 7a, and 8a, the integrated passive device also includes a third conductive layer 145 arranged between the second spacer layer 132 and the first conductive layer 141, and the third conductive layer 145 is prepared by an atomic layer deposition (ALD) process.

[0229] In some possible implementations, the dielectric layer 12 can be a single layer or a stacked layer structure including materials such as silicon nitride (Si3N4), hafnium dioxide (HfO2), zirconium dioxide (ZrO2), and aluminum oxide (Al2O3), wherein HfO2 and ZrO2 are high dielectric constant (high-K, HK) materials, and the materials of the first spacer layer 131 and the second spacer layer 132 can also include high dielectric constant materials.

[0230] After forming dielectric layer 12 and spacer layer 13, the Hf or Zr elements in the high-k dielectric material diffuse within the tool, contaminating the tool. Subsequent use of the tool for fabricating integrated passive devices will contaminate other layers already formed or to be formed, thereby impacting the performance of the integrated passive device. To address this issue, related techniques require the use of dedicated tools to form films containing high-k dielectric materials, increasing both equipment investment and device fabrication costs.

[0231] In the present application, although the materials of the dielectric layer 12, the first spacer layer 131 and the second spacer layer 132 also include high dielectric constant materials, since the third conductive layer 145 completely covers the dielectric layer 12, the first spacer layer 131 and the second spacer layer 132, the third conductive layer 145 can be used to prevent the Hf element or the Zr element from diffusing into other film layers that have been formed or are to be formed, thereby eliminating the need to use a dedicated machine to form a film layer containing a high dielectric constant material, greatly reducing equipment investment costs and device preparation costs.

[0232] On this basis, since the third conductive layer 145 completely covers the three-dimensional capacitor, when forming the pattern of the first conductive layer 141 and the second conductive layer 142, the third conductive layer 145 can be used to protect the electrode layer 11 of the three-dimensional capacitor. Therefore, after the three-dimensional capacitor is formed and before the third conductive layer 145 is formed, there is no need to form an etching stopper layer 21 on the side of the third conductive layer 145 facing away from the substrate 10.

[0233] In some possible implementations, the first connecting conductive layer 143, the second connecting conductive layer 144, and the third conductive layer 145 may be made of titanium nitride (TiN). The first conductive layer 141 and the second conductive layer 142 may be made of metal, such as Al.

[0234] In addition, as shown in Figures 6c, 7b, and 8b, based on the structures shown in Figures 6a-6b, 7a, and 8a, the integrated passive device may further include a passivation layer 23, a first conductive lead, and a second conductive lead, disposed on the side of the first conductive layer 141 and the second conductive layer 142 facing away from the substrate 10. The first conductive lead and the second conductive lead are disposed on the side of the passivation layer 23 facing away from the substrate 10. The passivation layer 23 may include a sixth through-hole 36 and a seventh through-hole 37. The first conductive lead may be electrically connected to the first conductive layer 141 via the sixth through-hole 36, and the second conductive lead may be electrically connected to the second conductive layer 142 via the seventh through-hole 37. In this way, the first electrode transmits a signal through the first conductive layer 141 and the first conductive lead, and the second electrode transmits a signal through the second conductive layer 142 and the second conductive lead.

[0235] Furthermore, the first conductive layer 141 and the second conductive layer 142 of the embodiment of the present application correspond to the oxide layer 22 of the related art, and both are arranged on the side of the stepped three-dimensional capacitor away from the substrate 10. The first conductive layer 141 and the second conductive layer 142 can be set to a larger thickness so that the first conductive layer 141 and the second conductive layer 142 are close to flat on the side away from the substrate 10, so that the thickness of the passivation layer 23 arranged on the side of the first conductive layer 141 and the second conductive layer 142 away from the substrate 10 is much smaller than the thickness of the oxide layer 22 of the related art. Therefore, even if the sixth through hole 36 and the seventh through hole 37 are also provided in the passivation layer 23, the width-to-depth ratio of the sixth through hole 36 and the seventh through hole 37 is much larger than the width-to-depth ratio of the through hole in the oxide layer 22. For example, the width-to-depth ratio of the through hole in the oxide layer 22 of the related art is about 1:3, and the aperture size of the through hole is about several hundred nanometers; while the width-to-depth ratio of the sixth through hole 36 and the seventh through hole 37 of the present application is about 1:2, and the aperture size of the sixth through hole 36 and the seventh through hole 37 is about tens of nanometers.

[0236] In the related art, in the direction of the interface between the electrode layer 11 and the dielectric layer 12, the size of the through hole of the oxide layer 22 is relatively small (for example, the size of the through hole is 0.18 μm), so that the contact area between the conductive material filling the through hole and the electrode layer 11 in contact with it is relatively small, resulting in a large contact resistance between the two, which affects the electrical properties such as ESL and ESR of the integrated passive device.

[0237] Furthermore, the width-to-depth ratio of each through hole in the oxide layer 22 is relatively large, and the through holes cannot be etched using the same machine as the conductive layer 14. In other words, etching through holes in the oxide layer requires a dedicated machine.

[0238] Compared to related art, the sixth and seventh through-holes 36 and 37 of the present application are larger in size, which can reduce the contact area and contact resistance between the first conductive lead and the first conductive layer 141, and reduce the contact area and contact resistance between the second conductive lead and the second conductive layer 142, thereby improving the electrical performance of the integrated passive device, such as ESL and ESR. Furthermore, due to the increased aspect ratio of the sixth and seventh through-holes 36 and 37, the process for etching the sixth and seventh through-holes 36 and 37 in the passivation layer 23 can share the same machine as the process for forming the first and second conductive layers 141 and 142, thus reducing production costs.

[0239] Third embodiment

[0240] As shown in Figure 9a, an embodiment of the present application provides an integrated passive device comprising a substrate 10, a three-dimensional capacitor, a spacer layer 13 composed of a dielectric material, and a first conductive layer 141 and a second conductive layer 141 spaced apart. The three-dimensional capacitor comprises multiple electrode layers 11 and multiple dielectric layers 12 alternately stacked on the surface of the substrate 10, forming a pyramid structure with multiple steps. In the direction from the substrate 10 toward the three-dimensional capacitor, the multiple electrode layers 11 comprise first and second electrodes that are isolated and alternate with each other. The explanation of the pyramid structure of the third embodiment is the same as that of the first embodiment and will not be repeated here.

[0241] On the first side of the pyramid structure, the spacer layer 13 is used to electrically isolate the second electrode from the first conductive layer 141; the step surface of the multi-step is the surface of the first electrode facing away from the substrate 10, and the first conductive layer 141 is electrically connected to the first electrode at the step surface.

[0242] On the second side of the pyramid structure, the spacer layer 13 is used to electrically isolate the first electrode from the second conductive layer 142; the step surface of the multi-step is the surface of the second electrode facing away from the substrate 10, and the second conductive layer 141 is electrically connected to the second electrode at the step surface.

[0243] In the present application, a three-dimensional capacitor is fabricated into a pyramid structure comprising multiple steps. This allows steps farther from substrate 10 to expose step surfaces closer to substrate 10. On the first side of the pyramid structure, by making the step surfaces of the multiple steps the surface of the first electrode facing away from substrate 10, the second electrode can be electrically isolated from the first conductive layer 141 by simply using a spacer layer 13. This allows the first conductive layer 141 covering the step surfaces on the first side of the pyramid structure to be electrically connected to the first electrode at the step surfaces. On the second side of the pyramid structure, by making the step surfaces of the multiple steps the surface of the second electrode facing away from substrate 10, the first electrode can be electrically isolated from the second conductive layer 142 by simply using a spacer layer 13. This allows the second conductive layer 142 covering the second side of the pyramid structure to be electrically connected to the second electrode at the step surfaces. This eliminates the need to form a thicker oxide layer 22 on the side of the three-dimensional capacitor facing away from substrate 10 and then perform a planarization process on the oxide layer 22, saving manufacturing costs. There is no need to form multiple through holes of varying depths in the oxide layer 22 , and there is no problem of the electrode layer 11 being damaged when etching multiple through holes of varying depths, thereby limiting the number of layers of the three-dimensional capacitor.

[0244] In some possible implementations, on the first side of the pyramid structure, because the stepped surfaces of the multiple steps are the surfaces of the first electrode facing away from the substrate 10, only the side surfaces of the second electrode are exposed. On the second side of the pyramid structure, because the stepped surfaces of the multiple steps are the surfaces of the second electrode facing away from the substrate 10, only the side surfaces of the first electrode are exposed.

[0245] Furthermore, by simply setting the spacer layer 13 on the side of the multiple steps, it can be achieved that on the first side of the pyramid structure, the spacer layer 13 is used to electrically isolate the second electrode from the first conductive layer 141; on the second side of the pyramid structure, the spacer layer 13 is used to electrically isolate the first electrode from the second conductive layer 142.

[0246] For the step farthest from the substrate 10, if the step surface is the surface of the first electrode facing away from the substrate 10, the spacer layer 13 is still on the second side of the pyramid structure, covering the surface of the first electrode facing away from the substrate 10. If the step surface is the surface of the second electrode facing away from the substrate 10, the spacer layer 13 is still on the first side of the pyramid structure, covering the surface of the second electrode facing away from the substrate 10.

[0247] In addition, as shown in FIG9b , the integrated passive device further includes a third conductive layer 146 and a fourth conductive layer 147. The third conductive layer 146 is disposed between the three-dimensional capacitor and the first conductive layer 141, and the fourth conductive layer 147 is disposed between the three-dimensional capacitor and the second conductive layer 142. The third conductive layer 146 and the fourth conductive layer 147 are formed by an ALD process.

[0248] The first conductive layer 141 and the second conductive layer 142 can be prepared, for example, by a physical vapor deposition (PVD) process.

[0249] Because the first conductive layer 141 and the second conductive layer 142 are prepared using processes such as PVD, their coverage is poor, and holes may exist in the film layer, causing defects in the integrated passive device and affecting the service life of the integrated passive device. However, because the ALD process has better coverage, the embodiment of the present application uses the ALD process before forming the first conductive layer 141 and the second conductive layer 142 to form a third conductive layer 146 between the three-dimensional capacitor and the first conductive layer 141, and a fourth conductive layer 147 between the three-dimensional capacitor and the second conductive layer 142, thereby avoiding the above-mentioned defects.

[0250] In some possible implementations, the materials of the first conductive layer 141 and the second conductive layer 142 may include metal, for example, Al or TiN.

[0251] As shown in FIG9c, based on the structures shown in FIG9a and FIG9b, the integrated passive device may further include an etch stop layer 21. The etch stop layer 21 may be disposed on the side of the step furthest from the substrate 10, facing away from the substrate 10, and may include a through hole. The first conductive layer 141 or the second conductive layer 142 contacts the electrode layer 11 through the through hole. When the first conductive layer 141 and the second conductive layer 142 are subsequently patterned, the etch stop layer 21 may be used to protect the electrode layer 11 of the three-dimensional capacitor.

[0252] Furthermore, as shown in FIG9d , based on the structures shown in FIG9a - FIG9c , the integrated passive device may further include a passivation layer 23, a first conductive lead, and a second conductive lead, disposed on the side of the first conductive layer 141 and the second conductive layer 142 facing away from the substrate 10. The first conductive lead and the second conductive lead are disposed on the side of the passivation layer 23 facing away from the substrate 10. The passivation layer 23 may include a first through-hole 31 and a second through-hole 32. The first conductive lead may be electrically connected to the first conductive layer 141 through the first through-hole 31, and the second conductive lead may be electrically connected to the second conductive layer 142 through the second through-hole 32. In this way, the first electrode transmits a signal through the first conductive layer 141 and the first conductive lead, and the second electrode transmits a signal through the second conductive layer 142 and the second conductive lead.

[0253] Furthermore, the first conductive layer 141 and the second conductive layer 142 of the embodiment of the present application correspond to the oxide layer 22 of the related art. Both are disposed on the side of the stepped three-dimensional capacitor facing away from the substrate 10. By setting the first conductive layer 141 and the second conductive layer 142 to a greater thickness, the side of the first conductive layer 141 and the second conductive layer 142 facing away from the substrate 10 is nearly flat, thereby making the thickness of the passivation layer 23 disposed on the side of the first conductive layer 141 and the second conductive layer 142 facing away from the substrate 10 much thinner than the thickness of the oxide layer 22 of the related art. Therefore, even if the passivation layer 23 is provided with a through hole, the aspect ratio of the through hole in the passivation layer 23 is much greater than the aspect ratio of the through hole in the oxide layer 22. For example, the aspect ratio of the through hole in the oxide layer 22 of the related art is approximately 1:3, and the aperture size of the through hole is approximately several hundred nanometers. In contrast, in the present application, the aspect ratio of the first through hole 31 and the second through hole 32 is approximately 1:2, and the aperture size of the first through hole 31 and the second through hole 32 is approximately several tens of nanometers.

[0254] Compared to related technologies, the vias in the passivation layer 23 of the present application are larger in size, which can reduce the contact area and contact resistance between the first conductive lead and the first conductive layer 141, and reduce the contact area and contact resistance between the second conductive lead and the second conductive layer 142, thereby improving the electrical performance of the integrated passive device, such as ESL and ESR. Furthermore, due to the increased aspect ratio of the first and second vias 31, 32, the process for etching the first and second vias 31, 32 in the passivation layer 23 can share the same machine as the process for forming the first and second conductive layers 141, 142.

[0255] The above lists in detail the positional relationships of various structures in integrated passive devices under five different situations. It should be understood that the above five situations are only examples, and the protection scope of the embodiments of the present application is not limited to the above five situations. Any technician familiar with this technical field can easily think of changes or replacements within the technical scope disclosed in this application, which should be covered by the protection scope of this application.

[0256] In addition, in some possible implementations, for any case, the electrode layer 11 can be formed on the substrate 10 first, and then the dielectric layer 12 can be formed; or, the dielectric layer 12 can be formed on the substrate 10 first, and then the electrode layer 11 can be formed.

[0257] In some possible implementations, referring to Figures 3a-3c, for any case, before forming the three-dimensional capacitor, an oxide material 15 can be formed on the substrate 10. The oxide material 15 is arranged between the substrate 10 and the three-dimensional capacitor to prevent the conductive material (such as metal) in the electrode layer 11 from diffusing into the substrate 10.

[0258] Optionally, the material of the electrode layer 11 may include at least one of polysilicon (poly Si), copper (Cu), and TiN.

[0259] In some possible implementations, for any case, as shown in FIG3 a , the substrate 10 may include a receiving groove, and the oxide material 15 and the three-dimensional capacitor may extend from outside the receiving groove into the groove.

[0260] The embodiments of the present application also provide a method for preparing an integrated passive device, which corresponds to the above three embodiments and is implemented through the fourth to sixth embodiments.

[0261] Fourth embodiment

[0262] As shown in FIG10 , the preparation method of the integrated passive device can be implemented by the following steps:

[0263] S110, as shown in FIG3a, forms a three-dimensional capacitor on a substrate 10. The three-dimensional capacitor includes multiple electrode layers 11 and multiple dielectric layers 12 alternately stacked on the surface of the substrate 10, forming a pyramid structure with multiple steps. Along the direction of the substrate 10 toward the three-dimensional capacitor, the multiple electrode layers 11 include first electrodes and second electrodes that are isolated and alternate with each other.

[0264] In a three-dimensional capacitor, a first electrode, a dielectric layer 12, and a second electrode constitute a capacitor. Furthermore, with the exception of the electrode layer 11 closest to the substrate 10 and the electrode layer 11 farthest from the substrate 10, other first electrodes can form a capacitor with either the dielectric layer 12 and the second electrode disposed adjacent to the side facing the substrate 10, or with the dielectric layer 12 and the second electrode disposed adjacent to the side facing away from the substrate 10. Other second electrodes can form a capacitor with either the dielectric layer 12 and the first electrode disposed adjacent to the side facing the substrate 10, or with the dielectric layer 12 and the first electrode disposed adjacent to the side facing away from the substrate 10.

[0265] When the three-dimensional capacitor is in operation, the plurality of first electrodes can transmit signals through the same first conductive layer 141 , and the plurality of second electrodes can transmit signals through the same second conductive layer 142 .

[0266] In some possible implementations, before forming a three-dimensional capacitor on the substrate 10 , a receiving groove may be formed in the substrate 10 . The three-dimensional capacitor may be disposed in the receiving groove of the substrate 10 and extend from inside the receiving groove to outside the receiving groove.

[0267] On this basis, referring to Figures 3a-3c, after forming the receiving groove in the substrate 10 and before forming the three-dimensional capacitor, an insulating oxide material 15 can be formed on the substrate 10. The oxide material 15 is arranged between the substrate 10 and the three-dimensional capacitor to prevent the conductive material (such as metal) in the electrode layer 11 from diffusing into the substrate 10.

[0268] Optionally, the material of the electrode layer 11 may include at least one of poly Si, Cu, and TiN. The dielectric layer 12 may be a single layer or a stacked layer structure including materials such as Si3N4, HfO2, ZrO2, and Al2O3.

[0269] In some possible implementations, for any case, the electrode layer 11 may be formed on the substrate 10 first, and then the dielectric layer 12 may be formed; or, the dielectric layer 12 may be formed on the substrate 10 first, and then the electrode layer 11 may be formed.

[0270] S120, as shown in FIG. 3a to FIG. 3c, a spacer layer 13 made of a dielectric material is formed on the multiple steps.

[0271] S130, a first conductive layer 141 is formed on the step surface on the first side of the pyramid structure, and a second conductive layer 142 is formed on the step surface on the second side of the pyramid structure; on the first side of the pyramid structure, a first through hole 31 connected to the first electrode is opened on the spacer layer 13, and the first conductive layer 141 is electrically connected to the first electrode through the first through hole 31; on the second side of the pyramid structure, a second through hole 32 connected to the second electrode is also opened on the spacer layer 13, and the second conductive layer 142 is electrically connected to the second electrode through the second through hole 32.

[0272] In the present application, a three-dimensional capacitor is fabricated into a pyramid structure comprising multiple steps. This allows the steps farther from the substrate 10 to expose the surface of the steps closer to the substrate 10. On the first side of the pyramid structure, a first through-hole 31 communicating with the first electrode is provided on the spacer layer 13, so that the first conductive layer 141 covering the first side of the pyramid structure is electrically connected to the first electrode via the first through-hole 31, and the second electrode is electrically isolated from the first conductive layer 141 by the spacer layer 13. On the second side of the pyramid structure, a second through-hole 32 communicating with the second electrode is provided on the spacer layer 13, so that the second conductive layer 142 covering the second side of the pyramid structure is electrically connected to the second electrode via the second through-hole 32, and the second electrode is electrically isolated from the second conductive layer 142 by the spacer layer 13. This eliminates the need to form a thicker oxide layer 22 on the side of the three-dimensional capacitor facing away from the substrate 10 and perform a planarization process on the oxide layer 22, thereby saving manufacturing costs. There is no need to form multiple through holes of varying depths in the oxide layer 22 , and there is no problem of the electrode layer 11 being damaged when etching multiple through holes of varying depths, thereby limiting the number of layers of the three-dimensional capacitor.

[0273] In some possible implementations, as shown in FIG3a , a step on the first side of the plurality of steps is disposed opposite a step on the second side of the plurality of steps. Thus, a step on the first side includes a first electrode, and a step on the second side opposite that step also includes a first electrode. A step on the first side includes a second electrode, and a step on the second side opposite that step also includes a second electrode.

[0274] On this basis, the surface of the dielectric layer 12 facing away from the substrate 10 includes a stepped surface, and the surface of the electrode layer 11 facing the substrate 10 includes a surface with steps facing the substrate 10. Alternatively, the surface of the electrode layer 11 facing away from the substrate 10 includes a stepped surface, and the surface of the dielectric layer 12 facing the substrate 10 includes a surface with steps facing the substrate 10. The following describes the preparation processes of several different structures of integrated passive devices in conjunction with the accompanying drawings:

[0275] In the first case, step S110 forms a three-dimensional capacitor on substrate 10, including: alternately forming multiple electrode layers 11 and multiple dielectric layers 12 on substrate 10 to form a first step. At the first step, the surface of dielectric layer 12 facing away from substrate 10 comprises the step surface of the first step, and the surface of electrode layer 11 facing substrate 10 comprises the surface of the first step facing substrate 10. Furthermore, a third through hole 33 is defined in dielectric layer 12, directly opposite first through hole 31 and second through hole 32.

[0276] Specifically, as shown in FIG11a , an insulating oxide material 15 is first formed on substrate 10. As shown in FIG11b , an opening is formed in oxide material 15 , the location of the opening corresponding to the location of the receiving groove to be formed. As shown in FIG11c , substrate 10 is partially etched using oxide material 15 as a hard mask to form the receiving groove in substrate 10.

[0277] Next, as shown in FIG11d , multiple electrode films 111 and multiple dielectric films 121 are alternately formed on the substrate 10. As shown in FIG11e , the multiple electrode films 111 and the multiple dielectric films 121 are sequentially etched using a photolithography process to form the multilayer electrode layers 11 and the multilayer dielectric films 121 of the three-dimensional capacitor. The multilayer electrode layers 11 and the multilayer dielectric films 121 have a pyramid structure with multiple steps. The etched dielectric film 121 in FIG11e does not include the third through hole 31.

[0278] Next, step S120 forms a spacer layer 13 made of a dielectric material on the multi-step steps, including:

[0279] Based on the steps shown in Figure 11e, as shown in Figure 11f, a spacer film 1311 is formed on the side of the three-dimensional capacitor facing away from the substrate 10. Spacer film 1311 completely covers the three-dimensional capacitor and the oxide material 15. As shown in Figure 11g, spacer film 1311 is patterned using a photolithography process to form a spacer layer 13. Spacer layer 13 covers the three-dimensional capacitor and includes a first through-hole 31 and a second through-hole 32. A hole is opened in dielectric layer 12 using a photolithography process to form dielectric layer 12. Dielectric layer 12 includes a third through-hole 33, which is directly opposite to first through-hole 31 and second through-hole 32.

[0280] As shown in Figure 11h, a first conductive film layer 41 is formed on the side of the spacer layer 13 facing away from the substrate 10. The first conductive film layer 41 covers the spacer layer 13 and the oxide material 15. As shown in Figure 3a, the first conductive film layer 41 is patterned using a photolithography process to form a first conductive layer 141 and a second conductive layer 142 spaced apart from each other. The first conductive layer 141 is located on the stepped surface on the first side of the pyramid structure, and the second conductive layer 142 is located on the stepped surface on the second side of the pyramid structure. On the first side of the pyramid structure, the first conductive layer 141 is electrically connected to the first electrode through the first through-hole 31 and the third through-hole 33. On the second side of the pyramid structure, the second conductive layer 142 is electrically connected to the second electrode through the second through-hole 32 and the third through-hole 33.

[0281] Because the three-dimensional capacitor has a multi-step pyramid structure, the depth of each first through-hole 31 and second through-hole 32, along the direction from substrate 10 toward spacer layer 13, is equal to the thickness of the same spacer layer 13, and the depth of each third through-hole 33 is equal to the thickness of one dielectric layer 12. As a result, the depths of the multiple first through-holes 31 and multiple second through-holes 32 are all the same, and the depths of the multiple third through-holes 33 are the same or have a small difference. This prevents the electrode layer 11 from being damaged by the varying depths of the through-holes formed during the same etching process, which would in turn limit the number of layers in the three-dimensional capacitor.

[0282] Furthermore, there is no need to provide a thick oxide layer 22 between the first conductive layer 141 , the second conductive layer 142 and the spacer layer 13 , and the oxide layer 22 can be planarized, thereby saving preparation costs.

[0283] In some embodiments, as shown in FIG3b , after step S110 and before step S120, the method for fabricating an integrated passive device further includes forming an etch stop layer 21 on a first step away from the substrate 10, with the etch stop layer 21 exposed in the gap between the first conductive layer 141 and the second conductive layer 142. This allows the etch stop layer 21 to protect the electrode layer 11 of the three-dimensional capacitor during the subsequent step S130 of etching to form the pattern of the first conductive layer 141 and the second conductive layer 142.

[0284] Here, in order not to affect the electrical connection between the first conductive layer 141 and the electrode layer 11 farthest from the substrate 10 , the etch stop layer 21 may also include a through hole, and the through hole of the etch stop layer 21 is opposite to the first through hole 31 or the second through hole 32 .

[0285] In the second case, as shown in Figure 4a, the multi-step structure, based on the first case, further includes a second step, formed after the first step. At the second step, the surface of electrode layer 11 facing substrate 10 comprises the surface of the second step facing substrate 10, while the surface of the electrode layer facing away from substrate 10 comprises the step surface of the second step. In other words, the second step consists of a portion of electrode layer 11 and does not include dielectric layer 12. Therefore, there is no need to open a through hole in dielectric layer 12 at the second step.

[0286] If the second step is composed of a portion of the first electrode, the first conductive layer 141 is directly electrically connected to the first electrode through the first through-hole 31, and the sidewall of the first electrode on the second side and the step surface are covered by the spacer layer 13, thereby achieving electrical isolation between the second conductive layer 142 and the first electrode.

[0287] As shown in Figure 4a, if the second step is composed of a portion of the second electrode, the second conductive layer 142 is directly electrically connected to the second electrode through the second through hole 32, and the sidewall of the second electrode on the first side and the step surface are covered by the spacer layer 13, thereby achieving electrical isolation between the first conductive layer 141 and the second electrode.

[0288] In some embodiments, as shown in FIG4b , after step S110 and before step S120, the method for fabricating an integrated passive device further includes forming an etch stop layer 21 on a second step away from the substrate 10, with the etch stop layer 21 exposed in the gap between the first conductive layer 141 and the second conductive layer 142. This allows the etch stop layer 21 to protect the electrode layer 11 of the three-dimensional capacitor during the subsequent step S130 of etching to form the pattern of the first conductive layer 141 and the second conductive layer 142.

[0289] Here, in order not to affect the electrical connection between the first conductive layer 141 and the electrode layer 11 farthest from the substrate 10 , the etch stop layer 21 may also include a through hole, and the through hole of the etch stop layer 21 is opposite to the first through hole 31 or the second through hole 32 .

[0290] The third scenario, shown in Figure 5a, differs from the first scenario in that step S110 forms a three-dimensional capacitor on substrate 10, including: alternately forming multiple electrode layers 11 and multiple dielectric layers 12 on substrate 10 to form a three-dimensional capacitor comprising multiple steps. In each step, the surface of electrode layer 11 facing away from substrate 10 comprises the step surface, so there is no need to form a through hole in dielectric layer 13; the surface of dielectric layer 12 facing substrate 10 comprises the surface of the step facing substrate 10. The first conductive layer 141 is electrically connected to the first electrode via a first through hole 31 in spacer layer 131, and the second conductive layer 142 is electrically connected to the second electrode via a second through hole 32 in spacer layer 131.

[0291] The sidewalls and top surface of the first electrode on the second side are covered by the spacer layer 13, thereby electrically isolating the second conductive layer 142 from the first electrode. The sidewalls and top surface of the second electrode on the first side are also covered by the spacer layer 13, thereby electrically isolating the first conductive layer 141 from the second electrode. With the exception of the fabrication process for the three-dimensional capacitor and the spacer layer 13, the fabrication process details for the third case can be found in the first case and are not repeated here.

[0292] Because the three-dimensional capacitor has a multi-step pyramid structure, the depth of each first through-hole 31 and second through-hole 32 along the direction from substrate 10 to spacer layer 13 is the same thickness of the same spacer layer 13. As a result, the depths of the multiple first through-holes 31 and second through-holes 32 are all the same, preventing damage to the electrode layer 11 caused by varying depths of through-holes formed during the same etching process, which would in turn limit the number of layers in the three-dimensional capacitor.

[0293] Furthermore, there is no need to provide a thick oxide layer 22 between the first conductive layer 141 , the second conductive layer 142 and the spacer layer 13 , and the oxide layer 22 can be planarized, thereby saving preparation costs.

[0294] In some embodiments, as shown in FIG5b , after step S110 and before step S120, the method for fabricating an integrated passive device further includes forming an etch stop layer 21 on the surface of the step furthest from the substrate 10, with the etch stop layer 21 exposed in the gap between the first conductive layer 141 and the second conductive layer 142. This allows the etch stop layer 21 to protect the electrode layer 11 of the three-dimensional capacitor during the subsequent step S130 of etching to form the pattern of the first conductive layer 141 and the second conductive layer 142.

[0295] Here, in order not to affect the electrical connection between the first conductive layer 141 and the electrode layer 11 farthest from the substrate 10 , the etch stop layer 21 may also include a through hole.

[0296] In addition, as shown in Figures 3c, 4c, and 5c, based on the first to third cases, after step S130, the method for preparing an integrated passive device may further include forming a passivation layer 23, a first conductive lead, and a second conductive lead on the side of the first conductive layer 141 and the second conductive layer 142 facing away from the substrate 10, wherein the first conductive lead and the second conductive lead are arranged on the side of the passivation layer 23 facing away from the substrate 10. The passivation layer 23 may include a fourth through hole 34 and a fifth through hole 35. The first conductive lead may be electrically connected to the first conductive layer 141 through the fourth through hole 34, and the second conductive lead may be electrically connected to the second conductive layer 142 through the fifth through hole 35. In this way, the first electrode transmits a signal through the first conductive layer 141 and the first conductive lead, and the second electrode transmits a signal through the second conductive layer 142 and the second conductive lead.

[0297] Furthermore, the first conductive layer 141 and the second conductive layer 142 of the embodiment of the present application correspond to the oxide layer 22 of the related art, and both are arranged on the side of the stepped three-dimensional capacitor away from the substrate 10. The first conductive layer 141 and the second conductive layer 142 can be set to a larger thickness so that the first conductive layer 141 and the second conductive layer 142 are close to flat on the side away from the substrate 10, so that the thickness of the passivation layer 23 arranged on the side of the first conductive layer 141 and the second conductive layer 142 away from the substrate 10 is much smaller than the thickness of the oxide layer 22 of the related art. Therefore, even if the fourth through hole 34 and the fifth through hole 35 are also provided in the passivation layer 23, the width-to-depth ratio of the fourth through hole 34 and the fifth through hole 35 is much larger than the width-to-depth ratio of the through hole in the oxide layer 22. For example, the width-to-depth ratio of the through hole in the oxide layer 22 of the related art is about 1:3, and the aperture size of the through hole is about several hundred nanometers; while the width-to-depth ratio of the fourth through hole 34 and the fifth through hole 35 of the present application is about 1:2, and the aperture size of the fourth through hole 34 and the fifth through hole 35 is about tens of nanometers.

[0298] In the related art, in the direction of the interface between the electrode layer 11 and the dielectric layer 12, the size of the through hole of the oxide layer 22 is relatively small (for example, the size of the through hole is 0.18 μm), so that the contact area between the conductive material filling the through hole and the electrode layer 11 in contact with it is relatively small, resulting in a large contact resistance between the two, which affects the electrical properties of the integrated passive device, such as the equivalent series inductance and equivalent series resistance.

[0299] Furthermore, the width-to-depth ratio of each through hole in the oxide layer 22 is relatively large, and the through holes cannot be etched using the same machine as the conductive layer 14. In other words, etching through holes in the oxide layer requires a dedicated machine.

[0300] Compared to related art, the fourth and fifth through-holes 34 and 35 of the present application are larger in size, which can reduce the contact area and contact resistance between the first conductive lead and the first conductive layer 141, and reduce the contact area and contact resistance between the second conductive lead and the second conductive layer 142, thereby improving the electrical performance of the integrated passive device, such as ESL and ESR. Furthermore, due to the increased aspect ratio of the fourth and fifth through-holes 34 and 35, the process for etching the fourth and fifth through-holes 34 and 35 in the passivation layer 23 can share the same machine as the process for forming the first and second conductive layers 141 and 142, thus saving production costs.

[0301] Fifth embodiment

[0302] As shown in FIG12 , the preparation method of the integrated passive device can be implemented by the following steps:

[0303] S210 , as shown in FIG6 a , a conductive bridge 16 and an insulating layer 17 are sequentially formed on the substrate 10 , and a second through hole 32 is opened in the insulating layer 16 .

[0304] S220, forming a three-dimensional capacitor on substrate 10; the three-dimensional capacitor includes multiple electrode layers 11 and multiple dielectric layers 12 alternately stacked on the surface of substrate 10, forming a pyramid structure with multiple steps. In the direction of substrate 10 toward the three-dimensional capacitor, multiple electrode layers 11 include first and second electrodes that are isolated and alternate with each other.

[0305] S230: A first spacer layer 131, a first interconnecting conductive layer 143, and a second spacer layer 132 are sequentially formed on the pyramid structure. The first interconnecting conductive layer 143 is located on the second side of the pyramid structure. On the first side of the pyramid structure, the second spacer layer 132 is provided with a first through hole 31 that is connected to the first electrode. On the second side of the pyramid structure, the first spacer layer 131 is used to electrically isolate the first electrode from the first interconnecting conductive layer 143, and the first interconnecting conductive layer 143 is electrically connected to the second electrode.

[0306] S240: Form a first conductive layer 141 and a second conductive layer 142. On the first side of the pyramid structure, the first conductive layer 141 is electrically connected to the first electrode via the first through-hole 31. On the second side of the pyramid structure, the insulating layer 17 is used to electrically isolate the first conductive layer 141 from the conductive bridge 16. The conductive bridge 16 is electrically connected to the first connecting conductive layer 143 via the second through-hole 32 defined in the insulating layer 17. The conductive bridge 16 extends outward from the pyramid structure and is electrically connected to the second conductive layer 142 outside the pyramid structure.

[0307] In the present application, a three-dimensional capacitor is fabricated into a pyramid structure comprising multiple steps, so that the steps farther from the substrate 10 can expose the surface of the steps closer to the substrate 10. On the first side of the pyramid structure: a first through hole 31 connected to the first electrode is provided on the second spacer layer 132, so that the first conductive layer 141 covering the pyramid structure is electrically connected to the first electrode through the first through hole 31. By arranging the second spacer layer 132 between the pyramid structure and the first conductive layer 141, the second spacer layer 132 can be used to electrically isolate the second electrode from the first conductive layer 141. On the second side of the pyramid structure: a first connecting conductive layer 143 is covered on the pyramid structure, so that the first connecting conductive layer 143 is electrically connected to the second conductive layer 142 on the second side of the pyramid structure; and the first connecting conductive layer 143 is electrically connected to the second conductive layer 142 disposed outside the pyramid structure through a conductive bridge 16. On this basis, on the second side of the pyramid structure: by arranging the first spacer layer 131 between the pyramid structure and the first connected conductive layer 143, the first spacer layer 131 can be used to electrically isolate the first connected conductive layer 143 from the first electrode. By arranging the second spacer layer 132 between the first conductive layer 141 and the first connected conductive layer 143, the second spacer layer 132 can be used to electrically isolate the first conductive layer 141 from the first connected conductive layer 143. There is no need to form a thicker oxide layer 22 on the side of the three-dimensional capacitor away from the substrate 10 as provided in the related art, and to flatten the oxide layer 22, thereby saving preparation costs. There is also no need to form multiple through holes of varying depths in the oxide layer 22, and thus there is no problem of the electrode layer 11 being damaged when etching multiple through holes of varying depths, thereby limiting the number of layers of the three-dimensional capacitor.

[0308] In some possible implementations, as shown in FIG6a , a step on the first side of the plurality of steps is disposed opposite a step on the second side of the plurality of steps. Thus, a step on the first side includes a first electrode, and a step on the second side opposite that step also includes a first electrode. A step on the first side includes a second electrode, and a step on the second side opposite that step also includes a second electrode.

[0309] On this basis, the surface of the dielectric layer 12 facing away from the substrate 10 includes a stepped surface, and the surface of the electrode layer 11 facing the substrate 10 includes a surface with steps facing the substrate 10. Alternatively, the surface of the electrode layer 11 facing away from the substrate 10 includes a stepped surface, and the surface of the dielectric layer 12 facing the substrate 10 includes a surface with steps facing the substrate 10. The following describes several different methods for preparing integrated passive devices with different structures in conjunction with the accompanying drawings:

[0310] In the first case, the multiple steps include a first step. At the first step, the surface of the dielectric layer 12 facing away from the substrate 10 includes the surface of the first step facing away from the substrate 10, and the surface of the electrode layer 11 facing the substrate 10 includes the surface of the first step facing the substrate 10. On the first side of the first step, the dielectric layer 12 includes a third through-hole 33 connected to the first electrode. The first conductive layer 1422 is electrically connected to the first electrode through the third through-hole 33 and the first through-hole 31. By disposing the second spacer layer 132 between the pyramid structure and the first conductive layer 141, the second spacer layer 132 can be used to electrically isolate the second electrode from the first conductive layer 141.

[0311] On the second side of the first step, the dielectric layer 12 includes a fourth through-hole 34 connected to the second electrode. The first connected conductive layer 143 is electrically connected to the second electrode via the fourth through-hole 34. By disposing a first spacer layer 131 on the side of the first step, the first connected conductive layer 143 can be electrically isolated from the first electrode by the first spacer layer 131. By disposing a second spacer layer 132 between the first conductive layer 141 and the first connected conductive layer 143, the first conductive layer 141 and the first connected conductive layer 143 can be electrically isolated by the second spacer layer 132.

[0312] Because the three-dimensional capacitor has a pyramid structure with multiple steps, the depth of each first through hole 31 along the direction of the substrate 10 pointing to the first spacer layer 13 is the thickness of the same second spacer layer 132, and the depth of each third through hole 33 and each fourth through hole 34 is the thickness of a dielectric layer 12. Therefore, the depths of the multiple first through holes 31 are the same, and the depths of the multiple third through holes 33 and the multiple fourth through holes 34 are the same or have little difference. This prevents the electrode layer 11 from being damaged due to the different depths of the through holes formed by the same etching process, which in turn leads to the problem of limiting the number of layers of the three-dimensional capacitor. In addition, there is no need to set a thick oxide layer 22 between the first conductive layer 141 and the second conductive layer 142 and the second spacer layer 132, and the oxide layer 22 does not need to be flattened, which can save manufacturing costs.

[0313] Specifically, as shown in FIG13a , an insulating oxide material 15 is first formed on the substrate 10; as shown in FIG13b , a conductive bridge 16 is formed on the side of the oxide material 15 facing away from the substrate 10; as shown in FIG13c , an insulating film 171 is formed on the side of the conductive bridge 16 facing away from the substrate 10, and the insulating film 171 does not yet include the fourth through hole 34; as shown in FIG13d , an oxide material 15 is formed on the side of the insulating film 171 facing away from the substrate 10, and the oxide material 15 can serve as a hard mask for forming a receiving groove in the substrate 10; as shown in FIG13e , a photolithography process is used to open the two layers of oxide material 15 and the insulating film 171, and the opening position corresponds to the position of the receiving groove to be formed; as shown in FIG13f , a receiving groove is formed in the substrate 10 under the protection of the hard mask; as shown in FIG13g , the oxide material 15 serving as the hard mask is removed; as shown in FIG13h , the receiving groove is filled with the oxide material 15 to prevent the conductive material (e.g., metal) in the electrode layer 11 to be formed from diffusing into the substrate 10.

[0314] Next, a three-dimensional capacitor is formed on the substrate, including: alternatingly forming multiple electrode layers 11 and multiple dielectric layers 12 on the substrate 10; the surface of the dielectric layer 12 facing away from the substrate 10 comprises a stepped surface, and the surface of the electrode layer 11 facing the substrate 10 comprises a surface with the stepped surface facing the substrate 10. Specifically, on the first side of the first step, the dielectric layer 12 includes a third through-hole 33 connected to the first electrode, and the first conductive layer 141 is electrically connected to the first electrode through the third through-hole 33 and the first through-hole 31. On the second side of the first step, the first spacer layer 131 is located on the side of the first step, and the dielectric layer 12 includes a fourth through-hole 34 connected to the second electrode. The first conductive layer 143 is electrically connected to the second electrode through the fourth through-hole 34.

[0315] Specifically, as shown in FIG13i , multiple electrode films 111 and multiple dielectric films 121 are alternately formed on a substrate 10. As shown in FIG13j , the multiple electrode films 111 and the multiple dielectric films 121 are sequentially etched using a photolithography process to form the multi-layer electrode layers 11 and the multi-layer dielectric films 121 of the three-dimensional capacitor. The multi-layer electrode layers 11 and the multi-layer dielectric films 121 form a pyramid structure with multiple steps. The etched dielectric film 121 in FIG13j does not include the third through hole 33 and the fourth through hole 34.

[0316] Next, a spacer layer 13 is formed on the side of the three-dimensional capacitor facing away from the substrate 10 , including: forming a first spacer layer 131 on the second side of the first step, wherein the first spacer layer 131 is located on the side of the first step.

[0317] Specifically, as shown in FIG13k, a first spacer film 1312 is formed on the side of the three-dimensional capacitor away from the substrate 10; as shown in FIG13l, the first spacer film 1312 is etched by a photolithography process to obtain a first spacer layer 131, which is located on the side of the first step.

[0318] As shown in FIG13m, after forming the first spacer layer 131, the dielectric film 121 is opened by a photolithography process to form the third through hole 33 and the fourth through hole 34; the insulating film 171 is opened by a photolithography process to form the second through hole 32.

[0319] 6 a and 13 n , a first connecting conductive layer 143 covering the step surface is formed on the second side of the pyramid structure. The first connecting conductive layer 143 is electrically connected to the second electrode through the fourth through hole 34 in the dielectric layer 12 .

[0320] In some possible implementations, as shown in FIG13n , while forming the first connecting conductive layer 143 on the pyramid structure, the method for fabricating an integrated passive device further includes forming a second connecting conductive layer 144 on the second side of the pyramid structure. The second connecting conductive layer 144 is co-layered with and spaced apart from the first connecting conductive layer 143. On the first side of the first step, a first spacer layer 131 is located on the side of the first step to electrically isolate the second electrode from the second connecting conductive layer 144. The second connecting conductive layer 144 is electrically connected to the first electrode via the third through hole 33 in the dielectric layer 12.

[0321] As shown in Figure 13o, a second spacer layer 132 is formed on the side of the first connected conductive layer 143 (or the first connected conductive layer and the second connected conductive layer) facing away from the substrate 10, the second spacer layer 132 includes at least one third through hole 33, and the second spacer layer covers the first connected conductive layer 143 (or the first connected conductive layer and the second connected conductive layer), and the three-dimensional capacitor.

[0322] As shown in Figure 13q, a second conductive film layer 42 is formed on the side of the second spacer layer 132 facing away from the substrate 10. As shown in Figure 6a, the second conductive film layer 42 is etched using a photolithography process to form a spaced first conductive layer 141 and a second conductive layer 142. On the first side of the first step, the first conductive layer 141 is electrically connected to the first electrode through the third through-hole 33 and the first through-hole 31. On the second side of the first step, the first connecting conductive layer 143 is electrically connected to the second electrode through the fourth through-hole 34 in the dielectric layer 12, and then electrically connected to the conductive bridge 16 through the second through-hole 32 in the insulating layer 17. The conductive bridge 16 extends outward and is electrically connected to the second conductive layer 142.

[0323] In some possible implementations, as shown in Figure 13p, after the step shown in Figure 13o and before the step shown in Figure 13q, the method for preparing an integrated passive device may further include: using an ALD process to form a third conductive layer 145 on the side of the second spacer layer 132 facing away from the substrate 10.

[0324] The dielectric layer 12 may be a single layer or a stacked layer structure including materials such as Si3N4, HfO2, ZrO2, Al2O3, etc., wherein HfO2 and ZrO2 are high dielectric constant materials, and the materials of the first spacer layer 131 and the second spacer layer 132 may also include high dielectric constant materials.

[0325] After forming dielectric layer 12 and spacer layer 13, the Hf or Zr elements in the high-k dielectric material diffuse within the tool, contaminating the tool. Subsequent use of the tool for fabricating integrated passive devices will contaminate other layers already formed or to be formed, thereby impacting the performance of the integrated passive device. To address this issue, related techniques require the use of dedicated tools to form films containing high-k dielectric materials, increasing both equipment investment and device fabrication costs.

[0326] In the present application, although the materials of the dielectric layer 12, the first spacer layer 131 and the second spacer layer 132 also include high dielectric constant materials, since the third conductive layer 145 completely covers the dielectric layer 12, the first spacer layer 131 and the second spacer layer 132, the third conductive layer 145 can be used to prevent the Hf element or the Zr element from diffusing into other film layers that have been formed or are to be formed, thereby eliminating the need to use a dedicated machine to form a film layer containing a high dielectric constant material, greatly reducing equipment investment costs and device preparation costs.

[0327] On this basis, since the third conductive layer 145 completely covers the three-dimensional capacitor, when forming the pattern of the first conductive layer 141 and the second conductive layer 142, the third conductive layer 145 can be used to protect the electrode layer 11 of the three-dimensional capacitor. Therefore, after the three-dimensional capacitor is formed and before the third conductive layer 145 is formed, there is no need to form an etching stopper layer 21 on the side of the third conductive layer 145 facing away from the substrate 10.

[0328] In the second case, as shown in Figure 7a, the multi-step structure, based on the first case, further includes a second step, formed after the first step. At the second step, the surface of electrode layer 11 facing substrate 10 comprises the surface of the second step facing substrate 10, while the surface of electrode layer 11 facing away from substrate 10 comprises the step surface of the second step. In other words, the second step consists of a portion of electrode layer 11 and does not include dielectric layer 12. Therefore, there is no need to open a through hole in dielectric layer 12 at the second step.

[0329] If the electrode layer 11 of the second step is the first electrode, then on the first side of the second step, the first conductive layer 141 is electrically connected to the first electrode via the first through-hole 31 in the second spacer layer 132. Alternatively, the first conductive layer 141 is electrically connected to the second connected conductive layer 144 via the first through-hole 31 in the second spacer layer 132, and the second connected conductive layer 144 is directly electrically connected to the first electrode. Of course, the first spacer layer 131 can also extend from the sidewall of the second step to the surface of the second step. In this way, the second connected conductive layer 144 can be electrically connected to the first electrode via the through-hole in the first spacer layer 131.

[0330] As shown in FIG7a , if the electrode layer 11 of the second step is a second electrode, then on the second side of the second step, the second electrode is directly electrically connected to the first connecting conductive layer 143. Alternatively, the first spacer layer 131 may extend from the sidewall of the second step to the surface of the second step. In this way, the first connecting conductive layer 143 can be electrically connected to the second electrode via a through hole in the first spacer layer 131. The first connecting conductive layer 143 is then electrically connected to the conductive bridge 16 via a second through hole 32 in the insulating layer 17, and the conductive bridge 16 is electrically connected to the second conductive layer 142.

[0331] Except that a second step is formed on the basis of the first case, the preparation process of the second case is basically the same as that of the first case, and will not be described again here.

[0332] In the third embodiment, referring to FIG8a , a three-dimensional capacitor is formed on a substrate, including forming the three-dimensional capacitor on the substrate with multiple steps. In any step, the surface of the electrode layer 11 facing away from the substrate 10 comprises the surface of the step facing away from the substrate 10, so no through-hole is required in the dielectric layer 12; and the surface of the electrode layer 11 facing the substrate 10 comprises the surface of the step facing the substrate 10.

[0333] Forming a first spacer layer 131 on the pyramid structure includes forming the first spacer layer 131 on the second side of the multi-step step, covering the multi-step step. The first spacer layer 131 includes a fifth through-hole 35 connected to the second electrode, and the first conductive layer 143 is electrically connected to the second electrode via the fifth through-hole 35. The process details for the third embodiment, except for the fabrication process of the three-dimensional capacitor and the first spacer layer 131, can be referred to as those for the first embodiment and are not repeated here.

[0334] According to this structure, on the first side of the pyramid structure, the first electrode is electrically connected to the first conductive layer 141 via the first through-hole 31 in the second spacer layer 132. On the second side of the pyramid structure, the second electrode is electrically connected to the first connected conductive layer 143 via the fifth through-hole 35 in the first spacer layer 131. The first connected conductive layer 143 is further electrically connected to the conductive bridge 16 via the second through-hole 32 in the insulating layer 17. The conductive bridge 16 is electrically connected to the second conductive layer 142.

[0335] Because the three-dimensional capacitor has a pyramid structure with multiple steps, the depth of each first through-hole 31 along the direction from the substrate 10 to the first spacer layer 13 is the thickness of the same second spacer layer 132, and the depth of each fifth through-hole 35 is the thickness of the same first spacer layer 131. Therefore, the depths of the multiple first through-holes 31 and the multiple fifth through-holes 35 are all the same, thus preventing the electrode layer 11 from being damaged due to the varying depths of the through-holes formed by the same etching process, which would in turn limit the number of layers in the three-dimensional capacitor. Furthermore, there is no need to provide a thicker oxide layer 22 between the first conductive layer 141, the second conductive layer 142, and the second spacer layer 132, and to perform a planarization process on the oxide layer 22, thereby saving manufacturing costs.

[0336] In some embodiments, as shown in Figure 8a, the integrated passive device may further include a second connecting conductive layer 144, which is fabricated using the same semiconductor process as the first connecting conductive layer 143. On the first side of the multi-stepped structure, a first spacer layer 131 covers the side of the multi-stepped structure, electrically isolating the second electrode from the second connecting conductive layer 144. The second connecting conductive layer 144 is electrically connected to the first electrode via a fifth through-hole 35 in the first spacer layer 131. There is at least one first through-hole, and the first conductive layer 141 is electrically connected to the second connecting conductive layer 144 via the first through-hole 31.

[0337] According to the structure shown in FIG8a , on the first side of the pyramid structure, the multi-layer first electrodes are electrically connected to the second connected conductive layer 1421 via the fifth through-hole 35 in the first spacer layer 131. The second connected conductive layer 1421 is further electrically connected to the first conductive layer 141 via at least one first through-hole 31 in the second spacer layer 132. On the second side of the pyramid structure, the second electrodes are electrically connected to the first connected conductive layer 143 via the fifth through-hole 35 in the first spacer layer 131. The first connected conductive layer 143 is further electrically connected to the conductive bridge 16 via the second through-hole 32 in the insulating layer 17. The conductive bridge 16 is further electrically connected to the second conductive layer 142.

[0338] In addition, as shown in Figures 6c, 7b, and 8b, after forming the first conductive layer 141 and the second conductive layer 142, the method for preparing an integrated passive device may further include: providing a passivation layer 23, a first conductive lead, and a second conductive lead on the side of the first conductive layer 141 and the second conductive layer 142 facing away from the substrate 10, wherein the first conductive lead and the second conductive lead are provided on the side of the passivation layer 23 facing away from the substrate 10. The passivation layer 23 may include a sixth through hole 36 and a seventh through hole 37. The first conductive lead may be electrically connected to the first conductive layer 141 through the sixth through hole 36, and the second conductive lead may be electrically connected to the second conductive layer 142 through the seventh through hole 37. In this way, the first electrode transmits a signal through the first conductive layer 141 and the first conductive lead, and the second electrode transmits a signal through the second conductive layer 142 and the second conductive lead.

[0339] Furthermore, the first conductive layer 141 and the second conductive layer 142 of the embodiment of the present application correspond to the oxide layer 22 of the related art, and both are arranged on the side of the stepped three-dimensional capacitor away from the substrate 10. The first conductive layer 141 and the second conductive layer 142 can be set to a larger thickness so that the first conductive layer 141 and the second conductive layer 142 are close to flat on the side away from the substrate 10, so that the thickness of the passivation layer 23 arranged on the side of the first conductive layer 141 and the second conductive layer 142 away from the substrate 10 is much smaller than the thickness of the oxide layer 22 of the related art. Therefore, even if the sixth through hole 36 and the seventh through hole 37 are also provided in the passivation layer 23, the width-to-depth ratio of the sixth through hole 36 and the seventh through hole 37 is much larger than the width-to-depth ratio of the through hole in the oxide layer 22. For example, the width-to-depth ratio of the through hole in the oxide layer 22 of the related art is about 1:3, and the aperture size of the through hole is about several hundred nanometers; while the width-to-depth ratio of the sixth through hole 36 and the seventh through hole 37 of the present application is about 1:2, and the aperture size of the sixth through hole 36 and the seventh through hole 37 is about tens of nanometers.

[0340] In the related art, in the direction of the interface between the electrode layer 11 and the dielectric layer 12, the size of the through hole of the oxide layer 22 is relatively small (for example, the size of the through hole is 0.18 μm), so that the contact area between the conductive material filling the through hole and the electrode layer 11 in contact with it is relatively small, resulting in a large contact resistance between the two, which affects the electrical properties of the integrated passive device, such as the equivalent series inductance and equivalent series resistance.

[0341] Furthermore, the width-to-depth ratio of each through hole in the oxide layer 22 is relatively large, and the through holes cannot be etched using the same machine as the conductive layer 14. In other words, etching through holes in the oxide layer requires a dedicated machine.

[0342] Compared to related art, the sixth and seventh through-holes 36 and 37 of the present application are larger in size, which can reduce the contact area and contact resistance between the first conductive lead and the first conductive layer 141, and reduce the contact area and contact resistance between the second conductive lead and the second conductive layer 142, thereby improving the electrical performance of the integrated passive device, such as ESL and ESR. Furthermore, due to the increased aspect ratio of the sixth and seventh through-holes 36 and 37, the process for etching the sixth and seventh through-holes 36 and 37 in the passivation layer 23 can share the same machine as the process for forming the first and second conductive layers 141 and 142, thus reducing production costs.

[0343] Sixth embodiment

[0344] As shown in FIG14 , the preparation method of the integrated passive device can be implemented by the following steps:

[0345] S310, as shown in FIG9a, forms a three-dimensional capacitor on a substrate 10. The three-dimensional capacitor includes multiple electrode layers 11 and multiple dielectric layers 12 alternately stacked on the surface of the substrate 10, forming a pyramid structure with multiple steps. Along the direction of the substrate 10 toward the three-dimensional capacitor, the multiple electrode layers 11 include first electrodes and second electrodes that are isolated and alternate with each other.

[0346] S320 , forming a spacer layer 13 made of a dielectric material on the pyramid structure.

[0347] S330: Form a first conductive layer 141 on the stepped surface on the first side of the pyramid structure, and form a second conductive layer 142 on the stepped surface on the second side of the pyramid structure. On the first side of the pyramid structure, the spacer layer 13 is used to electrically isolate the second electrode from the first conductive layer 141. The stepped surface of the multiple steps is the surface of the first electrode facing away from the substrate 10, and the first conductive layer 141 is electrically connected to the first electrode at the stepped surface. On the second side of the pyramid structure, the spacer layer 13 is used to electrically isolate the first electrode from the second conductive layer 142. The stepped surface of the multiple steps is the surface of the second electrode facing away from the substrate 10, and the second conductive layer 142 is electrically connected to the second electrode at the stepped surface.

[0348] In the present application, a three-dimensional capacitor is fabricated into a pyramid structure comprising multiple steps. This allows steps farther from substrate 10 to expose step surfaces closer to substrate 10. On the first side of the pyramid structure, by making the step surfaces of the multiple steps the surface of the first electrode facing away from substrate 10, the second electrode can be electrically isolated from the first conductive layer 141 by simply using a spacer layer 13. This allows the first conductive layer 141 covering the step surfaces on the first side of the pyramid structure to be electrically connected to the first electrode at the step surfaces. On the second side of the pyramid structure, by making the step surfaces of the multiple steps the surface of the second electrode facing away from substrate 10, the first electrode can be electrically isolated from the second conductive layer 142 by simply using a spacer layer 13. This allows the second conductive layer 142 covering the second side of the pyramid structure to be electrically connected to the second electrode at the step surfaces. This eliminates the need to form a thicker oxide layer 22 on the side of the three-dimensional capacitor facing away from substrate 10 and then perform a planarization process on the oxide layer 22, saving manufacturing costs. There is no need to form multiple through holes of varying depths in the oxide layer 22 , and there is no problem of the electrode layer 11 being damaged when etching multiple through holes of varying depths, thereby limiting the number of layers of the three-dimensional capacitor.

[0349] In some possible implementations, on the first side of the pyramid structure, because the stepped surfaces of the multiple steps are the surfaces of the first electrode facing away from the substrate 10, only the side surfaces of the second electrode are exposed. On the second side of the pyramid structure, because the stepped surfaces of the multiple steps are the surfaces of the second electrode facing away from the substrate 10, only the side surfaces of the first electrode are exposed.

[0350] Furthermore, by simply setting the spacer layer 13 on the side of the multiple steps, it can be achieved that on the first side of the pyramid structure, the spacer layer 13 is used to electrically isolate the second electrode from the first conductive layer 141; on the second side of the pyramid structure, the spacer layer 13 is used to electrically isolate the first electrode from the second conductive layer 142.

[0351] For the step farthest from the substrate 10, if the step surface is the surface of the first electrode facing away from the substrate 10, the spacer layer 13 is still on the second side of the pyramid structure, covering the surface of the first electrode facing away from the substrate 10. If the step surface is the surface of the second electrode facing away from the substrate 10, the spacer layer 13 is still on the first side of the pyramid structure, covering the surface of the second electrode facing away from the substrate 10.

[0352] Specifically, the preparation method of the integrated passive device includes the following steps:

[0353] As shown in Figure 11a, an insulating oxide material 15 is first formed on substrate 10. As shown in Figure 11b, an opening is formed in oxide material 15, the location of the opening corresponding to the location of the groove to be formed. As shown in Figure 11c, using oxide material 15 as a hard mask, substrate 10 is partially etched to form a receiving groove in substrate 10.

[0354] Next, as shown in FIG11d, a plurality of electrode films 111 and a plurality of dielectric films 121 are alternately formed on the substrate 10; as shown in FIG15b, the plurality of electrode films 111 and the plurality of dielectric films 121 are sequentially etched by photolithography to obtain a multi-layer electrode layer 11 and a multi-layer dielectric layer 12 alternately arranged, forming a pyramid structure including multiple steps.

[0355] In some possible implementations, as shown in Figure 15a, after the step shown in Figure 11d and before the step shown in Figure 15b, the method for preparing an integrated passive device may further include: forming an etching stopper film 211 on the side of the multiple electrode films 111 and the multiple dielectric films 121 facing away from the substrate 10, the etching stopper film 211 covering the multiple electrode films 111 and the multiple dielectric films 121; then, patterning the etching stopper film 211, the patterned etching stopper film 211 covering the surface of the electrode layer 11 farthest from the substrate 10.

[0356] Next, as shown in Figure 15c, a second spacer film 1313 is formed on the side of the three-dimensional capacitor and the etch stop film 211 facing away from the substrate 10. The second spacer film 1313 covers the three-dimensional capacitor. As shown in Figure 15d, the second spacer film 1313 is etched using a photolithography process to form a spacer layer 13. The spacer layer 13 is located on the side of the multi-step and covers the step surface farthest from the substrate 10.

[0357] As shown in FIG15f, a PVD process is used to form a conductive layer 14 on the side of the spacer layer 12 facing away from the substrate 10. As shown in FIG9a, a photolithography process is used to etch the conductive layer 14 to obtain a first conductive layer 141 and a second conductive layer 142 spaced apart from each other. The first conductive layer 141 is located on the first side of the pyramid structure, and the second conductive layer 142 is located on the second side of the pyramid structure.

[0358] In some possible implementations, if the integrated passive device further includes an etch stop film 211 as shown in Figures 15a and 15b, then as shown in Figure 15e, before the step shown in Figure 15f, a through hole may be formed in the etch stop film 211 to form an etch stop layer 21. The through hole in the etch stop layer 21 corresponds to the step surface of the step farthest from the substrate 10. In this way, the etch stop layer 21 can be used to protect the electrode layer 11 of the three-dimensional capacitor during the process of etching the conductive layer 14 to form the first conductive layer 141 and the second conductive layer 142.

[0359] In some embodiments, as shown in FIG9b , before forming the conductive layer 14 shown in FIG15f , the method for preparing an integrated passive device may further include: forming a third conductive layer 146 on the first side of the pyramid structure and forming a fourth conductive layer 147 on the second side of the pyramid structure using an ALD process.

[0360] Because the first conductive layer 141 and the second conductive layer 142 are prepared using processes such as PVD, their coverage is poor, and holes may exist in the film layer, causing defects in the integrated passive device and affecting the service life of the integrated passive device. However, because the ALD process has better coverage, the embodiment of the present application uses the ALD process before forming the first conductive layer 141 and the second conductive layer 142 to form a third conductive layer 146 between the three-dimensional capacitor and the first conductive layer 141, and a fourth conductive layer 147 between the three-dimensional capacitor and the second conductive layer 142, thereby avoiding the above-mentioned defects.

[0361] In some possible implementations, the materials of the first conductive layer 141 and the second conductive layer 142 may include metal, for example, Al or TiN.

[0362] Furthermore, as shown in FIG9 d , after forming the first conductive layer 141 and the second conductive layer 142, the method for preparing an integrated passive device may further include: providing a passivation layer 23, a first conductive lead, and a second conductive lead on the side of the first conductive layer 141 and the second conductive layer 142 facing away from the substrate 10, wherein the first conductive lead and the second conductive lead are provided on the side of the passivation layer 23 facing away from the substrate 10. The passivation layer 23 may include a first through-hole 31 and a second through-hole 32. The first conductive lead may be electrically connected to the first conductive layer 141 through the first through-hole 31, and the second conductive lead may be electrically connected to the second conductive layer 142 through the second through-hole 32. In this way, the first electrode transmits a signal through the first conductive layer 141 and the first conductive lead, and the second electrode transmits a signal through the second conductive layer 142 and the second conductive lead.

[0363] Furthermore, the first conductive layer 141 and the second conductive layer 142 of the embodiment of the present application correspond to the oxide layer 22 of the related art. Both are disposed on the side of the stepped three-dimensional capacitor facing away from the substrate 10. By setting the first conductive layer 141 and the second conductive layer 142 to a greater thickness, the side of the first conductive layer 141 and the second conductive layer 142 facing away from the substrate 10 is nearly flat, thereby making the thickness of the passivation layer 23 disposed on the side of the first conductive layer 141 and the second conductive layer 142 facing away from the substrate 10 much thinner than the thickness of the oxide layer 22 of the related art. Therefore, even if the passivation layer 23 is provided with a through hole, the aspect ratio of the through hole in the passivation layer 23 is much greater than the aspect ratio of the through hole in the oxide layer 22. For example, the aspect ratio of the through hole in the oxide layer 22 of the related art is approximately 1:3, and the aperture size of the through hole is approximately several hundred nanometers. In contrast, in the present application, the aspect ratio of the first through hole 31 and the second through hole 32 is approximately 1:2, and the aperture size of the first through hole 31 and the second through hole 32 is approximately several tens of nanometers.

[0364] Compared to related technologies, the vias in the passivation layer 23 of the present application are larger in size, which can reduce the contact area and contact resistance between the first conductive lead and the first conductive layer 141, and reduce the contact area and contact resistance between the second conductive lead and the second conductive layer 142, thereby improving the electrical performance of the integrated passive device, such as ESL and ESR. Furthermore, due to the increased aspect ratio of the first and second vias 31, 32, the process for etching the first and second vias 31, 32 in the passivation layer 23 can share the same machine as the process for forming the first and second conductive layers 141, 142.

[0365] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. An integrated passive device, characterized in that: The invention comprises a substrate, a three-dimensional capacitor, a spacer layer, and a first conductive layer and a second conductive layer which are spaced apart from each other; The three-dimensional capacitor comprises a plurality of electrode layers and a plurality of dielectric layers alternately stacked on the surface of the substrate to form a pyramid structure with a plurality of steps; along the direction of the substrate pointing toward the three-dimensional capacitor, the plurality of electrode layers comprises first electrodes and second electrodes that are isolated from each other and alternate; the plurality of steps are covered by the spacer layer composed of a dielectric material; The first side step surface of the pyramid structure is covered with the first conductive layer, the spacer layer is provided with a first through hole connected to the first electrode, and the first conductive layer is electrically connected to the first electrode through the first through hole; The second side step surface of the pyramid structure is covered with the second conductive layer, and the spacer layer is further provided with a second through hole connected to the second electrode, and the second conductive layer is electrically connected to the second electrode through the second through hole.

2. The integrated passive device according to claim 1, characterized in that: The step located at the first side among the multiple steps is arranged opposite to the step located at the second side among the multiple steps.

3. The integrated passive device according to claim 2, characterized in that: The multiple steps include a first step, a surface of the dielectric layer facing away from the substrate includes the step surface of the first step, and a surface of the electrode layer facing the substrate includes a surface of the first step facing the substrate; At the first step, a third through hole is opened on the dielectric layer, and the third through hole is arranged opposite to the first through hole and the second through hole; the first conductive layer is electrically connected to the first electrode through the third through hole and the first through hole, and the second conductive layer is electrically connected to the second electrode through the third through hole and the second through hole.

4. The integrated passive device according to claim 3, characterized in that: The multiple steps further include a second step, and the first step is arranged between the substrate and the second step; At the second step, a surface of one of the electrode layers facing the substrate includes a surface of the second step facing the substrate, and a surface of the electrode layer facing away from the substrate includes the step surface of the second step.

5. The integrated passive device according to claim 2, characterized in that: A surface of the electrode layer facing away from the substrate includes the step surface, and a surface of the dielectric layer facing the substrate includes a surface of the step facing the substrate.

6. The integrated passive device according to any one of claims 1 to 5, characterized in that: The integrated passive device further includes a passivation layer, wherein the passivation layer covers the first conductive layer, the second conductive layer, and the three-dimensional capacitor; The passivation layer is provided with a fourth through hole communicating with the first conductive layer and a fifth through hole communicating with the second conductive layer.

7. The integrated passive device according to any one of claims 1 to 6, characterized in that: The integrated passive device further comprises an etch stop layer, wherein the etch stop layer is arranged between a step away from the substrate and the spacer layer; The etch stop layer is exposed through a gap between the first conductive layer and the second conductive layer.

8. An integrated passive device, characterized in that: include: substrate; A three-dimensional capacitor, comprising multiple electrode layers and multiple dielectric layers alternately stacked on the surface of the substrate to form a pyramid structure with multiple steps; Along the direction from the substrate to the three-dimensional capacitor, the multi-layer electrode layer 11 includes first electrodes and second electrodes that are isolated from each other and alternate with each other; The pyramid structure is sequentially covered with a first spacing layer, a first connected conductive layer, a second spacing layer, and a first conductive layer; the first connected conductive layer is located on the second side of the pyramid structure; On the first side of the pyramid structure, the second spacer layer is provided with a first through hole connected to the first electrode. a conductive layer electrically connected to the first electrode through the first through hole; On the second side of the pyramid structure, the first spacing layer is used to electrically isolate the first electrode from the first connected conductive layer, and the first connected conductive layer is electrically connected to the second electrode; a conductive bridge and an insulating layer are provided between the substrate and the three-dimensional capacitor, and the insulating layer is used to electrically isolate the first conductive layer from the conductive bridge; The conductive bridge is electrically connected to the first connected conductive layer through a second through hole opened on the insulating layer, and extends to the outside of the pyramid structure to be electrically connected to the second conductive layer outside the pyramid structure.

9. The integrated passive device according to claim 8, characterized in that: The step located at the first side among the multiple steps is arranged opposite to the step located at the second side among the multiple steps.

10. The integrated passive device according to claim 9, characterized in that: The multiple steps include a first step, at which a surface of the dielectric layer facing away from the substrate includes a surface of the first step facing away from the substrate, and a surface of the electrode layer facing the substrate includes a surface of the first step facing the substrate; On the first side of the first step, the dielectric layer includes a third through hole communicating with the first electrode, and the first conductive layer is electrically connected to the first electrode through the third through hole and the first through hole; On the second side of the first step, the first spacer layer is located on the side of the first step, the dielectric layer includes a fourth through hole connected to the second electrode, and the first connected conductive layer is electrically connected to the second electrode through the fourth through hole.

11. The integrated passive device according to claim 10, characterized in that: The integrated passive device further includes a second connected conductive layer, which is in the same layer as the first connected conductive layer and is spaced apart from the first connected conductive layer; On the first side of the first step, the first spacing layer is located on the side of the first step, and is used to electrically isolate the second electrode from the second connected conductive layer; the second connected conductive layer is electrically connected to the first electrode through the third through hole; the number of the first through hole is at least one, and the first conductive layer is electrically connected to the second connected conductive layer through the first through hole.

12. The integrated passive device according to claim 10 or 11, characterized in that: The multiple steps further include a second step, and the first step is arranged between the substrate and the second step; At the second step, the surface of the electrode layer facing the substrate includes the surface of the second step facing the substrate, and the surface of the electrode layer facing away from the substrate includes the step surface of the second step; On the first side of the second step, the first conductive layer is electrically connected to the electrode layer through the first through hole; or, on the second side of the second step, the first connected conductive layer is electrically connected to the electrode layer.

13. The integrated passive device according to claim 9, characterized in that: In any one of the steps, the surface of the electrode layer facing away from the substrate includes the surface of the step facing away from the substrate, and the surface of the electrode layer facing the substrate includes the surface of the step facing the substrate; On the second side of the multi-step steps, the first spacer layer covers the multi-step steps, the first spacer layer includes a fifth through hole connected to the second electrode, and the first connected conductive layer is electrically connected to the second electrode through the fifth through hole.

14. The integrated passive device according to claim 13, characterized in that: The integrated passive device further includes a second connected conductive layer, which is in the same layer as the first connected conductive layer and is spaced apart from the first connected conductive layer; On the first side of the first step, the first spacing layer covers the first step, and is used to electrically isolate the second electrode from the second connected conductive layer; the first spacing layer includes a fifth through hole connected to the first electrode, and the second connected conductive layer is electrically connected to the first electrode through the fifth through hole; the number of the first through hole is at least one, and the first conductive layer is electrically connected to the second connected conductive layer through the first through hole.

15. The integrated passive device according to any one of claims 9 to 14, characterized in that: The integrated passive device further comprises a third conductive layer disposed between the second spacer layer and the first conductive layer, wherein the material of the third conductive layer comprises TiN; The third conductive layer covers the three-dimensional capacitor, and the third conductive layer is prepared by an atomic layer deposition process.

16. The integrated passive device according to any one of claims 9 to 15, characterized in that: The integrated passive device further includes a passivation layer, wherein the passivation layer covers the first conductive layer, the second conductive layer, and the three-dimensional capacitor; The passivation layer is provided with a sixth through hole communicating with the first conductive layer and a seventh through hole communicating with the second conductive layer.

17. An integrated passive device, characterized in that: The invention comprises a substrate, a three-dimensional capacitor, a spacer layer composed of a dielectric material, and a first conductive layer and a second conductive layer arranged at intervals; The three-dimensional capacitor comprises a plurality of electrode layers and a plurality of dielectric layers alternately stacked on the surface of the substrate to form a pyramid structure with multiple steps; along the direction of the substrate pointing to the three-dimensional capacitor, the plurality of electrode layers comprises first electrodes and second electrodes that are isolated from each other and alternate; On the first side of the pyramid structure, the spacer layer is used to electrically isolate the second electrode from the first conductive layer; a step surface of the multi-step is a surface of the first electrode facing away from the substrate, and the first conductive layer is electrically connected to the first electrode at the step surface; On the second side of the pyramid structure, the spacing layer is used to electrically isolate the first electrode from the second conductive layer; the step surface of the multi-step is the surface of the second electrode facing away from the substrate, and the second conductive layer is electrically connected to the second electrode at the step surface.

18. The integrated passive device according to claim 17, characterized in that: The spacing layer is arranged on the side surfaces of the multiple steps.

19. The integrated passive device according to claim 17 or 18, characterized in that: The integrated passive device further includes a third conductive layer and a fourth conductive layer; The third conductive layer is arranged between the three-dimensional capacitor and the first conductive layer, and the fourth conductive layer is arranged between the three-dimensional capacitor and the second conductive layer; the third conductive layer and the fourth conductive layer are prepared by an atomic layer deposition process.

20. The integrated passive device according to any one of claims 17 to 19, characterized in that: The integrated passive device further includes a passivation layer, wherein the passivation layer covers the first conductive layer, the second conductive layer, and the three-dimensional capacitor; The passivation layer is provided with a first through hole communicating with the first conductive layer and a second through hole communicating with the second conductive layer.

21. The integrated passive device according to any one of claims 17 to 20, characterized in that: The integrated passive device further comprises an etch stop layer, wherein the etch stop layer is arranged between a step away from the substrate and the spacer layer; The etch stop layer is exposed through a gap between the first conductive layer and the second conductive layer.

22. A chip, characterized in that: An integrated passive device comprising any one of claims 1-7, any one of claims 8-16, or any one of claims 17-21.

23. An electronic device, characterized in that: It comprises a circuit board and the chip according to claim 22, wherein the chip is arranged on the circuit board.

24. A method for preparing an integrated passive device, characterized in that: include: forming a three-dimensional capacitor on a substrate; The three-dimensional capacitor includes multiple electrode layers and multiple dielectric layers alternately stacked on the surface of the substrate to form a pyramid structure with multiple steps; Along the direction of the substrate pointing toward the three-dimensional capacitor, the multi-layer electrode layer includes first electrodes and second electrodes that are isolated from each other and alternate with each other; forming a spacer layer made of a dielectric material on the multiple steps; A first conductive layer is formed on the step surface on the first side of the pyramid structure, and a second conductive layer is formed on the step surface on the second side of the pyramid structure; on the first side of the pyramid structure, a first through hole connected to the first electrode is opened on the spacer layer, and the first conductive layer is electrically connected to the first electrode through the first through hole; on the second side of the pyramid structure, a second through hole connected to the second electrode is also opened on the spacer layer, and the second conductive layer is electrically connected to the second electrode through the second through hole.

25. The method for preparing an integrated passive device according to claim 24, characterized in that: The step located at the first side among the multiple steps is arranged opposite to the step located at the second side among the multiple steps.

26. The method for preparing an integrated passive device according to claim 25, characterized in that: The forming of a three-dimensional capacitor on a substrate comprises: The three-dimensional capacitor including multiple first steps is formed on the substrate, the surface of the dielectric layer facing away from the substrate includes the step surface of the first step, and the surface of the electrode layer facing the substrate includes the surface of the first step facing the substrate; at the first step, a third through hole is opened in the dielectric layer, and the third through hole is arranged opposite to the first through hole and the second through hole; the first conductive layer is electrically connected to the first electrode through the third through hole of the spacer layer and the first through hole of the dielectric layer, and the second conductive layer is electrically connected to the second electrode through the third through hole of the spacer layer and the second through hole of the spacer layer.

27. The method for preparing an integrated passive device according to claim 26, characterized in that: After forming a plurality of first steps on the substrate, forming a three-dimensional capacitor on the substrate further comprises: A second step is formed on the first step; at the second step, a surface of the electrode layer facing the substrate includes a surface of the second step facing the substrate, and a surface of the electrode layer facing away from the substrate includes the step surface of the second step.

28. The method for preparing an integrated passive device according to claim 25, characterized in that: The forming of a three-dimensional capacitor on a substrate comprises: Multiple electrode layers and multiple dielectric layers are alternately formed on the substrate; the surface of the electrode layer facing away from the substrate includes the step surface, and the surface of the dielectric layer facing the substrate includes the surface of the step facing the substrate.

29. The method for preparing an integrated passive device according to any one of claims 24 to 28, characterized in that: After forming the first conductive layer on the first side step surface of the pyramid structure and forming the second conductive layer on the second side step surface of the pyramid structure, the method for preparing the integrated passive device further includes: A passivation layer is formed on the first conductive layer and the second conductive layer on the side away from the substrate; a fourth through hole connected to the first conductive layer and a fifth through hole connected to the second conductive layer are opened on the passivation layer.

30. The integrated passive device according to any one of claims 24 to 29, characterized in that: After forming the three-dimensional capacitor on the substrate and before forming the spacer layer made of dielectric material on the multi-step steps, the method for preparing the integrated passive device further includes: An etch stop layer is formed on a step away from the substrate; and the etch stop layer is exposed in a gap between the first conductive layer and the second conductive layer.

31. A method for preparing an integrated passive device, characterized in that: include: A conductive bridge and an insulating layer are sequentially formed on the substrate, wherein a second through hole is formed on the insulating layer; forming a three-dimensional capacitor on a substrate; The three-dimensional capacitor comprises a plurality of electrode layers and a plurality of dielectric layers alternately stacked on the surface of the substrate to form a pyramid structure with multiple steps; along the direction of the substrate pointing to the three-dimensional capacitor, the plurality of electrode layers comprises first electrodes and second electrodes that are isolated from each other and alternate; A first spacing layer, a first connecting conductive layer, and a second spacing layer are sequentially formed on the pyramid structure; the first connecting conductive layer Located at the second side of the pyramid structure; on the first side of the pyramid structure, a first through hole connected to the first electrode is opened on the second spacing layer, and on the second side of the pyramid structure, the first spacing layer is used to electrically isolate the first electrode from the first connected conductive layer, and the first connected conductive layer is electrically connected to the second electrode; A first conductive layer and a second conductive layer are formed; on the first side of the pyramid structure, the first conductive layer is electrically connected to the first electrode through the first through hole; on the second side of the pyramid structure, the insulating layer is used to electrically isolate the first conductive layer from the conductive bridge, and the conductive bridge is electrically connected to the first connected conductive layer through a second through hole opened on the insulating layer, and extends to the outside of the pyramid structure to be electrically connected to the second conductive layer outside the pyramid structure.

32. The method for preparing an integrated passive device according to claim 31, characterized in that: The step located at the first side among the multiple steps is arranged opposite to the step located at the second side among the multiple steps.

33. The method for preparing an integrated passive device according to claim 32, characterized in that: The forming of a three-dimensional capacitor on a substrate comprises: The three-dimensional capacitor including a plurality of first steps is formed on the substrate; at the first step, the surface of the dielectric layer facing away from the substrate includes the surface of the first step facing away from the substrate, and the surface of the electrode layer facing the substrate includes the surface of the first step facing the substrate; wherein, on a first side of the first step, the dielectric layer includes a third through hole connected to the first electrode, and the first conductive layer is electrically connected to the first electrode through the third through hole and the first through hole; on a second side of the first step, the dielectric layer includes a fourth through hole connected to the second electrode, and the first conductive layer is electrically connected to the second electrode through the fourth through hole; The forming of the first spacer layer on the pyramid structure comprises: forming the first spacer layer on the second side of the first step, wherein the first spacer layer is located on the side of the first step.

34. The method for preparing an integrated passive device according to claim 33, characterized in that: While forming the first connected conductive layer on the pyramid structure, the method for preparing the integrated passive device further includes: A second connected conductive layer is formed, which is in the same layer as the first connected conductive layer and is spaced apart from each other; on the first side of the first step, the first spacing layer is located on the side of the first step, and is used to electrically isolate the second electrode from the second connected conductive layer; the second connected conductive layer is electrically connected to the first electrode through the third through hole; the number of the first through hole is at least one, and the first conductive layer is electrically connected to the second connected conductive layer through the first through hole.

35. The method for preparing an integrated passive device according to claim 33 or 34, characterized in that: After forming a plurality of first steps on the substrate, forming a three-dimensional capacitor on the substrate further comprises: A second step is formed on the first step; at the second step, the surface of the electrode layer facing the substrate includes the surface of the second step facing the substrate, and the surface of the electrode layer away from the substrate includes the step surface of the second step; on the first side of the second step, the first conductive layer is electrically connected to the electrode layer through the first through hole; or, on the second side of the second step, the first connected conductive layer is electrically connected to the electrode layer.

36. The method for preparing an integrated passive device according to claim 32, characterized in that: The forming of a three-dimensional capacitor on a substrate comprises: The three-dimensional capacitor including multiple steps is formed on the substrate; in any one of the steps, the surface of the electrode layer facing away from the substrate includes the surface of the step facing away from the substrate, and the surface of the electrode layer facing the substrate includes the surface of the step facing the substrate; The forming of the first spacer layer on the pyramid structure comprises: forming the first spacer layer covering the multiple steps on the second side of the multiple steps; the first spacer layer comprises a fifth through hole connected to the second electrode, and the first connected conductive layer is electrically connected to the second electrode through the fifth through hole.

37. The method for preparing an integrated passive device according to claim 36, characterized in that: While forming the first connected conductive layer on the pyramid structure, the method for preparing the integrated passive device further includes: forming a second connected conductive layer, the second connected conductive layer being in the same layer as the first connected conductive layer and being spaced apart from each other; on a first side of the first step, the first spacer layer covering the first step, for electrically isolating the second electrode from the second connected conductive layer; The forming of a first spacer layer on the pyramid structure further comprises: The first spacer layer covering the multi-step steps is formed on the second side of the multi-step steps; the first spacer layer includes a fifth through hole connected to the second electrode, and the second connected conductive layer is electrically connected to the first electrode through the fifth through hole.

38. The method for preparing an integrated passive device according to any one of claims 32 to 37, characterized in that: After forming the second spacer layer and before forming the first conductive layer and the second conductive layer, the method for preparing the integrated passive device further includes: An atomic layer deposition process is adopted to form a third conductive layer covering the three-dimensional capacitor; the material of the third conductive layer includes TiN.

39. The method for preparing an integrated passive device according to any one of claims 32 to 38, characterized in that: After the first side step surface of the pyramid structure is covered with the first conductive layer, and the second side step surface of the pyramid structure is covered with the second conductive layer, the method for preparing the integrated passive device further includes: A passivation layer is formed on the first conductive layer and the second conductive layer on the side away from the substrate; the passivation layer covers the first conductive layer, the second conductive layer, and the three-dimensional capacitor; and a sixth through hole connected to the first conductive layer and a seventh through hole connected to the second conductive layer are opened on the passivation layer.

40. A method for preparing an integrated passive device, characterized in that: include: forming a three-dimensional capacitor on a substrate; The three-dimensional capacitor includes multiple electrode layers and multiple dielectric layers alternately stacked on the surface of the substrate to form a pyramid structure with multiple steps; Along the direction of the substrate pointing toward the three-dimensional capacitor, the multi-layer electrode layer includes first electrodes and second electrodes that are isolated from each other and alternate with each other; forming a spacer layer composed of a dielectric material on the pyramid structure; A first conductive layer is formed on a step surface on a first side of the pyramid structure, and a second conductive layer is formed on a step surface on a second side of the pyramid structure; on the first side of the pyramid structure, the spacer layer is used to electrically isolate the second electrode from the first conductive layer, the step surface of the multi-step steps is a surface of the first electrode facing away from the substrate, and the first conductive layer is electrically connected to the first electrode at the step surface; On the second side of the pyramid structure, the spacer layer is used to electrically isolate the first electrode from the second conductive layer, the step surface of the multi-step is the surface of the second electrode facing away from the substrate, and the second conductive layer is electrically connected to the second electrode at the step surface.

41. The method for preparing an integrated passive device according to claim 40, characterized in that: The spacer layer is located on the side of the multiple steps.

42. The method for preparing an integrated passive device according to claim 40 or 41, characterized in that: After forming a spacer layer made of a dielectric material on the pyramid structure, forming a first conductive layer on a step surface of a first side of the pyramid structure, and before forming a second conductive layer on a second side of the pyramid structure, the method for preparing an integrated passive device further includes: By adopting an atomic layer deposition process, a third conductive layer is formed on the step surface of the first side of the pyramid structure, and a fourth conductive layer is formed on the second side of the pyramid structure.

43. The method for preparing an integrated passive device according to any one of claims 40 to 42, characterized in that: After forming the first conductive layer on the first side step surface of the pyramid structure and forming the second conductive layer on the second side step surface of the pyramid structure, the method for preparing the integrated passive device further includes: A passivation layer is formed on the first conductive layer and the second conductive layer on the side away from the substrate, and the passivation layer covers the three-dimensional conductive layer. The passivation layer is provided with a first through hole communicating with the first conductive layer and a second through hole communicating with the second conductive layer.

44. The method for preparing an integrated passive device according to any one of claims 40 to 43, characterized in that: After forming the three-dimensional capacitor on the substrate and before forming the spacer layer made of dielectric material on the pyramid structure, the method for preparing the integrated passive device further includes: An etch stop layer is formed on a step away from the substrate; and the etch stop layer is exposed in a gap between the first conductive layer and the second conductive layer.

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