Logic controller, flash memory upgrading method and device, electronic equipment and medium

Abstract

The invention discloses a logic controller, an upgrading method and device of a flash memory, electronic equipment and a medium, and relates to the technical field of equipment management, by setting a flash memory information storage to store flash memory information of a user flash memory of the logic controller, upgrading retry can be carried out through the flash memory information, the flash memory information does not need to be rewritten through physical disassembly, and the upgrading efficiency is improved. Therefore, faults possibly caused by disassembly are avoided, and the reliability of upgrade management is improved.

Description

Technical Field

[0001] The present application relates to the field of device management technology, and in particular to a logic controller, a flash memory upgrade method, a device, an electronic device, and a medium. Background Art

[0002] In the application scenarios of devices such as servers and switches, as R&D progresses, device functionality can be gradually expanded and improved through firmware upgrades. Device upgrades essentially involve physically programming the device's embedded flash memory.

[0003] In the related art, when a device upgrade fails, management is performed by disassembling the device, which has the problem of low reliability. Summary of the Invention

[0004] The present application provides a logic controller, a flash memory upgrade method, a device, an electronic device, and a medium to at least solve the problem of low reliability of upgrade management in related technologies.

[0005] The present application provides a logic controller, comprising: a user flash memory, a bus upgrade controller, a flash memory upgrade controller, a retry controller and a flash memory information memory; wherein the bus upgrade controller is connected to a management controller outside the logic controller via an integrated circuit bus, the bus upgrade controller is connected to the flash memory upgrade controller, the bus upgrade controller is used to receive an upgrade instruction sent by the management controller, and send the upgrade instruction to the flash memory upgrade controller; the flash memory upgrade controller is connected to the user flash memory and the retry controller, the flash memory upgrade controller is used to upgrade the user flash memory according to the upgrade instruction and determine the upgrade result; the retry controller is connected to the flash memory information memory and the bus upgrade controller, the retry controller is used to send the flash memory information stored in the flash memory information memory to the bus upgrade controller if the upgrade result is an upgrade failure, so that the bus upgrade controller instructs the flash memory upgrade controller to retry the upgrade of the user flash memory; the flash memory information memory is connected to the management controller, and the flash memory information memory is used to store the flash memory information according to the upgrade instruction.

[0006] The present application also provides a flash memory upgrade method, including: receiving an upgrade instruction sent by a management controller outside the logic controller; upgrading the user flash memory according to the upgrade instruction and determining the upgrade result; if the upgrade result is an upgrade failure, sending the flash memory information stored in the flash memory information memory to the bus upgrade controller through the retry controller, so that the bus upgrade controller instructs the flash memory upgrade controller to retry the upgrade of the user flash memory.

[0007] The present application also provides a flash memory upgrade device, including: a receiving module for receiving an upgrade instruction sent by a management controller outside the logic controller; an upgrade module for upgrading the user flash memory according to the upgrade instruction and determining the upgrade result; a management module for sending the flash memory information stored in the flash memory information memory to the bus upgrade controller through the retry controller if the upgrade result is an upgrade failure, so that the bus upgrade controller instructs the flash memory upgrade controller to retry the upgrade of the user flash memory.

[0008] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above-mentioned flash memory upgrade methods when executing the computer program.

[0009] The present application also provides a non-volatile computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned flash memory upgrade methods are implemented.

[0010] The present application also provides a computer program product, including a computer program, which implements the steps of any of the above-mentioned flash memory upgrade methods when executed by a processor.

[0011] Through this application, by setting up a flash information memory to store the flash information of the user flash memory of the logic controller, the upgrade can be retried through the flash information without the need to physically disassemble the machine to rewrite the flash information, thereby avoiding failures that may be caused by disassembly and improving the reliability of upgrade management. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0013] Figure 1 A schematic diagram of an application scenario of a flash memory upgrade method provided in an embodiment of the present application;

[0014] Figure 2 A schematic diagram of the structure of a logic controller provided in an embodiment of the present application;

[0015] Figure 3 A schematic diagram of the structure of the status register provided in an embodiment of the present application;

[0016] Figure 4 A schematic diagram of the structure of the logic controller provided in an embodiment of the present application;

[0017] Figure 5 A schematic diagram of the structure of the logic controller provided in an embodiment of the present application;

[0018] Figure 6 A flowchart of a flash memory upgrade method provided in an embodiment of the present application;

[0019] Figure 7 A flowchart of a flash memory upgrade method provided in an embodiment of the present application;

[0020] Figure 8 A schematic diagram of an upgrade retry provided in an embodiment of the present application;

[0021] Figure 9 A schematic diagram of the structure of a flash memory upgrade device provided in an embodiment of the present application;

[0022] Figure 10 A schematic diagram of the structure of a flash memory upgrade device provided in an embodiment of the present application;

[0023] Figure 11 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0024] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0025] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0026] Exemplarily, the logic controller may be a complex programmable logic device (CPLD), which is an integrated circuit whose logic functions are configured through programming in a hardware description language and is used to execute preset functions in devices such as servers. The logic controller includes user flash memory and configuration flash memory. The flash memory information of the user flash memory includes at least the identification of the logic controller (such as the hardware model or serial number, etc.), which is used for verification during the upgrade process. The flash memory information of the configuration flash memory includes the control logic of the device (such as a power supply, fan, or indicator light, etc.). The upgrade process of the logic controller is to write the upgrade package received from a remote location into the user flash memory and / or configuration flash memory.

[0027] For example, during the logic controller upgrade process, electromagnetic interference or other factors may cause the upgrade to fail. Configuration flash upgrade failures are recoverable and can be repaired directly through communication. User flash upgrade failures are unrecoverable and cannot be repaired directly through communication.

[0028] Specifically, the flash memory upgrade process verifies the flash memory by comparing the identifier in the flash memory information with the identifier in the upgrade package. Once verification is successful, the original flash memory information is erased and rewritten with the information in the upgrade package. If the user flash memory upgrade fails, if the original flash memory information has already been erased, subsequent verification cannot be performed, meaning that the upgrade retry process cannot be performed. However, if the configuration flash memory upgrade fails, the identifier in the user flash memory information is not erased, so verification can be performed, and the upgrade retry process can be performed.

[0029] In related technologies, the user's flash memory authentication function is restored by disassembling the logic controller and manually rewriting the flash memory information with a programmer to write the identifier. However, disassembling the device and operating the programmer carries the risk of physical damage. For example, the logic controller lacks physical pins for the Joint Test Working Group, requiring manual soldering of the historical interface, which carries the risk of pad damage and electrostatic breakdown, leading to low reliability of upgrade management.

[0030] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0031] In conjunction with the specific application environment architecture on which the flash memory upgrade method is executed, the specific application environment architecture is described here. Figure 1 , Figure 1This diagram illustrates an application scenario for a flash memory upgrade method. In the logic controller's initial state, flash memory information A is stored in the flash memory. An upgrade package triggers the upgrade. If the upgrade succeeds, the logic controller's flash memory information A is updated to flash memory information B. If the upgrade fails, a retry is performed. If the retry succeeds, the logic controller's flash memory information A is updated to flash memory information B.

[0032] For example, this application stores the identifier outside of the flash memory, so that even if the upgrade fails, the identifier can be retained, thereby verifying the upgrade retry based on the identifier. Compared with the methods in the related art, this application does not require physical disassembly during the upgrade retry process, thereby reducing the risk of upgrade retry and improving the reliability of upgrade management.

[0033] Figure 2 A schematic diagram of the structure of the logic controller provided in the embodiment of the present application is shown in FIG. Figure 2 As shown, an embodiment of the present application provides a logic controller, including: a user flash memory, a bus upgrade controller, a flash memory upgrade controller, a retry controller and a flash memory information memory; wherein,

[0034] The bus upgrade controller is connected to the management controller outside the logic controller through the integrated circuit bus, and the bus upgrade controller is connected to the flash memory upgrade controller. The bus upgrade controller is used to receive the upgrade instruction sent by the management controller and send the upgrade instruction to the flash memory upgrade controller;

[0035] The flash memory upgrade controller is connected to the user flash memory and the retry controller, and is used to upgrade the user flash memory according to the upgrade instruction and determine the upgrade result;

[0036] The retry controller is connected to the flash memory information storage and the bus upgrade controller. If the upgrade result is an upgrade failure, the retry controller is used to send the flash memory information stored in the flash memory information storage to the bus upgrade controller, so that the bus upgrade controller instructs the flash memory upgrade controller to retry the upgrade of the user flash memory.

[0037] The flash memory information storage is connected to the management controller, and the flash memory information storage is used to store the flash memory information according to the upgrade instruction.

[0038] For example, the management controller may be a baseboard management controller (BMC). The management controller sends an upgrade instruction to trigger the logic controller to upgrade. The upgrade instruction may include an upgrade package, so that the logic controller performs the upgrade process according to the upgrade package.

[0039] Optionally, a bus upgrade controller is connected to the integrated circuit bus and corresponds to an integrated circuit bus address, so that the management controller accurately sends upgrade instructions based on the address. The bus upgrade controller obtains the upgrade instruction from the integrated circuit bus based on the address and parses the upgrade instruction to obtain the upgrade package contained in the upgrade instruction.

[0040] Exemplarily, the flash memory upgrade controller is used to perform erasing and data writing of the flash memory to implement the flash memory upgrade. Specifically, the flash memory upgrade controller drives the user flash memory to perform erasing and data writing operations according to data in the upgrade instruction.

[0041] For example, in the scenario where the user flash memory upgrade fails, since the identifier in the user flash memory has been erased, verification is performed using the identifier included in the flash memory information, thereby reducing the need to disassemble the device.

[0042] Exemplarily, the flash information storage device, in response to the upgrade instruction, stores the flash information of the user flash memory before the initial upgrade process, so that a backup copy of the flash information is saved in the flash information storage device. During the initial upgrade process, the flash information in the flash information storage device no longer changes, thereby ensuring that the flash information in the user flash memory is backed up before being erased. The backup flash information can be effectively stored, thereby improving the reliability of upgrade management.

[0043] Exemplarily, the flash memory upgrade controller sends a FAIL_FLAG signal to the retry controller via the connection between the flash memory upgrade controller and the retry controller to trigger the upgrade retry.

[0044] Combined with the scenario example, the storage of flash information through the flash information memory can be completed by hardware logic throughout the upgrade retry process, thereby avoiding disassembly operations.

[0045] The logic controller provided in the embodiment of the present application, by setting a flash memory information memory to store the flash memory information of the user flash memory of the logic controller, can be upgraded and retried through the flash memory information without the need to physically disassemble the machine to rewrite the flash memory information, thereby avoiding failures that may be caused by disassembly, and thus improving the reliability of upgrade management.

[0046] A feasible implementation method is Figure 3 A schematic diagram of the structure of the status register provided in the embodiment of the present application is shown as follows: Figure 3 As shown, the logic controller further includes a status register; the pins of the status register are connected to the flash memory upgrade controller and the user flash memory, and the status register is used to send an upgrade result to the flash memory upgrade controller when the upgrade fails.

[0047] For example, the pin of the status register can read the upgrade status of the user flash memory, and the upgrade result can be determined according to the upgrade status.

[0048] Optionally, the upgrade status read by the status register may be a native electrical signal of the user flash memory, such as a high-voltage pulse or a verification level, etc. The status register converts the native electrical signal into a logic value, and the logic value represents different upgrade results.

[0049] Optionally, the flash memory upgrade controller reads a level signal of a pin of a status register and determines an upgrade result according to the level signal.

[0050] In this feasible implementation, by setting the status register, the user flash memory can be monitored in real time, so that the upgrade result can be determined immediately, so that the flash memory upgrade controller can retry the upgrade in time according to the upgrade result.

[0051] A feasible implementation method is Figure 4 A schematic diagram of the structure of the logic controller provided in the embodiment of the present application is shown in FIG. Figure 4 As shown, the logic controller also includes a check controller and a check value memory; the check controller is connected to the retry controller, the output end of the check value memory, and the bus upgrade controller, and the check controller is used to check the flash memory information according to the information check value to obtain a first check result, and send the flash memory information to the bus upgrade controller according to the first check result; the input end of the check value memory is connected to the bus upgrade controller, and the check value memory is used to generate an information check value corresponding to the user flash memory according to the upgrade instruction, and store the information check value.

[0052] Exemplarily, after the retry controller sends the flash memory information to the verification controller, the verification controller first verifies the flash memory information to obtain a first verification result, and then sends the flash memory information to the bus upgrade controller according to the first verification result.

[0053] Exemplarily, if the first verification result is verification passed, the verification controller sends the flash memory information to the bus upgrade controller.

[0054] Exemplarily, the verification process is based on an information verification value stored in a verification value memory, and the flash memory information is verified according to the information verification value.

[0055] In combination with the scenario example, if the first verification result is passed, it means that the flash memory information is correct, and the flash memory information can be used to retry the upgrade.

[0056] In this feasible implementation, verification processing is performed to perform upgrade retries based on accurate flash memory information, thereby improving the reliability of upgrade retries.

[0057] A feasible implementation method is Figure 5 A schematic diagram of the structure of the logic controller provided in the embodiment of the present application is shown in FIG. Figure 5As shown, the logic controller also includes a configuration flash memory; the flash memory upgrade controller is connected to the configuration flash memory, and the flash memory upgrade controller is used to perform upgrade retry processing on the configuration flash memory according to the upgrade instruction.

[0058] Exemplarily, the upgrade retry of the configuration flash memory is triggered by the bus upgrade controller.

[0059] Exemplarily, the configuration flash memory does not store an identifier. During the process of the flash memory upgrade controller upgrading the configuration memory, even if the upgrade fails and the configuration memory is erased, the upgrade can still be retried using the identifier in the user flash memory.

[0060] Exemplarily, the flash memory upgrade controller is independent of the channel connected to the configuration flash memory and the channel connected to the user flash memory to avoid conflicts between the upgrade of the configuration flash memory and the upgrade of the user flash memory. When the upgrade of one of the configuration flash memory and the user flash memory fails, only the upgrade of the failed flash memory can be retried.

[0061] In this feasible implementation, by isolating the channels of the configuration flash memory and the user flash memory, conflicts between upgrades of the configuration flash memory and user flash memory can be avoided, thereby improving the reliability of upgrade management.

[0062] Figure 6 A flow chart of a flash memory upgrade method provided in an embodiment of the present application is shown as follows: Figure 6 As shown, an embodiment of the present application provides a flash memory upgrade method, which is described in detail as follows:

[0063] S601: Receive an upgrade instruction sent by a management controller outside the logic controller.

[0064] Exemplarily, the management controller and the logic controller are connected via an integrated circuit bus. The management controller generates an upgrade instruction according to the upgrade package and sends it to the logic controller to instruct the logic controller to upgrade according to the upgrade package in the upgrade instruction.

[0065] S602: Perform upgrade processing on the user flash memory according to the upgrade instruction and determine the upgrade result.

[0066] Exemplarily, the upgrade result is a result obtained after the logic controller upgrades the user flash memory, and the upgrade result includes upgrade success or upgrade failure.

[0067] For example, a successful upgrade indicates that the upgrade package data has been written into the user flash memory. An upgrade failure indicates that an interruption occurred during the upgrade process, resulting in the upgrade package data not being written into the user flash memory.

[0068] In this scenario example, if the upgrade is successful, the logic controller can run according to the new data. If the upgrade fails, the logic controller lacks the necessary data and cannot run normally. To restore the normal operation of the logic controller, the upgrade retry method is used.

[0069] S603: If the upgrade result is upgrade failure, the retry controller sends the flash information stored in the flash information memory to the bus upgrade controller, so that the bus upgrade controller instructs the flash upgrade controller to retry the upgrade of the user flash memory.

[0070] For example, when the upgrade result is an upgrade failure, the flash memory upgrade controller has erased the user flash memory, but the flash memory information storage is not affected and can normally store the flash memory information. The flash memory information can be read from the flash memory information storage, and the flash memory information includes an identifier used for verification during the upgrade process, thereby ensuring that the upgrade retry process can be effectively verified.

[0071] Optionally, the bus upgrade controller receives a new upgrade package from the management controller via the integrated circuit bus, or the bus upgrade controller uses the upgrade package in the first upgrade instruction to trigger the flash memory upgrade controller to perform an upgrade.

[0072] The flash memory upgrade method provided in the embodiment of the present application, by setting the flash memory information of the user flash memory of the storage logic controller to be stored in the flash memory information memory, can perform upgrade retries through the flash memory information without the need to physically disassemble the machine to rewrite the flash memory information, thereby avoiding failures that may be caused by disassembly, and thus improving the reliability of upgrade management.

[0073] Based on any of the above embodiments, Figure 7 , describes the detailed process of the flash memory upgrade method.

[0074] Figure 7 A schematic diagram of a flash memory upgrade method provided in an embodiment of the present application. Figure 7 As shown, the method includes:

[0075] S701: Receive an upgrade instruction sent by a management controller outside the logic controller.

[0076] It should be noted that the execution process of S701 refers to S601 and will not be repeated here.

[0077] S702: Determine target data corresponding to the upgrade instruction stored in the user flash memory.

[0078] Exemplarily, the upgrade instruction includes an upgrade package specified by the management controller, which instructs the management controller to write the data in the upgrade package to the user flash memory. The target data is the data already in the user flash memory that corresponds to the data in the upgrade package. The essence of the upgrade process is that the data in the upgrade package replaces the target data.

[0079] In this example scenario, for example, if the target data is parameter A and the data in the upgrade package is parameter B, and both parameters A and B are of the same parameter type, the upgrade process requires determining parameter A of the same type in the user flash memory based on the parameter type of parameter B, and then performing the replacement process.

[0080] S703: Erase the target data and rewrite the data in the user flash memory according to the upgrade instruction to perform the upgrade process.

[0081] Exemplarily, the flash memory upgrade controller generates an erase instruction, triggers erasure of target data through the erase instruction, and rewrites the data into the user flash memory after the erasure is completed for upgrade processing.

[0082] Optionally, the flash memory upgrade controller generates a full erase instruction to erase all data in the user flash memory through the full erase instruction.

[0083] S704: Read the pin information of the status register and determine the upgrade result according to the pin information.

[0084] Exemplarily, the status register indicates different upgrade results through different pin information.

[0085] Optionally, the status register indicates the upgrade result of the configuration flash memory or the user flash memory through different pin information.

[0086] Optionally, a mapping relationship between pin information and upgrade results is pre-configured, and a corresponding upgrade result is determined according to the mapping relationship and the pin information.

[0087] S705: If the upgrade result is upgrade failure, the retry controller sends the flash information stored in the flash information memory to the bus upgrade controller, so that the bus upgrade controller instructs the flash upgrade controller to retry the upgrade of the user flash memory.

[0088] A feasible implementation method can send the flash memory information stored in the flash memory information memory to the bus upgrade controller through the retry controller through the following method, including: determining a retry number threshold; determining the upgrade result through the retry controller; if the upgrade result is an upgrade failure, determining the number of upgrade retries of the user flash memory through the retry controller; if the number of upgraded retries is less than or equal to the number threshold, reading the stored information from the flash memory information memory through the retry controller, and determining the flash memory information corresponding to the user flash memory from the stored information; determining the verification parameters of the flash memory information through the retry controller, the verification parameters including the flash memory corresponding to the flash memory information, and / or the format of the flash memory information; verifying the verification parameters of the flash memory information through the retry controller to obtain a verification result, the verification result being verification passed or verification failed; if the verification result is verification passed, sending the flash memory information to the bus upgrade controller through the retry controller.

[0089] Exemplarily, the retry count threshold represents an upper limit of the upgrade retry count, and the retry count threshold is used to avoid the problem of excessive overhead caused by repeated upgrade retries.

[0090] Optionally, if the current upgrade retry count is greater than the retry count threshold, a fuse is triggered and the management controller is notified of the upgrade failure, so that the management controller changes the upgrade strategy.

[0091] Optionally, if a circuit breaker is triggered, log information for the upgrade process and upgrade retry is obtained. This log information and upgrade instructions are fed into a prediction model to determine the cause of the upgrade retry failure and the corresponding solution. The prediction model is trained based on historical data.

[0092] Exemplarily, if the number of upgrade retries is less than or equal to the number threshold, it means that the number of upgrade retries is within a controllable range and further upgrade retries can be performed.

[0093] Exemplarily, the flash memory information memory may store a variety of information. When performing an upgrade retry, the flash memory information corresponding to the user flash memory is filtered from the information stored in the flash memory information memory.

[0094] Optionally, the information stored in the flash information memory is grouped according to fields, each group corresponds to a field information, and the type of data is distinguished by the field information, thereby accurately determining the flash information corresponding to the user flash memory.

[0095] For example, the memory corresponding to the flash information in the verification parameters indicates that the flash information originates from user flash memory or configuration flash memory. The format of the flash information in the verification parameters is used to verify whether the format of the flash information stored in the flash information memory is recognizable by the bus upgrade controller or the flash information memory. Verification processing using the verification parameters improves the accuracy of the flash information, thereby improving the reliability of upgrade management.

[0096] Next, combine Figure 8 Explain upgrade retries.

[0097] Figure 8 This is a schematic diagram of the upgrade retry provided in the embodiment of the present application. Figure 8 As shown, the management controller sends an upgrade command to trigger the upgrade and reads the status register according to the preset cycle. When the status information is neither busy nor failed, the next step is performed; otherwise, the upgrade fails. An erase command is sent to trigger the flash erase. After the status is detected as ready, the configuration flash start address is written. The data is written page by page, and the status register is read after each page is written. After the configuration flash area is written, the target address is switched to the user flash address. An upgrade completion command is sent to close the upgrade channel and complete the upgrade operation of the logic controller. When the user flash upgrade fails, the retry controller is instructed to retry the upgrade.

[0098] As explained in this scenario example, the management controller first issues an upgrade command via the integrated circuit bus. The logic controller then synchronizes the identifier stored in the user flash memory to the flash information memory. During the upgrade process, if an error occurs when reading the status register (i.e., the upgrade fails), the flash upgrade controller immediately sends a FAIL_FLAG signal to the retry controller to trigger an upgrade retry. The identifier is then retrieved from the flash information memory and sent to the bus upgrade controller, which then drives the bus upgrade controller to issue another upgrade command. If the upgrade fails again, the retry controller drives the bus upgrade controller to upgrade again. If the number of failures exceeds the retry threshold, a fuse is triggered, notifying the management controller of the upgrade failure.

[0099] In this feasible implementation, verification is performed through the upgrade times and verification parameters, which can improve the effectiveness of the upgrade process and thus improve the reliability of the upgrade management.

[0100] In a feasible implementation method, the logic controller also includes a configuration flash memory; if the upgrade result is an upgrade failure, the flash memory upgrade method also includes: generating a retry instruction through a retry controller; sending a retry instruction to a bus upgrade controller through the retry controller, so that the bus upgrade controller sends a retry instruction to the flash memory upgrade controller to perform upgrade retry processing on the configuration flash memory.

[0101] Exemplarily, the upgrade process is to upgrade the configuration flash memory first and then upgrade the user flash memory. In the scenario where the configuration flash memory upgrade fails, since the identifier in the user flash memory is not erased, the identifier in the user flash memory can be used for verification.

[0102] Combined with the scenario example, for the scenario where the configuration flash memory upgrade fails, the retry controller does not need to read the flash memory information from the flash memory information storage, and can directly trigger the bus upgrade controller to retry the upgrade.

[0103] In this feasible implementation, the identifier in the user flash memory is used to retry the upgrade of the configuration flash memory, thereby reducing the retry operations and improving the reliability of the upgrade management.

[0104] A feasible implementation method, if the upgrade result is that the upgrade is successful, the method also includes: determining a standard check value; determining the original data from the user flash memory and / or the configuration flash memory, and calculating and processing the original data according to the verification algorithm to obtain an original check value; comparing the original check value and the standard check value to perform a cyclic redundancy check to obtain a second check result, the second check result is a check pass or a check fail; if the second check result is a check fail, performing an upgrade retry process.

[0105] Illustratively, cyclic redundancy check is a type of error detection code based on polynomial division.

[0106] Exemplarily, the upgrade result is a successful upgrade, indicating that the data in the upgrade package has been written into the user flash memory and / or configuration flash memory. The cyclic redundancy check is used to determine whether there is an abnormality in the writing process, that is, whether the data actually written is the target data.

[0107] For example, the standard checksum is the checksum corresponding to the target data being written, and the original data is the data actually written to the flash memory. The original checksum calculated by the checksum algorithm on the original data is the actual checksum. By comparing the original checksum with the standard checksum, it can be determined whether the actual written data is correct. If not, further upgrade and retry processing is performed.

[0108] Optionally, the management controller generates an upgrade instruction and simultaneously generates a corresponding standard check value.

[0109] In this feasible implementation, cyclic redundancy check can ensure that the data actually written into the memory is correct data, thereby improving the reliability of upgrade management.

[0110] A feasible implementation manner, after receiving the upgrade instruction sent by the management controller outside the logic controller, further includes: determining the flash memory information of the user flash memory, and storing the flash memory information in the flash memory information memory.

[0111] Exemplarily, the logic controller triggers the storage of flash memory information after receiving the upgrade instruction.

[0112] In this scenario, the flash information in the user flash memory may change. Retrieving the latest flash information from the user flash memory in real time upon receiving an upgrade command ensures the validity of the flash information. This allows the latest flash information to be used when retrying the upgrade.

[0113] In this feasible implementation, by acquiring the latest flash memory information from the user flash memory in real time when receiving the upgrade instruction, the validity of the flash memory message can be ensured, thereby improving the reliability of the upgrade management.

[0114] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0115] Figure 9 This is a schematic diagram of the structure of the flash memory upgrade device provided in the embodiment of the present application. Figure 9 As shown, the embodiment of the present application further provides a flash memory upgrade device, the flash memory upgrade device 90 may include: a receiving module 91, an upgrade module 92 and a management module 93, wherein:

[0116] The receiving module 91 is configured to receive an upgrade instruction sent by a management controller outside the logic controller.

[0117] The upgrade module 92 is used to upgrade the user flash memory according to the upgrade instruction and determine the upgrade result.

[0118] The management module 93 is configured to send the flash information stored in the flash information memory to the bus upgrade controller through the retry controller if the upgrade result is upgrade failure, so that the bus upgrade controller instructs the flash upgrade controller to retry the upgrade of the user flash memory.

[0119] Optionally, the receiving module 91 may execute Figure 6 S601 in the embodiment.

[0120] Optionally, the upgrade module 92 may execute Figure 6 S602 in the embodiment.

[0121] Optionally, the management module 93 may execute Figure 6 S603 in the embodiment.

[0122] It should be noted that the flash memory upgrade device shown in the embodiment of the present application can execute the technical solution shown in the above method embodiment, and its implementation principle and beneficial effects are similar, which will not be repeated here.

[0123] In a possible implementation, the upgrade module 92 is specifically configured to:

[0124] Determine the target data corresponding to the upgrade instruction in the user flash memory;

[0125] Erases the target data and rewrites the user flash memory according to the upgrade instructions to perform the upgrade process;

[0126] Read the pin information of the status register and determine the upgrade result based on the pin information.

[0127] Figure 10 A schematic diagram of the structure of a flash memory upgrade device provided in an embodiment of the present application. Figure 9 Based on the embodiment shown, Figure 10 As shown, the flash memory upgrade device 90 further includes: a retry module 94, an execution module 95, a verification module 96 and a storage module 97, wherein:

[0128] The retry module 94 is used to:

[0129] Determine the retry threshold;

[0130] Determine the upgrade result through the retry controller;

[0131] If the upgrade result is an upgrade failure, the retry controller determines the number of upgrade retries of the user flash memory;

[0132] If the upgraded retry count is less than or equal to the count threshold, reading the stored information from the flash information memory through the retry controller, and determining the flash information corresponding to the user flash memory from the stored information;

[0133] determining, by the retry controller, verification parameters of the flash memory information, the verification parameters including the flash memory corresponding to the flash memory information and / or the format of the flash memory information;

[0134] Verifying the verification parameters of the flash memory information by the retry controller to obtain a verification result, which is a verification pass or a verification fail;

[0135] If the verification result is that the verification is passed, the flash memory information is sent to the bus upgrade controller through the retry controller.

[0136] The logic controller further includes a configuration flash memory; an execution module 95 for:

[0137] Generate a retry instruction through a retry controller;

[0138] The retry controller sends a retry instruction to the bus upgrade controller, so that the bus upgrade controller sends a retry instruction to the flash memory upgrade controller to perform upgrade retry processing on the configuration flash memory.

[0139] The verification module 96 is used to:

[0140] Determine the standard calibration value;

[0141] Determine original data from the user flash memory and / or the configuration flash memory, and perform calculation processing on the original data according to the verification algorithm to obtain an original verification value;

[0142] Comparing the original check value with the standard check value to perform a cyclic redundancy check to obtain a second check result, where the second check result is a check pass or a check fail;

[0143] If the second verification result is verification failure, the upgrade retry process is performed.

[0144] The storage module 97 is used to:

[0145] Flash information of the user flash memory is determined and stored in the flash information memory.

[0146] For the description of the features in the embodiment corresponding to the flash memory upgrade device, reference can be made to the relevant description of the embodiment corresponding to the flash memory upgrade method, which will not be repeated here.

[0147] Figure 11 This is a schematic diagram of the structure of the electronic device provided in this application. Figure 11 As shown, the electronic device 110 provided in this embodiment includes: at least one processor 1101 and a memory 1102. Optionally, the electronic device 110 further includes a communication component 1103. The processor 1101, the memory 1102 and the communication component 1103 are connected via a bus.

[0148] During the specific implementation process, at least one processor 1101 executes the computer-executable instructions stored in the memory 1102, so that the at least one processor 1101 executes the above-mentioned flash memory upgrade method embodiment.

[0149] The specific implementation process of the processor 1101 can be found in the above method embodiment. Its implementation principle and technical effects are similar and will not be repeated here in this embodiment.

[0150] In the above embodiments, it should be understood that the processor may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), etc. A general-purpose processor may be a microprocessor or any conventional processor. The steps of the method disclosed in the application may be directly executed by a hardware processor or by a combination of hardware and software modules within the processor.

[0151] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage.

[0152] A bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus. Buses can be categorized as address buses, data buses, and control buses. For ease of illustration, the buses in the drawings of this application are not limited to just one bus or just one type of bus.

[0153] An embodiment of the present application further provides a non-volatile computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above-mentioned flash memory upgrade method embodiments when running.

[0154] In an exemplary embodiment, the non-volatile computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0155] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps of any of the above-mentioned flash memory upgrade method embodiments are implemented.

[0156] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium, the non-volatile computer-readable storage medium storing a computer program, and when the computer program is executed by a processor, implementing the steps of any of the above-mentioned flash memory upgrade method embodiments.

[0157] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0158] The above describes in detail a logic controller, a flash memory upgrade method, a device, an electronic device, and a medium provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only intended to help understand the method and core ideas of the present application. It should be noted that, for those skilled in the art, without departing from the principles of the present application, several improvements and modifications may be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A logic controller, characterized in that: include: User flash memory, bus upgrade controller, flash memory upgrade controller, retry controller and flash memory information storage; wherein, The bus upgrade controller is connected to the management controller outside the logic controller via an integrated circuit bus, and is connected to the flash memory upgrade controller. The bus upgrade controller is used to receive an upgrade instruction sent by the management controller and send the upgrade instruction to the flash memory upgrade controller. The flash memory upgrade controller is connected to the user flash memory and the retry controller, and is used to upgrade the user flash memory according to the upgrade instruction and determine the upgrade result; The retry controller is connected to the flash memory information storage and the bus upgrade controller. If the upgrade result is an upgrade failure, the retry controller is configured to send the flash memory information stored in the flash memory information storage to the bus upgrade controller, so that the bus upgrade controller instructs the flash memory upgrade controller to perform an upgrade retry process on the user flash memory. The flash memory information storage is connected to the management controller, and the flash memory information storage is used to store the flash memory information according to the upgrade instruction.

2. The logic controller according to claim 1, characterized in that The logic controller also includes a status register; The pins of the status register are connected to the flash memory upgrade controller and the user flash memory, and the status register is used to send the upgrade result to the flash memory upgrade controller when the upgrade fails.

3. The logic controller according to claim 1, characterized in that The logic controller also includes a check controller and a check value memory; The verification controller is connected to the retry controller, the output end of the verification value memory, and the bus upgrade controller, and is configured to verify the flash memory information according to the information verification value to obtain a first verification result, and send the flash memory information to the bus upgrade controller according to the first verification result; An input end of the check value memory is connected to the bus upgrade controller. The check value memory is used to generate the information check value corresponding to the user flash memory according to the upgrade instruction and store the information check value.

4. The logic controller according to any one of claims 1 to 3, characterized in that: The logic controller also includes a configuration flash memory; The flash memory upgrade controller is connected to the configuration flash memory, and is used for performing an upgrade retry process on the configuration flash memory according to the upgrade instruction.

5. A flash memory upgrade method, characterized in that: Applicable to the logic controller according to any one of claims 1 to 4; the method comprising: receiving an upgrade instruction sent by a management controller outside the logic controller; Performing an upgrade process on the user flash memory according to the upgrade instruction and determining the upgrade result; If the upgrade result is an upgrade failure, the flash memory information stored in the flash memory information memory is sent to the bus upgrade controller via the retry controller, so that the bus upgrade controller instructs the flash memory upgrade controller to perform an upgrade retry process on the user flash memory.

6. The flash memory upgrade method according to claim 5, wherein: Upgrade the user flash memory and determine the upgrade results, including: Determining target data corresponding to the upgrade instruction stored in the user flash memory; Erasing the target data, and rewriting the data in the user flash memory according to the upgrade instruction to perform an upgrade process; The pin information of the status register is read, and the upgrade result is determined according to the pin information.

7. The flash memory upgrade method according to claim 5 or 6, characterized in that: The flash information stored in the flash information memory is sent to the bus upgrade controller through the retry controller, including: Determine the retry threshold; Determining the upgrade result by the retry controller; If the upgrade result is an upgrade failure, determining the number of upgrade retries of the user flash memory by the retry controller; If the upgraded retry count is less than or equal to the count threshold, reading stored information from the flash information memory through the retry controller, and determining the flash information corresponding to the user flash memory from the stored information; determining, by the retry controller, verification parameters of the flash memory information, the verification parameters including the flash memory corresponding to the flash memory information and / or the format of the flash memory information; Verifying the verification parameters of the flash memory information by the retry controller to obtain a verification result, wherein the verification result is verification passed or verification failed; If the verification result is verification passed, the flash memory information is sent to the bus upgrade controller through the retry controller.

8. The flash memory upgrade method according to claim 7, wherein: The logic controller further includes a configuration flash memory; if the upgrade result is an upgrade failure, the method further includes: generating a retry instruction by the retry controller; The retry controller sends the retry instruction to the bus upgrade controller, so that the bus upgrade controller sends the retry instruction to the flash memory upgrade controller to perform an upgrade retry process on the configuration flash memory.

9. The flash memory upgrade method according to claim 7, wherein: If the upgrade result is successful, the method further includes: Determine the standard calibration value; Determining original data from the user flash memory and / or the configuration flash memory, and performing calculation processing on the original data according to a verification algorithm to obtain an original verification value; Comparing the original check value with the standard check value to perform a cyclic redundancy check to obtain a second check result, where the second check result is a check pass or a check fail; If the second verification result is verification failure, an upgrade retry process is performed.

10. An electronic device, characterized in that: include: memory for storing computer programs; A processor, configured to implement the steps of the flash memory upgrade method according to any one of claims 4 to 9 when executing the computer program.

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