Method and device for obtaining multi-board-card interconnection structure

Abstract

The embodiment of the invention discloses a method and device for obtaining a multi-board-card interconnection structure. The method comprises the following steps: defining a first pin of a connector as an in-situ detection signal, and defining a second pin and a third pin as interconnection mode identification pins; the at least one connector is arranged on the board card to be identified; detecting the first pin through the detection card to judge whether a connector is inserted into the identification port of the detection card; and if a connector is inserted, detecting the second pin and the third pin through the detection card to obtain coding information, and obtaining the type of the board card to be identified according to the coding information. Compared with the prior art, the in-situ detection signal and the connection mode identification mark (namely defining the first pin, the second pin and the third pin) are added on the high-speed Serdes interconnected connector, whether the port is connected or not is determined through the acceleration card (detection card) identification signal, the board card type is further obtained through the identification mark, the complexity is low, the efficiency is high, and the method is suitable for popularization and application. And the method has relatively good expansibility.

Description

Technical Field

[0001] The present invention relates to the technical field of boards and cards, and in particular to a method and device for obtaining a multi-board interconnection structure. Background Art

[0002] In order to train complex models, a server may include multiple interconnected boards to implement multi-board parallel computing and data transmission and interaction between boards. The existing method for obtaining the interconnected structure of multiple boards is as follows:

[0003] (1) Select any board from multiple boards as a reference board;

[0004] (2) Modify the link parameters of the port of the reference board;

[0005] (3) traverse the ports of other boards to detect whether the link parameters of the ports of other boards have changed;

[0006] (4) Determine whether there is an interconnection relationship between the port where the link parameter changes and the port of the reference board, and record the interconnection relationship in a mapping table to obtain a multi-board interconnection structure.

[0007] Although the above solution solves the problem of obtaining a multi-board interconnection structure to a certain extent, it still has the following defects:

[0008] (1) Physical connection is not checked: If the physical connection of the port is not in good contact, the established interconnection relationship mapping table is inaccurate and the obtained results are also inaccurate;

[0009] (2) High complexity: The combination of modifying link parameters and traversal has high complexity and low efficiency;

[0010] (3) Poor scalability: Fixed topology models are difficult to support new connection architectures, and detection algorithms need to be redesigned. Summary of the Invention

[0011] In view of the technical deficiencies of the prior art, an object of the embodiments of the present invention is to provide a method and apparatus for obtaining a multi-board interconnection structure.

[0012] To achieve the above objectives, in a first aspect, an embodiment of the present invention provides a method for obtaining a multi-board interconnection structure, comprising:

[0013] The first pin of the connector is defined as a presence detection signal, and the second pin and the third pin are defined as interconnection mode identification pins; at least one of the connectors is provided on a board to be identified;

[0014] The detection card detects the first pin to determine whether a connector is inserted into the identification port of the detection card; wherein the detection card includes but is not limited to an AI accelerator card or an IO interconnection card;

[0015] If a connector is inserted, the second pin and the third pin are detected by the detection card to obtain coding information, and the type of the board to be identified is obtained according to the coding information.

[0016] As a specific implementation of the present application, if the first pin outputs a low level, a connector is inserted; otherwise, no connector is inserted.

[0017] As a specific implementation of the present application, when the coding information of the second pin is 0 and the coding information of the third pin is 1, the board to be identified is fully connected;

[0018] When the coding information of the second pin is 1 and the coding information of the third pin is 0, the board to be identified is connected in a ring;

[0019] When the coding information of the second pin is 0 and the coding information of the third pin is 0, the board to be identified is a two-card connection.

[0020] In a second aspect, an embodiment of the present application further provides a device for obtaining a multi-board interconnection structure, comprising:

[0021] A pin definition unit is used to define a first pin of a connector as a presence detection signal, and a second pin and a third pin as interconnection mode identification pins; at least one of the connectors is provided on a board to be identified;

[0022] a port detection unit, configured to detect the first pin by a detection card to determine whether a connector is inserted into the identification port of the detection card;

[0023] The board type identification unit is used to detect the second pin and the third pin through the detection card to obtain coding information if a connector is inserted, and obtain the type of the board to be identified according to the coding information, including full connection, loop connection or two-card connection.

[0024] By implementing an embodiment of the present invention, an in-place detection signal and a connection mode identification mark (i.e., defining the first, second, and third pins) are added to a connector for high-speed SerDes interconnection, and an accelerator card (detection card) is used to identify the signal to determine whether the port is connected. The board type is further obtained through the identification mark, which has low complexity, high efficiency, and good scalability. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the specific implementation of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for the specific implementation or the description of the prior art.

[0026] Figure 1 This is a flow chart of a method for obtaining a multi-board interconnection structure provided by an embodiment of the present invention;

[0027] Figure 2 This is a diagram of the connector plugged into the accelerator card (PCIe card);

[0028] Figure 3 This is the connector pinout diagram;

[0029] Figure 4 This is a diagram showing how the connector identifies various card types after the accelerator card (PCIe card) is inserted.

[0030] Figure 5 This is the correspondence diagram between pin ID1, ID0 and board type;

[0031] Figure 6 This is a structural diagram of a device for obtaining a multi-board interconnection structure provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0032] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0033] It will be understood that when used in this specification and the appended claims, the terms “comprises” and “comprising” indicate the presence of described features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0034] Please refer to Figure 1 , is a method for obtaining a multi-board interconnection structure provided by an embodiment of the present invention, comprising the following steps:

[0035] S1, defines the first pin of the connector as the in-position detection signal, and the second and third pins as the interconnection mode identification pins.

[0036] Wherein, at least one connector is provided on the board to be identified. Figure 2As shown in the figure, the pin definition of the interconnection card adds the in-position detection signals PRSNT0 and PRSNT1, and connects the two signals on the interconnection card, adding the interconnection mode identification pins ID0 and ID1. That is, the first and last pins are the in-position detection signals PRSNT0 and PRSNT1, the second pin is ID1, and the third pin is ID0. The schematic diagram of the pins in the connector is shown in the figure. Figure 3 shown.

[0037] S2, detecting the first pin by the detection card to determine whether a connector is inserted into the identification port of the detection card.

[0038] Among them, the detection card includes but is not limited to AI acceleration card or other boards that need to be interconnected; in this embodiment, Figure 2 As shown, the detection card is an AI accelerator card.

[0039] In specific implementation, the accelerator card (PCIe card) detects the connector presence signal PRSNT0 to identify whether a connector is inserted into the port. A high level is not in place, indicating that no connector is inserted into the accelerator card, and a low level is in place, indicating that a connector is inserted into the accelerator card.

[0040] S3, if a connector is inserted, the second pin and the third pin are detected by the detection card to obtain coding information, and the type of the board to be identified is obtained according to the coding information.

[0041] Specifically, please refer to Figure 4 and Figure 5 , detect the ID0 and ID1 pins of the connector through the accelerator card. When the encoding information of the second pin ID1 is 0 and the encoding information of the third pin ID0 is 1, the board to be identified is a fully connected LINK4FULL;

[0042] When the coding information of the second pin ID1 is 1 and the coding information of the third pin ID0 is 0, the board to be identified is a ring connection LINK4RING;

[0043] When the coding information of the second pin ID1 is 0 and the coding information of the third pin ID0 is 0, the board to be identified is the two-card connection LINK2.

[0044] It should be noted that the present invention provides two mechanisms:

[0045] Hardware-level connection verification mechanism: electrical verification of physical connections is achieved through PRSNT0 and PRSNT1 signals;

[0046] Topology self-identification mechanism: The ID pin provides topology type precoding.

[0047] The method for obtaining a multi-board interconnection structure provided by an embodiment of the present invention is implemented by adding an in-place detection signal and a connection mode identification identifier (i.e., defining the first, second, third, and last pins) to the connector of the high-speed SerDes interconnection. The accelerator card (detection card) identifies the signal to determine whether the port is connected, and the board type is further obtained through the identification identifier. This method has low complexity, high efficiency, and good scalability.

[0048] In addition, the present invention can be used in multi-card interconnection scenarios, including the interconnection topology definition of AI accelerator cards and IO interconnection cards.

[0049] Based on the same inventive concept, an embodiment of the present invention further provides a device for obtaining a multi-board interconnection structure, such as Figure 6 Shown, including:

[0050] A pin definition unit is used to define a first pin of a connector as a presence detection signal, and a second pin and a third pin as interconnection mode identification pins; at least one of the connectors is provided on a board to be identified;

[0051] a port detection unit, configured to detect the first pin by a detection card to determine whether a connector is inserted into the identification port of the detection card;

[0052] The board type identification unit is used to detect the second pin and the third pin through the detection card to obtain coding information if a connector is inserted, and obtain the type of the board to be identified according to the coding information, including full connection, loop connection or two-card connection.

[0053] Specifically, the port detection unit is specifically used to:

[0054] If the first pin outputs a low level, a connector is inserted; otherwise, no connector is inserted.

[0055] Specifically, the board type identification unit is specifically used to:

[0056] When the coding information of the second pin is 0 and the coding information of the third pin is 1, the board to be identified is fully connected;

[0057] When the coding information of the second pin is 1 and the coding information of the third pin is 0, the board to be identified is connected in a ring;

[0058] When the coding information of the second pin is 0 and the coding information of the third pin is 0, the board to be identified is a two-card connection.

[0059] It should be noted that the specific workflow of this embodiment can be found in the aforementioned method embodiment section and will not be described in detail here.

[0060] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the composition and steps of each example according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0061] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, or can be electrical, mechanical or other forms of connection.

[0062] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected according to actual needs to achieve the objectives of the embodiments of the present invention.

[0063] In addition, the functional units in the various embodiments of the present invention may be integrated into a single processing unit, each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0064] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and such modifications or substitutions are intended to be within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of protection of the claims.

Claims

1. A method for obtaining a multi-board interconnection structure, characterized in that: include: The first pin of the connector is defined as a presence detection signal, and the second pin and the third pin are defined as interconnection mode identification pins; at least one of the connectors is provided on a board to be identified; detecting the first pin by the detection card to determine whether a connector is inserted into the identification port of the detection card; If a connector is inserted, the second pin and the third pin are detected by the detection card to obtain coding information, and the type of the board to be identified is obtained according to the coding information.

2. The method for obtaining a multi-board interconnection structure according to claim 1, wherein: The detection card includes an AI acceleration card or an IO interconnection card.

3. The method for obtaining a multi-board interconnection structure according to claim 1, wherein: The detection card detects the first pin to determine whether a connector is inserted into the identification port of the detection card, specifically: If the first pin outputs a low level, a connector is inserted; otherwise, no connector is inserted.

4. The method for obtaining a multi-board interconnection structure according to claim 1, wherein: When the coding information of the second pin is 0 and the coding information of the third pin is 1, the board to be identified is fully connected; When the coding information of the second pin is 1 and the coding information of the third pin is 0, the board to be identified is connected in a ring; When the coding information of the second pin is 0 and the coding information of the third pin is 0, the board to be identified is a two-card connection.

5. A device for obtaining a multi-board interconnection structure, characterized in that: include: A pin definition unit is used to define a first pin of a connector as a presence detection signal, and a second pin and a third pin as interconnection mode identification pins; at least one of the connectors is provided on a board to be identified; a port detection unit, configured to detect the first pin by a detection card to determine whether a connector is inserted into the identification port of the detection card; The board type identification unit is used to detect the second pin and the third pin through the detection card if a connector is inserted to obtain coding information, and obtain the type of the board to be identified according to the coding information.

6. The device for obtaining a multi-board interconnection structure according to claim 5, wherein: The detection card includes an AI acceleration card or an IO interconnection card.

7. The device for obtaining a multi-board interconnection structure according to claim 5, wherein: The port detection unit is specifically used for: If the first pin outputs a low level, a connector is inserted; otherwise, no connector is inserted.

8. The device for obtaining a multi-board interconnection structure according to claim 5, wherein: The board type identification unit is specifically used for: When the coding information of the second pin is 0 and the coding information of the third pin is 1, the board to be identified is fully connected; When the coding information of the second pin is 1 and the coding information of the third pin is 0, the board to be identified is connected in a ring; When the coding information of the second pin is 0 and the coding information of the third pin is 0, the board to be identified is a two-card connection.

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