Testing machine and resource board card thereof

Abstract

The invention relates to a testing machine and a resource board card thereof, the resource board card comprises a first processing device and more than two second processing devices, the first processing device comprises a first synchronous control module and a first processing module, and the first synchronous control module receives a clock signal output by a control board card for a first preset duration and then sends the clock signal to the second processing device; controlling the first processing module to start, performing graph generation processing after the first processing module is started, and outputting corresponding data; each second processing device comprises a second synchronous control module and a second processing module, the second synchronous control module controls the second processing module to be started after receiving the clock signal output by the control board card for a second preset duration, and the second processing module obtains the data output by the first processing module for processing after being started. And outputting the test signal to the to-be-tested device. Synchronous signal processing between different second processing devices can be realized, it is ensured that test signals output by the second processing devices are synchronous, and the test reliability of the test machine is improved.

Description

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on May 17, 2024, with application number 202421095386.4, and invention name “Testing Machine and Resource Board Thereof”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present application relates to the field of semiconductor testing technology, and in particular to a testing machine and a resource board thereof. Background Art

[0003] Semiconductor automated testing refers to the use of automatic test equipment (ATE) to inspect various parameters of devices under test (DUTs), eliminating defective products and controlling the quality of semiconductor devices before they leave the factory. The resource board of the tester must be capable of testing at least one device. FPGAs (Field-Programmable Gate Arrays) are typically used in resource boards to implement the required test functions. However, the resources of a single FPGA chip are limited, and implementing all test functions on a single FPGA chip means that the cost will increase exponentially. Therefore, multiple low-cost FPGAs are often used as functional modules to jointly implement test functions, which helps reduce costs. However, how to coordinate the control between the various functional modules to improve the test reliability of the tester is an urgent problem that needs to be solved. Summary of the Invention

[0004] Based on this, it is necessary to provide a test machine and its resource board that can improve test reliability in order to address the above problems.

[0005] In a first aspect, the present application provides a resource board for a test machine, comprising:

[0006] The first processing device includes a first synchronization control module and a first processing module, wherein the first synchronization control module is connected to the first processing module and the control board, and controls the first processing module to start after receiving a clock signal of a first preset duration output by the control board. After starting, the first processing module performs a graphics generation process and outputs corresponding data;

[0007] There are more than two second processing devices, each of which includes a second synchronization control module and a second processing module; in each second processing device, the second synchronization control module is connected to the control board and the second processing module, and the second processing module is connected to the first processing module and the device to be tested; after receiving the second preset duration of the clock signal output by the control board, the second synchronization control module controls the start-up of the second processing module, and after starting, the second processing module obtains the data output by the first processing module for processing and outputs a test signal to the device to be tested.

[0008] In one embodiment, the first synchronization control module includes a first pre-synchronization module and a first phase-locked loop, the first pre-synchronization module is connected to the first phase-locked loop and the first processing module, and the first phase-locked loop is connected to the control board and the first processing module;

[0009] The first phase-locked loop is used to receive the clock signal and control signal transmitted by the control board, start working according to the received control signal, process the received clock signal and output the working clock; the first pre-synchronization module is used to obtain the synchronization count value based on the clock signal, and transmit the synchronization count value to the first processing module. The first processing module starts the graphics generation processing when the synchronization count value is the first preset time length.

[0010] In one embodiment, the first processing module includes a first algorithm graph generation module and a first counter, the first algorithm graph generation module is connected to the first phase-locked loop, the first pre-synchronization module and the first counter, and the first counter is connected to the second processing module;

[0011] After the first phase-locked loop receives the clock signal output by the control board for a first preset duration, the first pre-synchronization module controls the first algorithm graph generation module to start; after the first algorithm graph generation module is started, it performs the corresponding graph generation processing function according to the working clock output by the first phase-locked loop, and generates data to be transmitted to the first counter; the first counter starts timing after detecting the output data of the first algorithm graph generation module, and outputs the data to the second processing module after timing to the set timing duration.

[0012] In one embodiment, the first algorithm graph generation module includes a sequence controller connected to the first phase-locked loop, an address processing module, a data processing module, and a signal physical mapping module, wherein the sequence controller is connected to the address processing module and the data processing module, and the signal physical mapping module is connected to the address processing module, the data processing module, and the first counter;

[0013] The sequence controller is used to send data signals and control signals to the address processing module and the data processing module; the address processing module is used to select the original address from the data signal for processing based on the received control signal, and output the processed address information to the signal physical mapping module; the data processing module is used to select the original data from the data signal for processing based on the received control signal, and output the processed data information to the signal physical mapping module; the signal physical mapping module is used to select the specified physically mapped address and data from the processed address information and the processed data information based on the received control signal, and output them to the first counter.

[0014] In one embodiment, the signal physical mapping module controls each bit to select the data and address processed by the address processing module and the data processing module according to the received control signal, or the configuration data sent by the sequence controller for physical mapping, and the physical mapped address and data of the fixed bit are output to the first counter.

[0015] In one embodiment, the first algorithm graph generation module further includes a comparison enable parameter delay module and an output enable parameter delay module connected to the first phase-locked loop, the sequence controller is further connected to the comparison enable parameter delay module and the output enable parameter delay module, the comparison enable parameter delay module is connected to the first counter, and the output enable parameter delay module is connected to the first counter;

[0016] The output enable parameter delay module is used to delay the output enable parameter issued by the sequence controller and transmit it to the first counter; the comparison enable parameter delay module is used to delay the comparison enable parameter issued by the sequence controller and transmit it to the first counter; the physically mapped address and data, the delayed output enable parameter and the delayed comparison enable parameter are synchronously transmitted to the first counter.

[0017] In one embodiment, the address processing module includes an original address source selection module, an address calculation module, a verification module, and a first delay module, all of which are connected to the first phase-locked loop and are connected in sequence, the original address source selection module is connected to the sequence controller, and the first delay module is connected to the signal physical mapping module;

[0018] The original address source selection module selects a specified bit from the data signal as the original address according to the received control signal; the address operation module performs an operation on the original address and the data signal sent by the sequence controller according to the received control signal to obtain a calculated address; the verification module selects a verification rule according to the received control signal, verifies the calculated address according to the selected verification rule, and outputs the verification result and the calculated address to the signal physical mapping module after being delayed by the first delay module;

[0019] The original address source selection module, the address calculation module, the verification module and the first delay module all receive the output data of the previous module and the control signal sent by the sequence controller at the same time, and perform corresponding processing on the output data of the previous module based on the received control signal.

[0020] In one embodiment, the data processing module includes an original data source selection module, a data operation module, a flip module, a CRC check module, and a second delay module, all of which are connected to the first phase-locked loop and are connected in sequence, the original data source selection module is connected to the sequence controller, and the second delay module is connected to the signal physical mapping module;

[0021] The original data source selection module selects a specified bit from the data signal as the original data according to the received control signal; the data operation module performs an operation on the original data and the data signal sent by the sequence controller according to the received control signal to obtain the calculated data; the flip module performs a logic value flip on the specified position of the calculated data according to the received control signal to obtain the flipped data; the CRC check module selects a CRC check rule according to the received control signal, performs a CRC operation on the flipped data according to the selected CRC check rule, and sends the output CRC check result to the signal physical mapping module after delay by the second delay module;

[0022] The original data source selection module, the data operation module, the flip module, the CRC check module and the second delay module all receive the output data of the previous module and the control signal issued by the sequence controller at the same time, and perform corresponding processing on the output data of the previous module based on the received control signal.

[0023] In one embodiment, the second synchronization control module includes a second pre-synchronization module and a second phase-locked loop, and the second phase-locked loop is connected to the second pre-synchronization module, the second processing module and the control board;

[0024] The second phase-locked loop receives the clock signal and control signal sent by the control board, starts working according to the received control signal, processes the received clock signal and outputs the working clock to the second processing module and the second pre-synchronization module. The second pre-synchronization module is used to obtain a synchronization count value based on the working clock, and when the synchronization count value reaches a second preset time length, controls the start of the operation of the second processing module.

[0025] In one embodiment, the second processing module includes a cache unit, a second counter, a second algorithm graph generation module and a timing module connected in sequence, the cache unit is connected to the first processing module, and the cache unit, the second counter, the second algorithm graph generation module and the timing module are all connected to the second phase-locked loop; after the second phase-locked loop outputs the working clock for a second preset duration, the second pre-synchronization module outputs a start instruction to the second counter, controls the start of the second counter, and reads the data of the cache unit to the second algorithm graph generation module.

[0026] In one embodiment, the second synchronization control module includes a second pre-synchronization module and a second phase-locked loop, the second phase-locked loop is connected to the second pre-synchronization module, the second processing module and the control board; the second processing module includes a cache unit, a second counter, a second algorithm graph generation module and a timing module connected in sequence, the cache unit is connected to the first processing module, the cache unit, the second counter, the second algorithm graph generation module and the timing module are all connected to the second phase-locked loop, and the second pre-synchronization module is also connected to the cache unit;

[0027] The second pre-synchronization module starts timing when it detects that the data in the cache unit is not empty, and starts the second counter to read data from the cache unit after timing to the second preset time. The second counter sends the read data to the second algorithm graph generation module for corresponding processing.

[0028] In one embodiment, the second algorithm graph generation module includes an output enable data module, a comparison enable data module, a graph data storage module, and a multiplexer, all of which are connected to the second phase-locked loop; the output enable data module and the comparison enable data module are both connected to the second counter; and the multiplexer is connected to the second counter, the output enable data module, the comparison enable data module, the graph data storage module, and the timing module;

[0029] The output enable data module selects output enable data from preset data according to the output enable parameter output by the second counter and sends the data to the multiplexer;

[0030] The comparison enable data module selects comparison enable data from preset data according to the comparison enable parameter output by the second counter and sends the data to the multiplexer;

[0031] The multiplexer is used to output the output enable data, the comparison enable data, and the physically mapped address and data output by the second counter as calculated graphic data to the timing module, or to output the graphic data preset in the graphic data storage module to the timing module.

[0032] In one embodiment, the preset data stored in the output enable data module includes a PIN output enable preset table, and the preset data stored in the comparison enable data module includes a comparison enable preset table;

[0033] The output enable data module selects the output enable data of the corresponding row from the PIN output enable preset table according to the output enable parameter and sends it to the multiplexer;

[0034] The comparison enable data module selects the comparison enable data of a corresponding row from the comparison enable preset table according to the comparison enable parameter and sends the selected data to the multiplexer.

[0035] In one embodiment, the preset data stored in the output enable data module further includes custom PIN output enable data, and the preset data stored in the comparison enable data module further includes custom PIN comparison enable data;

[0036] The output enable data module also replaces part of the PIN in the output enable data of the selected corresponding row with the custom PIN output enable data according to the output enable parameter, and then sends it to the multiplexer;

[0037] The comparison enable data module also replaces part of the PIN in the comparison enable data of the selected corresponding row with the custom PIN comparison enable data according to the comparison enable parameter, and then sends it to the multiplexer.

[0038] In one embodiment, the timing module includes a waveform synthesis module, a timing control module, a timing generation module and a comparison module, all of which are connected to the second phase-locked loop. The waveform synthesis module, the timing control module and the timing generation module are connected in sequence. The waveform synthesis module is connected to the multiplexer, the timing generation module is connected to the device to be tested, and the comparison module is connected to the multiplexer and the timing generation module.

[0039] The second aspect of the present application provides a testing machine, including a control board and the above-mentioned resource board; the number of the resource boards is more than two, each of the resource boards is connected to the control board, and each of the resource boards is respectively connected to the corresponding device to be tested, and the first pre-synchronization module in each of the resource boards realizes the synchronization of data processing between different resource boards.

[0040] The above-mentioned test machine and its resource board include a first processing device and two or more second processing devices. The first processing device includes a first synchronization control module and a first processing module. The first synchronization control module is connected to the first processing module and the control board. After receiving a clock signal output by the control board for a first preset duration, it controls the first processing module to start up. After starting up, the first processing module performs graphic generation processing and outputs corresponding data. Each second processing device includes a second synchronization control module and a second processing module. In each second processing device, the second synchronization control module is connected to the control board and the second processing module, and the second processing module is connected to the first processing module and the device under test. The second synchronization control module controls the second processing module to start up after receiving a clock signal output by the control board for a second preset duration. After starting up, the second processing module obtains the data output by the first processing module for processing and outputs a test signal to the device under test. The synchronization control module controls the start-up of related processing modules according to the clock signal output by the control board, thereby achieving synchronous signal processing between different second processing devices, ensuring that the test signals output by each second processing device are synchronized, and improving the test reliability of the test machine. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 A structural block diagram of a resource board of a test machine in one embodiment;

[0042] Figure 2 A schematic diagram of the resource board structure of a test machine in one embodiment;

[0043] Figure 3 1 is a schematic diagram of the structure of a first algorithm graph generation module and a second algorithm graph generation module in one embodiment. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0046] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if there is transmission of electrical signals or data between the connected circuits, modules, units, etc.

[0047] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Furthermore, the term "and / or" as used in this specification includes any and all combinations of the relevant listed items.

[0048] In one embodiment, Figure 1 As shown, a resource board 100 of a test machine is provided, including a first processing device 110 and two or more second processing devices 120. The first processing device 110 includes a first synchronization control module 112 and a first processing module 114. The first synchronization control module 112 is connected to the first processing module 114 and the control board 200. After receiving the first preset duration of the clock signal output by the control board 200, the first processing module 114 is controlled to start. After starting, the first processing module 114 performs graphics generation processing and outputs corresponding data. Each second processing device 120 includes a second synchronization control module 122 and a second processing module 124. In each second processing device 120, the second synchronization control module 122 is connected to the control board 200 and the second processing module 124, and the second processing module 124 is connected to the first processing module 114 and the device under test DUT; after receiving the second preset duration of the clock signal output by the control board 200, the second synchronization control module 122 controls the second processing module 124 to start, and after starting, the second processing module 124 obtains the data output by the first processing module 114 for processing, and outputs a test signal to the device under test DUT.

[0049] Among them, the first synchronous control module 112 and the second synchronous control module 122 can start timing synchronously after receiving the clock signal output by the control board 200. The second preset time length is the sum of the first preset time length and the set delay value. The specific values ​​of the first preset time length and the set delay value are not unique and can be selected according to actual needs. Specifically, the set delay value is set according to the signal transmission delay between the first processing device 110 and the second processing device 120. After the first preset time length is reached, the first synchronous control module 112 controls the first processing module 114 to start graphics generation processing and output data to the second processing module 124. After the second preset time length is reached, the second synchronous control module 122 controls the second processing module 124 to start, continue to process the data output by the first processing module 114, and output the test signal to the device under test DUT. The first processing device 110 and the second processing device 120 can be FPGA (Field-Programmable Gate Array) or other types of processing devices. The number of second processing devices 120 can be two or more. As Figure 2 As shown, in this embodiment, there are two second processing devices 120, namely FPGA_0 and FPGA_1, and the first processing device 110 is FPGA_2. The first processing device 110 and the second processing device 120 are located on the same board. After the control board 200 outputs a clock signal, the three FPGAs will start operating synchronously. In other embodiments, the first processing device 110 and the second processing device 120 can also be located on different daughter boards.

[0050] By controlling the board 200 to output clock signals and control signals to the first processing device 110 and the second processing device 120, the first synchronization control module 112 / the second synchronization control module 122 synchronously counts according to the clock signals and controls the start-up of the first processing module 114 / the second processing module 124, thereby achieving synchronous start-up of the first processing device 110 and each second processing device 120. The test signals output by different second processing devices 120 during operation are synchronized, so as to perform parameter testing on the device under test (DUT) and ensure reliable testing.

[0051] It is understood that in other embodiments, the first synchronization control module 112 may start timing after receiving the clock signal output by the control board 200, and the second synchronization control module 122 may not start timing first. The value of the second preset time length has nothing to do with the first preset time length, and is mainly set according to the signal transmission delay between the first processing device 110 and the second processing device 120. For example, it can be directly set to a set delay value. After the first preset time length is reached, the first synchronization control module 112 controls the first processing module 114 to start graphics generation processing and output data to the second processing module 124. After the second processing module 124 receives data, the second synchronization control module 122 starts timing based on the clock signal output by the control board 200. After the timing reaches the second preset time length, it controls the second processing module 124 to start, continue processing the data output by the first processing module 114, and output a test signal to the device under test DUT.

[0052] Furthermore, after the first processing module 114 and the second processing module 124 are started, the actual data processing content performed is not unique. Specifically, a resource board 100 can meet the test resources required for the test of a device under test (DUT), that is, all the functions required for the test of a device under test (DUT). The first processing module 114 and the second processing module 124 respectively contain part of the test resources required for the test of the device under test (DUT), that is, part of the functions required for the test of the device under test (DUT). In order to realize the parameter test of the device under test (DUT), the resource board 100 needs to have functional modules such as a data source module, a waveform synthesis module, a timing control module, and a timing generation module. Among them, the data source module can be ALPG (Algorithmic Pattern Generator) or PG (Pattern Generator). The waveform synthesis module is used to synthesize the format of the waveform according to the set format. Commonly used waveform formats include NRZ\RZ\XORBC, etc. The timing control module calculates and analyzes the delay time of the timing generation module based on the set transmission signal edge position and sampling position. The timing generation module then controls the signal edge position and sampling position to achieve timing-compliant signal transmission and input signal sampling. The timing generation module delays the input signal and is implemented using hardware circuits, such as the FPGA's internal IDELAY, ODELAY, or CARRY or a separate delay chain chip.

[0053] Taking the ALPG module as an example, the data source module may include an ALU (data arithmetic unit), a PARITY (parity operation unit), a CPE (compare enable switch), a DEBUG (debug module), and so on. During testing, the first processing module 114 may include the complete ALPG module functionality, performing complete pattern generation processing and outputting pattern data (pattern) to the second processing module 124. The second processing module 124 then performs waveform synthesis, timing control, and timing generation based on the pattern data. Alternatively, the first processing module 114 may include partial ALPG module functionality, performing partial pattern generation processing and outputting the processed data to the second processing module 124. The second processing module 124 then executes the remaining ALPG module functionality to generate pattern data and then performs waveform synthesis, timing control, and timing generation based on the pattern data. It can be understood that both of these approaches distribute the required testing functions across different FPGAs, reducing the resource requirements of a single FPGA and the risk of timing violations. Multiple low-cost FPGAs can be used to implement the tester's functions, thereby lowering testing costs.

[0054] In one embodiment, Figure 2 As shown, the first synchronization control module 112 includes a first pre-synchronization module TB1 and a first phase-locked loop PLL1. The first pre-synchronization module TB1 connects the first phase-locked loop PLL1 and the first processing module 114. The first phase-locked loop PLL1 connects the control board 200 and the first processing module 114. The first phase-locked loop PLL1 is used to receive the clock signal and control signal transmitted by the control board 200, start working according to the received control signal, process the received clock signal and output the working clock. The first pre-synchronization module TB1 is used to obtain a synchronization count value based on the clock signal and transmit the synchronization count value to the first processing module 114. The first processing module 114 starts when the synchronization count value reaches a first preset time length and performs graphic generation processing. Specifically, the first pre-synchronization module TB1 beats according to the rising edge / falling edge of the clock signal to calculate the synchronization count value.

[0055] Furthermore, the first processing module 114 includes a first algorithm pattern generation module ALPG_1 and a first counter Cycle_1. The first algorithm pattern generation module ALPG_1 is connected to the first phase-locked loop (PLL) 1, the first pre-synchronization module TB1, and the first counter Cycle_1. The first counter Cycle_1 is connected to the second processing module 124. The first algorithm pattern generation module ALPG_1 includes most of the algorithm pattern generation functions, such as the ALU and PARITY functions, which are used to generate physical addresses, physical data, and control words for the service modules (ALPG_2, timing) in ALPG_2. The first pre-synchronization module TB1 controls the start, pause, and stop of the first algorithm pattern generation module ALPG_1. After the first phase-locked loop (PLL) 1 receives a clock signal output by the control board 200 for a first preset duration, the first pre-synchronization module TB1 controls the start of the first algorithm pattern generation module ALPG_1. After startup, the first algorithm pattern generation module ALPG_1 performs corresponding pattern generation processing functions based on the operating clock output by the first phase-locked loop (PLL) 1, generating data that is transmitted to the first counter Cycle_1. The first counter, Cycle_1, begins timing after detecting data output from the first algorithm and pattern generation module, ALPG_1, and outputs the data to the second processing module, 124, after reaching a set timing duration. The set timing duration is not unique and can be set based on actual needs. For example, the data size transmitted to the second processing module, 124, can be set to 5MB or other specifications, with the set timing duration determined based on the size of the data to be transmitted. When the set timing duration is reached, the first algorithm and pattern generation module, ALPG_1, is deemed to have generated the data to be transmitted, and the first counter, Cycle_1, begins data transmission, ensuring the integrity of the data.

[0056] It is understood that the number of first counters Cycle_1 will vary depending on the number of second processing devices 120. For example, if there are two second processing devices 120, there will also be two first counters Cycle_1. Each first counter Cycle_1 is connected to the first algorithm graph generation module ALPG_1, and each first counter Cycle_1 is connected to a second processing module 124 in the second processing device 120.

[0057] Each first counter, Cycle_1, has the same set timing duration. The first algorithm pattern generation module ALPG1 simultaneously transmits output data to each first counter, Cycle_1. Upon receiving the output data, the first counter, Cycle_1, begins timing. After the count reaches the set timing duration, the first counter, Cycle_1, synchronously transmits the data to the corresponding second processing module 124 in the second processing device 120. In other embodiments, the first processing module 114 may include only one first counter, Cycle_1. After the first counter, Cycle_1, reaches the set timing duration, the data output by the first algorithm pattern generation module ALPG_1 is simultaneously transmitted to each second processing module 124.

[0058] Specifically, the graphic data required for each test item includes multiple lines of data, each with an execution time. The execution time is the duration of each line of data. The set timing duration for each line of data can be determined based on the corresponding execution time; for example, the set timing duration can be less than or equal to the execution time. If the set timing duration is less than the execution time, the second processing module 124 can use a corresponding feedback mechanism to tell the first counter Cycle_1 to pause or resume transmission when data congestion occurs. Accordingly, when congestion occurs at the first counter Cycle_1, feedback can be sent to the first algorithm and graph generation module ALPG1 (an internal sequence controller) to suspend the generation of graphic data. The first counter Cycle_1 begins timing after receiving the current line of data. After the set timing duration corresponding to the current line of data is reached, the first counter Cycle_1 sends the current line of data to the second processing module 124. The timing of each generated line of data by the first counter Cycle_1 is sequentially transmitted to the second processing module 124, allowing the second processing module 124 to process the received line of data promptly and avoiding data congestion within the second processing module 124.

[0059] In one embodiment, referring to Figure 2 The second synchronization control module 122 includes a second pre-synchronization module TB2 and a second phase-locked loop PLL2. The second phase-locked loop PLL2 is connected to the second pre-synchronization module TB2, the second processing module 124, and the control board 200. The second phase-locked loop PLL2 receives the clock signal and control signal sent by the control board 200, starts working according to the received control signal, processes the received clock signal, and outputs the working clock Clk to the second processing module 124 and the second pre-synchronization module TB2. The second pre-synchronization module TB2 is used to obtain a synchronization count value based on the working clock Clk, and control the start of the operation of the second processing module 124 when the synchronization count value reaches a second preset time length. Specifically, the second pre-synchronization module TB2 beats according to the rising edge / falling edge of the clock signal to calculate the synchronization count value.

[0060] Furthermore, the second processing module 124 includes a cache unit, a second counter Cycle_2, a second algorithm graph generation module ALPG_2, and a timing module 1242, which are connected in sequence. The timing module 1242 is connected to the device under test (DUT). The cache unit is connected to the first processing module 114 and is used to receive and store data output by the first processing module 114. The cache unit can specifically be a FIFO (First Input First Output) unit. The cache unit, the second counter Cycle_2, the second algorithm graph generation module ALPG_2, and the timing module 1242 are all connected to the second phase-locked loop (PLL) 2 and receive the operating clock output by the second phase-locked loop (PLL) 2. The set value of the second counter Cycle_2 determines the time when the second algorithm graph generation module ALPG_2 retrieves the stored data from the cache unit. The second algorithm graph generation module ALPG_2 includes the waveform generation and processing functions for the algorithm graph generation. It outputs the waveform data to the timing module 1242 for processing, and then generates a test signal that is sent to the device under test (DUT).

[0061] Because the signals generated by FPGA1 and FPGA0 take different amounts of time to be transmitted to the device under test (DUT), a time difference is required to ensure that the signals generated by FPGA1 and FPGA0 reach the DUT simultaneously. This time difference is compensated for by the time difference in the start-up instructions output by the second pre-synchronization module TB2 within FPGA1 and FPGA0. Specifically, the second pre-synchronization module TB2 can control the activation of the second counter Cycle_2. After the second phase-locked loop (PLL2) outputs the operating clock Clk for a second preset duration, the second pre-synchronization module TB2 outputs a start instruction to the second counter Cycle_2, controlling the activation of the second counter Cycle_2 and reading the data from the cache unit to the second algorithm graph generation module ALPG_2. This prevents timing gaps caused by the cache unit being read empty, thereby ensuring data read integrity. It is understood that the start instruction output by the second pre-synchronization module TB2 can be transmitted to the second counter Cycle_2 after passing through the second phase-locked loop (PLL2). In other embodiments, the second pre-synchronization module TB2 may also be directly connected to the second counter Cycle_2 to transmit a start instruction to the second counter Cycle_2.

[0062] In other embodiments, the second pre-synchronization module TB2 starts timing after detecting that the data in the cache unit is not empty. For example, the second pre-synchronization module TB2 is also connected to the cache unit. When the cache unit receives data output by the first processing module 114, the cache unit outputs a non-empty signal to the second pre-synchronization module TB2, and the second pre-synchronization module TB2 starts timing. After the timing reaches the set delay value, it is considered that the cache unit has received the data. The second pre-synchronization module TB2 activates the second counter Cycle_2 to read data from the cache unit to avoid timing gaps caused by the cache unit being read empty. The read data is sent to the second algorithm graph generation module ALPG_2 for corresponding processing to ensure data read integrity and synchronize the activation of the second algorithm graph generation module ALPG_2 in each second processing module 124.

[0063] It is understood that the specific functions and internal structures of the first algorithm graph generation module ALPG1 and the second algorithm graph generation module ALPG_2 are not unique. The full functionality of the ALPG can be distributed between the first algorithm graph generation module ALPG1 and the second algorithm graph generation module ALPG_2, respectively, as needed. The functional modules within the first algorithm graph generation module ALPG1 are connected to the first phase-locked loop (PLL) 1 and execute corresponding processing functions based on the operating clock output by the first phase-locked loop (PLL) 1. The functional modules within the second algorithm graph generation module ALPG_2 are connected to the second phase-locked loop (PLL) 2 and execute corresponding processing functions based on the operating clock output by the second phase-locked loop (PLL) 2.

[0064] In one embodiment, Figure 3 As shown, the first algorithm graph generation module ALPG1 includes a sequence controller 310, an address processing module 320, a data processing module 330, and a signal physical mapping module PDM connected to the first phase-locked loop PLL1. The sequence controller 310 is connected to the address processing module 320 and the data processing module 330, and the signal physical mapping module PDM is connected to the address processing module 320, the data processing module 330, and the first counter Cycle_1. The sequence controller 310 is configured to send data signals and control signals to the address processing module 320 and the data processing module 330. The address processing module 320 is configured to select the original address from the data signal based on the received control signal, process it, and output the processed address information to the signal physical mapping module PDM. The data processing module 330 is configured to select the original data from the data signal based on the received control signal, process it, and output the processed data information to the signal physical mapping module PDM. The signal physical mapping module PDM is configured to select the specified physically mapped address and data from the processed address and data information based on the received control signal, and output it to the first counter Cycle_1.

[0065] Furthermore, the sequence controller 310 is also connected to the first pre-synchronization module TB1 and the signal physical mapping module PDM. After receiving the start signal from the first pre-synchronization module TB1, it sends data signals and control signals to the address processing module 320 and the data processing module 330, and sends control signals and configuration data (including address and data) to the signal physical mapping module PDM. The physically mapped address and data output by the signal physical mapping module PDM are data of a fixed bit length. The signal physical mapping module PDM controls each bit based on the received control signal to select the data and address processed by the address processing module 320 and the data processing module 330, or the configuration data sent by the sequence controller 310 for physical mapping, thereby forming a fixed bit of physically mapped address and data output to the first counter Cycle_1. In addition, the sequence controller 310 also sets the time interval for sending different control signals based on the time it takes for the address processing module 320, the data processing module 330, and the signal physical mapping module PDM to process data, so that the address processing module 320, the data processing module 330, and the signal physical mapping module PDM all receive the output data of the previous module and the control signal sent by the sequence controller 310 at the same time, and perform corresponding processing on the output data of the previous module based on the received control signal. It is understandable that the sequence controller 310 can also output the control signals of each module at the same time, and each control signal is delayed through the corresponding transmission path to ensure that the control signal received by each functional module and the output data of the previous module arrive at the same time.

[0066] Specifically, the sequence controller 310 is connected to the address processing module 320, the data processing module 330, and the signal physical mapping module PDM through corresponding channels, and generates data signals and control signals according to the actual test items and sends them to the corresponding modules. Among them, the address processing module 320 includes an original address source selection module 321, an address calculation module 322, a verification module 323, and a first delay module 324 connected in sequence. The original address source selection module 321, the address calculation module 322, the verification module 323, and the first delay module 324 are all connected to the first phase-locked loop PLL1 and the sequence controller 310. The original address source selection module 321 is connected to the sequence controller 310, and the first delay module 324 is connected to the signal physical mapping module PDM. The original address source selection module 321 is configured to select a specified bit from the data signal sent by the sequence controller 310 as the original address in accordance with the control signal sent by the sequence controller 310. The address calculation module 322 is configured to perform a calculation operation, such as addition, subtraction, multiplication, division, or exclusive-OR, on the original address and the data signal sent by the sequence controller 310 in accordance with the control signal sent by the sequence controller 310 to obtain a calculated address. The verification module 323 is configured to select a verification rule in accordance with the control signal sent by the sequence controller 310 and verify the calculated address according to the selected verification rule (e.g., an even parity rule). The output verification result and the calculated address are then delayed by the first delay module 324 and sent to the signal physical mapping module PDM. The original address source selection module 321, the address calculation module 322, the verification module 323, and the first delay module 324 all simultaneously receive the output data of the previous module and the control signal sent by the sequence controller 310, and perform corresponding processing on the output data of the previous module based on the received control signal.

[0067] Furthermore, the data processing module 330 includes a raw data source selection module 331, a data calculation module 332, a flip module 333, a CRC check module 334, and a second delay module 335, which are connected in sequence. The raw data source selection module 331, the data calculation module 332, the flip module 333, the CRC check module 334, and the second delay module 335 are all connected to the first phase-locked loop PLL1 and the sequence controller 310. The raw data source selection module 331 is connected to the sequence controller 310, and the second delay module 335 is connected to the signal physical mapping module PDM. The original data source selection module 331 is used to select a specified bit from the data signal sent by the sequence controller 310 as the original data according to the control signal sent by the sequence controller 310; the data operation module 332 is used to perform operations such as addition, subtraction, multiplication, division, and XOR on the original data and the data signal sent by the sequence controller 310 according to the control signal sent by the sequence controller 310 to obtain the calculated data; the flip module 333 is used to flip the logic value of the specified position (specified bit / area / bus) of the calculated data according to the control signal (specified bit / address area / bus) sent by the sequence controller 310 to obtain the flipped data. Among them, the specified bit is used to specify which bits to flip, the specified address area is used to specify which address field to flip, and the specified bus is used to specify that the entire bus is flipped. When the specified address area is flipped, the flip module 333 is also connected to the address operation module 322, and combined with the calculated address output by the address operation module 322, the corresponding address area in the calculated data is flipped. The CRC check module 334 is used to select a CRC check rule (including not performing a CRC operation) according to the control signal sent by the sequence controller 310, and perform a CRC operation on the flipped data output by the flip module 333 according to the selected CRC check rule. The output CRC check result is sent to the signal physical mapping module PDM after being delayed by the second delay module 335. The CRC check result includes the check result and, depending on the check rule, also includes or partially includes the flipped data. The original data source selection module 331, the data operation module 332, the flip module 333, the CRC check module 334, and the second delay module 335 all receive the output data of the previous module and the control signal sent by the sequence controller 310 at the same time, and perform corresponding processing on the output data of the previous module based on the received control signal.

[0068] The address and data signals are delayed by the first delay module 324 and the second delay module 335 to ensure that the address and data signals transmitted to the signal physical mapping module PDM at the same time correspond to the control signal and configuration data sent by the sequence controller 310. The signal physical mapping module PDM is used to select specified bits from the check result, the address after calculation, the CRC check result and the configuration data according to the control signal sent by the sequence controller 310, and output them as the address and data after physical mapping to the first counter Cycle_1. Among them, the sequence controller 310 sends the configuration data and the control signal together to the signal physical mapping module PDM. According to the control signal, the signal physical mapping module PDM can select the check result, the address after calculation and the CRC check result as the address and data after physical mapping, or select the address and data after physical mapping from the configuration data. It supports parameter configuration from the pre-set configuration data according to actual needs, which is convenient for testing. In this embodiment, the check result is an even check result.

[0069] It can be understood that the functions performed by each of the above modules are different, so the control signals sent by the sequence controller 310 to each module are also different. Each module performs a corresponding function based on the control signal it receives. For example, the check module 323 selects a check rule based on the received control signal to check the calculated address, and the CRC check module 334 selects a CRC check rule based on the received control signal to perform a CRC operation on the flipped data. Specifically, the original address source selection module 321, the address calculation module 322, the check module 323, the first delay module 324, the original data source selection module 331, the data calculation module 332, the flip module 333, the CRC check module 334, and the second delay module 335 are all directly connected to the sequence controller 310 to receive the control signal sent by the sequence controller 310. The signal physical mapping module PDM is directly connected to the sequence controller 310 to receive the control signal and configuration data sent by the sequence controller 310. When the sequence controller 310 sends control signals to each module (and also sends configuration data to the signal physical mapping module PDM at the same time), it can also set the time interval for sending different control signals according to the time it takes for each module to process data, so that each module can simultaneously receive the output data of the previous module and the control signal sent by the sequence controller 310, and perform corresponding processing on the output data of the previous module based on the control signal.

[0070] In addition, when the sequence controller 310 sends control signals according to time intervals, the original address source selection module 321, the address calculation module 322, the check module 323, the first delay module 324, the original data source selection module 331, the data calculation module 332, the flip module 333, the CRC check module 334 and the second delay module 335 do not need to be directly connected to the sequence controller 310, but can be connected according to the time intervals. Figure 3 In the serial connection relationship, the sequence controller 310 transfers the control signals required by different modules in serial and transmits them to each module in sequence according to the corresponding time intervals.

[0071] It can be understood that in other embodiments, when the sequence controller 310 sends control signals to each module at the same time, the control signal of each module can be transmitted to the corresponding module after being delayed through the corresponding path, or the control signal of each module can be transmitted serially and delayed through the internal modules of the address processing module 320 / data processing module 330, and the control signals and data signals required by the subsequent modules are delayed by the time required for processing by the modules at this level, and then sent to the subsequent modules, so that different modules can receive the output data and corresponding control signals of the previous module at the same time.

[0072] In one embodiment, referring to Figure 3 The first algorithm graph generation module ALPG1 also includes an output enable (DRE) parameter delay module 340 and a comparison enable (CPE) parameter delay module 350 connected to the first phase-locked loop PLL1. The sequence controller 310 is also connected to the output enable parameter delay module 340 and the comparison enable parameter delay module 350. The output enable parameter delay module 340 is connected to the first counter Cycle_1, and the comparison enable parameter delay module 350 is connected to the first counter Cycle_1. The output enable parameter delay module 340 is used to delay the output enable parameter (DRE parameter) issued by the sequence controller 310 and transmit it to the first counter Cycle_1. The comparison enable parameter delay module 350 is used to delay the comparison enable parameter (CPE parameter) issued by the sequence controller 310 and transmit it to the first counter Cycle_1.

[0073] Specifically, the DRE parameters and CPE parameters sent by the sequence controller 310 are delayed by the output enable parameter delay module 340 and the comparison enable parameter delay module 350. The first algorithm graph generation module ALPG1 packages the physically mapped address and data output by the signal physical mapping module PDM, the DRE parameters output by the output enable parameter delay module 340, and the CPE parameters output by the comparison enable parameter delay module 350 at the same time, and transmits them to the cache unit in the second processing module 124 via the first counter Cycle_1.

[0074] Among them, according to the time interval of the sequence controller 310 sending control signals to each module, and the time required for the signal physical mapping module PDM to perform physical mapping, the time when the signal physical mapping module PDM outputs the address and data after physical mapping can be known. Based on this, the output enable parameter delay module 340 / comparison enable parameter delay module 350 is parameterized so that it beats (pauses output) after receiving the DRE parameter / CPE parameter, and outputs the DRE parameter / CPE parameter after the signal physical mapping module PDM completes the physical mapping, so that the address and data after physical mapping, the delayed DRE parameter and the delayed CPE parameter are synchronously transmitted to the first counter Cycle_1.

[0075] It can be understood that in other embodiments, when the sequence controller 310 simultaneously sends control signals to each module, the control signal of each module can be transmitted to the corresponding module after being delayed through the corresponding path, or the control signal of each module can be transmitted serially and delayed through the internal modules of the address processing module 320 / data processing module 330, so that different modules can simultaneously receive the output data and corresponding control signals of the previous module. According to the data processing time of each module and the time required for the signal physical mapping module PDM to perform physical mapping, the time when the signal physical mapping module PDM outputs the address and data after physical mapping can be known. Based on this, the parameters of the output enable parameter delay module 340 / comparison enable parameter delay module 350 are set so that it beats (pauses output) after receiving the DRE parameter / CPE parameter until the signal physical mapping module PDM completes the physical mapping and then outputs the DRE parameter / CPE parameter, so that the address and data after physical mapping, the delayed DRE parameter and the delayed CPE parameter are synchronously transmitted to the first counter Cycle_1.

[0076] In one embodiment, Figure 3As shown, the second algorithm graph generation module ALPG2 includes an output enable data module 360, a comparison enable data module 370, a graph data storage module UBM and a multiplexer MUX, all of which are connected to the second phase-locked loop PLL2. The output enable data module 360 ​​and the comparison enable data module 370 are both connected to the second counter Cycle_2. The multiplexer MUX is connected to the second counter Cycle_2, the output enable data module 360, the comparison enable data module 370, the graph data storage module UBM and the timing module 1242. The output enable data module 360 ​​generates a timing signal according to the second counter Cycle_2. The output enable parameter output by le_2 selects output enable data from the preset data and sends it to the multiplexer MUX; the comparison enable data module 370 selects comparison enable data from the preset data according to the comparison enable parameter output by the second counter Cycle_2 and sends it to the multiplexer MUX; the multiplexer MUX is used to output the output enable data, the comparison enable data, and the physically mapped address and data output by the second counter Cycle_2 as calculated graphic data to the timing module 1242, or output the graphic data preset in the graphic data storage module UBM to the timing module 1242.

[0077] The output enable data module 360 ​​and the comparison enable data module 370 receive preset data from the host computer and select DRE data / CPE data from the preset data based on the received DRE parameters / CPE parameters. The graphics data storage module UBM is used to store preset graphics data, whose composition is consistent with the calculated graphics data. Based on actual testing needs, the multiplexer MUX can be controlled to select the calculated graphics data or the preset graphics data for output to the timing module 1242.

[0078] In one embodiment, the preset data stored in the output enable data module 360 ​​includes a PIN output enable preset table. Each row in the PIN output enable preset table contains output enable data that configures the output state (output or non-output) of all PINs. The output enable data module 360 ​​selects the output enable data in the corresponding row from the PIN output enable preset table based on the output enable parameters and sends it to the multiplexer MUX. Furthermore, the preset data stored in the output enable data module 360 ​​also includes customized PIN output enable data. The output enable data module 360 ​​can also replace some PINs (one or more PINs) in the selected corresponding row of output enable data with the customized PIN output enable data based on the output enable parameters, and then send the customized PIN output enable data to the multiplexer MUX, thereby implementing customized adjustment of PIN test configuration parameters.

[0079] In one embodiment, the preset data stored in the comparison enable data module 370 includes a comparison enable preset table. Each row in the comparison enable preset table contains comparison enable data that configures the comparison status of all PINs (no comparison, comparison and expected value is low, comparison and expected value is high, comparison and expected value is high impedance, and the sampled value is stored as the comparison result). The comparison enable data module 370 selects the comparison enable data for the corresponding row from the comparison enable preset table based on the comparison enable parameter and sends it to the multiplexer MUX. Furthermore, the preset data stored in the comparison enable data module 370 also includes custom PIN comparison enable data. The comparison enable data module 370 also replaces some PINs (one or more PINs) in the selected comparison enable data for the corresponding row with the custom PIN comparison enable data based on the comparison enable parameter, and then sends the data to the multiplexer MUX to implement custom adjustment of PIN test configuration parameters.

[0080] Furthermore, the multiplexer MUX may also receive control signals from the sequence controller 310 and, based on the control signals, select calculated or preset graphic data for output to the timing module 1242. Specifically, the sequence controller 310 may be directly or indirectly connected to the first counter Cycle_1. After the signal-physical mapping module PDM completes physical mapping, the sequence controller 310 synchronously transmits the control signal, the physically mapped address and data, the delayed DRE parameters, and the delayed CPE parameters to the first counter Cycle_1. Alternatively, the first algorithmic graph generation module ALPG1 may further include a signal delay module connected to the sequence controller 310 and the first counter Cycle_1. The signal delay module delays (pauses the output of the beat) the control signal output by the sequence controller 310 until the signal-physical mapping module PDM completes physical mapping and outputs the control signal. This allows the physically mapped address and data, the delayed control signal, the delayed DRE parameters, and the delayed CPE parameters to be synchronously transmitted to the first counter Cycle_1 and then to the cache unit in the second processing module 124. The second counter Cycle_2 reads the control signal in the cache unit and sends it to the multiplexer MUX, which controls the multiplexer MUX to select the calculated graphic data or the preset graphic data and output it to the timing module 1242 .

[0081] like Figure 3As shown, timing module 1242 can be connected to the device under test (DUT) via the PE (pin circuit) module. Timing module 1242 is used to perform waveform conversion and waveform change edge delay on the data, address, DRE (drive enable), and CPE (compare enable) output by the ALPG, and output them to the PE module. The PE module is used to convert the level of the signal output by timing module 1242 to the level required by the DUT pin, and then output it to the DUT. The PE module also performs a logic high comparison on the feedback signal of the DUT to obtain a CA signal, and a logic low comparison to obtain a CB signal, and transmits the CA and CB signals to timing module 1242. Timing module 1242 also samples the CA and CB signals returned by the PE module at a set time, compares the sampled values ​​with the CPE expected values ​​(determined by the compare enable data), and stores the comparison results.

[0082] like Figure 2 As shown, timing module 1242 includes a waveform synthesis module FC, a timing control module TC, a timing generation module TG, and a comparison module CP, all connected to the second phase-locked loop (PLL) 2. The waveform synthesis module FC, timing control module TC, and timing generation module TG are connected in sequence. The waveform synthesis module FC is connected to a multiplexer (MUX), while the timing generation module TG is connected to the device under test (DUT), specifically via a PE module. The comparison module CP is connected to the multiplexer (MUX) and the timing generation module TG. The output enable data, along with the physically mapped address and data, output from the multiplexer (MUX) are transmitted to the waveform synthesis module FC. After being processed by the waveform synthesis module FC, timing control module TC, and timing generation module TG, the test signal is output to the device under test (DUT). The comparison enable data output from the multiplexer (MUX) is transmitted to the comparison module CP. The comparison module CP samples the CA and CB signals based on the comparison enable data, compares them with the CPE expected value, and stores the comparison result.

[0083] In one embodiment, Figure 2As shown, a test machine is also provided, including a control board 200 and the above-mentioned resource board 100. The control board 200 is connected to the first synchronization control module 112 and the second synchronization control module 122 in the resource board 100, and outputs a clock signal to the first synchronization control module 112 and the second synchronization control module 122. Among them, the number of resource boards 100 is more than two, each resource board 100 is connected to the control board 200, and each resource board 100 is respectively connected to the corresponding device under test DUT. The first pre-synchronization module TB1 in each resource board 100 realizes the synchronization of data processing between different resource boards 100. In addition, the control board 200 is also connected to the resource board 100 through a data interface for data communication. The data interface can be a GTX interface or other types of interfaces.

[0084] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0085] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A resource board for a test machine, characterized in that: include: The first processing device includes a first synchronization control module and a first processing module, wherein the first synchronization control module is connected to the first processing module and the control board, and controls the first processing module to start after receiving a clock signal of a first preset duration output by the control board. After starting, the first processing module performs a graphics generation process and outputs corresponding data; Two or more second processing devices, each of the second processing devices comprising a second synchronization control module and a second processing module; In each of the second processing devices, the second synchronization control module is connected to the control board and the second processing module, and the second processing module is connected to the first processing module and the device to be tested; after receiving the second preset duration of the clock signal output by the control board, the second synchronization control module controls the start-up of the second processing module, and after startup, the second processing module obtains the data output by the first processing module for processing and outputs a test signal to the device to be tested.

2. The resource board according to claim 1, wherein: The first synchronization control module includes a first pre-synchronization module and a first phase-locked loop, the first pre-synchronization module is connected to the first phase-locked loop and the first processing module, and the first phase-locked loop is connected to the control board and the first processing module; The first phase-locked loop is used to receive the clock signal and control signal transmitted by the control board, start working according to the received control signal, process the received clock signal and output the working clock; the first pre-synchronization module is used to obtain the synchronization count value based on the clock signal, and transmit the synchronization count value to the first processing module. The first processing module starts the graphics generation processing when the synchronization count value is the first preset time length.

3. The resource board according to claim 2, wherein: The first processing module includes a first algorithm graph generation module and a first counter, the first algorithm graph generation module is connected to the first phase-locked loop, the first pre-synchronization module and the first counter, and the first counter is connected to the second processing module; After the first phase-locked loop receives the clock signal output by the control board for a first preset duration, the first pre-synchronization module controls the first algorithm graph generation module to start; after the first algorithm graph generation module is started, it performs the corresponding graph generation processing function according to the working clock output by the first phase-locked loop, and generates data to be transmitted to the first counter; the first counter starts timing after detecting the output data of the first algorithm graph generation module, and outputs the data to the second processing module after timing to the set timing duration.

4. The resource board according to claim 3, wherein: The first algorithm graph generation module includes a sequence controller connected to the first phase-locked loop, an address processing module, a data processing module and a signal physical mapping module, the sequence controller is connected to the address processing module and the data processing module, and the signal physical mapping module is connected to the address processing module, the data processing module and the first counter; The sequence controller is used to send data signals and control signals to the address processing module and the data processing module; the address processing module is used to select the original address from the data signal for processing according to the received control signal, and output the processed address information to the signal physical mapping module; the data processing module is used to select the original data from the data signal for processing according to the received control signal, and output the processed data information to the signal physical mapping module; The signal physical mapping module is used to select a designated physically mapped address and data from the processed address information and the processed data information according to the received control signal and output them to the first counter.

5. The resource board according to claim 4, characterized in that: The signal physical mapping module controls each bit to select the data and address processed by the address processing module and the data processing module according to the received control signal, or performs physical mapping on the configuration data sent by the sequence controller, and outputs the fixed bit physical mapping address and data to the first counter.

6. The resource board according to claim 4, characterized in that: The first algorithm graph generation module further includes a comparison enable parameter delay module and an output enable parameter delay module connected to the first phase-locked loop, the sequence controller is further connected to the comparison enable parameter delay module and the output enable parameter delay module, the comparison enable parameter delay module is connected to the first counter, and the output enable parameter delay module is connected to the first counter; The output enable parameter delay module is used to delay the output enable parameter issued by the sequence controller and transmit it to the first counter; the comparison enable parameter delay module is used to delay the comparison enable parameter issued by the sequence controller and transmit it to the first counter; the physically mapped address and data, the delayed output enable parameter and the delayed comparison enable parameter are synchronously transmitted to the first counter.

7. The resource board according to claim 4 or 5, characterized in that: The address processing module includes an original address source selection module, an address operation module, a verification module and a first delay module, all of which are connected to the first phase-locked loop and are connected in sequence, the original address source selection module is connected to the sequence controller, and the first delay module is connected to the signal physical mapping module; The original address source selection module selects a specified bit from the data signal as the original address according to the received control signal; the address calculation module performs a calculation operation on the original address and the data signal sent by the sequence controller according to the received control signal to obtain a calculated address; The verification module selects a verification rule according to the received control signal, verifies the calculated address according to the selected verification rule, and outputs the verification result and the calculated address to the signal physical mapping module after being delayed by the first delay module; The original address source selection module, the address calculation module, the verification module and the first delay module all receive the output data of the previous module and the control signal sent by the sequence controller at the same time, and perform corresponding processing on the output data of the previous module based on the received control signal.

8. The resource board according to claim 4 or 5, characterized in that: The data processing module includes an original data source selection module, a data operation module, a flip module, a CRC check module and a second delay module, all of which are connected to the first phase-locked loop and are connected in sequence, the original data source selection module is connected to the sequence controller, and the second delay module is connected to the signal physical mapping module; The original data source selection module selects a specified bit from the data signal as the original data according to the received control signal; the data operation module performs an operation on the original data and the data signal sent by the sequence controller according to the received control signal to obtain the calculated data; the flip module performs a logic value flip on the specified position of the calculated data according to the received control signal to obtain the flipped data; the CRC check module selects a CRC check rule according to the received control signal, performs a CRC operation on the flipped data according to the selected CRC check rule, and sends the output CRC check result to the signal physical mapping module after delay by the second delay module; The original data source selection module, the data operation module, the flip module, the CRC check module and the second delay module all receive the output data of the previous module and the control signal issued by the sequence controller at the same time, and perform corresponding processing on the output data of the previous module based on the received control signal.

9. The resource board according to claim 1, wherein: The second synchronization control module includes a second pre-synchronization module and a second phase-locked loop, and the second phase-locked loop is connected to the second pre-synchronization module, the second processing module and the control board; The second phase-locked loop receives the clock signal and control signal sent by the control board, starts working according to the received control signal, processes the received clock signal and outputs the working clock to the second processing module and the second pre-synchronization module. The second pre-synchronization module is used to obtain a synchronization count value based on the working clock, and when the synchronization count value reaches a second preset time length, controls the start of the operation of the second processing module.

10. The resource board according to claim 9, wherein: The second processing module includes a cache unit, a second counter, a second algorithm graph generation module and a timing module connected in sequence, the cache unit is connected to the first processing module, and the cache unit, the second counter, the second algorithm graph generation module and the timing module are all connected to the second phase-locked loop; After the second phase-locked loop outputs the working clock for a second preset duration, the second pre-synchronization module outputs a start instruction to the second counter, controls the second counter to start, and reads the data of the cache unit to the second algorithm graph generation module.

11. The resource board according to claim 1, wherein: The second synchronization control module includes a second pre-synchronization module and a second phase-locked loop, the second phase-locked loop is connected to the second pre-synchronization module, the second processing module and the control board; the second processing module includes a cache unit, a second counter, a second algorithm graph generation module and a timing module connected in sequence, the cache unit is connected to the first processing module, the cache unit, the second counter, the second algorithm graph generation module and the timing module are all connected to the second phase-locked loop, and the second pre-synchronization module is also connected to the cache unit; The second pre-synchronization module starts timing when it detects that the data in the cache unit is not empty, and starts the second counter to read data from the cache unit after timing to the second preset time length. The second counter sends the read data to the second algorithm graph generation module for corresponding processing.

12. The resource board according to claim 10 or 11, characterized in that: The second algorithm graph generation module includes an output enable data module, a comparison enable data module, a graph data storage module and a multiplexer, all of which are connected to the second phase-locked loop; the output enable data module and the comparison enable data module are both connected to the second counter; the multiplexer is connected to the second counter, the output enable data module, the comparison enable data module, the graph data storage module and the timing module; The output enable data module selects output enable data from preset data according to the output enable parameter output by the second counter and sends the data to the multiplexer; The comparison enable data module selects comparison enable data from preset data according to the comparison enable parameter output by the second counter and sends the data to the multiplexer; The multiplexer is used to output the output enable data, the comparison enable data, and the physically mapped address and data output by the second counter as calculated graphic data to the timing module, or to output the graphic data preset in the graphic data storage module to the timing module.

13. The resource board according to claim 12, wherein: The preset data stored in the output enable data module includes a PIN output enable preset table, and the preset data stored in the comparison enable data module includes a comparison enable preset table; The output enable data module selects the output enable data of the corresponding row from the PIN output enable preset table according to the output enable parameter and sends it to the multiplexer; The comparison enable data module selects the comparison enable data of a corresponding row from the comparison enable preset table according to the comparison enable parameter and sends the selected data to the multiplexer.

14. The resource board according to claim 13, wherein: The preset data stored in the output enable data module further includes custom PIN output enable data, and the preset data stored in the comparison enable data module further includes custom PIN comparison enable data; The output enable data module also replaces part of the PIN in the output enable data of the selected corresponding row with the custom PIN output enable data according to the output enable parameter, and then sends it to the multiplexer; The comparison enable data module also replaces part of the PIN in the comparison enable data of the selected corresponding row with the custom PIN comparison enable data according to the comparison enable parameter, and then sends it to the multiplexer.

15. The resource board according to claim 12, wherein: The timing module includes a waveform synthesis module, a timing control module, a timing generation module and a comparison module, all of which are connected to the second phase-locked loop. The waveform synthesis module, the timing control module and the timing generation module are connected in sequence. The waveform synthesis module is connected to the multiplexer, the timing generation module is connected to the device to be tested, and the comparison module is connected to the multiplexer and the timing generation module.

16. A testing machine, characterized in that: It comprises a control board and a resource board as described in any one of claims 1 to 15; the number of the resource boards is more than two, each of the resource boards is connected to the control board, and each of the resource boards is respectively connected to a corresponding device to be tested, and the first pre-synchronization module in each of the resource boards realizes the synchronization of data processing between different resource boards.

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