A chipset-based modular motherboard expansion architecture

Abstract

The application relates to a modular mainboard architecture technology and discloses a modular mainboard expansion architecture based on a chip set, which comprises a substrate, at least two pluggable chip modules and a programmable silicon intermediate module; wherein the pluggable chip modules are detachably and physically connected with the substrate through magnetic suction interface modules; the magnetic suction interface adopts a Halbach permanent magnet array in a 15-degree spiral layout, and is matched with an electromagnetic compensation coil to realize rapid demagnetization and anti-adhesion; the programmable silicon intermediate module is composed of a basic routing layer and a protocol conversion layer; the basic routing layer is integrated on the substrate, and the protocol conversion layer is integrated in the pluggable chip module; the pluggable chip module generates a non-clonable PUF function, which is used for chip identity authentication; the substrate sends a verification request through the PUF function, generates a unique signature, and then loads a module configuration file by the protocol conversion layer, so that dynamic protocol conversion and topology reconstruction are supported.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of modular mainboard architecture, in particular to a modular mainboard expansion architecture based on a chipset. BACKGROUND

[0002] Embedded systems are widely used in various fields. As an important part of embedded systems, the performance and reliability of single-board computers are crucial to the operation of the entire system.

[0003] The prior art has a single-board computer mainboard based on a VPX architecture, as proposed in Chinese patent application CN112380162A. In this patent, the processor module is connected with the first interface module, GPU module, MXM graphics card module, and storage module. The processor module is connected with the mainboard expansion chipset through the PCIE signal line, and the processor module and the mainboard expansion chipset are respectively connected with the VPX connector module, wherein a plurality of interfaces are provided on the mainboard to meet different requirements and improve compatibility.

[0004] However, there are several key technical bottlenecks in most current mainboard architectures, which limit their performance in complex and variable application scenarios.

[0005] The traditional single-board computer mainboard structure is fixed and cannot support flexible expansion and hot plug operations of heterogeneous computing modules such as CPUs, FPGAs (Field Programmable Gate Array), NPUs (Neural Processing Unit), etc. This hardware staticity greatly limits the adaptability and maintainability of the system. Once the system needs to be upgraded or a component needs to be replaced, the entire device needs to be disassembled and replaced, and then serial transmission, decompression, and reconstruction are required, and the problem of dynamic compatibility of heterogeneous protocols also needs to be solved.

[0006] Not only does this increase maintenance costs, but it also causes long service interruptions. In particular, in some critical application scenarios such as vehicle-mounted, military, aerospace, etc., any service interruption can have a serious impact. SUMMARY

[0007] Based on the above technical problems, the present application proposes a modular mainboard expansion architecture based on a chipset.

[0008] The technical solution of the present application is as follows:

[0009] A modular mainboard expansion architecture based on a chipset, characterized by comprising:

[0010] a substrate,

[0011] a pluggable chip module,

[0012] A programmable silicon intermediary module, which is composed of a basic routing layer and a protocol conversion layer;

[0013] Wherein, the pluggable chip module is detachably connected with the substrate by a magnetic interface module, the basic routing layer is integrated on the substrate, and the protocol conversion layer is integrated on the pluggable chip module.

[0014] The pluggable chip module generates a non-clonable PUF function for chip identity authentication.

[0015] The substrate sends a verification request through the PUF function to generate a unique signature, and then loads a module configuration file through the protocol conversion layer to reconstruct the substrate signal topology.

[0016] In the present application, the pluggable chip module is composed of a liquid cooling interface, a quantum contact layer, a functional chip layer and an electromagnetic locking layer.

[0017] The substrate integrates a liquid cooling system connected with the liquid cooling interface, and the liquid cooling interface is a plurality of copper micro-pipes for conducting heat from the functional chip layer.

[0018] In the present application, the quantum contact layer is used to provide power supply, wherein the quantum contact layer comprises:

[0019] A plurality of power contacts;

[0020] A plurality of high-speed signal contacts for high-speed data communication transmission;

[0021] A PUF identity contact for generating a physically unclonable PUF function based on a quantum dot array for chip identity authentication.

[0022] A functional chip layer;

[0023] An electromagnetic locking layer for detachable plugging of the pluggable chip module.

[0024] In the present application, the electromagnetic locking layer comprises an electromagnetic lock and an anti-misplug guide key.

[0025] In the present application, the magnetic interface module is composed of a contact layer, a soft magnetic guide layer, a permanent magnet array and an electromagnetic compensation coil,

[0026] The soft magnetic guide layer is used to guide and focus magnetic induction lines, the permanent magnet array is arranged in a 15° spiral layout, and the electromagnetic compensation coil is arranged around the permanent magnet array.

[0027] In the present application, the protocol conversion layer comprises a TSV silicon through hole, a clock tree grid and a protocol bridge IP core, the TSV silicon through hole is vertically interconnected with the functional chip layer, and the protocol bridge IP core realizes dynamic adjustment of protocols by RTL code.

[0028] In the application, the basic routing layer comprises:

[0029] a plurality of independent power supply areas,

[0030] an overcurrent fuse for overcurrent tripping of the power supply path;

[0031] a clock buffer for driving a clock signal to a plurality of load ends;

[0032] a signal path divided into a main path, a backup path and a detection path;

[0033] a PUF verification unit for generating a unique identity and a key based on a physically unclonable PUF function;

[0034] a topology preset unit for controlling the connection topology and the operation mode switching inside the substrate.

[0035] In the application, the substrate further comprises a CAN bus, a gigabit Ethernet, a BMC management network port, a USB2.0, an HDMI1.0, an LVDS, a SATA storage, and a power state interface.

[0036] In the application, the substrate further comprises a gigabit Ethernet, a USB3.0, an RS232 debugging serial port, an RS422 serial port, a DVI-D, a SATA storage, a CPCI expansion slot, an XMC expansion slot, an RTC clock, and a status indicator light.

[0037] In the application, the substrate further comprises a gigabit optical port, a gigabit electrical port, a PCIe4.0 slot, an MXM graphics card slot, a USB3.0, a multi-protocol serial port, a video output interface, a BMC debugging interface, and a SATA storage.

[0038] The chip set-based modular mainboard expansion architecture of the application has the following beneficial effects:

[0039] 1. By introducing the pluggable chip module and the magnetic interface module, the system supports quick hot plugging operation, and users can flexibly replace the computing chip modules such as FPGA, NPU and CPU according to actual needs, thereby improving the system adaptability and scalability and meeting the computing needs of different application scenarios.

[0040] 2. The pluggable chip module integrates a liquid cooling interface, adopts a copper micro-tube heat conduction structure, and can efficiently conduct the heat generated during the operation of the chip. The liquid cooling interface is automatically sealed during plugging, prevents leakage of the cooling liquid, and ensures the stability and safety of the system under high load operation.

[0041] 3、The power contact in the quantum contact layer adopts a triple redundancy design, which can maintain normal power supply in the case of partial contact failure, significantly improve the stability and fault tolerance of system power supply, and reduce performance degradation or system interruption caused by power fluctuations.

[0042] 4、The high-speed signal contact supports large-scale parallel data transmission, has good anti-electromagnetic interference ability, ensures the data integrity and low error rate of high-speed communication between chips, and is suitable for high-bandwidth, low-delay computing scenarios.

[0043] 5、The PUF identity contact generates a unique physical unclonable function, realizes identity authentication of the chip module, and prevents illegal modules from accessing the system. At the same time, the PUF verification unit generates a 256-bit quantum-level key for device authentication and data encryption, improving the security level of the system. BRIEF DESCRIPTION OF DRAWINGS

[0044] Figure 1 It is a structural schematic diagram of the modular mainboard expansion architecture of the application;

[0045] Figure 2 It is another angle structural schematic diagram of the modular mainboard expansion architecture of the application;

[0046] Figure 3 It is a structural block diagram of the modular mainboard expansion architecture of the application;

[0047] Figure 4 It is a cross-sectional structural block diagram of the pluggable chip module of the application;

[0048] Figure 5 It is a cross-sectional structural block diagram of the magnetic attraction interface module of the application;

[0049] Figure 6 It is a cross-sectional structural block diagram of the basic routing layer of the application;

[0050] Figure 7 It is a flowchart of the modular mainboard expansion architecture of the application;

[0051] Figure 8 It is a flowchart of the modular mainboard expansion architecture of the application.

[0052] The reference signs are as follows: 10 - substrate, 20 - pluggable chip module, 21 - liquid cooling interface, 22 - quantum contact layer, 221 - power contact, 222 - high-speed signal contact, 223 - PUF identity contact, 23 - functional chip layer, 24 - electromagnetic locking layer, 241 - electromagnetic lock, 242 - anti-misplug guide key, 30 - programmable silicon intermediary module, 31 - basic routing layer, 311 - independent power supply area, 312 - overcurrent fuse, 313 - clock buffer, 314 - signal path, 315 - PUF verification unit, 316 - topology preset unit, 32 - protocol conversion layer, 321 - TSV silicon through hole, 322 - clock tree grid, 323 - protocol bridge IP core, 40 - magnetic attraction interface module, 41 - contact layer, 42 - soft magnetic guide layer, 43 - permanent magnet array, 44 - electromagnetic compensation coil. DETAILED DESCRIPTION

[0053] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.

[0054] Referring to Figures 1 to 8 As shown in the figure, the embodiment provides a chip group-based modular mainboard expansion architecture, which includes a substrate 10, at least two pluggable chip modules 20, and a programmable silicon intermediary module 30. The pluggable chip module 20 is detachably physically connected to the substrate 10 through a magnetic attraction interface module 40. The programmable silicon intermediary module 30 is composed of a basic routing layer 31 and a protocol conversion layer 32. The basic routing layer 31 is integrated on the substrate 10, and the protocol conversion layer 32 is integrated in the pluggable chip module 20.

[0055] In one embodiment, the substrate 10 includes an 8-way CAN2.0 bus with a rate of 250 kbps~1 Mbps and an isolation of 2500 Vrms; a 4-way gigabit Ethernet with a rate of 100 / 1000 Mbps; a 1-way BMC management network interface supporting the IPMI protocol; a 2-way USB2.0 with a standard Type-A; a 1-way HDMI1.0 for video output; a 1-way LVDS for display screen interface; a 1-way SATA storage with a capacity of ≥1 TB and a read / write speed of ≥100 MB / s; and a 1-way power / status interface with a light ring switch, specifically white / green / yellow / red status indication.

[0056] In one embodiment, the substrate 10 includes 4-way Gigabit Ethernet, 2-way front-out RJ45, 2-way rear-out J3 interface; 2-way USB3.0, front-out Type-A; 1-way RS232 debugging serial port, front-out RJ45, baud rate 115200; 4-way RS422 serial port, rear-out J5 interface; 1-way DVI-D, front-out, supporting 1920x1080; 3-way SATA storage, specifically 1-way nSATA + 2-way rear-out SATA; at least 4-way CPCI expansion slot, 32-bit / 33MHz; 1-way XMC expansion slot, reserved installation space; 1-way RTC clock, motherboard integrated battery holder; 2-way status indicator light, specifically power light + hard drive light; 1-way reset button.

[0057] In one embodiment, the substrate 10 includes 4-way 10G optical port, SFP+; 4-way Gigabit electrical port, RJ45; 4-way PCIe4.0 slot; 1-way MXM graphics card slot, PCIe4.0x8 signal; 6-way USB3.0; 6-way multi-protocol serial port, specifically RS232x2 + RS422x2 + RS485x2; 3-way video output, specifically 2-way HDMI + 1-way VGA; 1-way BMC debugging interface, specifically 2-way VGA + 1-way RS232 + 1-way network port; 2-way SATA storage; 6-way fan control, specifically 4-way case fan + 2-way CPU fan; 5-way front panel control, specifically power key + reset key + 3 status indicator lights.

[0058] Referring again to Figures 4 to 5 The pluggable chip module 20 is composed of a liquid cooling interface 21, a quantum contact layer 22, a functional chip layer 23, and an electromagnetic locking layer 24. The substrate 10 integrates a liquid cooling system and is connected with the liquid cooling interface 21. The liquid cooling interface 21 is a plurality of copper micro-pipes for quickly conducting heat from the functional chip layer 23. The liquid cooling interface 21 is automatically sealed during rapid plugging to prevent leakage of the cooling liquid and ensure stable operation of the system.

[0059] The quantum contact layer 22 is used to provide stable power supply for the chip. The quantum contact layer 22 includes:

[0060] The power contact 221 adopts a triple redundancy design. Even if one or two contacts fail, the system can still operate normally, reducing the impact of power fluctuations on the performance of the chip.

[0061] The 32 pairs of differential high-speed signal contacts 222 transmit high-speed differential signals, support high-speed data communication between chips, and support large-scale parallel data transmission. The differential signals have good suppression ability to low-noise electromagnetic interference.

[0062] PUF identity contact 223, based on quantum dot array to generate physically unclonable PUF function, for chip identity authentication, PUF of each chip is unique, preventing unauthorized chip access to the system.

[0063] The functional chip layer 23 is a computing chip such as FPGA / NPU / CPU.

[0064] The electromagnetic locking layer 24 is used to realize the quick plugging of the pluggable chip module 20, and the electromagnetic locking layer 24 includes an electromagnetic lock 241 and a mistaken insertion prevention guide key 242. The electromagnetic lock 241 is opened to automatically release when power is off, preventing damage to the pluggable chip module 20. The mistaken insertion prevention guide key 242 ensures that the pluggable chip module 20 is correctly inserted, preventing mistaken insertion.

[0065] Further, the magnetic attraction interface module 40 is composed of a contact layer 41, a soft magnetic guide layer 42, a permanent magnet array 43, and an electromagnetic compensation coil 44. The contact layer 41 is gold-palladium alloy with an alloy ratio of Au:Pd being 90:10, providing a low-resistance, high-stability electrical contact interface, maintaining a low wear rate and long-term conductivity during plugging. The soft magnetic guide layer 42 is a permalloy, used to guide and focus magnetic induction lines, improve magnetic attraction efficiency, reduce edge magnetic leakage, and enhance anti-external magnetic field interference capability. During the docking process, the soft magnetic guide layer 42 is self-aligned by magnetism.

[0066] The permanent magnet array 43 is a Halbach permanent magnet array arranged in a 15° spiral layout. By alternating N / S poles, the magnetic field on one side is enhanced and the magnetic field on the other side is offset. By adopting a 15° spiral layout, four-dimensional magnetic force distribution in the axial, circumferential, radial, and spiral directions is achieved. Among them, the central magnetic attraction force reaches 45N, and the edge is 12N, realizing gradient adsorption control.

[0067] The electromagnetic compensation coil 44 is arranged around the permanent magnet array, usually with multi-layer winding; the material is high-conductivity copper wire or high-temperature superconducting coil. When energized, the magnetic attraction force is enhanced; when de-energized, a reverse current is applied to quickly demagnetize and avoid residual magnetic adhesion after disconnection.

[0068] In this embodiment, referring again to Figure 7 As shown in the figure, before the hot plug operation is performed, the management system first issues an unload instruction, and the substrate 10 starts the state saving mechanism, including freezing data flow, refreshing cache, and backing up the register state to the non-volatile dual in-line memory module (NVDIMM). Subsequently, the quantum contact layer 22 is quickly reduced to a safety threshold, and the liquid cooling interface 21 is switched to a bypass mode to ensure safety during the hot plug process.

[0069] This stage involves manual operation, which is prevented by the electromagnetic lock 241 and the anti-misplug guide key 242. The anti-misplug guide key 242 has an angle tolerance of ±0.5°, and when a pulling force of more than 8N is applied, the electromagnetic lock 241 automatically pops open.

[0070] After the physical replacement is completed, the activation stage is entered through the protocol conversion layer 32. The protocol conversion layer 32 includes a TSV silicon through hole 321, a clock tree grid 322, and a protocol bridge IP core 323. The TSV silicon through hole 321 adopts a 2.5D package with a diameter of 5μm and is vertically interconnected with the functional chip layer 23 through the TSV silicon through hole 321. The clock tree grid 322 is a copper column array that provides precise clock synchronization signals to ensure that the modules inside the functional chip layer 23 operate synchronously. The protocol bridge IP core 323 realizes dynamic adjustment of the protocol through RTL code and converts between different protocols. The substrate 10 sends a verification through the PUF identity contact 223 and returns a response signature to confirm the module identity. Subsequently, the signal topology is reconstructed according to the loaded module configuration file, the microkernel driver is injected into the functional chip, and the BIST self-checking process is performed, and finally the self-checking result is fed back to the substrate 10.

[0071] Referring again to Figure 6 As shown in the figure, the base routing layer 31 includes:

[0072] An independent power supply area 311 divides the substrate 10 into multiple independent power supply areas, each of which is set with a voltage (0.8V, 1.2V, 1.8V) as needed to realize voltage domain management;

[0073] An overcurrent fuse 312 quickly cuts off the power supply path when an overcurrent or short circuit fault occurs to protect the circuit;

[0074] A clock buffer 313 is used to drive the clock signal to multiple load ends to maintain signal integrity;

[0075] A signal path 314 is divided into a main path, a backup path, and a detection path to realize signal transmission redundancy and fault tolerance and enable fault switching and error detection mechanisms;

[0076] A PUF verification unit 315 generates a unique identity and key based on a physically unclonable PUF function to realize hardware-level security authentication;

[0077] A topology preset unit 316 presets 16 modes to control the connection topology and operation mode switching inside the substrate 10.

[0078] Referring again to Figure 8As shown, the signal path 314 is provided by a hard-wired redundant structure, a master / standby / detection three-channel, the master path uses 8 pm line width to optimize the delay, the standby path uses 12 pm line width to improve the anti-interference ability, and the delay difference is controlled within ±5 ps. Vertical signal interconnection is realized, and differential pair wiring is used to ensure high-frequency signal integrity.

[0079] When the signal quality monitoring module detects that the CRC error exceeds the set threshold, the redundant path switching process is triggered: starting the standby path, closing the master path, completing the routing switching, updating the routing state to the NVDIMM, and maintaining the topology consistency.

[0080] At the same time, the PUF verification unit generates a 256-bit quantum-level key for device identity authentication and data encryption to prevent illegal access.

[0081] In summary, the magnetic attraction interface 40 and the PUF authentication 223 solve the problems of physical connection security and identity verification. When a pluggable chip module is inserted for replacement, only relying on the topology preset unit 316 cannot dynamically adapt to protocol differences, resulting in incompatibility.

[0082] Further, in one embodiment, the protocol bridge IP core 323 realizes the dynamic adjustment of the protocol through RTL code, and realizes the conversion between different protocols. The specific steps include the following:

[0083] Step 1: Real-time analysis of input data stream, identification of current communication protocol.

[0084] The preamble (Preamble) is extracted from the first 64 bits of the input stream, which is used for preliminary judgment of the protocol type.

[0085] The subsequent 64-bit data is extracted, and the information entropy feature vector (Feature Vector) is calculated, which reflects the data distribution characteristics. The topology preset unit 316 pre-stores the configuration bit stream and parameters corresponding to multiple protocols.

[0086] The input feature vector is matched with the protocol signature vector , specifically, the Hamming distance (Hamming Distance) and cosine similarity (Cosine Similarity) matching are performed with the pre-stored protocol signature vector .

[0087] Protocol matching calculation:

[0088]

[0089] Where S is the cosine similarity of the input signal and the protocol signature, ranging from 0 to 1, and the larger the value, the more similar. n is the dimension number of the feature vector, usually 64 or 128 dimensions. Xi is the i-th dimension feature value of the input data stream, which forms the input feature vector . Xi is the i-th dimension reference feature value of the pre-stored protocol signature, which forms the protocol signature vector When S>0.95 and the Hamming distance is less than the threshold value, the protocol match is confirmed, and the matched target protocol type is output.

[0090] Step2: According to the matched target protocol type, the corresponding bit stream is loaded from the topology preset unit 316, the specific logic area is partially reconfigured, and the specific data packet format conversion is performed.

[0091] Establish a reconfiguration time model:

[0092]

[0093] Wherein, Ttotal is the total time required for one RTL reconfiguration. Tbase is the basic overhead time of reconfiguration, which is a fixed value, usually 100 ns. Tdelay is the delay increment introduced by each logic unit change, Tclock is the delay coefficient caused by clock frequency change. Usually Tclock is 2 ns, Tclock is 5 ns / MHz. N is the number of logic units changed in this reconfiguration. F is the difference between the working clock frequencies of the source protocol and the target protocol.

[0094] According to the above reconfiguration time model, the reconfiguration time is proportional to the logic change amount and the frequency jump amplitude.

[0095] Using a reconfigurable finite state machine architecture, different protocol state transition logic is supported to be loaded at runtime. The transition time model is:

[0096]

[0097] Wherein, Ttransition is the time required for state transition. Fcurrent is the current working clock frequency, Ntotal is the total number of states that need to be migrated, Npipeline is the number of pipeline stages.

[0098] The transition time is affected by the clock period and the pipeline efficiency, further reducing the switching delay. The data stream interruption time during protocol switching is <1 μs, which meets the high real-time scenarios such as military and vehicle-mounted.

[0099] Specifically, protocol conversion is essentially a linear transformation process of mapping input data packet I to output data packet O.

[0100] Data packet format conversion: . Wherein,

[0101] O is the output protocol data packet vector, a 64-dimensional floating point or integer vector. W is the protocol conversion weight matrix, a 64x64 matrix, which stores address mapping, command coding rules, etc. I is the input protocol data packet vector, and B is the bias vector, such as adding packet header, CRC, virtual channel identifier, etc. Fixed field.

[0102] Weight matrix dynamic fusion formula:

[0103]

[0104] Wherein, is the new weight matrix actually applied, is the protocol similarity factor. is the dedicated conversion matrix of the target protocol, obtained by pre-training or configuration. is the default basic conversion matrix, used for unknown protocols or fault tolerance.

[0105] New and old data packet format mutation causes CRC check failure or field loss, causing communication interruption. In this embodiment, the data packet format is ensured to gradually transition. The basic conversion matrix provides basic compatibility for unknown protocols, prevents data packet loss or format error during protocol switching, and ensures communication continuity. Further, to ensure the stability of cross-clock domain operation, the path delay difference is compensated.

[0106] Step 3: Establish a distributed clock network between the clock buffer 313 of the basic routing layer 31 and the clock tree grid 322 of the protocol conversion layer 32. Through dynamic compensation of path delay, the clock offset in signal transmission is eliminated, and the synchronization of cross-clock domain operation is ensured.

[0107] Mathematical constraint condition:

[0108]

[0109] Wherein, is the maximum offset of each path in the clock network. For example: when =5GHz, <20ps. In traditional clock networks, the maximum offset of each path is >3 GHz, which can easily cause setup / hold time violations. The error rate of cross-clock domain data transmission soars, dynamic reconfiguration timing conflicts, and clock frequency jumps during protocol switching, so the original clock network cannot adaptively compensate for the delay.

[0110] The traditional scheme needs to serially execute bit stream transmission, decompression and reconstruction, with high delay. Hot plug causes service interruption, which cannot meet the needs of high real-time switching.

[0111] Reconfiguration time optimization model:

[0112]

[0113] Where, is the actual total reconfiguration time consumption, is the compressed bitstream size, is the DMA transmission bandwidth. is the decompression time required, Referring to the above formula.

[0114] Transmission and decompression are performed in parallel, and the longer time-consuming part is processed first.

[0115] The transmission time and the decompression time are taken as the maximum value, balancing the compression rate and the decompression speed.

[0116] Traditional protocol switching needs to stop loading firmware, requires serial transmission, decompression and reconstruction, and takes a long time, which cannot meet the real-time requirements of vehicle / military scenarios. The embodiment completes heterogeneous protocol recognition, clock synchronization and data packet format gradual conversion within μs level time, ensures zero data loss and uninterrupted service during hot plug.

[0117] Real-time extraction of input data stream entropy feature vector , calculation of cosine similarity and Hamming distance with pre-stored signature , loading target protocol when S>0.95, otherwise enabling basic conversion matrix to solve unknown protocol compatibility.

[0118] Weight fusion formula and linear transformation are used, CRC fields are automatically filled through bias vector B, and conversion rules are dynamically adjusted through protocol similarity factor to eliminate packet loss caused by format mutation.

[0119] Transmission and decompression stages are executed in parallel, reconstruction delay is compressed by 60%, and interruption time is less than 1 μs; a distributed network is established between the clock buffer 313 and the clock tree grid 322, the path offset is constrained, for example, <20ps at 5GHz, and the timing violation during high-frequency switching is eliminated.

[0120] Protocol matching provides adjustment basis for matrix gradual change, Ensure that the basic communication under unknown protocol is not interrupted; parallel reconstruction cooperates with clock compensation to guarantee the switching time of μs level, and the weight fusion mechanism maintains the continuity of data packets; finally, zero data loss, μs level completion of protocol switching, and unknown module basic compatibility are achieved in the hot plug process.

[0121] The above merely describes preferred embodiments of the present application and is not intended to limit the present application. Any modification, equivalent replacement, and improvement within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A chipset-based modular motherboard expansion architecture, comprising: Comprise: a substrate, a pluggable chip module, a programmable silicon intermediary module, which is composed of a basic routing layer and a protocol conversion layer; wherein the pluggable chip module is detachably connected with the substrate by a magnetic interface module, the basic routing layer is integrated on the substrate, and the protocol conversion layer is integrated on the pluggable chip module, the pluggable chip module generates a non-clonable PUF function for chip identity authentication, the substrate sends a verification request through the PUF function to generate a unique signature, and then loads a module configuration file by the protocol conversion layer to reconstruct the signal topology of the substrate.

2. The modular motherboard expansion architecture of claim 1, wherein, The pluggable chip module is composed of a liquid cooling interface, a quantum contact layer, a functional chip layer, and an electromagnetic locking layer, the substrate is connected with the liquid cooling interface by integrating a liquid cooling system, and the liquid cooling interface is a plurality of copper micro-pipes for conducting heat out of the functional chip layer.

3. The modular motherboard expansion architecture of claim 2, wherein, The quantum contact layer is used to provide power supply, wherein the quantum contact layer comprises: a plurality of power supply contacts; a plurality of high-speed signal contacts for high-speed data communication transmission; a PUF identity contact for generating a physically unclonable PUF function based on a quantum dot array for chip identity authentication; a functional chip layer; an electromagnetic locking layer for detachable plugging of the pluggable chip module.

4. The modular motherboard expansion architecture of claim 3, wherein, The electromagnetic locking layer comprises an electromagnetic lock and a misplug prevention guide key.

5. The modular motherboard expansion architecture of claim 1, wherein, The magnetic interface module is composed of a contact layer, a soft magnetic guide layer, a permanent magnet array, and an electromagnetic compensation coil, the soft magnetic guide layer is used to guide and focus magnetic induction lines, the permanent magnet array is arranged in a 15° spiral layout, and the electromagnetic compensation coil is arranged around the permanent magnet array.

6. The modular motherboard expansion architecture of claim 2, wherein, The protocol conversion layer comprises a TSV silicon through hole, a clock tree grid, and a protocol bridge IP core, the TSV silicon through hole is vertically interconnected with the functional chip layer, and the protocol bridge IP core realizes dynamic adjustment of protocols by RTL code.

7. The modular motherboard expansion architecture of claim 1, wherein, The basic routing layer comprises: a plurality of independent power supply areas, an overcurrent fuse for overcurrent cut-off of a power supply path; a clock buffer for driving a clock signal to a plurality of load ends; a signal path, which is divided into a main path, a backup path, and a detection path; a PUF verification unit for generating a unique identity and a key based on a physically unclonable PUF function; a topology preset unit for controlling a connection topology and an operation mode switching inside the substrate.

8. The modular motherboard expansion architecture of claim 1, wherein, The substrate further comprises a CAN bus, a gigabit Ethernet, a BMC management network port, a USB2.0, an HDMI1.0, an LVDS, a SATA storage, and a power state interface.

9. The modular motherboard expansion architecture of claim 1, wherein, The substrate further comprises a gigabit Ethernet, a USB3.0, an RS232 debugging serial port, an RS422 serial port, a DVI-D, a SATA storage, a CPCI expansion slot, an XMC expansion slot, an RTC clock, and a status indicator light.

10. The modular motherboard expansion architecture of claim 1, wherein, The substrate further comprises a 10-gigabit optical port, a gigabit electrical port, a PCIe4.0 slot, an MXM graphics card slot, a USB3.0, a multi-protocol serial port, a video output interface, a BMC debugging interface, and a SATA storage.

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