A matrix calculation adaptive optimization method and system based on ARM architecture

Abstract

This invention discloses an adaptive optimization method and system for matrix computation based on ARM architecture, comprising: preprocessing the matrix data to be processed; calculating local activity and identifying hotspot regions on the preprocessed matrix data to determine the long-tail distribution characteristics of the matrix; calculating the optimal block size range of the matrix based on the long-tail distribution characteristics of the matrix and multi-level cache capacity parameters in the processor information, and generating an asymmetric block partitioning scheme; establishing a mapping relationship between matrix characteristics and optimal block parameters based on the asymmetric block partitioning scheme; calculating the computation density and memory access pattern of each block based on the asymmetric block partitioning scheme and the mapping relationship, and generating a task scheduling scheme; executing matrix computation on the processor based on the task scheduling scheme, and outputting the final computation result. This invention improves the performance and energy efficiency of matrix computation on ARM by identifying the long-tail distribution characteristics of the matrix and realizing adaptive block partitioning and heterogeneous core scheduling.

Description

Technical Field

[0001] This invention relates to the field of computer science and technology, and specifically to an adaptive optimization method and system for matrix computation based on ARM architecture. Background Technology

[0002] With the rapid development of artificial intelligence technology, deep learning algorithms are widely used in various smart devices. Matrix computation, as a core operation of these algorithms, directly affects the overall performance and energy efficiency of the system. Efficiently performing matrix operations on resource-constrained ARM architecture devices has become a key technical challenge.

[0003] Currently, commonly used matrix computation optimization methods in the industry mainly include general-purpose matrix multiplication libraries (such as OpenBLAS) and hardware acceleration libraries (such as the ARM Compute Library). These methods typically employ a static block partitioning strategy, decomposing large matrices into fixed-size submatrices to improve cache utilization and parallelism. For example, OpenBLAS decomposes matrix multiplication into multiple submatrix operations using the Strassen algorithm and block partitioning techniques, while the ARM Compute Library utilizes the NEON SIMD instruction set for vectorized computation.

[0004] More advanced matrix computation optimization techniques introduce automatic tuning mechanisms, pre-determining the optimal block parameters based on matrix size and hardware characteristics. This method establishes performance models through offline analysis, selects predefined computational kernels for matrix computation tasks of different specifications, and utilizes the ARM NEON instruction set for low-level optimization. However, this technique assumes a uniform distribution of matrix elements and uses a uniform block size, ignoring the uneven distribution of matrix element activity in real-world applications.

[0005] Existing technologies suffer from two main drawbacks: First, the fixed block partitioning strategy cannot adapt to the long-tail distribution of matrix elements, leading to uneven allocation of computing resources, with excessive computational pressure in highly active areas and wasted resources in inactive areas. Second, it fails to fully utilize the characteristics of the ARM big.LITTLE heterogeneous multi-core architecture, failing to dynamically schedule processing to the most suitable cores based on the block partitioning characteristics, resulting in performance bottlenecks and low energy efficiency. These problems are particularly prominent in computationally intensive scenarios such as large model inference, severely limiting the ability of ARM devices to handle complex matrix calculations. Summary of the Invention

[0006] The purpose of this invention is to provide an adaptive optimization method and system for matrix computation based on ARM architecture. This method identifies the long-tail distribution characteristics of matrix elements, implements an asymmetric partitioning strategy, and combines the heterogeneous architecture of ARM big.LITTLE to allocate computational tasks with different characteristics to the most suitable processing core, thereby significantly improving the performance and energy efficiency of matrix computation.

[0007] To achieve the above objectives, this invention provides an adaptive optimization method for matrix computation based on ARM architecture, comprising the following steps:

[0008] Obtain the matrix data to be processed and the ARM processor information, preprocess the matrix data to be processed, and obtain the preprocessed matrix data;

[0009] The preprocessed matrix data is subjected to local activity calculation and hotspot region identification to determine the long-tail distribution characteristics of the matrix.

[0010] Based on the long-tail distribution characteristics of the matrix and the multi-level cache capacity parameters in the ARM processor information, the optimal block size range of the matrix is ​​calculated, and an asymmetric block scheme is generated.

[0011] Based on the asymmetric partitioning scheme, the execution time and cache hit rate of each partition are collected, and a mapping relationship between matrix features and optimal partitioning parameters is established, wherein the partition is the basic sub-block of the preprocessed matrix data.

[0012] Based on the asymmetric partitioning scheme and the mapping relationship between the matrix features and the optimal partitioning parameters, the computational density and memory access pattern of each partition are calculated to generate a task scheduling scheme.

[0013] Based on the task scheduling scheme, matrix calculations are performed on a processor with an ARM big.LITTLE architecture, and the final calculation results are output.

[0014] Preferably, the step of calculating the local activity of the preprocessed matrix data includes:

[0015] The preprocessed matrix data is divided into basic sub-blocks of a reference size, and the proportion of non-zero elements and the variance of numerical distribution are calculated for each basic sub-block.

[0016] Based on the proportion of non-zero elements and the variance of numerical distribution of each basic sub-block, the relative importance score of each basic sub-block is calculated to obtain the sub-block's computational contribution.

[0017] Based on the contribution of the sub-blocks, the statistical distribution data of the local activity of the basic sub-blocks is calculated using the NEON SIMD instruction to obtain the local activity distribution map of the matrix.

[0018] The local activity distribution map is standardized to obtain a standardized local activity distribution map.

[0019] Based on the standardized local activity distribution map, a sparse data structure is used to store basic sub-block information whose activity exceeds a first preset threshold.

[0020] Preferably, the hotspot area identification includes:

[0021] Based on the preprocessed matrix data, the statistical distribution data of global activity is calculated, and a global activity distribution map is constructed. The statistical distribution data of global activity includes the mean and standard deviation.

[0022] Based on the statistical distribution data of global activity, the OTSU algorithm is used to optimize the activity threshold cut-off point to obtain the optimized activity threshold.

[0023] Obtain the optimized activity threshold and convert the global activity distribution map into a hotspot distribution binary map;

[0024] Receive the hotspot distribution binary map, execute the connected component labeling algorithm, cluster and merge adjacent hotspot regions to obtain the clustering and merging result;

[0025] Obtain the clustering and merging results, apply morphological operations to refine the hotspot regions, remove isolated hotspots with an area smaller than the second preset threshold, and obtain the refined hotspot regions.

[0026] Receive the modified hotspot areas and obtain the location information, shape features, and activity features of each hotspot area.

[0027] Preferably, the step of calculating the optimal block size range of the matrix based on the long-tail distribution characteristics of the matrix and the multi-level cache capacity parameters in the ARM processor information, and generating an asymmetric block partitioning scheme, includes:

[0028] Obtain the statistical distribution data of the global activity and the statistical distribution data of the local activity, design blocks adapted to L1 cache for regions with activity exceeding a third preset threshold, and design blocks adapted to L2 / L3 cache for regions with activity below a fourth preset threshold, to obtain an initial block segmentation scheme.

[0029] Based on the initial segmentation scheme, cross-segment hotspot regions are identified, and overlapping cutting is used to ensure that hotspot elements are completely contained within a single segment, and segmentation boundary data is output.

[0030] Obtain the block boundary data and perform memory alignment optimization to ensure that the block boundaries are aligned with cache lines;

[0031] Obtain historical execution data and fine-tune the size and shape of the blocks based on execution efficiency metrics.

[0032] Preferably, establishing the mapping relationship between matrix features and optimal block parameters includes:

[0033] Obtain block execution data, and collect the execution time, cache hit rate and instruction throughput of each block;

[0034] Obtain performance metrics and analyze the correlation between the block execution data and the performance metrics;

[0035] Obtain the correlation data between the block execution data and the performance indicators, and establish a mapping relationship model between matrix features and optimal block parameters;

[0036] Deploy the mapping model to the ARM TrustZone environment and update the block strategy history library;

[0037] Obtain historical database data and record the optimal block parameters under different matrix features.

[0038] Preferably, the task scheduling scheme includes:

[0039] Obtain block characteristic data, allocate blocks with computational density exceeding a fifth preset threshold to the first core for processing, allocate blocks with computational density below a sixth preset threshold to the second core for processing, and ensure that the number of the first core is greater than the number of the second core;

[0040] Receive block priority data and set task execution order and preemption strategy;

[0041] Obtain the core features of the ARM processor, configure core affinity, obtain the core affinity configuration, and specify the execution core for a specific type of task;

[0042] It receives the dependencies of the tasks to be executed, and enables task group scheduling and synchronization checkpoint setting;

[0043] Obtain cache characteristic data, optimize shared cache and memory access strategies, and reduce inter-core data transfer.

[0044] Preferably, performing matrix calculations on an ARM big.LITTLE architecture processor includes:

[0045] Obtain the block characteristic data and select the corresponding NEON instruction set optimized kernel for different types of blocks;

[0046] Obtain the block activity characteristics and configure the parameters of the mixed precision calculation matrix;

[0047] Obtain the memory access mode, configure ARM cache prefetch instructions, and optimize memory access order;

[0048] Based on the core affinity configuration, each block computation is executed in parallel to obtain the computation results of each block.

[0049] Obtain the calculation results of each block, and perform result merging and correctness verification.

[0050] Preferably, the method further includes:

[0051] We obtain the matrix operation process and the characteristics of the ARM processor, define the operation axiomatic system using a formal language, and obtain the formal specification;

[0052] The formal specifications are analyzed and processed to generate system verification assertions and output executable verification rules.

[0053] According to the executable verification rules, the correctness of the asymmetric block partitioning scheme is verified using theorem proving tools, and a verification report is generated.

[0054] Based on the verification report and the mixed accuracy calculation data, error propagation analysis was performed to establish an accuracy error model;

[0055] Based on the aforementioned accuracy error model and actual execution data, formal verification is performed, and formal proof results are output.

[0056] Preferably, the method further includes on-time verification and recovery, including:

[0057] Obtain matrix calculation execution status information, perform verification checks, and generate verification results;

[0058] Based on the verification results and the preset error level standards, perform hierarchical error classification and determine the error handling strategy;

[0059] Based on the error handling strategy and accuracy problem data, perform accuracy path adjustment and output the corrected calculation path;

[0060] Based on the modified computation path and the numerical distribution characteristics of the matrix, numerical stability adjustment is performed to obtain optimized computation parameters;

[0061] Based on the optimized calculation parameters and the current ARM processor state, task scheduling is reorganized, and a new execution plan is output.

[0062] Preferably, the method includes:

[0063] Obtain the preprocessed matrix data and state-space model parameters, perform dynamic characteristic analysis, and obtain the feature sequence;

[0064] Construct a complete computational operation graph, combine it with the feature sequence, identify fusionable operation combinations, and output a fusion scheme;

[0065] Based on the aforementioned fusion scheme and the characteristics of the ARM processor, optimized execution code is obtained;

[0066] Collect runtime information from multiple sources, and use the optimized execution code to output a dynamic switching strategy;

[0067] Based on the dynamic switching strategy and execution feedback data, an optimization feedback model is constructed to obtain a continuous optimization scheme.

[0068] Preferably, the method further includes blending accuracy optimization, comprising:

[0069] Obtain the numerical distribution characteristics and accuracy requirements of the matrix, perform block floating-point representation design, and output a bidirectional block floating-point scheme;

[0070] Based on the bidirectional block floating-point scheme and matrix region features, ternary region identification is performed to determine the quantization region, wherein the matrix region features are a set of parameters describing the geometric, numerical, and computational features of different spatial regions of the matrix;

[0071] The quantization region and precision parameters are subjected to ternary quantization with scaling factor to obtain compressed representation data, wherein the precision parameters are a set of configuration parameters that control the precision of numerical representation and calculation.

[0072] Perform a pre-filling operation on the compressed representation data and the memory characteristics of the ARM processor, and output a memory access optimization scheme;

[0073] Based on the memory access optimization scheme and the ARM processor instruction set, bit operation acceleration processing is performed to obtain the final optimization result.

[0074] Preferably, the method further includes energy efficiency optimization and monitoring, including:

[0075] Acquire ARM processor status data and energy efficiency targets, execute controller design, and output energy efficiency control strategy;

[0076] Based on the energy efficiency control strategy and ARM processor parameters, dynamic adjustments are made to obtain optimized operating parameters, wherein the ARM processor parameters are a set of parameters describing the hardware characteristics and operating status of the ARM architecture processor.

[0077] Error tracking analysis is performed on the optimized operating parameters and precision representation data, and a cumulative error report is output. The precision representation data is detailed information recording different numerical precision representation methods.

[0078] Based on the accumulated error report and the characteristics of the calculation task, an accuracy enhancement configuration is performed to obtain a balanced accuracy scheme. The characteristics of the calculation task are feature parameters that describe the attributes and requirements of the matrix calculation task.

[0079] Based on the balanced accuracy scheme and system operation data, an accuracy energy efficiency model is constructed, and the final optimization strategy is output.

[0080] This invention also provides an adaptive optimization system for matrix computation based on ARM architecture, comprising:

[0081] The acquisition module is used to acquire the matrix data to be processed and ARM processor information, and to preprocess the matrix data to be processed to obtain the preprocessed matrix data.

[0082] The identification module is used to calculate local activity and identify hotspot regions in the preprocessed matrix data to determine the long-tail distribution characteristics of the matrix.

[0083] The calculation module is used to receive the long-tail distribution characteristics of the matrix and the multi-level cache capacity parameters of the ARM processor, calculate the optimal block size range, and generate an asymmetric block scheme.

[0084] A module is established to obtain the asymmetric partitioning scheme, collect the execution time and cache hit rate of each partition, and establish a mapping relationship between matrix features and optimal partitioning parameters;

[0085] The generation module is used to obtain the asymmetric partitioning scheme and mapping relationship, calculate the computational density and memory access mode of each partition, and generate a task scheduling scheme.

[0086] The output module is used to obtain the task scheduling scheme, perform matrix calculations on the ARM big.LITTLE architecture processor, and output the final calculation results.

[0087] The beneficial effects of this invention are:

[0088] (1) By accurately identifying the long-tail distribution characteristics of matrix elements and implementing the asymmetric partitioning strategy, the allocation of computing resources is precisely matched with the matrix characteristics, which significantly improves cache utilization and computing efficiency.

[0089] (2) Combining the characteristics of the ARM big.LITTLE heterogeneous multi-core architecture, computationally intensive tasks are allocated to the big core and memory-intensive tasks are allocated to the small core, so as to achieve the optimal matching between task characteristics and processing core characteristics, improve overall computing performance and reduce energy consumption;

[0090] (3) Through precise online detection of matrix hotspot areas and boundary optimization technology, we ensure that highly active elements are fully contained in a single block, reduce cross-block communication overhead, and optimize execution efficiency.

[0091] (4) Use the ARM TrustZone security environment to maintain the execution history database, establish the mapping relationship between matrix features and optimal block parameters, realize experience-driven continuous optimization, and adapt to different types of matrix calculation tasks;

[0092] (5) By using a hybrid precision computing strategy, differentiated precision configurations are applied to different activity regions, which improves processing efficiency and reduces energy consumption while maintaining computing precision. This is especially suitable for resource-constrained ARM devices. Attached Figure Description

[0093] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the embodiments will be briefly described below. These drawings are incorporated in and constitute a part of this specification. They illustrate embodiments conforming to this disclosure and, together with the specification, serve to explain the technical solutions of this disclosure. It should be understood that the following drawings only show some embodiments of this disclosure and should not be considered as limiting the scope. Those skilled in the art can obtain other related drawings based on these drawings without creative effort.

[0094] Figure 1 This is a flowchart of an adaptive optimization method for matrix computation based on ARM architecture according to the present invention;

[0095] Figure 2 This is a flowchart of the adaptive block generation method of the present invention;

[0096] Figure 3 This is a flowchart of the historical execution data feedback and optimization method of the present invention;

[0097] Figure 4 This is a flowchart of the heterogeneous kernel task weight prediction and scheduling method of the present invention;

[0098] Figure 5 This is a flowchart of the NEON instruction set optimized execution method of the present invention;

[0099] Figure 6 This is a structural diagram of an adaptive optimization system for matrix computation based on ARM architecture according to the present invention. Detailed Implementation

[0100] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. The components of the embodiments of this disclosure described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this disclosure provided in the accompanying drawings is not intended to limit the scope of the claimed disclosure, but merely represents selected embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without inventive effort are within the scope of protection of this disclosure.

[0101] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0102] In this document, the term "and / or" merely describes a relationship, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" in this document means any combination of at least two of any one or more elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0103] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0104] Example 1

[0105] like Figure 1 As shown, this invention provides an adaptive optimization method for matrix computation based on ARM architecture, which mainly includes the following steps:

[0106] Step 101: Obtain the matrix data to be processed and the ARM processor information, and preprocess the matrix data to be processed to obtain the preprocessed matrix data;

[0107] The preprocessing in step 101 specifically includes: loading the matrix data into main memory via DMA, and obtaining the multi-level cache capacity information and core configuration parameters of the ARM processor. For the matrix data, the system supports multiple input formats, including dense matrix format and compressed sparse row format. Processor parameter information includes L1 / L2 / L3 cache capacity, core configuration, and NEON vector unit parameters, etc.

[0108] This step first receives two key inputs: the matrix data to be processed and the target ARM processor information. The system supports multiple matrix data input formats, including dense matrix format and compressed sparse row format (CSRformat), which is significant for processing matrix data in different scenarios. Subsequently, the system efficiently loads the matrix data into main memory through direct memory access (DMA) mechanism. This mechanism significantly reduces the overhead of CPU intervention in data transfer and improves data loading efficiency. At the same time, the system automatically detects and obtains detailed parameter information of the target ARM processor, focusing on multi-level cache capacity (including L1 instruction cache, L1 data cache, L2 unified cache, and L3 shared cache on some high-end ARM chips), core configuration (including the number, frequency, and power consumption characteristics of big and little cores under the big.LITTLE architecture), and NEON vector unit parameters (including register width and supported instruction set extensions). The system organizes these processor parameters into a structured configuration set for easy reference by subsequent optimization algorithms.

[0109] Step 102: Calculate local activity and identify hotspot regions on the preprocessed matrix data to determine the long-tail distribution characteristics of the matrix.

[0110] In this step, the system first divides the matrix into fixed-size basic analysis units (basic sub-blocks), typically choosing 8×8 or 16×16 dimensions. This size selection considers two factors: it must be small enough to capture local feature variations, and large enough to reduce analysis overhead. For each basic sub-block, the system calculates activity indicators such as the proportion of non-zero elements, the variance of numerical distribution, and computational contribution. These calculations are accelerated using NEON SIMD instructions, such as VABD.F32, VCGT.F32, and VPADD.F32. Subsequently, the system uses an adaptive thresholding algorithm to identify high-activity regions, converting the activity distribution map into a binary hotspot distribution map, and uses a connected component labeling algorithm to cluster and merge adjacent hotspot regions. Finally, the system extracts long-tail distribution feature descriptions of the matrix, including key parameters such as overall sparsity, hotspot region proportion, hotspot distribution divergence, and long-tail exponent, providing an important basis for subsequent block-sharing strategy formulation.

[0111] Step 103: Based on the long-tail distribution characteristics of the matrix and the multi-level cache capacity parameters in the ARM processor information, calculate the optimal block size range of the matrix and generate an asymmetric block scheme.

[0112] In this step, the system first establishes a cache optimization model based on the multi-level cache characteristics of the ARM processor, considering parameters such as cache capacity at each level, cache line size, cache associativity, and access latency, to calculate the theoretically optimal block size range. Subsequently, based on the long-tail distribution characteristics of the matrix, the system adopts differentiated block partitioning strategies for different activity regions: small blocks (e.g., 4×4, 8×8, or 16×16) are designed for highly active regions (hot spots) to ensure full adaptation to the L1 cache, maximizing cache utilization and NEON vectorization efficiency; large blocks (e.g., 32×32, 64×64, or larger) are designed for low-active regions (long tail) to match L2 / L3 cache capacity and reduce task scheduling overhead. The system also uses overlapping cutting techniques to handle cross-block hot spots, ensuring that highly active elements are completely contained within a single block, and performs memory alignment optimization to ensure that block boundaries are aligned with cache lines, avoiding additional overhead caused by cross-cache line access.

[0113] Step 104: Based on the asymmetric partitioning scheme, collect the execution time and cache hit rate of each partition, and establish a mapping relationship between matrix features and optimal partitioning parameters, wherein the partition is the basic sub-block of the preprocessed matrix data.

[0114] In this step, the system collects detailed performance data for each block execution through the ARM Performance Monitoring Unit (PMU), including metrics such as execution time, cache hit rate, instruction throughput, and memory access latency. The system preprocesses this raw performance data, including outlier detection, missing value imputation, and data standardization. Then, it correlates the performance data with block characteristics to construct an analysis matrix. Through multidimensional correlation analysis, the system identifies key factors affecting performance, including the functional relationship between block size and cache hit rate, the relationship between matrix activity patterns and computational efficiency, and ARM architecture-specific performance factors. Based on these analyses, the system establishes a mapping model between matrix characteristics and optimal block parameters. Using a lightweight machine learning algorithm, it predicts the optimal block parameters under different matrix characteristics and deploys this model in the ARM TrustZone security environment, continuously updating the historical block strategy database.

[0115] Step 105: Based on the asymmetric partitioning scheme and the mapping relationship between the matrix features and the optimal partitioning parameters, calculate the computational density and memory access pattern of each partition, and generate a task scheduling scheme.

[0116] The system analyzes the computational characteristics of each block, including computational density ratio (CDR), memory access patterns, parallelism, and dependencies. Based on these characteristics, the system applies a pre-trained lightweight task weight prediction model to evaluate the execution efficiency and energy consumption of each block on different processing cores. The system adopts a "computation-intensive priority allocation strategy," assigning blocks with high CDR (typically small, highly active blocks) to large cores and blocks with low CDR (typically large, inactive blocks) to small cores. The system designs a core load balancing algorithm to ensure a reasonable workload ratio between large and small cores and implements a work-stealing mechanism, energy-aware scheduling, and temperature balancing strategies. Finally, the system generates a complete task scheduling scheme, including task priority, core affinity, and execution timing information, to guide subsequent matrix computation execution.

[0117] Step 106: Based on the task scheduling scheme, perform matrix calculations on the ARM big.LITTLE architecture processor and output the final calculation results.

[0118] Specifically, based on the characteristics of the blocks and the task scheduling scheme, the system selects the most suitable NEON instruction set optimized kernel for different types of blocks. For small blocks with high activity, the system selects computationally intensive optimized instruction templates, such as VLDM, VMLA, and VSTM; for large blocks with low activity, the system selects memory-optimized instruction templates, focusing on optimizing cache utilization and memory access patterns. The system also configures mixed-precision computation parameters according to the block activity characteristics, using FP32 for high-activity regions, FP16 for medium-activity regions, and INT8 or lower precision for low-activity regions. The system configures ARM cache prefetch instructions (PLD) to preload data to be used into the cache and optimize memory access order to reduce cache miss rate. Based on core affinity configuration, the system executes block computations in parallel on heterogeneous multi-cores to achieve dynamic load balancing. Finally, the system collects all block computation results, reassembles them into a complete matrix, performs multi-level verification checks to ensure the correctness and reliability of the computation results, and outputs the final optimized computation results.

[0119] Example 2

[0120] The detailed steps of this invention for calculating local activity and identifying hotspot regions in preprocessed matrix data include:

[0121] Step 201: Divide the preprocessed matrix data into basic sub-blocks of a reference size, and calculate the proportion of non-zero elements and the variance of numerical distribution for each basic sub-block;

[0122] In step 201, the system divides the matrix into basic sub-blocks of 8×8 or 16×16. This size selection considers two factors: firstly, it should be small enough to capture local feature changes, and secondly, it should be large enough to reduce analysis overhead. For the ARM architecture, the 8×8 sub-block size occupies exactly 256 bytes, which is suitable for loading into an L1 cache line.

[0123] Specifically, the system first determines the appropriate size for the basic sub-blocks in the ARM architecture, typically choosing 8×8 or 16×16. This choice carefully balances computational efficiency with analytical accuracy: too small a size leads to excessive analysis overhead, while too large a size results in the loss of local feature variations. For the ARM architecture, an 8×8 sub-block size (assuming float type) occupies exactly 256 bytes, suitable for loading into an L1 cache line (typically 64-128 bytes), enabling efficient local activity analysis. The system traverses the entire matrix, performing quantitative analysis on each basic sub-block. First, it calculates the percentage of non-zero elements (NZR), which is the number of non-zero elements in the sub-block divided by the total number of elements in the sub-block. For floating-point matrices, the system sets a small threshold (typically 1e-6), treating elements with absolute values ​​below this threshold as zero. Then, it calculates the variance of the numerical distribution (VDS), reflecting the statistical variance of the absolute values ​​of elements within the sub-block. This metric captures the dispersion of numerical distributions within the sub-block, which is particularly important for identifying hotspot regions in the matrix.

[0124] Step 202: Based on the proportion of non-zero elements and the variance of numerical distribution in each basic sub-block, calculate the relative importance score of each basic sub-block to obtain the sub-block's computational contribution. In this step, based on the basic features obtained in step 201, the system further calculates the computational contribution (CC) of each sub-block to estimate its relative importance in matrix computation. For common operations such as matrix multiplication, the system uses a weighted combination formula, comprehensively considering the proportion of non-zero elements, the variance of numerical distribution, and the sum of the absolute values ​​of elements to generate an importance score for each sub-block. This scoring mechanism can effectively identify key sub-blocks that, although having a small number of elements, have significant numerical values ​​and contribute greatly to the computational results. For example, in the attention matrix of a deep learning model, there are often a few highly active regions that determine the final computational accuracy. The system uses normalization to map the computational contribution to the [0,1] interval for easier subsequent processing and comparison. This refined importance assessment is the basis for subsequent asymmetric block partitioning strategies, ensuring that computational resources are concentrated on the most needed regions.

[0125] Step 203: Based on the contribution of the sub-blocks, the system uses NEON SIMD instructions to calculate the statistical distribution data of the local activity of the basic sub-blocks, obtaining a local activity distribution map of the matrix. In this step, the system fully utilizes the NEON SIMD (Single Instruction Multiple Data) instruction set of the ARM architecture to perform efficient local activity calculations on the basic sub-blocks. The system uses the VABD.F32 (Absolute Difference) instruction to quickly calculate the absolute value of elements, the VCGT.F32 (Greater Than Compare) instruction to efficiently identify non-zero elements exceeding a threshold, and the VPADD.F32 (Parallel Addition) instruction to accelerate the accumulation operation. For large matrices, the system adopts a multi-threaded parallel processing strategy, dividing the matrix into multiple regions, with each thread responsible for the activity calculation of one region, significantly improving processing speed. These calculation results are finally integrated into a local activity distribution map of the matrix, which is a dimensionality-reduced representation, where each cell corresponds to a basic sub-block of the original matrix, and the cell value is the activity index of that sub-block. Through this local activity analysis, the system can accurately capture the differences in computational density and importance in different regions of the matrix, providing a key basis for subsequent hotspot identification and block segmentation strategies.

[0126] Step 204: Standardize the local activity distribution map to obtain a standardized local activity distribution map. In this step, the system standardizes the local activity distribution map to ensure that matrices of different sizes and types are comparable and to facilitate the subsequent setting of a common threshold. The standardization process first calculates global statistical features, including the minimum, maximum, average, and standard deviation of activity. Then, the system uses an appropriate standardization method, such as min-maximum standardization or Z-score standardization, to map the activity values ​​of each sub-block to a uniform range (usually the [0,1] interval). This process ensures that matrices of different scales can use a consistent activity metric, avoiding comparison bias caused by differences in the absolute values ​​of matrix elements. For matrices with extreme values, the system also applies robust standardization methods, such as percentile-based scaling, to reduce the impact of outliers on the overall distribution. The standardized activity distribution map more clearly shows the relative activity patterns of the matrix, facilitating accurate identification of hotspot regions and long-tail distribution characteristics.

[0127] Step 205: Based on the standardized local activity distribution map, use a sparse data structure to store basic sub-block information whose activity exceeds the first preset threshold.

[0128] In this step, the system uses an efficient sparse data structure to store information on sub-blocks with significant activity levels, instead of saving the complete activity distribution map. The system sets a first preset threshold (typically 0.3-0.5, depending on the matrix type) and only saves information on sub-blocks with activity levels exceeding this threshold, including the sub-block's location coordinates and corresponding activity values. This sparse representation method significantly saves storage space, which is especially important for large matrices. In implementation, the system can use efficient data structures such as coordinate lists (COO), compressed sparse rows (CSR), or quadtrees, selecting the most suitable representation method based on the matrix's sparsity pattern. For example, for matrices where active regions exhibit a block-like distribution, quadtree representation provides good spatial locality; while for matrices with dispersed active regions, coordinate lists may be more suitable. This sparse representation not only reduces storage overhead but also accelerates subsequent hotspot region identification and processing, because the system only needs to focus on sub-blocks with significant activity levels, without needing to process a large number of low-activity regions.

[0129] Step 206: Based on the preprocessed matrix data, calculate the statistical distribution data of global activity and construct a global activity distribution map. The statistical distribution data of global activity includes the mean and standard deviation.

[0130] In this step, the system analyzes the activity distribution characteristics of the matrix from a holistic perspective and calculates key statistical indicators. First, the system calculates the average activity level (μ) across the entire matrix, reflecting the overall activity level. Then, it calculates the standard deviation (σ), characterizing the dispersion of the activity distribution; a larger standard deviation usually indicates the presence of significant hotspot regions in the matrix. The system also calculates higher-order statistics, such as skewness (reflecting the asymmetry of the distribution) and kurtosis (reflecting the sharpness of the distribution), which help identify long-tailed distributions. Furthermore, the system calculates quantile information for activity, such as the 25th, 50th (median), 75th, and 90th percentiles, which provide a more comprehensive description of the shape of the activity distribution. Based on these statistical data, the system constructs a global activity distribution map, visually representing the overall distribution characteristics of activity, such as a histogram or cumulative distribution function (CDF). These global statistical features provide a mathematical basis for identifying hotspot regions, enabling the system to adaptively set hotspot judgment criteria according to the overall characteristics of the matrix.

[0131] Step 207: Based on the statistical distribution data of the global activity, the OTSU algorithm is used to optimize the activity threshold segmentation point to obtain the optimized activity threshold.

[0132] In this step, the system uses the OTSU algorithm (Otsu algorithm) to automatically determine the optimal activity threshold, dividing the matrix region into hotspot and non-hotspot regions. The OTSU algorithm is a classic image segmentation method whose core idea is to maximize the inter-class variance and find the optimal binary classification threshold. The system treats the activity distribution as a gray-level histogram, traversing possible thresholds to calculate the average activity and weights of hotspot and non-hotspot regions, and selecting the threshold that maximizes the variance between the two classes as the optimal segmentation point. The advantage of this adaptive thresholding method is that it does not require manually setting a fixed threshold, but can automatically adjust the segmentation criteria according to the activity distribution characteristics of different matrices. For matrices with highly uneven activity distributions, the system can also extend to use a multi-threshold OTSU algorithm to divide the matrix region into multiple activity levels, achieving more refined hotspot classification. The thresholds determined by the OTSU algorithm have strong theoretical basis, enabling more objective identification of hotspot regions in the matrix and providing a reliable foundation for subsequent segmentation strategies.

[0133] Step 208: Obtain the optimized activity threshold and convert the global activity distribution map into a hotspot distribution binary map.

[0134] In this step, the system binarizes the global activity distribution map based on the optimal threshold determined by the OTSU algorithm, generating a hotspot distribution binary map. For each basic sub-block, if its activity value exceeds the optimized threshold, it is marked as 1 (representing a hotspot region) in the binary map; otherwise, it is marked as 0 (representing a non-hotspot region). The binarization process can utilize ARM NEON instructions for vectorization, such as using VCGT (vector comparison greater than) and VBSL (vector bit selection) instructions, to efficiently implement large-scale binarization operations. The generated hotspot distribution binary map clearly shows the spatial distribution of hotspot regions in the matrix, simplifying the complexity of subsequent processing. For special cases, such as extremely sparse matrices or matrices with highly uneven activity distribution, the system also applies additional optimization strategies, such as combining a fixed percentage method (e.g., taking the top 10% of the most active sub-blocks as hotspots) with the results of the OTSU algorithm to ensure the rationality and stability of hotspot identification.

[0135] Step 209: Receive the hotspot distribution binary map, execute the connected component labeling algorithm, and cluster and merge adjacent hotspot regions to obtain the clustering and merging results.

[0136] In this step, the system applies a connected component labeling algorithm to merge spatially adjacent hotspot sub-blocks into larger connected regions. The system first scans the binary map of the hotspot distribution, assigning a temporary label to each cell (hotspot sub-block) with a value of 1. Then, in a second scan, the system merges adjacent cells with the same label, establishing equivalence class relationships, and finally labels all sub-blocks belonging to the same connected region with the same unique identifier. The system implements two neighbor definition strategies: 4-adjacency (considering only the adjacency in the four directions of up, down, left, and right) and 8-adjacency (additionally considering the four diagonal directions). For large matrices, the system employs parallelized connected component labeling algorithms, such as parallel two-pass scanning or parallel algorithms based on the Union-Find data structure, to accelerate the processing. After connected component labeling, the system obtains a series of hotspot clusters, each composed of multiple adjacent highly active sub-blocks. This clustering and merging not only reduces the complexity of subsequent processing but also better reflects the physical characteristics of hotspot regions in actual matrix calculations, because in real applications, highly active elements often exhibit spatially clustered distributions.

[0137] Step 210: Obtain the clustering and merging results, apply morphological operations to refine the hotspot regions, remove isolated hotspots with an area smaller than the second preset threshold, and obtain the refined hotspot regions.

[0138] In this step, the system further optimizes the connected component labeling results, applying mathematical morphology operations to improve the shape and coherence of hotspot regions. First, the system applies a morphological opening operation (erosion followed by dilation) to remove small protrusions and noise; then, it applies a morphological closing operation (dilation followed by erosion) to fill small holes within the hotspot regions, making the region boundaries smoother. These operations are processed using structured elements (typically 3×3 or 5×5 square or cross-shaped convolution kernels), which can be efficiently implemented using ARM NEON instructions. Subsequently, the system sets a second preset threshold (typically 5-10 basic sub-blocks) to remove isolated hotspot regions with areas smaller than this threshold. These small regions are often noisy or unimportant active points; processing them increases the complexity of block segmentation and scheduling with limited benefits. For some special applications, the system also retains small hotspots with special significance, such as elements on the matrix diagonal or known key points. This refinement process significantly improves the quality of hotspot regions, providing a more reasonable region division for subsequent block segmentation strategies.

[0139] Step 211: Receive the modified hotspot areas and obtain the location information, shape features, and activity features of each hotspot area.

[0140] In this step, the system extracts detailed features from each refined hotspot region to construct a complete description of the hotspot region. Location information includes the region's boundary coordinates (top-left and bottom-right corner coordinates) and centroid location, which are directly used for subsequent block localization. Shape features include the region's area (number of basic sub-blocks), perimeter (boundary length), rectangularity (ratio of region area to its smallest bounding rectangle), aspect ratio, and orientation (principal axis direction). These features help design block localization strategies suitable for specific hotspot shapes. Activity features include the region's average activity, maximum activity, activity standard deviation, and activity distribution pattern. These metrics reflect the computational density and importance of the hotspot region. The system integrates this information into a structured hotspot region description, containing a complete feature set for each hotspot region. For a typical deep learning matrix, this step typically identifies 5-20 key hotspot regions, greatly simplifying subsequent processing complexity while preserving the most important computational features in the matrix.

[0141] Step 212: Calculate key feature parameters such as the overall sparsity of the matrix, the proportion of hotspot regions, and the divergence of hotspot distribution, and output the long-tail distribution feature description of the matrix.

[0142] In this step, based on the hotspot region information obtained in the previous steps, the system further extracts and quantifies the long-tail distribution characteristics of the matrix. The system first calculates the overall sparsity index (GS), which is the proportion of non-zero elements in the entire matrix. Then, it calculates the hotspot percentage (HR), the proportion of elements covered by all hotspot regions to the total number of elements in the matrix, and the hotspot activity concentration (HAC), the proportion of non-zero elements within hotspot regions to the total number of non-zero elements in the entire matrix. The system also calculates the hotspot distribution divergence (HDD), using the average distance or standard deviation of the centroids of hotspot regions to characterize the degree of dispersion in the hotspot distribution. A higher divergence value indicates a more dispersed hotspot distribution, which may require a more complex partitioning strategy. Furthermore, the system calculates the long-tail index (α) by fitting a power-law distribution P(x) ∝ x^(-α), reflecting the degree of long-tail distribution; a larger α value indicates a more concentrated distribution. The system also calculates the Gini coefficient (G) and entropy value (H), quantifying the characteristics of the activity distribution from the perspectives of unevenness and information theory, respectively. Finally, based on these features, the system classifies the matrix into "strong long-tailed," "moderately long-tailed," "weakly long-tailed," or "uniformly distributed" types, providing guidance for subsequent optimization strategy selection. These long-tailed distribution features collectively constitute the matrix's feature fingerprint, which is a key input for generating adaptive block partitioning strategies.

[0143] Example 3

[0144] like Figure 2 As shown, the detailed steps for generating the adaptive block partitioning strategy of the present invention include:

[0145] Step 301: Obtain the statistical distribution data of the global activity and the statistical distribution data of the local activity, design blocks adapted to L1 cache for regions with activity exceeding a third preset threshold, and design blocks adapted to L2 / L3 cache for regions with activity below a fourth preset threshold, to obtain an initial block segmentation scheme.

[0146] In this step, the system first comprehensively analyzes the global activity distribution and local activity characteristics of the matrix to identify high computational density regions. The system sets a third preset threshold (typically 0.7-0.8, dynamically adjustable based on application scenarios) and marks regions with activity exceeding this threshold as high-priority processing objects. For these highly active regions, the system designs a small-size block strategy to ensure that the blocks fully adapt to the ARM processor's L1 cache. The system analyzes L1 cache characteristics in detail, including capacity (typically 16-64KB), row size (typically 64 bytes), and associativity (typically 4-way or 8-way set-associative), and then calculates the optimal block size. For typical ARM architectures, the system typically chooses block sizes of 4×4, 8×8, or 16×16, which ensure that block data and intermediate computation results remain entirely in the L1 cache, maximizing cache hit rate. The system also considers the characteristics of NEON vector instructions and optimizes the block size to meet SIMD processing requirements. For example, for 32-bit floating-point numbers, the dimension of the inner loop should be a multiple of the four elements that a 128-bit NEON register can process. This small-size block strategy significantly improves the computational efficiency of highly active regions and reduces cache misses and memory access latency.

[0147] In this step, the system identifies regions in the matrix with activity levels below a fourth preset threshold (typically 0.3-0.4). These regions typically have low computational density and contribute relatively little to the final result. For these inactive regions, the system designs a large-block strategy to match the characteristics of the ARM processor's L2 or L3 cache. The system analyzes the capacity and access characteristics of the L2 cache (typically 256KB-2MB) and L3 cache (typically 2-4MB) and then determines an appropriate block size, typically 32×32, 64×64, or larger. This large-block approach offers several key advantages: first, it reduces the overall overhead of task scheduling, as larger blocks mean fewer tasks; second, it reduces the complexity of block boundary handling; and third, it facilitates the use of ARM's cache prefetching mechanism, improving memory access efficiency. For extremely inactive regions, the system can also employ special optimization strategies, such as using compressed sparse formats (CSR or CSC) for storage, or applying low-precision representations (such as FP16 or INT8), to further reduce memory footprint and improve processing efficiency. This activity-based differentiated partitioning strategy ensures a precise match between computing resource allocation and matrix characteristics, significantly improving overall computing efficiency.

[0148] Step 302: Based on the initial segmentation scheme, identify cross-segment hotspot regions, ensure that hotspot elements are completely contained within a single segment by overlapping cutting, and output segmentation boundary data.

[0149] In step 302, the system processes cross-block hotspot regions using an overlap cutting technique. For cases where adjacent blocks share a hotspot region, the system creates a new block containing the overlapping region. The size of the overlapping region is dynamically adjusted based on the hotspot activity and shape, typically ranging from 10% to 30% of the original block size.

[0150] In this step, the system addresses the issue that the initial partitioning scheme might result in hotspot regions being divided into multiple blocks. This partitioning significantly impacts computational efficiency because hotspot regions across blocks require frequent inter-block communication and data synchronization. The system first identifies cross-block hotspot regions that meet the following conditions: they contain the hotspot region elements identified in step 211, and these elements have been divided into two or more blocks by the initial partitioning scheme. For identified cross-block hotspot regions, the system employs an overlapping segmentation strategy: when adjacent blocks share hotspot regions, a new block containing the overlapping area is created to ensure the hotspot region is completely contained. The size of the overlapping area is dynamically adjusted based on the hotspot activity and shape, typically ranging from 10% to 30% of the original block size. The system also implements a hotspot merging strategy. When multiple small hotspot regions are located close to each other, they are merged into a larger block. The merging condition is based on the ratio of hotspot distance to hotspot size, using an adaptive threshold. Furthermore, the system can adjust the block shape to better accommodate irregular hotspot regions; for example, for strip-shaped hotspots, the block can be adjusted from a square to a rectangle. These boundary optimization techniques significantly improve the locality and efficiency of hotspot processing and reduce cross-block communication overhead, which are key steps in improving overall performance.

[0151] Step 303: Obtain block boundary data and perform memory alignment optimization to ensure that block boundaries are aligned with cache lines.

[0152] In step 303, the system ensures that the block boundaries are aligned with the cache line boundaries, typically multiples of 64 bytes, to avoid additional overhead caused by cross-cache line accesses. Simultaneously, the system adjusts the block start position to meet the memory alignment requirements of NEON vector instruction operations.

[0153] In this step, the system optimizes memory alignment of block boundaries to suit the cache characteristics of ARM processors. The system first obtains the block boundary data output in step 302, including the start and end coordinates of each block. Then, the system performs memory alignment optimization, adjusting the block boundary positions to ensure that the block start address is aligned to the cache line boundary, which is typically a multiple of 64 bytes. This alignment optimization has several important advantages: First, it avoids the additional overhead of accessing split cache lines, improving memory access efficiency; second, it reduces cache conflicts and false sharing issues, especially in multi-core parallel computing environments; third, it optimizes NEON vector instruction access, as many NEON operations require memory address alignment. The system implements an intelligent adjustment algorithm to minimize redundant data caused by alignment adjustments while maintaining the integrity of the block logic. For example, where possible, the system will choose to align the block start address upwards while aligning the end address downwards to avoid unnecessary expansion. For hotspot regions that must cross cache line boundaries, the system designs special access patterns to reduce the frequency of cross-line access. This memory alignment optimization fully utilizes the characteristics of the ARM cache architecture, significantly improving memory access efficiency, which is particularly important for computations with limited memory bandwidth.

[0154] Step 304: Obtain historical execution data and fine-tune the block size and shape based on execution efficiency metrics. In this step, the system further optimizes the block parameters based on historical execution data through a feedback optimization mechanism.

[0155] The system first checks for available historical execution data, derived from the feedback mechanism in step 4 or a pre-defined optimization experience base. If historical data is available, the system calculates the similarity between the current matrix features and the matrix features recorded in the historical data, using a multi-dimensional feature vector distance metric, including matrix dimension, sparsity pattern, and hotspot distribution features. The system selects the historical record with the highest similarity as a reference, extracting block parameters, including block size, shape, and overlap strategy, and applies these parameters to adjust the current block scheme. The system also progressively fine-tunes the current block parameters based on performance trends in historical records. For example, if historical data shows that increasing the size of a specific type of block improves performance, similar adjustments are attempted in the current scheme, with the variation controlled within a safe range, typically ±20% of the baseline value. For the first execution (without historical data), the system adopts a safe default strategy, such as setting the block size to 85%-95% of the theoretical optimal value, to prevent potential cache capacity estimation errors. The system also performs block equalization, adjusting the size of blocks with similar activity levels to make them as uniform as possible, reducing scheduling complexity. Through this experience-based fine-tuning, the system can continuously learn and improve its block partitioning strategy, adapt to the characteristics of different matrix calculations, and provide optimized execution performance.

[0156] Example 4

[0157] like Figure 3 As shown, the detailed steps of historical execution data feedback and optimization in this invention include:

[0158] Step 401: Obtain block execution data, and collect the execution time, cache hit rate and instruction throughput of each block.

[0159] In step 401, the system collects detailed execution data through the ARM Performance Monitoring Unit (PMU), including execution time metrics, cache-related metrics, instruction execution metrics, and memory access metrics. This data provides empirical evidence for subsequent optimization.

[0160] The system performs matrix calculations based on the block-based scheme output in step 3, while simultaneously activating the ARM processor's Performance Monitoring Unit (PMU) to collect detailed execution performance data. The ARM PMU is a hardware counter system integrated within the processor, capable of recording various performance events with minimal overhead. The system focuses on monitoring the following performance metrics: First, execution time metrics, including the absolute execution time (microseconds) of each block, normalized execution time (time per element), and variance in execution time between blocks; these metrics directly reflect computational efficiency and load balancing. Second, cache-related metrics, obtained through PMU event counters such as L1D_CACHE_REFILL and L2D_CACHE_REFILL, including L1 / L2 / L3 cache hit rate, cache line replacement frequency, and TLB miss rate; these metrics reflect memory system efficiency. Third, instruction execution metrics, including instruction throughput (IPC), branch prediction failure rate, NEON instruction percentage, and instruction pause cycles; these metrics reflect processor core utilization efficiency. Finally, memory access metrics, including memory bandwidth utilization, memory access latency, and cross-node memory access ratio (in multi-chip systems). The system employs a low-interference design to collect this data, using the PMU's sampling mode instead of a full counting mode, and batch processing for data aggregation to minimize the impact on the main computational process. This detailed performance data provides a solid empirical foundation for subsequent optimization and is a key input for data-driven optimization.

[0161] Step 402: Obtain performance metrics and analyze the correlation between the block execution data and the performance metrics.

[0162] In step 402, the system performs multidimensional correlation analysis, including single-factor performance sensitivity analysis, multi-factor interaction effect analysis, and hotspot bottleneck identification. Through these analyses, the system can identify key factors affecting performance.

[0163] In this step, the system performs in-depth analysis of the raw performance data collected in step 401 to identify key factors affecting performance. The system first preprocesses the raw data, including outlier detection and handling, missing value imputation, data standardization, and time series smoothing, to ensure the reliability of the analysis. Then, the system correlates the performance data with block features to construct a multi-dimensional analysis matrix, including feature dimensions (block size, location, activity, etc.), performance dimensions (execution time, cache hit rate, etc.), and environmental dimensions (CPU frequency, temperature, etc.). The system performs multi-level correlation analysis: First, single-factor performance sensitivity analysis is conducted, calculating the Pearson correlation coefficient between each feature and key performance indicators (such as execution time), plotting scatter plots to identify linear / non-linear relationships, and using ANOVA variance analysis to assess the significance of performance differences for categorical features. Second, multi-factor interaction effect analysis is performed, identifying the impact of interactions between features on performance, such as the interaction between block size and cache capacity on cache hit rate, and using methods such as partial least squares regression to handle multicollinearity among features. Third, hotspot bottleneck localization involves in-depth analysis of blocks with abnormal performance, identifying the causes of bottlenecks, and classifying common performance problem patterns, such as cache thrashing and misprediction. The system pays particular attention to several key correlation patterns: the functional relationship between block size and cache hit rate, the relationship between matrix activity patterns and computational efficiency, the impact of non-zero element distribution on NEON vectorization efficiency, and the adaptability differences of the ARM big.LITTLE core to different block characteristics. These analytical results directly guide the formulation of subsequent optimization strategies, ensuring that optimization decisions are based on a solid data foundation.

[0164] Step 403: Obtain the correlation data between the block execution data and the performance indicators, and establish a mapping relationship model between matrix features and optimal block parameters.

[0165] In step 403, the system uses a lightweight machine learning algorithm to construct a mapping relationship model, which is divided into a classification layer (using decision trees or simplified random forests), a regression layer (using piecewise linear regression or simplified multilayer perceptrons), and a fine-tuning layer (using local search algorithms such as Hill Climbing or simulated annealing).

[0166] In this step, the system constructs a machine learning model to predict the optimal block parameters based on the correlation analysis results from step 402. The system first defines an optimization objective function, typically minimizing the total execution time while balancing energy consumption, memory usage, and computational accuracy. These objectives are combined into a weighted objective function F = w1T + w2E + w3M, where T is time, E is energy consumption, M is memory usage, and w are the corresponding weights. The system constructs a training dataset, where the feature vector X contains features such as matrix dimension, sparsity, and hotspot distribution patterns; the label vector Y contains parameters such as the corresponding optimal block size, shape, and overlap strategy; and the weight vector W assigns different weights based on sample reliability and importance. Considering the resource limitations of the ARM embedded environment, the system adopts a lightweight model structure to implement a hierarchical prediction framework: the first layer predicts the block partitioning strategy type (uniform / asymmetric / mixed), using decision trees or simplified random forests; the second layer predicts the main block partitioning parameters (size range, proportion), using piecewise linear regression or simplified multilayer perceptrons; the third layer fine-tunes specific parameters (precise size, overlap), using local search algorithms such as HillClimbing or simulated annealing. The system uses incremental learning to train the model, continuously updating it as new performance data accumulates, and utilizes NEON instructions to accelerate the model training process. To improve generalization ability, the system implements feature engineering (constructing combined features to capture interaction effects), regularization (applying L1 / L2 regularization to reduce overfitting), and cross-validation (using k-fold cross-validation to evaluate model stability). For the cold start problem (novel matrices without historical data), the system employs transfer learning to transfer initial parameters from models of similar matrix types, generating prior knowledge based on the theoretical model. The final established mapping model can accurately predict the optimal block partitioning parameters from matrix features, providing decision support for adaptive optimization.

[0167] Step 404: Deploy the mapping relationship model to the ARM TrustZone environment and update the block strategy history library.

[0168] In step 404, the system deploys and updates the block policy history library within the ARM TrustZone security environment to ensure the reliability of optimization decisions and data integrity. TrustZone provides a hardware isolation mechanism to prevent policy data from being maliciously modified.

[0169] The system securely deploys the mapping model constructed in step 403 to the ARM TrustZone environment and updates the block strategy history database. TrustZone is a security technology provided by the ARM architecture, creating a hardware-isolated trusted execution environment that prevents malicious modification of strategy data and ensures the reliability of optimization decisions. The system designs the data structure of the block strategy history database, using technologies such as LSH (Local Sensitive Hash) to build an efficient index that supports fast similarity queries; the record format includes complete block scheme parameters, execution environment information, and performance results; and lossless compression is applied to data that has not been used for a long time to save storage space. The system executes the policy library update process as follows: First, new data integration: the features of the currently executed matrix and the optimal block parameters are added to the historical library. If similar records exist, a weighted average is calculated to update the parameters, while recording the execution context, such as CPU load, temperature, and other environmental factors. Second, policy generalization and induction: rules covering a wider parameter space are generated based on the model. Common rules are summarized for similar matrix types to reduce redundant storage, extract parameter change trends, and construct dynamic adjustment guidelines. Third, redundancy optimization and pruning: highly similar historical records are identified and merged, outdated records that have been replaced by new data for a long time are deleted, and special case records are retained as guidelines for handling extreme cases. Finally, version management and consistency maintenance: an incremental update mechanism is implemented to ensure the atomicity of library updates, the policy version history is maintained, rollback to stable versions is supported, and the policy library is synchronized in a distributed environment to ensure consistency across nodes. The system pays special attention to the extraction and updating of several types of specialized policies: matrix type specialized policies (such as dedicated optimizations for Toeplitz matrices for convolutional networks and Transformer attention matrices), hardware adaptation policies (parameter differences between different ARM processor models), and dynamic environment response policies (adjustment policies when system load changes). Through the policy library management of the TrustZone security environment, the system enables the secure accumulation and effective utilization of optimization experience.

[0170] Step 405: Obtain historical database data and record the optimal block parameters under different matrix features.

[0171] In this step, the system establishes a complete database of the correspondence between matrix features and optimal partitioning parameters, forming a knowledge base to support subsequent optimization decisions. The system first retrieves historical data from the TrustZone environment, obtaining recorded matrix features and their corresponding optimal partitioning parameters. This data is then systematically organized, categorized according to matrix type (e.g., dense matrix, sparse matrix, structured matrix), application scenario (e.g., deep learning inference, scientific computing, image processing), and hardware configuration (e.g., different ARM processor models, core configurations), establishing a multi-dimensional index structure. For each combination of matrix features, the system records its optimal partitioning parameter set, including partitioning size for high-activity regions, partitioning size for low-activity regions, overlapping region processing strategies, core affinity configuration, and precision strategies. The system also records performance metrics for these parameters under different execution environments, such as execution time, energy consumption, cache utilization, and parameter sensitivity analysis results, indicating which parameter changes have a significant impact on performance. The system implements an efficient query mechanism for the knowledge base, supporting similarity retrieval based on matrix features, enabling the rapid finding of reference configurations for new matrix computation tasks. Furthermore, the system maintains a history of parameter evolution, tracking how optimization parameters for specific types of matrices change over time and with data accumulation. This helps in understanding long-term optimization trends and potential areas for improvement. Through this systematic recording and management of historical data, the system transforms scattered execution experience into structured knowledge, significantly improving the quality and efficiency of optimization decisions, enabling experience-driven continuous optimization, and providing robust support for handling various types of matrix computation tasks.

[0172] Example 5

[0173] like Figure 4 As shown, the detailed steps of heterogeneous core task weight prediction and scheduling in this invention include:

[0174] Step 501: Obtain block characteristic data, allocate blocks with computation density exceeding a fifth preset threshold to the first core for processing, allocate blocks with computation density below a sixth preset threshold to the second core for processing, and ensure that the number of the first core is higher than the number of the second core.

[0175] In step 501, the system analyzes the computational density ratio (CDR) of each block, assigning high-density blocks with a CDR > 10 to large cores (such as the Cortex-A7x series, i.e., the first core) for processing, and assigning low-density blocks with a CDR < 5 to small cores (such as the Cortex-A5x series, i.e., the second core) for processing. This allocation strategy fully utilizes the heterogeneous characteristics of the ARM big.LITTLE architecture.

[0176] In this step, the system first analyzes the computational characteristics of each block, focusing on evaluating the Computation Density Ratio (CDR), which is the ratio of computational operations to memory accesses for each block. For matrix multiplication blocks, the calculation formula is CDR = (2mn-1)k / (mk + kn + m*n), where m, n, and k are the block dimensions. The system sets a fifth preset threshold (usually 10) and a sixth preset threshold (usually 5) to classify blocks into computationally intensive, memory-intensive, and hybrid types. The system adopts a "computationally intensive priority allocation strategy," prioritizing high computational density blocks (CDR>10, typically small-sized, high-activity blocks) for processing by large cores (such as the Cortex-A7x series). These blocks typically have high instruction-level parallelism, fully utilizing the deep pipeline and complex execution units of large cores, and their datasets are usually perfectly suited for L1 cache. Conversely, the system allocates low computational density blocks (CDR<5, typically large-sized, low-activity blocks) to small cores (such as the Cortex-A5x series). These blocks experience frequent memory access, causing processor wait times and hindering the full utilization of the high computing power of large cores. They also exhibit high memory access randomness and low cache hit rates, making them more efficient to process on lower-power smaller cores. For blocks with mixed characteristics falling between these two extremes, the system dynamically allocates resources based on the current core load. The system also analyzes each block's memory access patterns (spatial locality, temporal locality, access regularity, and bandwidth pressure), parallelism characteristics (instruction-level parallelism, data-level parallelism, and task-level parallelism), and dependencies. These features provide a basis for subsequent fine-grained scheduling.

[0177] Step 502: Receive block priority data and set task execution order and preemption strategy.

[0178] In step 502, the system assigns execution priorities based on the position and criticality of the blocks in the dependency graph, determines which high-priority tasks can preempt low-priority tasks, and sets a maximum execution time to prevent a single task from occupying resources for a long time.

[0179] In this step, the system assigns execution priorities to each task block based on its position and criticality within the matrix computation dependency graph. The system first constructs a Dependency Graph (DAG) between blocks, analyzing critical paths and task dependency depths. Blocks located on critical paths with longer dependency chains are given higher execution priorities because their execution latency directly impacts the overall computation completion time. The system assigns priority levels to each task block, typically categorized as high, medium, and low, and configures corresponding scheduling strategies. For the highest-priority critical task, the system allows it to preempt lower-priority tasks, ensuring that critical computation paths are not blocked. The system also sets a maximum execution time threshold to prevent a single task from occupying processing resources for an extended period, leading to priority inversion. For groups of blocks with dependencies, the system calculates the overall priority to ensure that dependencies are handled correctly, avoiding deadlocks or resource starvation. The system also implements a dynamic priority adjustment mechanism, adjusting task priorities based on real-time execution data: when the execution time of certain tasks significantly exceeds expectations, the system increases the priority of their successors, accelerating the critical path; when the system load is light, it reduces the priority difference between tasks, improving resource utilization; when excessively high temperatures are detected, the priority strategy is adjusted to prevent persistent high loads in hotspot areas. This fine-grained priority management and preemption strategy ensures that computing resources are allocated rationally, critical tasks are processed promptly, and overall execution efficiency is significantly improved.

[0180] Step 503: Obtain the core characteristics of the ARM processor, configure core affinity, obtain the core affinity configuration, and specify the execution core for a specific type of task.

[0181] In step 503, the system configures core affinity, including hard affinity (tasks that must be executed on a specified core type) and soft affinity (tasks that preferentially execute on a specified core type but allow migration during load balancing). This configuration ensures that tasks are assigned to the most suitable processing core.

[0182] In this step, the system configures a precise core affinity strategy based on the detailed characteristics of the ARM processor and the computational requirements of the task chunks, ensuring that tasks are assigned to the most suitable processing cores. The system first obtains the core configuration information of the ARM processor, including detailed parameters such as the specific model, frequency range, pipeline depth, cache configuration, and instruction set extensions of the large cores (e.g., the Cortex-A7x series) and small cores (e.g., the Cortex-A5x series). The system implements two types of core affinity configurations: hard affinity and soft affinity. Hard affinity specifies tasks that must be executed on a specific core type, typically applied to critical chunks with stringent computational requirements, such as computationally intensive chunks heavily reliant on NEON instructions, which must be executed on large cores supporting advanced NEON extensions. Soft affinity specifies tasks that preferentially execute on a specific core type but allow migration during load balancing, providing greater scheduling flexibility. The system also evaluates task portability, i.e., the cost-benefit ratio of migrating tasks between different cores, which influences dynamic load balancing decisions. To address specific computational characteristics, the system implements a fine-grained affinity strategy: for example, for chunks relying on high-level vector instructions, it assigns cores from the latest ARM architecture; for memory-intensive chunks, it considers the memory controller topology and selects cores with lower memory access latency; for chunk groups with data dependencies, it allocates cores to shared caches to reduce synchronization overhead. The system also maintains a core capability database, recording the efficiency characteristics of different ARM cores for specific computational modes to guide affinity decisions. This fine-grained core affinity configuration fully leverages the characteristics of the ARM heterogeneous multi-core architecture, ensuring optimal matching between tasks and processing cores, significantly improving computational efficiency and energy utilization.

[0183] Step 504: Receive the dependencies of the tasks to be executed, and implement task group scheduling and synchronization checkpoint setting.

[0184] In step 504, the system combines dependent blocks into scheduling units, determines the ideal execution order of each task group, and sets necessary synchronization checkpoints to ensure that data dependencies are satisfied.

[0185] In this step, the system handles complex task dependencies and designs efficient task group scheduling strategies and synchronization mechanisms. The system first receives the task dependency graph (DAG) generated in step 502 and analyzes the dependency types between tasks: data dependency (the output of one task is the input of another), resource dependency (tasks compete for shared resources), and control dependency (task execution order constraints). The system adopts a batch processing scheduling strategy, combining closely dependent blocks into scheduling units to reduce scheduling overhead and task switching frequency. For typical matrix multiplication calculations, the system analyzes the multiplication path, identifies blocks that can be executed in parallel, and constructs balanced execution batches. The system sets key synchronization checkpoints to ensure the correct execution order of dependent tasks. These checkpoints are typically set between major computational stages, such as row block completion points or column block processing switching points in matrix multiplication. The system implements lightweight synchronization primitives, including barriers, semaphores, and condition variables, using atomic operation instructions of the ARM architecture for efficient implementation and minimizing synchronization overhead. For tasks on the critical path, the system employs an advance notification mechanism, triggering preparations for subsequent tasks in advance when a preceding task is nearing completion, reducing task switching latency. The system also implements adaptive batch size adjustment, dynamically adjusting batch size based on execution progress and resource availability: in the early stages of computation, when all tasks are available, larger batches are used to increase parallelism; in the later stages of computation, when the number of tasks decreases, batch sizes are reduced to improve flexibility. Furthermore, the system handles task cancellation and error recovery scenarios, ensuring safe rollback or continuation of remaining tasks when some tasks fail. This efficient task group scheduling and synchronization mechanism maximizes parallel execution opportunities while ensuring computational correctness, significantly improving overall execution efficiency.

[0186] Step 505: Obtain cache characteristic data, optimize shared cache and memory access strategies, and reduce inter-core data transfer. In this step, the system deeply optimizes cache usage and memory access patterns in a multi-core ARM processor environment, focusing on resolving inter-core data sharing and transfer issues. The system first obtains detailed information about the ARM processor's cache hierarchy, including the capacity, correlation, sharing relationships, and MESI (Modify, Exclusive, Shared, Invalidate) cache coherence protocol characteristics of each cache level. For the heterogeneous multi-core environment of the ARM big.LITTLE architecture, the system implements inter-core data sharing optimization: First, shared cache-aware scheduling prioritizes allocating data-dependent blocks to core groups with shared L2 / L3 caches to maximize cache sharing benefits; second, a data migration minimization strategy replaces data migration with task migration, prioritizing the migration of computational tasks to the core where the data resides, rather than moving the data to the execution core; third, NUMA-aware optimization (applicable to multi-chip ARM servers) considers the physical topology relationship between the memory controller and the processing cores to minimize memory access across NUMA nodes. The system also implements cache partitioning and partitioning techniques, allocating independent cache regions for different types of block tasks to reduce cache pollution and conflicts. For data that needs to be shared frequently, the system employs cache pinning to prevent critical data from being replaced from the cache. The system optimizes memory consistency management, precisely using memory barrier instructions (such as DMB and DSB) to insert barriers only at necessary synchronization points, reducing consistency maintenance overhead. For independent blocks that can be executed in parallel, the system implements a data replication strategy, allowing data to exist redundantly in multiple core caches, eliminating sharing conflicts at the cost of a slight increase in memory usage. The system also employs a prefetch shared data strategy, loading data to be shared into the consumer core's cache before the producer task completes, masking memory access latency. These caching and memory optimization strategies significantly reduce inter-core data transfer overhead, improving computational efficiency and scalability in multi-core environments.

[0187] Example 6

[0188] like Figure 5 As shown, the detailed steps of the NEON instruction set optimization execution of the present invention include:

[0189] Step 601: Obtain the block characteristic data and select the corresponding NEON instruction set optimized kernel for different types of blocks.

[0190] In step 601, the system selects the most suitable NEON instruction set optimized kernel based on the characteristics of the blocks. For small blocks with high activity, the system selects computationally intensive optimized instruction templates, such as VLDM (Vector Load Multiple Registers), VMLA (Vector Multiply-Accumulate), and VSTM (Vector Store Multiple Registers). For large blocks with low activity, the system selects memory-optimized instruction templates, focusing on optimizing cache utilization and memory access patterns.

[0191] In this step, based on the block characteristic data obtained in step 501, the system selects and configures the most suitable NEON instruction set optimized kernel for each type of block. The system first performs a fine-grained classification of blocks, considering not only computational density but also data type (e.g., FP32, FP16, INT8), matrix structure characteristics (e.g., dense, sparse, structured), and computation mode (e.g., general matrix multiplication, matrix transpose, element-level operations). For small blocks with high activity, the system selects instruction templates optimized for intensive computation. These templates fully utilize NEON's SIMD parallel capabilities, processing multiple data elements simultaneously through vectorized operations. Typical instruction sequences include VLDM (vector loading multiple registers), VMLA (vector multiply-accumulate), and VSTM (vector storing multiple registers). The system meticulously adjusts loop parameters according to the block dimension to achieve optimal loop unrolling and register allocation. For example, for FP32 matrix multiplication in a 4×4 block, 16 scalar multiplications are completed using 4 VMLA.F32 instructions, achieving a 4x speedup. The system automatically adjusts the inner loop boundary to a multiple of 4 for the 128-bit NEON register (which can hold four 32-bit floating-point numbers) to ensure full utilization of vector instructions. For large blocks with low activity, the system selects memory-optimized instruction templates, focusing on optimizing cache utilization and memory access patterns, using PLD (preload) instructions to preload data into the cache and reduce memory access latency. For blocks with significant sparsity, the system selects conditional execution instructions, such as VCVT (conditional transition) combined with masking operations, to skip calculations for zero or minimum values. For boundary regions or irregularly shaped blocks, the system selects a dedicated boundary handling template, including boundary condition checking logic, to achieve branchless computation through ARM's conditional execution features. The system also considers the microarchitecture characteristics of ARM processors; for processors supporting FMA (fused multiply-accumulate) instructions (such as Cortex-A73 and newer architectures), VFMA instructions are preferentially used instead of VMLA to improve accuracy and performance. This method of precisely matching block characteristics with NEON instruction templates significantly improves the instruction-level parallelism and vectorization efficiency of matrix computation.

[0192] Step 602: Obtain the block activity characteristics and configure the mixed precision calculation matrix parameters.

[0193] In step 602, the system configures mixed-precision computation parameters based on the block activity characteristics. For high-activity regions, the system configures FP32 (32-bit single-precision floating-point) computation; for medium-activity regions, the system configures FP16 (16-bit half-precision floating-point) computation; and for low-activity regions, the system can be configured with INT8 (8-bit integer) or even lower precision representation. This mixed-precision strategy significantly improves processing efficiency and reduces energy consumption while maintaining critical computational accuracy.

[0194] In this step, the system implements a hybrid precision computation strategy that balances accuracy and performance based on the activity characteristics of each block. The system first evaluates the precision sensitivity of each block, primarily considering factors such as numerical activity, computational stability, and result impact. For high-activity regions (corresponding to "hot spots" in the matrix), where the absolute values ​​of elements are large and contribute significantly to the final result, the system configures FP32 (32-bit single-precision floating-point) computation to ensure numerical accuracy. This high-precision configuration is particularly suitable for high-information-density regions near the matrix diagonal or corresponding to eigenvectors, ensuring that critical calculations are not affected by insufficient precision, thus maintaining result quality. For medium-activity regions, the system configures FP16 (16-bit half-precision floating-point) computation. FP16 offers significant advantages on ARM processors: halved memory usage, improved cache efficiency; NEON instructions can process twice the number of elements simultaneously, increasing computational throughput; and significantly reduced power consumption, making it particularly suitable for mobile devices. In ARMv8.2 and later versions, the system uses dedicated half-precision instructions (such as VCVT.F16.F32) for precision conversion and uses instructions like VFMUL.F16 to perform half-precision computation. For low-activity regions (the long tail), the system employs a more aggressive precision degradation strategy, potentially using INT8 (8-bit integer) or even lower precision representation. The system maps floating-point values ​​to the integer range using quantization techniques, maintaining relative precision using scaling factors and offsets. ARM NEON provides a rich set of integer vector instructions (such as VMULL.S8), allowing each 128-bit register to process 16 INT8 elements simultaneously, achieving higher parallelism. The system pays special attention to precision conversion boundaries, inserting necessary type conversion instructions at the intersection of different precision regions to ensure data type compatibility. To reduce the overhead of frequent conversions, the system implements a precision conversion buffer to batch type conversion operations. The system also tracks accumulated errors and dynamically improves the computational precision on the critical path when potential precision issues are detected (such as numerical overflow risks). This intelligent hybrid precision strategy significantly improves processing efficiency while maintaining computational accuracy, making it particularly suitable for resource-constrained ARM devices.

[0195] Step 603: Obtain the memory access mode, configure the ARM cache prefetch instruction, and optimize the memory access order.

[0196] In step 603, the system configures the ARM cache prefetch instruction (PLD - Preload Data) to preload the data to be used into the cache. The system selects an appropriate prefetch target level based on data reuse characteristics and dynamically adjusts the prefetch distance, typically 16-64 cache lines (approximately 1-4KB of data).

[0197] In this step, the system configures optimized cache prefetching strategies and memory access patterns for each block's memory access characteristics. The system first analyzes the memory access patterns of the blocks, including spatial locality (proportion of contiguous memory accesses), temporal locality (data reuse frequency), access regularity (predictability of access patterns), and bandwidth pressure (memory access volume per unit time). For highly regular access patterns (such as row and column scans in matrix multiplication), the system configures hardware prefetching instructions (PLD - Preload Data) to preload the data to be used into the cache. The ARM architecture supports different prefetching strategies, and the system selects the appropriate prefetching target level based on data reuse characteristics: highly reused data is prefetched into the L1 cache; moderately reused data is prefetched into the L2 cache; and streaming data accessed only once is hinted to be retained in the L1 cache using the PLDL1KEEP instruction. The prefetch distance (the time before computation) is a key parameter, dynamically adjusted by the system based on processor characteristics and memory latency, typically 16-64 cache lines (approximately 1-4KB of data). The system also avoids over-prefetching to prevent useful cached content from being replaced by unnecessary prefetched data. For large blocks, the system implements a segmented prefetching strategy, prefetching only the parts to be processed, reducing the risk of cache pollution. The system also optimizes memory access order, rearranging the computation order to maximize the continuity of memory access. For small blocks with intensive computation, the system optimizes data alignment and padding to ensure that memory accesses are aligned to cache line boundaries (typically 64 bytes); for operations with unfriendly access patterns, such as matrix transpose, the system implements matrix rearrangement and buffering techniques to convert column access into more efficient row access; for large blocks with sparse computation, the system applies compressed storage format optimization, selecting an appropriate storage format based on the characteristics of the sparse pattern, such as row compression (CSR), column compression (CSC), or coordinate format (COO). The system specifically optimizes the use of the ARM architecture's TLB (Translation Lookaside Buffer), prioritizing the use of large page mappings (typically 2MB instead of 4KB) to reduce TLB miss rate. These cache prefetching and memory optimization strategies directly improve data access efficiency and significantly reduce the impact of memory latency on computational performance.

[0198] Step 604: Based on the core affinity configuration, perform each block calculation in parallel to obtain the calculation results of each block.

[0199] In step 604, the system executes each block of computation in parallel on heterogeneous multi-core processors according to the task scheduling scheme. The system adopts a dynamic scheduling model, allocating computationally intensive blocks to large cores and memory-intensive tasks to small cores. The system implements a job-stealing mechanism, allowing idle cores to acquire tasks from other queues, thereby improving resource utilization.

[0200] In this step, the system coordinates the execution of each computational block on the ARM heterogeneous multi-core architecture based on the core affinity configured in step 503 and the task scheduling strategy generated in step 504. The system first initializes the parallel execution environment, establishing a thread pool and task queues, creating independent task queues for big cores and small cores respectively. For a typical ARM big.LITTLE architecture, the system identifies the processor core type (e.g., Cortex-A7x for big cores, Cortex-A5x for small cores) and configures corresponding execution parameters according to their characteristics. The system uses lightweight synchronization primitives (such as spinlocks and atomic operations) to implement inter-thread communication, minimizing synchronization overhead. The system applies the optimization parameters configured in steps 601 to 603 to each block, including the NEON instruction sequence, precision configuration, and memory access strategy. The parallel execution phase employs a dynamic scheduling model to implement the core strategy of "allocating computationally intensive blocks to big cores and memory-intensive tasks to small cores." When a core completes its current task, it retrieves a new task from the corresponding queue. If the queue is empty, the system initiates a work-stealing mechanism, allowing idle cores to acquire tasks from other queues, improving resource utilization. The system implements fine-grained load monitoring and dynamic balancing, detecting load imbalances by tracking the task completion rate and queue length of each core in real time. When an imbalance is detected (e.g., large cores are backlogged while small cores are idle), the system triggers task reallocation, migrating some tasks from busy queues to idle queues. Migration decisions consider task characteristics and migration costs, prioritizing "floating" tasks with moderate computational characteristics. The system also integrates frequency-aware scheduling and thermal management, monitoring the operating frequency of each core (which may dynamically change due to temperature and power consumption limitations), allocating high-intensity computations to cores with higher current frequencies. Simultaneously, the system implements a temperature balancing strategy to prevent some cores from experiencing continuous high loads, leading to localized overheating and frequency drops. For data-dependent blocks, the system implements precise dependency tracking and synchronization mechanisms, ensuring that the current block is only scheduled for execution after all prerequisites are completed. This efficient parallel execution strategy fully leverages the advantages of the ARM heterogeneous multi-core architecture, achieving optimal allocation of computational load.

[0201] Step 605: Obtain the calculation results of each block, and perform result merging and correctness verification.

[0202] In step 605, the system collects all block calculation results and reassembles them into a complete matrix according to the mapping relationship of the original block scheme. For overlapping regions, the system applies a merging strategy to ensure result consistency. The system performs multi-level verification checks, including numerical stability checks, accuracy verification, and characteristic verification, to ensure the correctness and reliability of the calculation results.

[0203] In this step, the system collects and integrates the calculation results of all blocks, performs result merging and comprehensive correctness verification. The system first collects the calculation results of each block completed in parallel execution in step 604, and reassembles them into a complete matrix according to the mapping relationship of the original block scheme. For overlapping regions, the system applies a merging strategy: for addition operations, any copy can be directly taken; for accumulation operations (such as matrix multiplication), the impact of duplicate calculations needs to be eliminated, usually achieved through weight allocation of overlapping regions. The system uses atomic operations to ensure data consistency during concurrent writes, avoiding race conditions caused by multiple threads updating the same memory location simultaneously. After merging the results, the system performs multi-level verification checks: first, numerical stability checks, calculating key statistical indicators such as maximum, minimum, average, and standard deviation to ensure the results are within a reasonable range; second, accuracy verification, sampling and comparing the differences between mixed-precision calculation results and standard-precision (usually FP64) calculation results to ensure accuracy loss is within an acceptable range; and third, characteristic verification, for matrix operations with theoretically known characteristics (such as the unit property of orthogonal matrix multiplication), checking whether the results meet mathematical expectations. The system pays special attention to potential numerical problems, such as underflow (values ​​that are too small are rounded to zero), overflow (values ​​that exceed the representation range), and outliers (NaN or infinity), and implements an automatic detection and reporting mechanism. For iterative algorithms (such as matrix inversion and eigenvalue calculation), the system verifies convergence conditions to ensure that the results meet predetermined error thresholds. As a quality assurance measure, the system also performs self-consistency checks, recalculating some calculation results using different algorithm paths and comparing the consistency of multiple results. For detected problems, the system implements a tiered response strategy: minor precision problems generate warnings but do not affect the output; medium problems trigger automatic correction processes, such as recalculating the problem region; serious problems (such as numerical instability) trigger error handling, which may revert to a conservative algorithm or report the error status to the application. After verification, the system performs final data post-processing, including format conversion, memory rearrangement, and result optimization, outputting the final calculation results that meet the application requirements. This rigorous result merging and verification mechanism ensures the correctness and reliability of block parallel computing, providing quality assurance for optimized computation.

[0204] Example 7

[0205] like Figure 6 As shown, the present invention also provides a matrix computation adaptive optimization system based on ARM architecture, comprising:

[0206] The acquisition module 701 is used to acquire the matrix data to be processed and ARM processor information, and to preprocess the matrix data to be processed to obtain the preprocessed matrix data.

[0207] The identification module 702 is used to calculate the local activity and identify hotspot regions on the preprocessed matrix data to determine the long-tail distribution characteristics of the matrix.

[0208] The calculation module 703 is used to receive the long-tail distribution characteristics of the matrix and the multi-level cache capacity parameters of the ARM processor, calculate the optimal block size range, and generate an asymmetric block scheme.

[0209] Module 704 is established to obtain the asymmetric partitioning scheme, collect the execution time and cache hit rate of each partition, and establish a mapping relationship between matrix features and optimal partitioning parameters.

[0210] The generation module 705 is used to obtain the asymmetric partitioning scheme and mapping relationship, calculate the computational density and memory access mode of each partition, and generate a task scheduling scheme.

[0211] Output module 706 is used to obtain the task scheduling scheme, perform matrix calculations on a processor with ARM big.LITTLE architecture, and output the final calculation results.

[0212] Example 8

[0213] The method of this invention also includes optimization and verification of ARM matrix calculation based on formal specifications, specifically including the following steps:

[0214] The system acquires the matrix operation flow and the characteristics of the ARM processor, and defines an axiomatic system of operations using a formal language to obtain a formal specification. In this step, the system first establishes a rigorous formal specification to precisely describe the mathematical characteristics and expected behavior of matrix operations. The system uses a formal language (such as Z-notation, TLA+, or Coq) to define the axiomatic system of matrix operations, including the mathematical properties of basic operations such as addition, multiplication, and transpose, such as associative and distributive laws and various boundary conditions. For long-tailed matrices, the system specifically defines their activity characteristics, formally describing the characteristics and processing requirements of hot and inactive regions. The formal specification also includes numerical precision requirements, explicitly defining acceptable error ranges and rounding behavior. For ARM architecture characteristics, the system also incorporates hardware characteristics (such as NEON instruction semantics, cache coherence model, and heterogeneous core characteristics) into the formal specification, constructing a hardware-software collaborative formal framework. The system also defines the composability properties of operations to ensure that complex matrix operations can be implemented through the correct combination of basic operations. This precise formal definition ensures that subsequent optimization processes have clear correctness standards, avoiding the introduction of unexpected behavior during optimization. In this way, the system establishes a "golden reference model" for matrix computation, serving as a benchmark for subsequent verification. This formal approach is particularly suitable for scenarios with high reliability requirements, such as scientific computing, financial analysis, or safety-critical systems.

[0215] The formal specification is analyzed and processed to generate system verification assertions (SVAs), outputting executable verification rules. In this step, the system automatically generates SVAs based on the formal specification to verify the correctness of the optimization implementation. The system first converts the formal specification into two types of assertions: static assertions and dynamic assertions. Static assertions are derived directly from the specification using formal methods to verify the structural properties of the optimization algorithm, such as no deadlock, correct resource release, and boundary condition handling. These assertions can be verified at compile time using static analysis tools. Dynamic assertions, on the other hand, target runtime behavior, verifying whether the computation results satisfy mathematical properties, such as the associative and distributive laws of matrix multiplication, or the inherent properties of special matrices (such as orthogonal matrices). To improve the coverage and accuracy of SVAs, the system introduces Large Language Model (LLM) technology to convert the optimization intent and potential edge cases described in natural language into formal assertions. LLM analyzes existing code and specifications, automatically generating test scenarios and assertion expressions, paying particular attention to corner cases that are difficult to identify manually, such as matrices with special shapes and extreme numerical distributions. The system also generates verification rules specific to ARM characteristics, such as the correct use of NEON instructions, memory alignment requirements, and cache coherence maintenance. The generated assertions are converted into executable verification rules, including preconditions, postconditions, and invariants. These rules are represented as input formats for assertion macros, runtime checking functions, or formal verification tools, and can be embedded into actual code or used as input for external verification tools. The system optimizes the verification rules, removing redundant checks, merging related assertions, and categorizing them according to execution cost to ensure that the verification process itself does not become a performance bottleneck.

[0216] According to the executable verification rules, the asymmetric partitioning scheme is verified for correctness using theorem proving tools, and a verification report is generated. In this step, the system performs a rigorous formal correctness proof of the asymmetric partitioning strategy in step 2 to ensure its mathematical equivalence. The system uses theorem proving tools (such as Coq, Isabelle / HOL, or Lean) to construct a proof model for matrix partitioning computation, proving the consistency of computation results under different partitioning strategies. The proof process first formally defines the semantics of standard matrix operations (as a reference implementation), then defines the operational semantics of the asymmetric partitioning version, and subsequently proves, through mathematical induction or other proof techniques, that the two implementations produce equivalent results under all possible input conditions. The system pays special attention to the merging logic of overlapping partitioned regions, and proves, through formal methods, that the final result satisfies mathematical equivalence regardless of the merging strategy used (such as weighted average, preferred selection, or rule-specific merging). For precision-sensitive operations, the system establishes an accurate error bound model, proving that, under a given precision configuration, the cumulative error does not exceed a preset threshold. The system also verifies the correctness of boundary condition handling, such as cases where the matrix dimension is not an integer multiple of the block size, or special cases where hotspot regions cross block boundaries. For performance-critical paths, the system verifies the safety of parallel execution through model checks, proving that there is no risk of data races or deadlocks. The verification process generates a detailed proof tree and intermediate steps, ultimately outputting a formal verification report containing all verification results. This report details the scope, methods, results, and possible boundary conditions of the verification, providing a solid theoretical guarantee for optimization decisions and ensuring computational correctness even under extreme conditions.

[0217] Based on the verification report and mixed-precision calculation data, error propagation analysis is performed to establish a precision error model. In this step, the system deeply analyzes the errors introduced by mixed-precision calculations and their propagation characteristics, constructing an accurate error model. First, based on the formal definitions in the verification report, the system determines the error limits and behavioral characteristics of each precision representation (e.g., FP32, FP16, INT8). Then, the system analyzes the error propagation path in matrix calculations, paying particular attention to the error amplification effect in cumulative operations (e.g., dot product calculation). The system establishes a hierarchical error model: an element-level error model captures the rounding error of individual operations; a block-level error model analyzes the error accumulation within blocks; and a global error model evaluates the error propagation of the overall calculation. For mixed-precision calculations, the system specifically analyzes the error introduction at precision conversion points (e.g., from FP32 to FP16 or from FP16 to FP32), as well as the impact of boundary processing between different precision regions. The system uses techniques such as interval arithmetic, error polynomials, or probabilistic error models to quantify the error characteristics of different matrix regions and operation types. For iterative algorithms (e.g., matrix inversion or eigenvalue calculation), the system establishes an error accumulation model to predict the error growth after multiple iterations. The system also considers ARM processor-specific error sources, such as the precision characteristics of NEON instructions and the rounding behavior of fused multiply-accumulate operations. Based on these analyses, the system constructs a complete precision error model that can predict the error distribution and limits under a given computation graph and precision configuration. This model supports an adaptive precision strategy: maintaining high precision in error-sensitive hotspot regions while safely reducing precision in error-insensitive regions. The system parameterizes the model, supporting dynamic adjustment of the precision configuration under different matrix characteristics and computational requirements to achieve an optimal balance between precision and performance. This precise error modeling significantly improves the reliability of mixed-precision computation, ensuring that optimization does not sacrifice necessary computational precision.

[0218] Based on the aforementioned accuracy error model and actual execution data, formal verification is performed, and formal proof results are output. In this step, the system combines the theoretical error model with actual execution data for final formal verification, ensuring the correctness and stability of the entire optimization system. The system first collects key data points during the actual execution process, including intermediate results, error samples, and boundary condition behavior. Then, the system compares these data with the predictions of the accuracy error model to verify the model's accuracy and completeness. If significant deviations are found, the system refines the error model parameters to improve its prediction accuracy. After model verification, the system uses formal verification tools for comprehensive correctness proof. This process includes several key aspects: first, functional correctness verification, proving the consistency between the optimization implementation and mathematical specifications; second, numerical stability verification, proving that the algorithm does not produce numerical overflow, underflow, or unstable behavior across all possible input ranges; and third, resource safety verification, proving that the implementation correctly manages memory, cache, and parallel resources without leakage or race conditions. The system uses a hybrid verification method, combining static formal proof and dynamic symbolic execution to comprehensively cover all possible execution paths. For key optimization techniques, such as asymmetric partitioning, mixed-precision computation, and heterogeneous kernel scheduling, the system specifically constructs formal models to prove their correct behavior under various conditions. The verification process pays particular attention to edge cases of long-tailed distribution matrices, such as highly unbalanced activity distributions, extremely sparse patterns, or special numerical distributions. The system ultimately outputs detailed formal proof results, including proof coverage, verification status of key properties, boundary condition handling, and verified performance guarantees. This rigorous formal verification provides the highest level of quality assurance for the optimization implementation, making it particularly suitable for critical application areas such as scientific computing, financial analysis, or safety-critical systems. Through the combination of theoretical proof and practical verification, the system ensures the reliability and correctness of the optimization while maintaining high performance.

[0219] The system acquires matrix computation execution status information, performs verification checks, and generates verification results. In this step, the system implements a real-time verification mechanism during matrix computation execution, monitoring the computation status and promptly identifying potential problems. The system first defines key execution status information collection points, including computation stage boundaries, important intermediate results, resource usage, and system environment parameters. At these collection points, the system collects multiple types of status information: numerical status (such as the range, distribution characteristics, and outliers of intermediate results), computation status (such as progress, number of completed blocks, and pending tasks), resource status (such as memory usage, cache hit rate, and core utilization), and system status (such as processor temperature, frequency, and power consumption). The system uses lightweight monitoring mechanisms for data acquisition to ensure that monitoring itself does not significantly impact computational performance, such as using sampling techniques instead of full monitoring, or directly obtaining key indicators using ARM's hardware performance counters. Based on the collected status information, the system performs multi-level verification checks: numerical correctness checks verify whether intermediate results meet theoretical expectations and promptly identify numerical instability or accuracy issues; resource integrity checks ensure that memory allocation, cache usage, and core scheduling conform to design specifications; progress consistency checks monitor the execution progress of different blocks and identify potential load imbalances or scheduling anomalies; boundary condition checks pay special attention to system behavior under extreme conditions, such as performance degradation when near full load. The system uses the verification rules generated in step 2 to perform these checks and records the results and relevant context of each check. For any anomalies found, the system records detailed information, including the anomaly type, severity, location, and related status data. The system ultimately generates structured verification results, including the status of all checkpoints, the problems found and their detailed information, resource usage statistics, and performance metrics. These verification results provide crucial evidence for subsequent error handling and recovery, achieving real-time quality control of the computation process.

[0220] Based on the verification results and preset error level standards, a hierarchical error classification is performed to determine the error handling strategy. In this step, the system systematically classifies the problems found during the verification process and determines appropriate handling strategies according to their severity. The system first loads the preset error level standards, which categorize possible anomalies into multiple levels, such as: critical level (serious problems that lead to completely incorrect calculation results or system instability), severe level (important problems that significantly affect calculation accuracy or performance), warning level (minor problems that may affect result quality but are not fatal), and information level (anomalies that do not affect the results but are noteworthy). The system analyzes various anomalies in the verification results and classifies them according to multi-dimensional standards: error type (such as numerical anomalies, resource problems, scheduling conflicts), scope of impact (local blocks, specific regions, or global calculations), potential consequences (data corruption, performance degradation, or reduced accuracy), and difficulty of repair (immediate correction, parameter adjustment, or recalculation required). The system combines the characteristics of the problem with the current execution context to determine the final severity level of each problem. Based on this classification, the system formulates corresponding handling strategies for each type of problem: For critical problems, it may be necessary to suspend the current computation, roll back to a safe state, and restart with an alternative algorithm; for severe problems, the system may recalculate the problem region without interrupting the overall computation, or adjust key parameters and continue; for warning problems, the system records problem details, may adjust relevant parameters, but continues executing the current computation path; for informational problems, the system only records information for subsequent optimization reference and does not interfere with the current execution. The system also considers the combined effect of problems; when multiple lower-level problems occur simultaneously and may affect each other, their overall severity may increase. The handling strategies also include execution timing (immediate processing or delaying to a specific checkpoint) and resource allocation decisions (such as allocating additional resources to fix the problem). The system outputs the final error classification and handling strategies in a structured format to guide the subsequent recovery and adjustment process. This sophisticated error classification and handling mechanism ensures that the system can gracefully handle various abnormal situations, maximizing the correctness of the computation results and the stability of the system.

[0221] Based on the error handling strategy and accuracy issue data, the system performs accuracy path adjustment and outputs the corrected computation path. In this step, the system implements precise computation path adjustments for detected accuracy-related issues to ensure that the calculation results meet accuracy requirements. The system first analyzes accuracy issues in the error handling strategy, including numerical instability (such as asymptotic divergence, oscillation, or outliers), insufficient accuracy (such as loss of significant digits or excessive relative error), and inconsistency in accuracy (such as error accumulation at mixed precision boundaries). The system also collects detailed context of the accuracy issues, including the matrix characteristics of the problem region, the currently used precision configuration, and computation path information. Based on this data, the system implements a multi-level precision path adjustment strategy: First, precision upgrade adjustment: for matrix regions detected as having insufficient precision (usually hotspots or important computational paths), the system increases their computational precision, such as from FP16 to FP32, or from INT8 to FP16, ensuring that critical computations have sufficient numerical precision. Second, algorithm path switching: for numerically unstable operations (such as the computation of ill-conditioned matrices), the system switches to more stable algorithm implementations, such as switching from a fast but potentially unstable algorithm to a more conservative but stable one, such as switching matrix inversion from a direct method to an iterative method. Third, precision hybrid optimization: the system re-evaluates the overall precision allocation scheme, possibly adjusting the precision boundaries of different regions, or inserting precision enhancement points on critical paths to balance precision and performance. For precision-sensitive computations (such as scientific computing or financial analysis), the system may implement strict precision protection measures, such as using the Kahan summation algorithm to reduce rounding errors, or using interval arithmetic to track error limits. The system also optimizes precision conversion operations, minimizing frequent precision conversions, merging adjacent operations of the same precision, and reducing conversion overhead. After adjustment, the system re-verifies the expected precision of the corrected path to ensure it meets application requirements. The system outputs a complete corrected computation path, including precision configuration, algorithm selection, and key checkpoints, providing clear guidance for subsequent execution. This precise precision path adjustment maximizes performance while ensuring computational quality, and is a key guarantee for high-quality matrix computation.

[0222] Based on the corrected computation path and the numerical distribution characteristics of the matrix, numerical stability adjustment is performed to obtain optimized computational parameters. In this step, the system further optimizes the numerical stability-related computational parameters for the corrected computation path, ensuring reliable numerical behavior while improving performance. The system first analyzes the numerical distribution characteristics of the matrix, focusing on factors that may affect stability, such as the numerical range (the ratio of the maximum to the minimum value), the condition number (representing the matrix's sensitivity to input perturbations), and special structures (such as diagonal dominance or sparse patterns). The system also identifies key numerically sensitive points in the computation, such as division operations, square root calculations, or iterative convergence judgments. Based on these characteristics, the system implements several numerical stability adjustment techniques: First, scaling transformation: for matrices with excessively large numerical ranges, the system applies row / column scaling or global scaling transformations to compress the values ​​to a suitable range, reducing accuracy issues caused by dynamic range. Second, condition improvement: for matrices approaching singularity or ill-conditioned conditions, the system adds regularization terms or preprocessing steps to improve the matrix's condition number and numerical stability. Third, alternative formula selection: the system may replace the original formula with a numerically stable equivalent form, such as using the logarithm of the sum of squares instead of direct sum of squares calculation, avoiding overflow or accuracy loss. For iterative calculations, the system optimizes convergence conditions and step size parameters to balance convergence speed and stability. The system configures safety thresholds for critical calculations, such as minimum division values, rounding thresholds, and outlier judgment criteria, to prevent calculation errors caused by extreme values. For identified stability risk points, the system may also insert runtime check code to monitor critical values ​​and adjust parameters or paths promptly when potential problems are detected. The system pays special attention to stability issues in mixed-precision environments and may perform accuracy enhancement or use compensation techniques (such as double compensation algorithms) at critical points to maintain accuracy. Through these techniques, the system comprehensively optimizes computational parameters, improving numerical stability while maintaining high performance. Ultimately, the system outputs a complete set of optimized parameters, including scaling factors, regularization parameters, algorithm control parameters, and safety thresholds. These parameters are directly applied to the actual execution process, ensuring the stability and reliability of matrix computations.

[0223] Based on the optimized computational parameters and the current ARM processor state, task scheduling is reorganized to output a new execution plan. In this step, the system reorganizes task allocation and execution order based on the optimized computational parameters and the current ARM processor state to generate an optimized execution plan. The system first obtains the latest processor state information, including the load level, operating frequency, temperature status, and available resources of each core. The system also considers the overall system state, such as memory pressure, I / O wait status, and resources occupied by other applications. Based on these real-time states and optimized computational parameters, the system performs multi-level scheduling reorganization: First, task repartitioning: the system re-evaluates the computational complexity and resource requirements of each block based on the corrected precision path and numerical stability parameters, possibly adjusting block boundaries or merging / splitting specific blocks to make the task granularity more suitable for the current processor state; second, priority reassignment: the system adjusts task execution priorities based on numerical dependencies and stability considerations to ensure that stability-sensitive computations on the critical path are processed first; third, resource allocation optimization: the system allocates the most suitable processing resources to tasks with different characteristics, such as allocating cores with advanced NEON functions to precision-sensitive tasks and cores with large cache capacity to memory-intensive tasks. The system also optimizes core affinity strategies, adjusting the mapping between tasks and cores based on current temperature distribution to prevent hot cores from continuing to run under high load. For detected performance bottlenecks, the system implements targeted optimizations: for example, for memory bottlenecks, the system reorganizes task execution order to maximize data locality and cache utilization; for uneven core load, the system adjusts job stealing parameters and task migration thresholds to improve load balancing. The system also considers energy efficiency targets, potentially reducing the execution frequency of some non-critical paths or allocating floating tasks to the cores with the highest current energy efficiency, while meeting performance requirements. The system ultimately generates a complete execution plan, including detailed task allocation tables, execution order, core affinity settings, synchronization point configurations, resource allocation guidelines, and performance monitoring points. This dynamic, environmentally adaptive scheduling and reorganization capability enables the system to maintain optimal performance under various execution conditions, while ensuring computational correctness and stability, achieving true adaptive optimization.

[0224] Example 9

[0225] The method of this invention also includes fine-grained fusion ARM matrix calculation optimization, specifically including the following steps:

[0226] The system acquires the preprocessed matrix data and state-space model parameters, performs dynamic characteristic analysis, and obtains a feature sequence. In this step, the system first establishes a dynamic characteristic analysis framework for matrix computation, deeply exploring the changing characteristics of the matrix data during execution. The system acquires the preprocessed matrix data, including basic features (dimension, sparsity, numerical distribution) and long-tail distribution features (hotspot location, activity distribution). Simultaneously, the system loads state-space model parameters, including the state transition matrix, observation matrix, and noise covariance matrix. These parameters describe the mathematical model of the system's dynamic behavior and observation process. Based on these inputs, the system performs multi-dimensional dynamic characteristic analysis: time-dimensional analysis tracks changes in matrix characteristics with execution stages, such as the evolution of sparsity patterns in iterative algorithms; spatial-dimensional analysis studies the differences in computational characteristics across different matrix regions, such as the migration patterns of hotspot regions; and computational-dimensional analysis evaluates changes in computational intensity and memory access patterns. The system uses state-space models (such as Kalman filters or particle filters) to predict the dynamic changes of these characteristics, achieving forward-looking optimization. The analysis process employs an adaptive sampling strategy, increasing the sampling frequency for key regions or stages to reduce system overhead. The system also performs feature extraction and dimensionality reduction, employing techniques such as Principal Component Analysis (PCA) or autoencoders to compress the raw observation data and extract key features. Ultimately, the system generates structured feature sequences containing temporal patterns, spatial distribution characteristics, and computational load properties. These feature sequences are represented in a compact manner, such as feature vector sequences or state transition diagrams, providing a data foundation for subsequent fusion optimization. This dynamic characteristic analysis overcomes the limitations of traditional static optimization, capturing complex dynamic behaviors in matrix computation and providing accurate feature descriptions for fine-grained fusion operations.

[0227] A complete computational operation graph is constructed, and based on the aforementioned feature sequence, fusionable operation combinations are identified, outputting a fusion scheme. In this step, the system deeply analyzes the operational dependencies of matrix computations and identifies operation combinations that can be optimized for fusion. The system first constructs a complete computational operation graph, representing matrix computations as a directed graph structure of operation nodes and data flow edges. This graph includes not only major operations (such as matrix multiplication, addition, and transpose) but also auxiliary operations (such as data movement, format conversion, and synchronization points). Based on the feature sequence obtained in step 1, the system identifies multiple fusionable patterns: temporal fusion merges operations that are temporally adjacent and have close data dependencies, reducing intermediate result storage and loading; spatial fusion merges operations that are computed in the same matrix region, improving data locality; and algorithmic fusion reorganizes multiple independent operations into equivalent composite operations, such as fusion of matrix multiplication and addition into a GEMM operation. The system employs a multi-stage identification strategy: first, pattern matching is used to identify common fusion patterns, such as matrix multiplication chains, transpose-multiplication combinations, or scaling-addition sequences; then, data flow analysis is used to identify data reuse opportunities and optimize memory access patterns; finally, algebraic optimization techniques are used, applying mathematical equivalence transformations of matrix operations, such as associative and distributive laws, to discover implicit fusion opportunities. The system evaluates the benefits of each fusion candidate, constructs a performance model to predict execution efficiency before and after fusion, considering changes in computational intensity, improvements in memory access patterns, and the impact of parallelism. The system also assesses the feasibility of fusion, considering ARM architecture constraints (such as the number of registers and cache hierarchy) and accuracy requirements. For conflicting fusion options, the system applies priority rules or global optimization algorithms to find the optimal fusion combination. Finally, the system outputs a structured fusion scheme, including the type, boundaries, execution order, and data dependencies of the fusion operations, as well as an analysis of expected performance benefits. This fine-grained operation fusion strategy significantly reduces memory access and control overhead, improves computational density and hardware utilization, and is a key technology for optimizing matrix computation performance.

[0228] Based on the fusion scheme and the characteristics of the ARM processor, optimized execution code is obtained. In this step, the system converts the high-level fusion scheme into execution code highly optimized for the ARM architecture. The system first loads detailed ARM processor characteristic information, including instruction set architecture version (e.g., ARMv7, ARMv8), microarchitectural characteristics (e.g., pipeline depth, instruction issue width, out-of-order execution capability), NEON vector unit specifications, and cache parameters. For each fusion operation group, the system implements multi-level code generation and optimization: First, operation conversion maps the fusion operations to instruction modes supported by ARM, such as mapping matrix multiplication-addition fusion operations to NEON's VMLA or VFMA instructions; second, memory access optimization generates efficient data load / store sequences, utilizing ARM's multi-register load / store instructions (e.g., VLDM / VSTM) and alignment hints to maximize memory bandwidth utilization; third, instruction scheduling optimization rearranges instruction order, reducing pipeline stalls caused by data dependencies and increasing instruction-level parallelism. The system implements ARM-specific loop optimization techniques, including loop unrolling (automatically determining the unrolling factor based on the number of registers), loop blocking (adjusting the block size according to the cache hierarchy), and loop vectorization (converting scalar operations into NEON vector operations). For complex fusion operations, the system employs the following strategies: automatically generating specialized kernels for the fusion mode, such as a matrix multiply-accumulate kernel (C=A×B+C) or a scaled multiply-accumulate kernel (C=αA×B+βC); applying register reuse strategies to reduce register overflow and loading redundancy; inserting prefetch instructions (such as PLDs) to optimize memory access; and generating code variants with optimized big and little cores for the ARM big.LITTLE architecture. The system also implements advanced optimization techniques, such as software pipelining, SIMD instruction refactoring, and branch prediction optimization. The final generated code is implemented using inline assembly or highly optimized C / C++ to ensure the compiler generates the most efficient machine code. The system also generates necessary performance comments and memory alignment constraints to guide the runtime system in optimal scheduling. This fine-grained code optimization tailored to the characteristics of the ARM architecture significantly improves the execution efficiency of fusion operations, achieving maximum matching between theoretical and practical performance.

[0229] The system collects multi-source runtime information and uses the optimized execution code to output a dynamic switching strategy. In this step, the system constructs an intelligent runtime control mechanism to achieve dynamic adaptation and switching of fused operations. The system first designs a controller architecture, including decision logic, status monitoring, and an execution engine. Based on feedback control theory, this controller continuously monitors the system status and adjusts the execution strategy. The system configures decision parameters for each fused operation group, including start conditions (such as matrix size threshold, sparsity threshold), switching conditions (such as performance counter trigger values, temperature threshold), and exit conditions. The controller collects multi-source runtime information: hardware status information (such as core frequency, temperature, cache hit rate), execution progress information (such as completed computation amount, remaining task amount), and matrix dynamic characteristics (such as sparse pattern changes, numerical distribution evolution). Based on this runtime information, the controller implements multi-strategy dynamic switching: algorithm variant switching selects between different implementation methods, such as dynamically switching between dense matrix multiplication and sparse matrix multiplication based on sparsity; precision configuration switching adjusts computational precision according to numerical characteristics, balancing precision and performance; resource configuration switching adjusts computational resource allocation, such as core count and frequency settings. The system implements a predictive switching mechanism, predicting future characteristic changes based on a state-space model to make switching decisions in advance and reduce switching latency. The controller is lightweight, minimizing decision overhead and using fast table lookups and heuristic rules to replace complex calculations. For ARM heterogeneous multi-core environments, the controller specifically optimizes the core migration strategy, selecting the most suitable core type (large or small cores) for execution based on the computational characteristics of the fusion operation and the current system load. The system outputs a complete dynamic switching strategy, including a decision tree, state transition diagram, and threshold parameter table. This adaptive control mechanism enables the execution of fusion operations to dynamically adapt to changes in matrix characteristics and system state fluctuations, maintaining optimal performance under various execution environments and truly achieving fine-grained adaptive optimization.

[0230] Based on the dynamic switching strategy and execution feedback data, an optimized feedback model is constructed to obtain a continuous optimization scheme. In this step, the system establishes a complete learning feedback loop to achieve continuous evolution of matrix calculation optimization. The system first designs a structured execution feedback data collection mechanism to record performance indicators, resource usage, and optimization decision effects at key execution points. The feedback data contains multi-dimensional information: time-dimensional data tracks the performance trend over time; spatial-dimensional data records the execution efficiency differences in different matrix regions; and decision-dimensional data correlates switching decisions with performance results. The system establishes a multi-level optimized feedback model: the short-term feedback model adjusts the control parameters of the current execution, such as decision thresholds and switching timing, through online learning; the medium-term feedback model optimizes pattern recognition and initial configuration similar to matrix calculations to improve cold start performance; and the long-term feedback model accumulates execution experience to drive the evolution of the fusion pattern library and code generation strategy. The system uses incremental learning algorithms to process feedback data and employs lightweight models such as linear regression, decision trees, or simplified neural networks to adapt to the computing resource limitations of ARM devices. The model training process adopts an online update strategy, updating model parameters immediately after each execution, enabling the system to quickly adapt to new matrix characteristics or execution environments. The system implements multi-level optimization adjustments: parameter-level adjustments fine-tune controller parameters and switching thresholds; strategy-level adjustments improve decision logic and priority rules; and structure-level adjustments modify fusion operation combinations and code generation patterns. The system also maintains an optimization knowledge base, recording successful optimization patterns and best practices for specific matrix types, supporting case-based optimization reasoning. Finally, the system outputs a continuous optimization scheme, including an adaptive parameter table, a dynamic decision tree, and an optimization evolution roadmap. This scheme not only guides current execution but also provides an optimization benchmark for similar future calculations, forming a positive feedback loop. This learning-based continuous optimization mechanism enables the system to adapt to constantly changing matrix characteristics and hardware environments, maintaining long-term optimal performance—a core characteristic of intelligent computing systems. Through continuous learning and improvement from actual execution, the system achieves true adaptive evolution, significantly improving matrix computation efficiency in diverse scenarios.

[0231] Example 10

[0232] The method of this invention also includes optimization and acceleration of ARM matrix calculation with mixed precision quantization, specifically including the following steps:

[0233] The system acquires the numerical distribution characteristics and accuracy requirements of the matrix, executes block floating-point representation design, and outputs a bidirectional block floating-point scheme. In this step, the system first deeply analyzes the numerical characteristics of the matrix, laying the foundation for efficient mixed-precision representation. The system calculates the fine numerical distribution characteristics of the matrix, including global statistical indicators (maximum, minimum, mean, standard deviation) and local distribution characteristics (value range variation in the row and column directions). The system performs multi-scale information entropy analysis on the matrix, assesses the information density and accuracy sensitivity of different regions, and determines the acceptable upper limit of error for each region based on the accuracy requirements of the application domain. Based on these analyses, the system designs an innovative bidirectional block floating-point representation scheme: First, in the row direction, the system divides the matrix into several row blocks, each row block sharing an exponent value, with each element storing only the mantissa; simultaneously, in the column direction, a similar strategy is used to divide column blocks, and an exponent is assigned to each column block. This bidirectional block floating-point representation forms a two-dimensional grid structure, where each grid intersection (sub-block) is jointly influenced by the exponents of both the row and column blocks, and its effective accuracy is determined by the scaling factors in both directions. The system employs an adaptive block size strategy, dynamically adjusting the block size based on the local similarity of the numerical distribution: larger blocks are used in regions with gradual numerical changes to improve compression ratio, while smaller blocks are used in regions with large numerical spans to ensure accuracy. The system also optimizes exponent bit width allocation, allocating more bits to regions with high information density to maximize compression ratio while maintaining accuracy. Finally, the system outputs a complete bidirectional block floating-point scheme, including the block partitioning strategy, exponent allocation scheme, and quantization parameters. This representation method is particularly suitable for long-tailed distributed matrices, significantly reducing overall storage space and computational complexity while maintaining accuracy in critical regions.

[0234] Based on the bidirectional block floating-point scheme and matrix region features, ternary region identification is performed to determine the quantization region. The matrix region features are a set of parameters describing the geometric, numerical, and computational characteristics of different spatial regions of the matrix. In this step, the system further analyzes the matrix structure to identify regions suitable for extreme quantization, laying the foundation for ternary representation. The system first analyzes the numerical distribution under bidirectional block floating-point representation, paying particular attention to the distribution characteristics of the mantissa. Through hierarchical clustering analysis, the system classifies matrix elements into three categories: significantly positive values ​​(making a significant positive contribution to the result), significantly negative values ​​(making a significant negative contribution to the result), and near-zero values ​​(with negligible contribution). The system uses adaptive thresholding technology to determine the ternary boundary, employing different criteria for different regions: highly active regions (usually hot spots in the matrix) use a more conservative threshold to ensure no loss of key information; low-activity regions (usually the long tail) use a more aggressive threshold to maximize compression. The system performs ternary evaluation of region specialization, considering multiple factors: the distribution of absolute element values, the relative magnitudes of elements, the sensitivity of elements in computation (estimated through gradient analysis), and the functional role of the region in matrix operations. The system also employs information theory methods to evaluate the information retention rate after ternaryization, ensuring that key information is not lost due to quantization. For each candidate region, the system calculates the KL divergence or mean squared error before and after ternaryization to predict the impact of quantization on the final result. The system pays particular attention to structured features, such as diagonal elements, frequently accessed rows / columns, or regions related to eigenvectors, and develops specific quantization strategies for these regions. Finally, the system generates detailed ternary region maps, including the boundaries of each region, applicable quantization parameters, and expected compression ratio. The system also generates hierarchical ternaryization schemes, allowing dynamic adjustment of the quantization range based on accuracy requirements and resource availability during execution, achieving a flexible balance between accuracy and efficiency. This intelligent region identification strategy ensures that ternaryization is applied to the most suitable regions, maximizing compression benefits while keeping accuracy loss within an acceptable range. Matrix region features refer to the computational and numerical characteristics of different regions of the matrix in the spatial dimension. Specifically, these include the geometric features of the region (such as its location coordinates, area, and shape parameters), numerical features (such as the numerical distribution, sparsity, and activity level of elements within the region), and computational features (such as the region's importance in matrix operations, computational complexity, and memory access patterns). For example, in a 1024×1024 deep learning weight matrix, the top-left 128×128 region might have high sparsity (90% of elements are zero) and low activity (contributing little to the result), while the central 256×256 region might have dense distribution (only 10% of elements are zero) and high activity (contributing significantly to the result). These regional characteristics directly influence the choice of quantization strategy; high-activity regions require maintaining high precision, while low-activity regions can employ more aggressive quantization schemes.

[0235] The quantization region and precision parameters are subjected to ternary quantization with a scaling factor to obtain compressed representation data. The precision parameters are a set of configuration parameters controlling the precision of numerical representation and computation. In this step, the system performs precise ternary quantization on the determined quantization region, converting the original floating-point data into a highly compressed representation. The system first optimizes the ternary quantization parameters, calculating the optimal scaling factor for each quantization region. This factor is typically determined based on the statistical distribution characteristics of the elements within the region, such as using the mean or median of the absolute values ​​of non-zero elements within the region as a benchmark. The system implements multiple ternary quantization strategies: threshold ternary quantization quantizes elements with absolute values ​​less than a threshold to 0, and the remaining elements are quantized to ±1 based on their sign; random ternary quantization introduces randomness near the threshold, making the overall expected value closer to the original distribution; lossy clustering ternary quantization clusters the original values ​​into three centers, minimizing the overall quantization error. For each element, the system applies an optimized quantization function: Q(x) = sign(x) * (|x|>threshold) * scale_factor, where sign() extracts the sign, the threshold determines whether to retain the element, and scale_factor is the scaling factor. The quantization process is accelerated using ARM NEON vector instructions, employing instructions such as VCGT (vector comparison greater than) and VBSL (vector bit selection) to process multiple elements in parallel. The system uses a block-parallel quantization strategy, with each thread processing one region of the matrix, fully utilizing the ARM multi-core architecture. After quantization, the system implements an efficient compressed storage format: for a ternary matrix, each element requires only 2 bits (00 represents 0, 01 represents +scale, and 10 represents -scale), and all 32 elements can be compressed and stored in a 64-bit integer. The system also maintains a scaling factor mapping table, recording the scaling coefficients for each region for subsequent dequantization operations. For special regions (such as those requiring high precision), the system implements mixed-precision storage, retaining key elements at their original precision. The system ultimately outputs highly compressed representation data, including the bit-compressed representation of the ternary matrix and the scaling factor mapping. This representation reduces storage space by more than 87.5% compared to the original floating-point format while retaining the critical information required for computation. The precision parameters refer to the set of key configuration parameters that control the precision of numerical representation and computation. This mainly includes numerical representation parameters (such as the bit width, exponent bits, and mantissa bits of floating-point numbers), quantization parameters (such as quantization threshold, scaling factor, and zero offset), and computation control parameters (such as rounding mode, overflow handling strategy, and error tolerance). For example, in mixed-precision computation, critical regions may use FP32 precision parameters (32-bit floating-point, 8-bit exponent, 23-bit mantissa), moderately important regions may use FP16 precision parameters (16-bit floating-point, 5-bit exponent, 10-bit mantissa), and non-critical regions may use INT8 quantization parameters (8-bit integer, scaling factor 0.1, zero offset 128).These parameters directly determine the range of numerical representation, the level of precision, and the computational cost.

[0236] The system performs a pre-padding operation on the compressed representation data and the memory characteristics of the ARM processor, outputting a memory access optimization scheme. In this step, the system further optimizes data storage and access patterns based on the compressed representation and the memory characteristics of the ARM processor. The system first analyzes the memory hierarchy of the ARM processor, including cache line size (typically 64 bytes), cache capacity, memory alignment requirements, and DMA transfer characteristics. For ternary compressed data, the system optimizes memory layout: it uses cache line aligned storage to ensure that frequently accessed data does not cross cache lines, reducing cache misses; it uses data rearrangement techniques to place frequently accessed elements in adjacent positions, improving spatial locality; and it applies special encoding, such as run-length encoding or bitmap indexing, to sparse regions to further compress all-zero or highly sparse blocks. The system performs a pre-padding operation, inserting carefully designed padding bits into the data structure to achieve multiple optimization goals: ensuring that the starting address of critical data structures is aligned with the cache line boundary, improving memory access efficiency; reserving operation space for special processing instructions (such as NEON bit operations), simplifying runtime processing; and adjusting the data block size to be an integer multiple of the width of the ARM processor's vector register, optimizing vector loading and storage operations. The system also optimizes the prefetch strategy, generating dedicated prefetch instruction sequences for ternary matrix operations: it analyzes the data access sequence under typical computational patterns and inserts PLD (preload) instructions to preload the data to be used into the cache; for predictable access patterns, it configures hardware prefetcher parameters to maximize prefetch efficiency; and it designs specialized prefetch templates for different operation patterns (such as matrix multiplication and convolution). The system specifically optimizes the access pattern of scaling factors, organizing scaling factors of relevant regions into contiguous blocks to reduce cache misses when accessing the scaling table. The system ultimately outputs a complete memory access optimization scheme, including a memory layout diagram, prefilling strategy, and prefetch instruction templates. These optimizations significantly reduce memory access latency and bandwidth requirements, which are key factors in improving the performance of ternary matrix computation.

[0237] Based on the aforementioned memory access optimization scheme and the ARM processor instruction set, bitwise operations are accelerated to obtain the final optimized result. In this step, the system utilizes the bitwise operation instructions of the ARM architecture to design an efficient algorithm to accelerate the calculation of ternary matrices. The system first analyzes the bitwise operation instruction set supported by the ARM processor, focusing on instructions such as bit counting (VCNT), bit selection (VBSL), bit clearing (BIC), and bit logic operations (AND, OR, XOR). Considering the characteristics of ternary representation, the system designs a dedicated computing kernel to achieve efficient execution of basic matrix operations. For ternary matrix multiplication, the system implements a bit-parallel algorithm: decomposing the ternary matrix into a sign matrix and a mask matrix, converting multiplication into bitwise operations, processing 32 or 64 elements at a time; using NEON vector instructions to execute bitwise operations in parallel, such as using VAND and VEOR instructions to process the sign bit, and using VCNT instructions to quickly calculate the result. The system employs specialized algorithms for different operations: for matrix addition, it directly calculates the result using the sign bit and scaling factor; for matrix multiplication, it implements a sparsity-aware algorithm to skip calculations with zero elements; and for special operations (such as dot product and convolution), it designs optimized algorithms for ternary representation. The system implements a mixed-precision calculation strategy, using high-precision accumulation for key intermediate results and quantizing them before final output to ensure accuracy requirements. The system specifically optimizes scaling factor handling: it pre-calculates and caches commonly used scaling factor combinations to reduce runtime computation; and it uses approximation techniques to accelerate scaling factor application, such as using bit shifting and addition to approximate multiplication operations. The system also implements an automatic vectorization framework, analyzing computational patterns and automatically generating optimal bit operation sequences, enabling the compiler to generate efficient machine code. To improve instruction-level parallelism, the system applies instruction pipelining optimization techniques, such as software pipelining and loop unrolling, to hide instruction latency. The system ultimately outputs a complete bit operation acceleration scheme, including optimized algorithms, instruction templates, and execution parameters. These optimizations improve the speed of ternary matrix operations by 3-15 times compared to traditional floating-point implementations, while significantly reducing energy consumption, making it particularly suitable for resource-constrained ARM devices. By tightly integrating numerical representation, memory optimization, and instruction optimization, the system achieves extreme performance in ternary matrix computation.

[0238] The method of the present invention also includes energy efficiency optimization and monitoring, specifically including the following steps:

[0239] The system acquires ARM processor status data and energy efficiency targets, executes execution controller design, and outputs energy efficiency control strategies. In this step, the system constructs a fine-grained energy efficiency control mechanism to balance computing performance and energy consumption. The system first acquires comprehensive ARM processor status data, including the operating frequency, utilization, temperature status, and power consumption data for each core. For processors supporting DVFS (Dynamic Voltage and Frequency Scaling), the system acquires available frequency levels and corresponding power consumption characteristic curves. The system also defines explicit energy efficiency targets, such as a performance-first mode (pursuing maximum computational throughput), an energy-first mode (pursuing the highest performance / power ratio), or a power-constrained mode (maximizing performance within a fixed power limit). Based on these parameters, the system designs a multi-layered execution controller: first, a macro-level strategy controller, which selects the core operating mode based on overall task characteristics and system status, such as selecting the number of cores, big.LITTLE core allocation strategy, and overall frequency range; second, a fine-grained DVFS controller, which adjusts the frequency and voltage of each core in real time, responding to load changes and temperature fluctuations; and third, a task scheduling controller, which allocates tasks based on computational characteristics and current energy efficiency status, assigning computationally intensive tasks to high-efficiency cores and memory-intensive tasks to low-power cores. The system implements predictive control algorithms, using least squares or Kalman filters to build load prediction models and proactively adjust processor states to handle upcoming computational peaks. The system also designs a feedback control loop, monitoring actual execution through performance counters and dynamically adjusting control parameters to achieve closed-loop optimization. For the ARM big.LITTLE architecture, the system implements a specialized heterogeneous scheduling strategy to optimize load allocation and migration decisions between large and small cores. The system pays special attention to thermal management, designing a temperature-sensing control strategy to proactively reduce power consumption when approaching thermal thresholds, preventing a sharp performance drop caused by thermal throttling. The system ultimately outputs a complete energy-efficient control strategy, including control rules, state transition diagrams, and parameter configuration tables. These strategies significantly reduce energy consumption while maintaining computational performance, extending the runtime of battery-powered devices, which is particularly important for mobile and embedded ARM devices.

[0240] Based on the energy efficiency control strategy and ARM processor parameters, dynamic adjustments are made to obtain optimized operating parameters. The ARM processor parameters are a set of parameters describing the hardware characteristics and operating state of the ARM architecture processor. In this step, the system translates the energy efficiency control strategy into specific runtime configuration parameters, achieving precise dynamic adjustment. The system first establishes a detailed power consumption model for the ARM processor, including static power consumption (leakage current related to temperature and voltage) and dynamic power consumption (related to computational load, clock frequency, and voltage). For a typical ARM processor, the system collects power consumption characteristic curves for each core type at different frequencies and establishes a power consumption prediction function. The system designs a dynamic parameter adjustment framework, including multiple control dimensions: frequency control dynamically selects the optimal processor frequency, choosing the lowest energy consumption configuration based on task computation intensity and current temperature conditions while meeting performance requirements; core selection determines the number and type of active processor cores, optimizing the usage ratio of large and small cores; memory control adjusts memory controller parameters, such as bandwidth limits and latency settings, balancing memory performance and power consumption; peripheral control manages the status of peripherals related to matrix computation, such as reducing unnecessary GPU or DSP power consumption. The system implements an adaptive adjustment algorithm, dynamically adjusting these parameters based on task characteristics and real-time performance feedback: for computationally intensive phases, the system increases core frequency and activates more cores; for memory-waiting phases, the system reduces frequency to save energy; for temperature-sensitive scenarios, the system implements a temperature balancing strategy to avoid localized hotspots. The system specifically optimizes parameter configuration for ternary matrix calculations: leveraging the low-power characteristics of bit operations, it selects lower voltage and frequency points; and optimizes front-end and back-end configurations based on instruction characteristics, such as predictor strategies and execution unit allocation. The system implements a segmented control strategy, configuring different energy efficiency parameters for different stages of matrix calculations (such as initialization, computationally intensive phases, and finalization phases). The system ultimately outputs a complete runtime parameter configuration, including frequency levels, core usage strategies, memory control parameters, and scheduling priority settings. These optimized parameters minimize energy consumption while ensuring performance targets, achieving true adaptive energy efficiency optimization. Here, ARM processor parameters refer to the set of parameters describing the hardware characteristics and operating state of the ARM architecture processor. These include architectural parameters (such as instruction set version, core type, NEON vector unit specifications), performance parameters (such as clock frequency, cache configuration, memory bandwidth), power consumption parameters (such as voltage level, power state, thermal design power), and dynamic status parameters (such as current load, temperature, and available resources). For example, typical ARM Cortex-A78 processor parameters include: ARMv8.2 instruction set, 4 large cores, 32KB L1 instruction cache, 32KB L1 data cache, 512KB L2 cache, 128-bit NEON unit, 2.4GHz maximum frequency, and 1.2V operating voltage.These parameters provide hardware constraints and optimization objectives for algorithm optimization and resource allocation.

[0241] Error tracking analysis is performed on the optimized operating parameters and precision representation data, and a cumulative error report is output. The precision representation data records detailed information about different numerical precision representation methods. In this step, the system implements a precise error monitoring mechanism to assess the precision loss introduced during optimization. The system first establishes an error measurement framework, defining multiple error measurement indicators: absolute error quantifies the error magnitude of a single element; relative error assesses the ratio of error to the original value; cumulative error tracks the error growth after continuous operations; and stability indicators assess the risk of numerical instability. The system implements a multi-level error tracking strategy: element-level tracking selects key elements or statistical sampling points to compare the differences between optimized calculations and full-precision reference calculations; operation-level tracking analyzes the error changes before and after a single matrix operation (such as matrix multiplication); and computation graph-level tracking evaluates the end-to-end error accumulation of the entire computation process. The system employs progressive sampling technology to reduce tracking overhead. In the initial stage, high-frequency full-coverage sampling is used to establish baseline data; in the stable stage, sampling monitoring is switched to sampling; and when an abnormal pattern is detected, it returns to dense sampling. The system pays special attention to error patterns introduced by ternary representation and block floating-point representation: quantization error (loss in mapping continuous values ​​to discrete values), truncation error (the impact of discarding small values), and rounding error (constraints in numerical representation during computation). The system implements an error propagation model to predict the cumulative error characteristics under different operation combinations, identifying potential error amplification points (such as inversion operations) or error cancellation points (such as the statistical averaging of random errors). The system also focuses on special numerical patterns, such as minimum value handling (avoiding information loss due to underflow to zero) and maximum value representation (preventing computational crashes caused by overflow). Finally, the system generates a detailed cumulative error report, including statistical error distribution (maximum value, mean, standard deviation), critical location error analysis (hotspot areas and sensitive points in the calculation results), and error trend prediction (estimated error growth in subsequent calculations). Furthermore, the system provides error visualization views, such as heatmaps displaying error distribution in matrices, to help intuitively understand error patterns. This precise error tracking mechanism provides a reliable basis for subsequent precision adjustments, ensuring that precision loss during optimization remains within a controllable range. Precision representation data refers to detailed information recording and describing different numerical precision representation methods. This includes a precision mapping table (specifying the precision type used in different regions of the matrix), a quantization configuration table (recording the quantization parameters and conversion rules for each region), error statistics (recording precision loss and error distribution), and precision conversion instructions (specifying the timing and method of precision conversion). For example, a precision representation might include: region A using FP32 representation with an error upper limit of 1e-6; region B using FP16 representation with a scaling factor of 2.5 and an error upper limit of 1e-3; and region C using 3-bit quantization with a threshold of 0.1 and an expected compression ratio of 8:1. This data provides detailed guidance for precision optimization and error control.

[0242] Based on the accumulated error report and computational task characteristics, a precision enhancement configuration is performed to obtain a balanced precision scheme. The computational task characteristics are feature parameters describing the attributes and requirements of the matrix computation task. In this step, the system implements a precise precision balancing strategy based on the error analysis results, selectively enhancing computational precision at key locations. The system first analyzes the accumulated error report and computational task characteristics to identify areas requiring precision enhancement, mainly including: error-sensitive areas (areas where error changes significantly affect the final result), error accumulation areas (areas where error grows rapidly with computational steps), and functionally critical areas (areas where the accuracy of the result is crucial from an application perspective). For these areas, the system designs a precision enhancement configuration and implements various precision balancing techniques: a precision hybrid strategy uses higher precision representation in critical areas (e.g., upgrading from ternary to block floating-point or from block floating-point to full-precision floating-point), while maintaining lower precision representation in non-critical areas, optimizing the overall precision and performance balance; precision compensation algorithms correct quantization errors through additional computational steps, such as using residual calculations to record and compensate for quantization loss information; and numerical stability enhancement techniques apply special computational orders or algorithm variants, such as the Kahan summation algorithm to reduce rounding error accumulation. The system employs specialized precision balancing strategies for different computational modes: for matrix multiplication, high precision may be used during the accumulation phase, with quantization performed only in the final output; for sensitive operations such as inversion, high precision may be used entirely to avoid error amplification; for element-level operations, a position-adaptive precision strategy may be implemented, with high precision in hotspot regions and low precision in edge regions. The system establishes a cost model for precision control, evaluating the resource overhead (computational load, memory requirements, and increased energy consumption) of each precision enhancement strategy, and selecting the precision configuration with the highest return on investment. The system ultimately generates a detailed precision balancing scheme, including a precision allocation map (specifying the precision representation used in each region of the matrix), an algorithm selection strategy (selecting the optimal algorithm suitable for the current precision configuration), and a precision conversion guide (specifying the location and method of precision conversion). This intelligent precision balancing strategy ensures that the system meets precision requirements with minimal resource overhead, achieving an optimal balance between precision and performance. The computational task characteristics refer to the feature parameters describing the attributes and requirements of a specific matrix computation task. These characteristics include task type features (such as matrix multiplication, inversion, and eigenvalue calculation), performance requirements (such as latency requirements, throughput targets, and energy efficiency constraints), accuracy requirements (such as result accuracy requirements and tolerance for intermediate computational accuracy), and resource constraints (such as memory limitations, computation time limitations, and power budget). For example, scientific computing tasks may have high accuracy requirements (relative error <1e-12) and medium performance requirements (completion time <1 hour); while mobile inference tasks may have medium accuracy requirements (relative error <1e-3), high performance requirements (latency <100ms), and strict power consumption constraints (<2W). These characteristics guide the formulation of overall optimization strategies and parameter tuning.

[0243] Based on the balanced precision scheme and system operation data, a precision energy efficiency model is constructed, and the final optimization strategy is output. In this step, the system delves into the relationship between precision configuration and energy efficiency performance, constructing a systematic precision energy efficiency model to guide the final optimization decision. The system first collects system operation data after the implementation of the precision scheme, including performance indicators (throughput, latency) and energy efficiency indicators (power consumption, energy consumption / operation). The system correlates these data with precision configuration parameters, establishing a multi-dimensional mapping relationship and analyzing the impact patterns of different precision choices on performance and energy efficiency. Based on these analyses, the system constructs a precision energy efficiency model that describes the functional relationship between precision selection and computational efficiency on a given hardware platform. The model considers several key factors: the computational complexity of precision representation (e.g., the performance ratio of FP32 operations to ternary operations), the overhead of precision conversion (e.g., the cost of converting between different precisions), changes in memory access patterns (e.g., the improvement in cache efficiency after reducing precision), and power consumption characteristics (e.g., the energy consumption differences between different precision representations). The system implements model-based optimization strategy generation: priority optimization determines the accuracy allocation priority for different stages and regions, prioritizing accuracy in critical regions; automatic parameter tuning uses a model-based search algorithm to explore the optimal balance between accuracy and energy efficiency; adaptive strategy generation generates different optimization schemes for different execution environments (such as battery status and temperature conditions). The system pays special attention to ARM-specific optimization opportunities, such as leveraging the heterogeneity of the big.LITTLE architecture to perform critical high-precision calculations on large cores and non-critical low-precision calculations on small cores, maximizing energy efficiency. The system also considers temperature management, designing an accuracy degradation cooling strategy to selectively reduce the accuracy of non-critical calculations under high-temperature conditions, reducing power consumption and heat generation. The system finally outputs a complete optimization strategy, including specific implementation steps, parameter configuration tables, and expected benefit analysis. This strategy typically achieves a 30-70% improvement in energy efficiency while maintaining computational accuracy within an acceptable range for the application. Through systematic accuracy and energy efficiency modeling and optimization, the system finds the optimal balance between accuracy, performance, and energy efficiency in matrix calculations, making it particularly suitable for battery-powered ARM devices, significantly extending the effective operating time of the device while meeting computational quality requirements.

[0244] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. In summary, the present invention is not limited to the specific implementation methods described above. Any simple equivalent changes made based on the technical solutions of the present invention fall within the protection scope of the present invention.

[0245] This disclosure also provides a computer-readable storage medium storing a computer program. When a processor executes the program, it performs the steps of an ARM-based adaptive optimization method for matrix computation described in the above-described method embodiments. The storage medium can be either volatile or non-volatile computer-readable storage.

[0246] Furthermore, this disclosure also provides a computer program product storing a computer program. When the computer program is run by a processor, it executes the steps of an adaptive optimization method for matrix calculation based on ARM architecture provided in any of the above embodiments of this disclosure. For details, please refer to the above method embodiments, which will not be repeated here.

[0247] The aforementioned computer program product can be implemented through hardware, software, or a combination thereof. In one optional embodiment, the computer program product is specifically embodied in a computer storage medium, which can be a volatile or non-volatile computer-readable storage medium. In another optional embodiment, the computer program product is specifically embodied in a software product, such as a software development kit (SDK), etc.

[0248] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the devices and apparatuses described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. In the several embodiments provided in this disclosure, it should be understood that the disclosed devices, apparatuses, and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Another point is that the displayed or discussed mutual coupling or direct coupling or communication connection may be through some communication interfaces; the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms.

[0249] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0250] In addition, the functional units in the various embodiments of this disclosure can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0251] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this disclosure, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this disclosure. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0252] Finally, it should be noted that the above-described embodiments are merely specific implementations of this disclosure, used to illustrate the technical solutions of this disclosure, and not to limit it. The protection scope of this disclosure is not limited thereto. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this disclosure; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure, and should all be covered within the protection scope of this disclosure. Therefore, the protection scope of this disclosure should be determined by the protection scope of the claims.

Claims

1. An adaptive optimization method for matrix computation based on ARM architecture, characterized in that, include: Obtain the matrix data to be processed and the ARM processor information, preprocess the matrix data to be processed, and obtain the preprocessed matrix data; The preprocessed matrix data is subjected to local activity calculation and hotspot region identification to determine the long-tail distribution characteristics of the matrix. Based on the long-tail distribution characteristics of the matrix and the multi-level cache capacity parameters in the ARM processor information, the optimal block size range of the matrix is ​​calculated, and an asymmetric block partitioning scheme is generated, including: Obtain statistical distribution data of global activity and statistical distribution data of local activity. Design blocks adapted to L1 cache for regions with activity exceeding the third preset threshold, and design blocks adapted to L2 / L3 cache for regions with activity below the fourth preset threshold to obtain the initial block partitioning scheme. Based on the initial segmentation scheme, cross-segment hotspot regions are identified, and overlapping cutting is used to ensure that hotspot elements are completely contained within a single segment, and segmentation boundary data is output. Obtain the block boundary data and perform memory alignment optimization to ensure that the block boundaries are aligned with cache lines; Acquire historical execution data and fine-tune the block size and shape based on execution efficiency metrics; Based on the asymmetric partitioning scheme, the execution time and cache hit rate of each partition are collected, and a mapping relationship between matrix features and optimal partitioning parameters is established. The partition is the basic sub-block of the preprocessed matrix data. Establishing the mapping relationship between matrix features and optimal partitioning parameters includes: Obtain block execution data, and collect the execution time, cache hit rate and instruction throughput of each block; Obtain performance metrics and analyze the correlation between the block execution data and the performance metrics; Obtain the correlation data between the block execution data and the performance indicators, and establish a mapping relationship model between matrix features and optimal block parameters; Deploy the mapping model to the ARM TrustZone environment and update the block strategy history library; Acquire historical database data and record the optimal block parameters under different matrix features; Based on the asymmetric partitioning scheme and the mapping relationship between the matrix features and the optimal partitioning parameters, the computational density and memory access pattern of each partition are calculated to generate a task scheduling scheme. Based on the task scheduling scheme, matrix calculations are performed on a processor with an ARM big.LITTLE architecture, and the final calculation results are output.

2. The method according to claim 1, characterized in that, The calculation of local activity in the preprocessed matrix data includes: The preprocessed matrix data is divided into basic sub-blocks of a reference size, and the proportion of non-zero elements and the variance of numerical distribution are calculated for each basic sub-block. Based on the proportion of non-zero elements and the variance of numerical distribution of each basic sub-block, the relative importance score of each basic sub-block is calculated to obtain the sub-block's computational contribution. Based on the contribution of the sub-blocks, the statistical distribution data of the local activity of the basic sub-blocks is calculated using the NEON SIMD instruction to obtain the local activity distribution map of the matrix. The local activity distribution map is standardized to obtain a standardized local activity distribution map. Based on the standardized local activity distribution map, a sparse data structure is used to store basic sub-block information whose activity exceeds a first preset threshold.

3. The method according to claim 2, characterized in that, The hotspot area identification includes: Based on the preprocessed matrix data, the statistical distribution data of global activity is calculated, and a global activity distribution map is constructed. The statistical distribution data of global activity includes the mean and standard deviation. Based on the statistical distribution data of global activity, the OTSU algorithm is used to optimize the activity threshold cut-off point to obtain the optimized activity threshold. Obtain the optimized activity threshold and convert the global activity distribution map into a hotspot distribution binary map; Receive the hotspot distribution binary map, execute the connected component labeling algorithm, cluster and merge adjacent hotspot regions to obtain the clustering and merging result; Obtain the clustering and merging results, apply morphological operations to refine the hotspot regions, remove isolated hotspots with an area smaller than the second preset threshold, and obtain the refined hotspot regions. Receive the modified hotspot areas and obtain the location information, shape features, and activity features of each hotspot area.

4. The method according to claim 1, characterized in that, The task scheduling scheme includes: Obtain block characteristic data, allocate blocks with computational density exceeding a fifth preset threshold to the first core for processing, allocate blocks with computational density below a sixth preset threshold to the second core for processing, and ensure that the number of the first core is greater than the number of the second core; Receive block priority data and set task execution order and preemption strategy; Obtain the core features of the ARM processor, configure core affinity, obtain the core affinity configuration, and specify the execution core for a specific type of task; It receives the dependencies of the tasks to be executed, and enables task group scheduling and synchronization checkpoint setting; Obtain cache characteristic data, optimize shared cache and memory access strategies, and reduce inter-core data transfer.

5. The method according to claim 4, characterized in that, The execution of matrix calculations on an ARM big.LITTLE architecture processor includes: Obtain the block characteristic data and select the corresponding NEON instruction set optimized kernel for different types of blocks; Obtain the block activity characteristics and configure the parameters of the mixed precision calculation matrix; Obtain the memory access mode, configure the ARM cache prefetch instruction, and optimize the memory access order; Based on the core affinity configuration, each block computation is executed in parallel to obtain the computation results of each block. Obtain the calculation results of each block, and perform result merging and correctness verification.

6. The method according to claim 1, characterized in that, The method further includes: We obtain the matrix operation process and the characteristics of the ARM processor, define the operation axiomatic system using a formal language, and obtain the formal specification; The formal specifications are analyzed and processed to generate system verification assertions and output executable verification rules. According to the executable verification rules, the correctness of the asymmetric block partitioning scheme is verified using theorem proving tools, and a verification report is generated. Based on the verification report and the mixed accuracy calculation data, error propagation analysis was performed to establish an accuracy error model; Based on the aforementioned accuracy error model and actual execution data, formal verification is performed, and formal proof results are output.

7. The method according to claim 1 or 6, characterized in that, The method also includes on-time verification and recovery, including: Obtain matrix calculation execution status information, perform verification checks, and generate verification results; Based on the verification results and the preset error level standards, perform hierarchical error classification and determine the error handling strategy; Based on the error handling strategy and accuracy problem data, perform accuracy path adjustment and output the corrected calculation path; Based on the modified computation path and the numerical distribution characteristics of the matrix, numerical stability adjustment is performed to obtain optimized computation parameters; Based on the optimized calculation parameters and the current ARM processor state, task scheduling is reorganized, and a new execution plan is output.

8. The method according to claim 1, characterized in that, The method includes: Obtain the preprocessed matrix data and state-space model parameters, perform dynamic characteristic analysis, and obtain the feature sequence; Construct a complete computational operation graph, combine it with the feature sequence, identify fusionable operation combinations, and output a fusion scheme; Based on the aforementioned fusion scheme and the characteristics of the ARM processor, optimized execution code is obtained; Collect runtime information from multiple sources, and use the optimized execution code to output a dynamic switching strategy; Based on the dynamic switching strategy and execution feedback data, an optimization feedback model is constructed to obtain a continuous optimization scheme.

9. The method according to claim 1 or 8, characterized in that, The method also includes hybrid precision optimization, including: Obtain the numerical distribution characteristics and accuracy requirements of the matrix, perform block floating-point representation design, and output a bidirectional block floating-point scheme; Based on the bidirectional block floating-point scheme and matrix region features, ternary region identification is performed to determine the quantization region, wherein the matrix region features are a set of parameters describing the geometric, numerical, and computational features of different spatial regions of the matrix; The quantization region and precision parameters are subjected to ternary quantization with scaling factor to obtain compressed representation data, wherein the precision parameters are a set of configuration parameters that control the precision of numerical representation and calculation. Perform a pre-filling operation on the compressed representation data and the memory characteristics of the ARM processor, and output a memory access optimization scheme; Based on the memory access optimization scheme and the ARM processor instruction set, bit operation acceleration processing is performed to obtain the final optimization result.

10. The method according to claim 1, characterized in that, The method also includes energy efficiency optimization and monitoring, including: Acquire ARM processor status data and energy efficiency targets, execute controller design, and output energy efficiency control strategy; Based on the energy efficiency control strategy and ARM processor parameters, dynamic adjustments are made to obtain optimized operating parameters, wherein the ARM processor parameters are a set of parameters describing the hardware characteristics and operating state of the ARM architecture processor. Error tracking analysis is performed on the optimized operating parameters and precision representation data, and a cumulative error report is output. The precision representation data is detailed information recording different numerical precision representation methods. Based on the accumulated error report and the characteristics of the calculation task, an accuracy enhancement configuration is performed to obtain a balanced accuracy scheme. The characteristics of the calculation task are feature parameters that describe the attributes and requirements of the matrix calculation task. Based on the balanced accuracy scheme and system operation data, an accuracy-energy-efficiency model is constructed, and the final optimization strategy is output.

11. An adaptive optimization system for matrix computation based on ARM architecture, characterized in that, include: The acquisition module is used to acquire the matrix data to be processed and ARM processor information, and to preprocess the matrix data to be processed to obtain the preprocessed matrix data. The identification module is used to calculate local activity and identify hotspot regions in the preprocessed matrix data to determine the long-tail distribution characteristics of the matrix. The calculation module receives the long-tail distribution characteristics of the matrix and the multi-level cache capacity parameters of the ARM processor, calculates the optimal block size range, and generates an asymmetric block partitioning scheme, including: obtaining statistical distribution data of global activity and statistical distribution data of local activity; designing blocks adapted to L1 cache for regions with activity exceeding a third preset threshold, and designing blocks adapted to L2 / L3 cache for regions with activity below a fourth preset threshold, to obtain an initial block partitioning scheme; based on the initial block partitioning scheme, identifying cross-block hotspot regions, ensuring that hotspot elements are completely contained within a single block through overlapping cutting, and outputting block boundary data; obtaining the block boundary data, performing memory alignment optimization to ensure that block boundaries are aligned to cache lines; obtaining historical execution data, and fine-tuning the block size and shape according to execution efficiency indicators; A module is established to acquire the asymmetric partitioning scheme, collect the execution time and cache hit rate of each partition, and establish a mapping relationship between matrix features and optimal partitioning parameters. The partition is the basic sub-block of the preprocessed matrix data. Establishing the mapping relationship between matrix features and optimal partitioning parameters includes: acquiring partition execution data, collecting the execution time, cache hit rate, and instruction throughput of each partition; acquiring performance metrics and analyzing the correlation between the partition execution data and the performance metrics; acquiring correlation data between the partition execution data and the performance metrics, and establishing a mapping relationship model between matrix features and optimal partitioning parameters; deploying the mapping relationship model to the ARM TrustZone environment and updating the partitioning strategy history database; acquiring historical database data and recording the optimal partitioning parameters under different matrix features. The generation module is used to obtain the asymmetric partitioning scheme and mapping relationship, calculate the computational density and memory access mode of each partition, and generate a task scheduling scheme. The output module is used to obtain the task scheduling scheme, perform matrix calculations on the ARM big.LITTLE architecture processor, and output the final calculation results.

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