Quantum gate scheduling method and device, equipment, storage medium and program product

Abstract

The embodiment of the invention discloses a quantum gate scheduling method and device, equipment, a storage medium and a program product, and the method comprises the steps: generating a DAG according to the dependency relationship of a quantum gate in a quantum circuit, and enabling a node of the DAG to be a quantum gate node; according to the probability that the nodes of the DAG are selected, heuristically selecting the quantum gate nodes in the DAG to obtain a scheduling result, and the scheduling result comprises the quantum gate nodes arranged according to the selection sequence.

Description

Technical Field

[0001] The present application belongs to the field of quantum computing and relates to, but is not limited to, a quantum gate scheduling method, apparatus, device, storage medium, and program product. Background Art

[0002] In related technologies, qubit mapping and quantum gate scheduling support the execution of quantum circuits by quantum processors. Qubit mapping allocates hardware resources to quantum circuits, mapping the logical qubits in quantum circuits to the physical qubits in quantum chips. Quantum gate scheduling plans the execution of quantum gates in quantum circuits. The quantum gate scheduling process is relatively complex, making it difficult to achieve optimal scheduling results quickly for complex and other quantum circuits. Summary of the Invention

[0003] The embodiments of the present application provide a quantum gate scheduling method, apparatus, device, storage medium, and program product.

[0004] This embodiment of the present application proposes a quantum gate scheduling method, the method comprising: Generate a directed acyclic graph (DAG) based on the dependency relationship of quantum gates in the quantum circuit, where nodes of the DAG are quantum gate nodes; According to the probability of the nodes of the DAG being selected, quantum gate nodes are heuristically selected in the DAG to obtain a scheduling result, where the scheduling result includes the quantum gate nodes arranged in a selection order.

[0005] The present application also provides a quantum gate scheduling device, which includes: A first processing module is configured to generate a DAG according to the dependency relationship of quantum gates in the quantum circuit, wherein the nodes of the DAG are quantum gate nodes; The second processing module is configured to heuristically select quantum gate nodes in the DAG according to the probability of the nodes of the DAG being selected, and obtain a scheduling result, wherein the scheduling result includes the quantum gate nodes arranged in a selection order.

[0006] An embodiment of the present application further provides an electronic device, comprising a processor and a memory for storing a computer program that can be run on the processor; wherein the processor is configured to run the computer program to perform any one of the above-mentioned quantum gate scheduling methods.

[0007] An embodiment of the present application further provides a computer storage medium storing a computer program, which, when executed by a processor, implements any of the above-mentioned quantum gate scheduling methods.

[0008] An embodiment of the present application further provides a computer program product, including a computer program, which implements any of the above-mentioned quantum gate scheduling methods when executed by a processor.

[0009] It can be seen that in the embodiment of the present application, after generating a DAG based on the dependency relationship of the quantum gates in the quantum circuit, the selection of quantum gate nodes in the DAG can be guided by a heuristic selection method based on the probability of the DAG nodes being selected. In this way, by using the heuristic selection method, it is possible to avoid the scheduling result from falling into the local optimum to a certain extent, thereby facilitating the rapid acquisition of a better quantum gate scheduling result. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 Schematic diagram of the atomic array in a quantum processor; Figure 2 A flowchart of a quantum gate scheduling method according to an embodiment of the present application; Figure 3 Schematic diagram of the last selected single-bit gate node and the single-bit gate node currently to be scheduled in an embodiment of the present application; Figure 4 This is a flowchart of obtaining scheduling results in an embodiment of the present application; Figure 5 This is a flow chart of the quantum bit mapping and quantum gate scheduling method in the embodiment of the present application; Figure 6 This is a schematic diagram of the structure of a quantum gate scheduling device according to an embodiment of the present application; Figure 7 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0011] Neutral atom quantum computing technology has made significant progress in recent years. Due to its high fidelity, long coherence time, good scalability, and configuration flexibility, it is widely considered by researchers to be the most promising candidate for realizing quantum computers. Within the field of neutral atom quantum computing, reconfigurable atom arrays (RAAs) are a promising new technology approach. They allow the creation and manipulation of logical qubits by reconfiguring physical qubits, and feature high-fidelity two-qubit gates and arbitrary connectivity.

[0012] In related technologies, for RAAs quantum processors, the atomic array can be divided into a storage area and a manipulation area. Figure 1The storage area 101 is used to store quantum bits, and the manipulation area 102 is used to perform quantum gate operations. When performing quantum gate operations, the corresponding quantum bits can be moved from the storage area 101 to the idle position of the manipulation area 102 through a migration (mov) operation to apply the gate operation. Figure 1 In FIG, Q0 and Q1 represent two quantum bits that need to be moved from the storage area 101 to the manipulation area 102.

[0013] For RAAs quantum processors, in order to ensure fidelity, the quantum gate operations in the control area 102 should all be global operations, and only one quantum gate operation can be executed at a time. Therefore, how to schedule the execution order of quantum gates in the quantum circuit is crucial.

[0014] In related technologies, neutral atom qubit mapping and quantum gate scheduling methods are designed for fixed atom arrays (FAAs). Unlike RAAs, FAAs cannot guarantee full qubit connectivity (i.e., any two physical qubits are connected). Therefore, during qubit mapping, swap (SWAP) gates must be inserted into the quantum circuit to meet the execution constraints of the two-qubit gates. This generates additional gate operations and reduces execution fidelity. Therefore, most qubit mapping methods in related technologies focus on optimizing the number of inserted SWAP gates. Regarding quantum gate scheduling, FAAs quantum processors support the simultaneous operation of multiple quantum gates. Therefore, scheduling only requires considering the dependencies between quantum gates. A DAG is generated through the quantum circuit, and the DAG is then searched to determine the quantum gate scheduling sequence with the shortest execution time.

[0015] In order to provide a quantum bit mapping and quantum gate scheduling method for RAAs quantum processors, the following aspects need to be considered: First, since the control area only allows the execution of one quantum gate at a time, the serial execution of quantum gate operations will lead to a waste of quantum hardware resources. Therefore, reasonable scheduling of the execution order of quantum gates in the quantum circuit will help reduce the movement of quantum bits and improve the fidelity and efficiency of quantum circuit execution. Second, based on the characteristic that the control area can only execute one quantum gate at a time, it is necessary to merge identical quantum gates as much as possible, which will help improve the execution efficiency of the quantum circuit. Third, due to the limitations of noisy intermediate-scale quantum (NISQ) hardware, the fidelity of quantum circuit execution is often difficult to guarantee. Reasonable quantum bit mapping will help ensure the fidelity of quantum circuit execution. Fourth, the quantum gate scheduling process is relatively complex. For some quantum circuits, such as complex quantum circuits, it is difficult to obtain better scheduling results in a short period of time.

[0016] In response to the technical problems existing in related technologies, the technical solutions of the embodiments of the present application are proposed. The embodiments of the present application can optimize execution efficiency and fidelity and provide a technical solution for quantum circuit execution of RAAs.

[0017] The following is a further detailed description of the embodiments of the present application in conjunction with the accompanying drawings and examples. It should be understood that the embodiments provided herein are merely for explaining the embodiments of the present application and are not intended to limit the embodiments of the present application. In addition, the embodiments provided below are partial embodiments for implementing the present application, rather than providing all embodiments for implementing the present application. In the absence of conflict, the technical solutions described in the embodiments of the present application can be implemented in any combination.

[0018] It should be noted that, in the embodiments of the present application, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a method or apparatus comprising a series of elements includes not only the elements explicitly stated, but also other elements not explicitly listed, or also includes elements inherent to the implementation of the method or apparatus. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the presence of other related elements (such as steps in the method or units in the apparatus, for example, a unit may be a portion of a circuit, a portion of a processor, a portion of a program or software, etc.) in the method or apparatus comprising the element.

[0019] The quantum gate scheduling method provided in the embodiments of the present application includes a series of steps, but the quantum gate scheduling method provided in the embodiments of the present application is not limited to the steps described. Similarly, the quantum gate scheduling device provided in the embodiments of the present application includes a series of modules, but the device provided in the embodiments of the present application is not limited to including the modules explicitly described and may also include modules required for obtaining relevant information or performing processing based on the information.

[0020] Figure 2 This is a flow chart of the quantum gate scheduling method according to an embodiment of the present application. Figure 2 As shown, the process includes: Step 201: Generate a DAG based on the dependency relationship of quantum gates in the quantum circuit, where the nodes of the DAG are quantum gate nodes.

[0021] A quantum circuit, also known as a quantum circuit, is an abstract computational model based on the principles of quantum mechanics. It describes the operation of quantum information storage units (such as qubits). In this computational model, a quantum gate can be considered a quantum circuit that operates on a small number of qubits. Quantum gates can be represented using matrices and can be either single-bit or two-bit gates.

[0022] Quantum gate dependencies represent the relationship between logical qubits and quantum gates. Based on these dependencies, a DAG containing quantum gate nodes can be constructed. A DAG is a directed graph without loops. Quantum gate nodes in a DAG can be either single-bit gate nodes based on single-bit gates or two-bit gate nodes based on two-bit gates.

[0023] Step 202: Based on the probability of a node being selected in the DAG, heuristically select quantum gate nodes in the DAG to obtain a scheduling result, which includes quantum gate nodes arranged in a selection order.

[0024] In an embodiment of the present application, the probability of a single-bit gate node being selected and the probability of a two-bit gate node being selected in a DAG can be determined separately. Then, a quantum gate node is heuristically selected in the DAG based on the probabilities of the single-bit gate node being selected and the probabilities of the two-bit gate node being selected. In practical applications, a heuristic algorithm can be used to select quantum gate nodes in the DAG based on the probabilities of the DAG nodes being selected. When quantum gate nodes are selected multiple times in the DAG using the heuristic algorithm, the selection order can be determined, thereby obtaining quantum gate nodes arranged in the selection order.

[0025] In practical applications, steps 201 to 202 may be implemented based on a processor, and the processor may be at least one of an application specific integrated circuit (ASIC), a digital signal processor (DSP), a digital signal processing device (DSPD), a programmable logic device (PLD), a field programmable gate array (FPGA), a central processing unit (CPU), a controller, a microcontroller, and a microprocessor.

[0026] It can be seen that in the embodiment of the present application, after generating a DAG based on the dependency relationship of the quantum gates in the quantum circuit, the selection of quantum gate nodes in the DAG can be guided by a heuristic selection method based on the probability of the DAG nodes being selected. In this way, by using the heuristic selection method, it is possible to avoid the scheduling result from falling into the local optimum to a certain extent, thereby facilitating the rapid acquisition of a better quantum gate scheduling result.

[0027] In the embodiment of the present application, quantum gate nodes can be heuristically selected during the quantum gate scheduling phase without the need for a time-consuming optimization algorithm. Therefore, the possibility of finding the optimal solution at a low time cost can be increased while avoiding falling into a local optimum, thereby helping to reduce the time complexity of the quantum gate scheduling solution.

[0028] To ensure the fidelity of quantum gate operations in quantum circuits, high-quality qubit mapping is required before quantum gate scheduling. In some embodiments, before generating a DAG based on the dependencies of quantum gates in the quantum circuit, the logical qubits in the quantum circuit can be sorted in descending order of the number of quantum gates applied to them. Based on the sorting results, each logical qubit is sequentially mapped to multiple physical qubits ranked in descending fidelity, with the mapping relationship between the logical qubits and the physical qubits being one-to-one.

[0029] In order to determine the fidelity of multiple physical quantum bits, in some embodiments, a preset reference quantum circuit can be mapped to different physical quantum bits, and quantum gate operations can be performed based on different physical quantum bits. Then, by comparing the execution results with the theoretical results, the fidelity of different physical quantum bits can be obtained. Thus, multiple physical quantum bits can be sorted in order of fidelity from large to small.

[0030] The quantum gates applied to the logical qubits can be quantum gates in the quantum circuit or basic quantum gates derived by decomposing the quantum gates in the quantum circuit. In some embodiments, the quantum gates in the quantum circuit can be decomposed into basic quantum gates that can be directly executed in the quantum processor. The number of basic quantum gates applied to each logical qubit in the quantum circuit is then counted. In other embodiments, the number of quantum gates applied to each logical qubit in the quantum circuit can be calculated.

[0031] After sorting the logical and physical qubits based on the aforementioned logical qubit and physical qubit ordering methods, each logical qubit can be sequentially mapped to multiple physical qubits ranked from highest to lowest fidelity, forming a one-to-one mapping relationship between the logical qubits and the physical qubits. This embodiment of the present application allows for a reasonable mapping of the physical qubits to the logical qubits based on the fidelity of the physical qubits and the number of quantum gates applied to the logical qubits in the quantum circuit.

[0032] It can be seen that the embodiment of the present application can map each logical qubit in sequence to multiple physical qubits arranged in descending order of fidelity based on the sorting results of each logical qubit. Since the sorting results of the logical qubits are determined based on the number of quantum gates applied to the logical qubit, and the number of quantum gates applied to the logical qubit can reflect the number of quantum gate operations in which the logical qubit participates, the embodiment of the present application can improve the fidelity of quantum gate operations in the quantum circuit by mapping logical qubits that participate in more quantum gate operations to high-quality physical qubits, thereby helping to improve the overall fidelity of the quantum circuit execution scheme.

[0033] After mapping logical qubits to physical qubits, a DAG can be generated based on the dependencies of quantum gates in the quantum circuit. For example, the quantum gate nodes in the DAG include single-bit gate nodes, which consist of multiple consecutive single-bit gates acting on the same qubit. In practical applications, multiple consecutive single-bit gates acting on the same qubit can be combined into a single single-bit gate node. A single-bit gate node in the DAG can be denoted as node_s.

[0034] It can be seen that by merging consecutive single-bit gates acting on the same quantum bit in the quantum circuit as single-bit gate nodes, the complexity of subsequent calls to single-bit gates can be reduced, which is conducive to reducing the time complexity of quantum gate scheduling.

[0035] The quantum gate nodes in the DAG also include two-bit gate nodes. In practical applications, each two-bit gate in the quantum circuit can be regarded as a two-bit gate node. A two-bit gate node in the DAG can be denoted as node_m.

[0036] After generating a DAG, the nodes to be scheduled can be determined from the quantum gate nodes in the DAG. For example, the in-degree of each quantum gate node in the DAG can be calculated. The in-degree of each node represents the number of edges pointing to that node. Next, quantum gate nodes with an in-degree of 0 in the DAG are identified as nodes to be scheduled. Here, quantum gate nodes with an in-degree of 0 in the DAG are the top-level nodes in the DAG. After determining the nodes to be scheduled, a quantum gate node can be heuristically selected from the nodes to be scheduled based on the probability of each node being selected, resulting in a scheduling result.

[0037] In the embodiment of the present application, the probability of a node being selected in the DAG is used to guide the selection of quantum gate nodes in the nodes to be scheduled through a heuristic selection method. In this way, by using the heuristic selection method, it is possible to avoid the scheduling result from falling into the local optimum to a certain extent, thereby facilitating the rapid scheduling of the nodes to be scheduled.

[0038] Regarding the implementation method of obtaining the scheduling result, in some embodiments, after each quantum gate node is selected from the nodes to be scheduled, the selected quantum gate node is added to the scheduling result, and the selected quantum gate node is deleted from the quantum gate nodes with an in-degree of 0, and the nodes to be scheduled are re-determined. The step of selecting quantum gate nodes from the nodes to be scheduled is repeated until the number of nodes to be scheduled is 0.

[0039] It can be understood that after the selected quantum gate node is added to the scheduling result, if the selected quantum gate node is deleted from the quantum gate nodes with an in-degree of 0 and the nodes to be scheduled are re-determined, the number of nodes to be scheduled will gradually decrease. When the number of nodes to be scheduled is 0, it means that the scheduling of all quantum gate nodes with an in-degree of 0 is completed. That is, the embodiment of the present application can comprehensively schedule the quantum gate nodes with an in-degree of 0.

[0040] Regarding the implementation method for determining the probability of a quantum gate node being selected in a node to be scheduled, in some embodiments, when initially selecting a quantum gate node in the node to be scheduled, the quantum gate node is selected in the node to be scheduled based on a first probability of each single-bit gate node being selected in the node to be scheduled and a second probability of each two-bit gate node being selected in the node to be scheduled; wherein the first probability is determined based on the number of quantum gates included in each single-bit gate node in the node to be scheduled and the sum of the number of quantum gates included in each single-bit gate node in the node to be scheduled, and the second probability is determined based on the number of two-bit gate nodes in the node to be scheduled.

[0041] Here, the probability of each single-bit gate node being selected in the node to be scheduled is positively correlated with the number of quantum gates contained in the corresponding single-bit gate node, and negatively correlated with the sum of the numbers of quantum gates contained in each single-bit gate node in the node to be scheduled.

[0042] The node to be scheduled The number of quantum gates contained in a single-bit gate node can be recorded as , the sum of the number of quantum gates contained in each single-bit gate node in the node to be scheduled can be recorded as , the node to be scheduled The probability of a single-bit gate node being selected can be recorded as For example, when the quantum gate node is selected for the first time in the node to be scheduled, the first node in the node to be scheduled can be calculated according to formula (1). The probability of a single-bit gate node being selected .

[0043] (1) in, Represents the set global factor, The value is between 0 and 1.

[0044] The probability of each two-bit gate node being selected in the nodes to be scheduled is negatively correlated with the number of two-bit gate nodes in the nodes to be scheduled.

[0045] The number of two-bit gate nodes in the nodes to be scheduled can be recorded as For example, when the quantum gate node is first selected in the node to be scheduled, the probability of each two-bit gate node being selected in the node to be scheduled can be calculated according to formula (2): .

[0046] (2) When the quantum gate node is first selected in the node to be scheduled, the more quantum gates there are in the single-bit gate node, the greater the chance of merging with the next node. At the same time, the possibility of selecting a two-bit gate node needs to be given to seek the global optimal solution. Therefore, formulas (1) and (2) are used to calculate the probability of each quantum gate node in the scheduling node being selected.

[0047] It can be seen that when the quantum gate node is initially selected in the node to be scheduled, the embodiment of the present application can relatively accurately determine the probability of each single-bit gate node being selected in the node to be scheduled based on a comprehensive consideration of the number of quantum gates contained in each single-bit gate node in the node to be scheduled and the sum of the number of quantum gates contained in the single-bit gate nodes in the node to be scheduled. When the quantum gate node is initially selected in the node to be scheduled, the embodiment of the present application can relatively accurately determine the probability of each two-bit gate node being selected in the node to be scheduled based on the number of two-bit gate nodes in the node to be scheduled.

[0048] Regarding the implementation method for determining the probability of a quantum gate node being selected in a node to be scheduled, in some embodiments, in response to the last selected quantum gate node in the node to be scheduled being a two-bit gate node, the quantum gate node is selected in the node to be scheduled based on a third probability of each two-bit gate node being selected in the node to be scheduled and a fourth probability of each single-bit gate node being selected in the node to be scheduled; wherein the third probability is determined based on the number of two-bit gate nodes in the node to be scheduled, and the fourth probability is determined based on the number of quantum gates contained in each single-bit gate node in the node to be scheduled and the sum of the number of quantum gates contained in each single-bit gate node in the node to be scheduled.

[0049] Here, the probability of each two-bit gate node being selected in the nodes to be scheduled is negatively correlated with the number of two-bit gate nodes in the nodes to be scheduled.

[0050] For example, the first quantum gate node is performed in the node to be scheduled. Second choice, and When it is greater than 1, the probability of each two-bit gate node being selected in the node to be scheduled can be calculated according to formula (3): .

[0051] (3) The probability of each single-bit gate node being selected in the node to be scheduled is positively correlated with the number of quantum gates contained in the corresponding single-bit gate node, and negatively correlated with the sum of the numbers of quantum gates contained in each single-bit gate node in the node to be scheduled.

[0052] For example, the first quantum gate node is performed in the node to be scheduled. Second choice, and When it is greater than 1, the first node in the node to be scheduled can be calculated according to formula (4). The probability of a single-bit gate node being selected .

[0053] (4) When the last selected quantum gate node in the node to be scheduled is a two-bit gate node, if the two-bit gate node is selected, it can be combined with the previous node for execution. However, in order to find the global optimal solution, it is necessary to give the possibility of selecting a single-bit gate node. Therefore, the probability of each quantum gate node in the scheduling node being selected can be calculated using formulas (3) and (4).

[0054] It can be seen that when the last selected quantum gate node in the node to be scheduled is a two-bit gate node, the embodiment of the present application can more accurately determine the probability of each single-bit gate node in the node to be scheduled being selected based on a comprehensive consideration of the number of quantum gates contained in each single-bit gate node in the node to be scheduled and the sum of the number of quantum gates contained in the single-bit gate nodes in the node to be scheduled. When the last selected quantum gate node in the node to be scheduled is a two-bit gate node, the embodiment of the present application can more accurately determine the probability of each two-bit gate node in the node to be scheduled being selected based on the number of two-bit gate nodes in the node to be scheduled.

[0055] Regarding the implementation method for determining the probability of a quantum gate node being selected in a node to be scheduled, in some embodiments, when the quantum gate node last selected in the node to be scheduled is a single-bit gate node, in response to the existence of at least one candidate single-bit gate node in the node to be scheduled, the node containing the most quantum gates among the at least one candidate single-bit gate node is determined as the node to be selected this time; in response to the absence of a candidate single-bit gate node in the node to be scheduled, a fifth probability for selecting a quantum gate node this time is determined in accordance with the method for determining the probability of a node being selected when the quantum gate node in the node to be scheduled is first selected, and the quantum gate node is selected in the node to be scheduled based on the fifth probability; wherein the candidate single-bit gate node and the last selected single-bit gate node have multiple consecutive quantum gates in the same order.

[0056] In an embodiment of the present application, if a single-bit gate node in the node to be scheduled has multiple consecutive quantum gates in the same order as the single-bit gate node selected last time, the corresponding single-bit gate node is determined as a candidate single-bit gate node. The number of candidate single-bit gate nodes in the node to be scheduled can be one or more.

[0057] The following combination Figure 3 Several cases of candidate single-bit gate nodes are illustrated, referring to Figure 3 , node s0 represents the last selected single-bit gate node, node s1 represents a single-bit gate node in the current node to be scheduled, H, X, Y and Z represent different quantum gates, Q0 and Q1 represent two different quantum bits, H Q0, X Q0, Y Q0 and Z Q0 represent the application of quantum gates H, X, Y and Z at Q0 respectively; H Q1, X Q1, Y Q1 and Z Q1 represent the application of quantum gates H, X, Y and Z at Q1 respectively. Figure 3 It can be seen that for case 1, there are four consecutive quantum gates X, H, Y and Z in the same order in nodes s0 and s1; for case 2, there are four consecutive quantum gates H, Y, Z and H in the same order in nodes s0 and s1; for case 3, there are three consecutive quantum gates Y, Z and H in the same order in nodes s0 and s1.

[0058] For example, if the quantum gate node selected last time in the node to be scheduled is a single-bit gate node, and there is no candidate single-bit gate node for the node to be scheduled, the probability of selecting the quantum gate node this time in the node to be scheduled can be determined by formula (1) and formula (2).

[0059] It can be seen that when the quantum gate node last selected in the node to be scheduled is a single-bit gate node, if there is no candidate single-bit gate node for the node to be scheduled, the embodiment of the present application can more accurately determine the probability of selecting the quantum gate node this time by using the method of determining the probability of the node being selected when the quantum gate node in the node to be scheduled is first selected.

[0060] In an embodiment of the present application, in response to the last selected quantum gate node among the nodes to be scheduled being a single-bit gate node, and there being at least one candidate single-bit gate node for the node to be scheduled, the node containing the most quantum gates among the at least one candidate single-bit gate node may be determined as the node to be selected this time. This is beneficial for preferentially executing quantum gate operations on nodes containing more quantum gates, thereby facilitating improved execution efficiency of quantum circuits.

[0061] In an embodiment of the present application, the nodes in the DAG can be scheduled and sorted by a strategy combining the Kahn algorithm and the heuristic search algorithm. The following is an illustrative example of a node scheduling scheme using the Kahn algorithm and the heuristic search algorithm with reference to the accompanying drawings.

[0062] Reference Figure 4 , the process of obtaining scheduling results may include: Step 401: Determine the top-level quantum gate node in the DAG.

[0063] Here, the top-level quantum gate node represents a quantum gate node with an in-degree of 0.

[0064] Step 402: Assign a probability of being selected to each node in the top-level quantum gate nodes.

[0065] The implementation of step 402 has been described in the aforementioned content. In the embodiment of the present application, by executing step 402, quantum gate nodes that may be combined for execution can be heuristically selected.

[0066] Step 403: Heuristically select a quantum gate node.

[0067] Step 404: Add the selected node to the scheduling result and delete the selected node from the top layer.

[0068] Step 405: Recalculate the in-degree of the nodes in the DAG and update the quantum gate node at the top level.

[0069] Step 406: Determine whether the top-level quantum gate node is empty. If so, execute step 407; if not, return to step 402.

[0070] Here, if the number of quantum gate nodes at the top level is 0, step 407 is executed; if the number of quantum gate nodes at the top level is greater than 0, the process returns to step 402 .

[0071] Step 407: Output the scheduling result.

[0072] When the number of quantum gate nodes at the top level is 0, it means that the scheduling of quantum gate nodes in the quantum circuit has been completed.

[0073] To obtain a more accurate scheduling result, in some embodiments, steps 401 to 407 may be repeated m times to obtain m groups of scheduling results, where m is an integer greater than 1. The m groups of scheduling results may then be evaluated to obtain an evaluation result, and the optimal scheduling result may be selected from the m groups of scheduling results based on the evaluation result.

[0074] In summary, in the embodiments of the present application, a strategy combining the Kahn algorithm and heuristic search can be used to guide the selection of quantum gate nodes in the DAG, which can avoid the scheduling results from falling into local optimality to a certain extent, and can use a probability-assigned approach to heuristically select quantum gate nodes that can be merged for execution.

[0075] In order to optimize the scheduling results, after obtaining the scheduling results, when the adjacent nodes in the scheduling results are all single-bit gate nodes and there are multiple consecutive quantum gates in the same order in the adjacent nodes, the execution strategy of the quantum gates of the adjacent nodes can be determined as: a strategy of merging the execution of the same quantum gates of the adjacent nodes; when the adjacent nodes in the scheduling results are all two-bit gate nodes, the execution strategy of the quantum gates of the adjacent nodes can be determined as: a strategy of merging the execution of the adjacent nodes.

[0076] Here, when the adjacent nodes in the scheduling result are all single-bit gate nodes and there are multiple consecutive quantum gates in the same order in the adjacent nodes, the execution strategy of the quantum gates of the adjacent nodes can be determined as a strategy of merging the execution of the same quantum gates in the adjacent nodes, on the premise of satisfying the execution order of the quantum gates in each single-bit gate node of the adjacent nodes.

[0077] For example, the four consecutive nodes in the scheduling result are node_s0, node_s1, node_m0, and node_m1, where node_m0 and node_m1 are different two-bit gate nodes. The quantum gates in node_s0, arranged in execution order, are HQ0, XQ0, and HQ0; the quantum gates in node_s1, arranged in execution order, are XQ1 and HQ1. When the two bits in node_m0 are Q0 and Q1, node_m0 can be represented as CXQ0Q1; when the two bits in node_m1 are Q2 and Q3, node_m1 is represented as CXQ2Q3.

[0078] After optimizing the execution order of quantum gates of node_s0, node_s1, node_m0, and node_m1, the following execution order can be obtained: 1) H Q0 2) X Q0; X Q1 3) H Q0; H Q1 4) CX Q0Q1; CX Q2Q3.

[0079] It can be seen that the embodiment of the present application proposes a merge execution strategy, which optimizes and analyzes the node scheduling results. It can maximize the merging of identical quantum gate operations without generating additional mov operations. Compared with the solution that does not optimize the scheduling results, it can reduce the number of mov operations that need to be executed for the scheduling results, effectively ensuring the overall fidelity of the quantum circuit execution solution.

[0080] Based on the above records, it can be seen that the technical solution of the embodiment of the present application can effectively optimize the execution efficiency of the quantum circuit. By proposing a strategy combining the Kahn algorithm and heuristic search to guide the selection of quantum gate nodes that can be merged for execution, and then maximizing the merging of identical quantum gate operations through the merge execution strategy, the reasonable scheduling of the execution order of quantum gates is achieved, which greatly reduces the number of quantum gate operations and the number of required mov operations, and effectively improves the reliability and efficiency of quantum circuit execution.

[0081] Figure 5 This is a flow chart of the quantum bit mapping and quantum gate scheduling method in the embodiment of the present application. Figure 5 As shown, the process includes: Step 501: Map logical qubits to physical qubits.

[0082] Step 502: Generate a DAG based on the dependencies of quantum gates in the quantum circuit.

[0083] Step 503: Heuristically select quantum gate nodes in the DAG to obtain a scheduling result.

[0084] Step 504: Determine the merge execution strategy for adjacent nodes.

[0085] The implementation of steps 501 to 504 has been described in the aforementioned content and will not be repeated here.

[0086] Step 505: Add mov operations and move back (bac) operations according to the quantum gate execution order.

[0087] In this embodiment, before executing a quantum gate operation, the control area is checked for qubits unrelated to the quantum gate being operated. If so, a bac operation is performed to move them back to the storage area. A mov operation is performed to move the qubit corresponding to the quantum gate to an unoccupied position in the control area. For a two-bit gate, the corresponding qubits must be located adjacent to each other in the control area.

[0088] An exemplary quantum gate execution sequence is: H Q0, X Q1, and CX Q0Q1. For this quantum gate execution sequence, step 505 can be performed. For this quantum gate execution sequence, the operations to be performed in this execution sequence are: movQ0, execute quantum gate H on Q0, bacQ0, movQ1, execute quantum gate X on Q1, movQ0, and execute quantum gate operation on the two-bit gate node containing Q0 and Q1.

[0089] Step 506: Evaluate the scheduling result using the number of mov operands and the number of optimized quantum gates as indicators.

[0090] Here, the number of mov operations added in step 505 and the number of quantum gates optimized in step 504 can be determined as evaluation indicators. In practical applications, the above m groups of scheduling results can be evaluated based on the evaluation indicators.

[0091] Step 507: Select the optimal solution of multiple groups of scheduling results through a non-dominated sorting algorithm.

[0092] Here, based on the evaluation results of the m groups of scheduling results, the m groups of scheduling results can be non-dominated sorted. For example, the optimal solution of the m groups of scheduling results can be determined from the Pareto front with the mov operand as the first priority. Of course, in other embodiments, other optimization algorithms can also be used to determine the optimal solution of the m groups of scheduling results.

[0093] In summary, to achieve measurement and control of the RAAs quantum processor, the embodiments of the present application propose a quantum bit mapping and quantum gate scheduling method for a reconfigurable neutral atom array. This embodiment of the present application can provide a solution for the execution of quantum circuits in the RAAs quantum processor, effectively improving the efficiency and fidelity of quantum circuit execution and possessing high practical value. The technical solution of the embodiments of the present application can be used to achieve measurement and control of the RAAs quantum processor, and the hardware conditions for the RAAs quantum processor are already in place, making it relatively easy to obtain measurement and control information for the quantum processor.

[0094] Those skilled in the art will understand that in the above-mentioned method of the specific implementation method, the writing order of each step does not mean a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic.

[0095] Figure 6 This is a schematic diagram of the structure of the quantum gate scheduling device according to an embodiment of the present application. Figure 6 As shown, the device includes: A first processing module 601 is configured to generate a DAG according to the dependency relationship of quantum gates in a quantum circuit, wherein nodes of the DAG are quantum gate nodes; The second processing module 602 is configured to heuristically select quantum gate nodes in the DAG according to the probability of the nodes of the DAG being selected, and obtain a scheduling result, where the scheduling result includes the quantum gate nodes arranged in a selection order.

[0096] In some embodiments, the second processing module 602 is specifically configured to determine a quantum gate node with an in-degree of 0 in the DAG as a node to be scheduled; and heuristically select a quantum gate node from the nodes to be scheduled based on a probability of each node being selected, to obtain a scheduling result.

[0097] In some embodiments, the second processing module 602 is further configured to, after each time the quantum gate node is selected from the nodes to be scheduled, add the selected quantum gate node to the scheduling result, delete the selected quantum gate node from the quantum gate nodes with an in-degree of 0, re-determine the nodes to be scheduled, and repeat the step of selecting quantum gate nodes from the nodes to be scheduled until the number of nodes to be scheduled is 0.

[0098] In some embodiments, the first processing module 601 is further configured to, after generating a DAG according to the dependencies of the quantum gates in the quantum circuit, select the quantum gate node in the node to be scheduled based on a first probability of selection of each single-bit gate node in the node to be scheduled and a second probability of selection of each two-bit gate node in the node to be scheduled when performing the initial selection of the quantum gate node in the node to be scheduled; wherein the first probability is determined based on the number of quantum gates included in each single-bit gate node in the node to be scheduled and the sum of the number of quantum gates included in each single-bit gate node in the node to be scheduled, and the second probability is determined based on the number of two-bit gate nodes in the node to be scheduled.

[0099] In some embodiments, the first processing module 601 is further configured to, after generating a DAG based on the dependencies of quantum gates in the quantum circuit, select the quantum gate node in the node to be scheduled based on a third probability of selection of each two-bit gate node in the node to be scheduled and a fourth probability of selection of each single-bit gate node in the node to be scheduled, if the last selected quantum gate node in the node to be scheduled is a two-bit gate node; wherein the third probability is determined based on the number of two-bit gate nodes in the node to be scheduled, and the fourth probability is determined based on the number of quantum gates included in each single-bit gate node in the node to be scheduled and the sum of the number of quantum gates included in each single-bit gate node in the node to be scheduled.

[0100] In some embodiments, the first processing module 601 is further configured to, after generating a DAG based on the dependencies of quantum gates in the quantum circuit, determine, in response to the existence of at least one candidate single-bit gate node for the node to be scheduled, a node containing the most quantum gates among the at least one candidate single-bit gate node as the node to be selected this time, if the quantum gate node last selected in the node to be scheduled is a single-bit gate node; and, in response to the absence of a candidate single-bit gate node for the node to be scheduled, determine a fifth probability for selecting a quantum gate node this time in accordance with the method of determining the probability of a node being selected when the quantum gate node in the node to be scheduled is first selected, and select the quantum gate node in the node to be scheduled based on the fifth probability; wherein the candidate single-bit gate node and the last selected single-bit gate node have multiple consecutive quantum gates in the same order.

[0101] In some embodiments, the second processing module 602 is further configured to, after obtaining the scheduling result, determine, when all adjacent nodes in the scheduling result are single-bit gate nodes and the adjacent nodes have multiple consecutive quantum gates in the same order, an execution strategy for the quantum gates of the adjacent nodes as a strategy of merging and executing the same quantum gates of the adjacent nodes; and when all adjacent nodes in the scheduling result are two-bit gate nodes, determine, when the adjacent nodes are two-bit gate nodes, an execution strategy for the quantum gates of the adjacent nodes as a strategy of merging and executing the adjacent nodes.

[0102] In some embodiments, the first processing module 601 is further configured to, before generating a DAG based on the dependency relationship of the quantum gates in the quantum circuit, sort the logical quantum bits in the quantum circuit in descending order of the number of quantum gates applied to the logical quantum bits; and, based on the sorting results of the logical quantum bits, sequentially map the logical quantum bits to a plurality of physical quantum bits arranged in descending order of fidelity.

[0103] In some embodiments, the quantum gate nodes in the DAG include single-bit gate nodes, each of which includes a plurality of consecutive single-bit gates acting on the same quantum bit.

[0104] In practical applications, the first processing module 601 and the second processing module 602 can be implemented based on a processor.

[0105] It should be noted that the description of the above device embodiment is similar to the description of the above method embodiment and has similar beneficial effects as the method embodiment. For technical details not disclosed in the device embodiment of this application, please refer to the description of the method embodiment of this application for understanding.

[0106] It should be noted that in the embodiments of the present application, if the above-mentioned method is implemented in the form of a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiments of the present application, or the part that contributes to the existing technology, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a number of instructions for enabling a computer device (which can be a terminal, server, etc.) to execute all or part of the methods described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program code, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a magnetic disk, or an optical disk. In this way, the embodiments of the present application are not limited to any specific combination of hardware and software.

[0107] Correspondingly, an embodiment of the present application further provides a computer program product, which includes computer-executable instructions, and the computer-executable instructions are used to implement any one of the quantum gate scheduling methods provided in the embodiments of the present application.

[0108] Accordingly, an embodiment of the present application further provides a computer storage medium, on which computer executable instructions are stored. The computer executable instructions are used to implement any one of the quantum gate scheduling methods provided in the above embodiments.

[0109] An embodiment of the present application also provides an electronic device. Figure 7 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application is shown in FIG. Figure 7 As shown, the electronic device 70 may include: Memory 701, used to store executable instructions; The processor 702 is configured to implement any one of the aforementioned quantum gate scheduling methods when executing the executable instructions stored in the memory 701.

[0110] The processor 702 may be at least one of an ASIC, a DSP, a DSPD, a PLD, an FPGA, a CPU, a controller, a microcontroller, and a microprocessor.

[0111] The computer-readable storage medium and memory 701 may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic random access memory (FRAM), a flash memory, a magnetic surface mount storage device, an optical disc, or a compact disc read-only memory (CD-ROM); or various terminals including one or any combination of the above memories, such as a mobile phone, a computer, a tablet device, a personal digital assistant, etc.

[0112] In some embodiments, the functions or modules included in the device provided in the embodiments of the present application can be used to execute the method described in the above method embodiments. The specific implementation can refer to the description of the above method embodiments. For the sake of brevity, it will not be repeated here.

[0113] The above description of the various embodiments tends to emphasize the differences between the various embodiments. The same or similar aspects can be referenced with each other and will not be repeated herein for the sake of brevity.

[0114] The methods disclosed in the various method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0115] The features disclosed in the various product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0116] The features disclosed in the various method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0117] Through the description of the above embodiments, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus the necessary general hardware platform. Of course, they can also be implemented by hardware, but in many cases the former is a more preferred embodiment. Based on this understanding, the technical solution of this application, or the part that contributes to the existing technology, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for enabling a terminal (which can be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in each embodiment of this application.

[0118] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the scope of protection of the purpose of this application, which all fall within the protection of this application.

Claims

1. A quantum gate scheduling method, characterized in that: The method comprises: Generate a directed acyclic graph (DAG) based on the dependency relationship of quantum gates in the quantum circuit, where the nodes of the DAG are quantum gate nodes; According to the probability of the nodes of the DAG being selected, quantum gate nodes are heuristically selected in the DAG to obtain a scheduling result, where the scheduling result includes the quantum gate nodes arranged in a selection order.

2. The quantum gate scheduling method according to claim 1, characterized in that: The heuristically selecting a quantum gate node in the DAG according to the probability of the node being selected to obtain a scheduling result includes: Determine a quantum gate node with an in-degree of 0 in the DAG as a node to be scheduled; According to the probability of each node being selected in the nodes to be scheduled, a quantum gate node is heuristically selected in the nodes to be scheduled to obtain a scheduling result.

3. The quantum gate scheduling method according to claim 2, characterized in that: After selecting the quantum gate node from the nodes to be scheduled each time, the method further includes: The selected quantum gate node is added to the scheduling result, and the selected quantum gate node is deleted from the quantum gate node with in-degree 0, the node to be scheduled is re-determined, and the step of selecting the quantum gate node from the node to be scheduled is repeated until the number of nodes to be scheduled is 0.

4. The quantum gate scheduling method according to claim 2 or 3, characterized in that: After generating a DAG according to the dependency relationship of quantum gates in the quantum circuit, when performing the first selection of the quantum gate node in the node to be scheduled, the method further includes: The quantum gate node is selected in the node to be scheduled according to a first probability of each single-bit gate node being selected in the node to be scheduled and a second probability of each two-bit gate node being selected in the node to be scheduled; wherein the first probability is determined based on the number of quantum gates included in each single-bit gate node in the node to be scheduled and the sum of the number of quantum gates included in each single-bit gate node in the node to be scheduled, and the second probability is determined based on the number of two-bit gate nodes in the node to be scheduled.

5. The quantum gate scheduling method according to claim 2 or 3, characterized in that: After generating a DAG according to the dependency relationship of quantum gates in the quantum circuit, when the quantum gate node last selected in the to-be-scheduled node is a two-bit gate node, the method further includes: The quantum gate node is selected in the node to be scheduled based on a third probability that each two-bit gate node in the node to be scheduled is selected and a fourth probability that each single-bit gate node in the node to be scheduled is selected; wherein the third probability is determined based on the number of two-bit gate nodes in the node to be scheduled, and the fourth probability is determined based on the number of quantum gates included in each single-bit gate node in the node to be scheduled and the sum of the numbers of quantum gates included in each single-bit gate node in the node to be scheduled.

6. The quantum gate scheduling method according to claim 2 or 3, characterized in that: After generating a DAG according to the dependency relationship of quantum gates in the quantum circuit, when the quantum gate node last selected among the nodes to be scheduled is a single-bit gate node, the method further includes: In response to the existence of at least one candidate single-bit gate node for the node to be scheduled, determining the node containing the most quantum gates among the at least one candidate single-bit gate node as the node to be selected this time; in response to the absence of a candidate single-bit gate node for the node to be scheduled, determining a fifth probability for selecting a quantum gate node this time in accordance with a method for determining a probability of a node being selected when the quantum gate node in the node to be scheduled is first selected, and selecting the quantum gate node in the node to be scheduled based on the fifth probability; wherein the candidate single-bit gate node and the single-bit gate node selected last time have multiple consecutive quantum gates in the same order.

7. The quantum gate scheduling method according to claim 1, characterized in that: After obtaining the scheduling result, the method further includes: when the adjacent nodes in the scheduling result are all single-bit gate nodes and the adjacent nodes have multiple consecutive quantum gates in the same order, determining the execution strategy of the quantum gates of the adjacent nodes as a strategy of merging the same quantum gates in the adjacent nodes for execution; In the case that the adjacent nodes in the scheduling result are all two-bit gate nodes, the execution strategy of the quantum gates of the adjacent nodes is determined as: a strategy of merging and executing the adjacent nodes.

8. The quantum gate scheduling method according to claim 1, characterized in that: Before generating the DAG according to the dependency relationship of the quantum gates in the quantum circuit, the method further includes: Sorting the logical qubits in the quantum circuit in descending order of the number of quantum gates applied to the logical qubits; According to the sorting results of the logical qubits, the logical qubits are sequentially mapped to a plurality of physical qubits arranged in descending order of fidelity.

9. The quantum gate scheduling method according to claim 1, characterized in that: The quantum gate nodes in the DAG include single-bit gate nodes, and the single-bit gate nodes include a plurality of consecutive single-bit gates acting on the same quantum bit.

10. A quantum gate scheduling device, characterized in that: The device comprises: A first processing module is configured to generate a directed acyclic graph (DAG) according to the dependency relationship of quantum gates in the quantum circuit, wherein the nodes of the DAG are quantum gate nodes; The second processing module is configured to heuristically select quantum gate nodes in the DAG according to the probability of the nodes of the DAG being selected, and obtain a scheduling result, wherein the scheduling result includes the quantum gate nodes arranged in a selection order.

11. An electronic device, characterized in that: The electronic device comprises a processor and a memory for storing a computer program that can be run on the processor; wherein, The processor is configured to run the computer program to execute the quantum gate scheduling method according to any one of claims 1 to 9.

12. A computer storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the quantum gate scheduling method according to any one of claims 1 to 9 is implemented.

13. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the computer program implements the quantum gate scheduling method according to any one of claims 1 to 9.

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