Three-dimensional stacked structure and manufacturing method thereof

Abstract

The invention provides a three-dimensional stacked structure and a manufacturing method thereof, and the method employs a first interconnection layer and a second interconnection layer which are provided with organic dielectric layers as bonding layers between stacked units, and carries out the organic hybrid bonding. Gaps between the stacking units of the three-dimensional stacking structure and the key size and spacing of the conductive structures in the conductive circuits of the interconnection layer are small, so that denser IO interconnection and stacking of more layers can be achieved, heat conduction is conducted between the stacking units through interconnection of the conductive circuits, and the heat dissipation effect is better.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging, and in particular to a three-dimensional stacking structure using organic hybrid bonding and a manufacturing method thereof. Background Art

[0002] Advanced packaging uses heterogeneous integration technology to stack chips with different functions (such as logic, storage, and sensors) in three dimensions or interconnect them with high density in two dimensions, achieving higher performance and smaller size. Compared to traditional packaging, advanced packaging uses more complex processes and designs to improve chip performance, integration, and functionality, meeting the needs of high-end electronic devices.

[0003] In the implementation of advanced packaging three-dimensional (3D) stacking structures, existing methods have a rigorous and precise process flow. First, the two wafers are firmly bonded together through copper-copper hybrid bonding technology. The interaction between the copper atoms enables the two wafers to be reliably connected, laying the foundation for subsequent stacking. Then, with the help of micro-bumps (UBMP) using thermal compression bonding (TCB) thermal bonding technology, multiple chip dies are welded together to form a C2W (Chip to Wafer) stacking structure. Finally, epoxy molding compound (EMC) is used for plastic encapsulation to protect the entire stacking structure, enabling it to work stably in various complex environments.

[0004] Figure 1 This is a schematic diagram of an advanced packaging three-dimensional stacking structure. Figure 2 yes Figure 1 The enlarged schematic diagram of area A is shown in the figure. Figure 1 and Figure 2 As shown, the three-dimensional stacking structure includes a plurality of stacked stacking units 100 , two adjacent stacking units 100 are bonded together via micro bumps 110 , and a molding compound 120 covers the stacking units 100 and is filled between the two adjacent stacking units 100 .

[0005] In this advanced packaging three-dimensional stacking structure, the physical size and arrangement rules of the microbumps 110 limit the integration and size of the stacking structure, making it impossible to achieve denser IO interconnection and stacking of more layers; specifically, the critical dimension CD of the microbump 110 needs to be greater than 10 microns, the spacing P between two adjacent microbumps 110 needs to be greater than 20 microns, and the distance H between two adjacent stacking units 100 needs to be greater than 16 microns, which makes it impossible for the stacking structure to achieve denser IO interconnection and stacking of more layers.

[0006] A molding compound 120 needs to be used to fill between two adjacent stacking units 100. The thermal conductivity of the molding compound is low. When the number of stacked layers increases, the "thermal barrier layer" formed by the molding compound will hinder the vertical conduction of heat, limiting the heat dissipation of the three-dimensional stacking structure, resulting in thermal stress concentration in the three-dimensional stacking structure and reduced device reliability.

[0007] Therefore, an improved advanced packaging three-dimensional stacking structure and a manufacturing method thereof are needed to avoid the restriction of the micro-bumps on the advanced packaging three-dimensional stacking structure and to improve the heat dissipation performance of the advanced packaging three-dimensional stacking structure. Summary of the Invention

[0008] The technical problem to be solved by the present invention is to provide a three-dimensional stacked structure and a manufacturing method thereof, which can have a higher degree of integration and better heat dissipation performance.

[0009] In order to solve the above problems, the present invention provides a method for manufacturing a three-dimensional stacked structure, comprising the following steps: providing a stacking unit, wherein the stacking unit includes at least one chip, and the stacking unit includes a first surface and a second surface arranged opposite to each other; forming a first interconnection layer on the first surface of the stacking unit, wherein the first interconnection layer includes a first organic medium layer and a first conductive circuit arranged in the first organic medium layer; forming a second interconnection layer on the second surface of the stacking unit, wherein the second interconnection layer includes a second organic medium layer and a second conductive circuit arranged in the second organic medium layer; stacking a plurality of the stacking units along a first direction and bonding them together, wherein the first interconnection layer on the first surface of one of two adjacent stacking units is bonded to the second interconnection layer on the second surface of the other stacking unit.

[0010] In a specific embodiment, in the step of providing a stacking unit, the stacking unit includes an initial unit, the initial unit includes at least one wafer, and the wafer includes a plurality of the chips; the step of forming a first interconnection layer on the first surface of the stacking unit includes: forming the first interconnection layer on the first surface of the initial unit; the step of forming a second interconnection layer on the second surface of the stacking unit includes: forming the second interconnection layer on the second surface of the initial unit; before the step of stacking the plurality of stacking units along the first direction and bonding them together, the following step is also included: cutting the initial unit to form a plurality of independent stacking units.

[0011] In a specific embodiment, the initial unit includes a plurality of wafers stacked along the first direction, and two adjacent wafers are connected via an inorganic hybrid bonding layer.

[0012] In a specific embodiment, the chip includes a through-silicon via, and the step of forming a first interconnection layer on the first surface of the stacking unit includes: exposing one end surface of the through-silicon via to the first surface; forming the first interconnection layer, wherein the first conductive line is connected to the through-silicon via; the step of forming a second interconnection layer on the second surface of the stacking unit includes: exposing the other end surface of the through-silicon via to the second surface; forming the second interconnection layer, wherein the second conductive line is connected to the through-silicon via.

[0013] In a specific embodiment, the stacking unit includes a plurality of chips stacked along the first direction, each chip includes a through-silicon via, and the through-silicon vias of all the chips are connected in sequence, and in the step of forming a first interconnection layer on the first surface of the stacking unit, the end faces of the through-silicon vias of the chips adjacent to the first surface of the stacking unit are exposed to the first surface; in the step of forming a second interconnection layer on the second surface of the stacking unit, the end faces of the through-silicon vias of the chips adjacent to the second surface of the stacking unit are exposed to the second surface.

[0014] In a specific embodiment, the method of exposing one end face of the through silicon via to the first surface and the other end face of the through silicon via to the second surface includes: using a back side through silicon via exposure process to expose the end face of the through silicon via to the first surface and to expose the other end face of the through silicon via to the second surface.

[0015] In a specific embodiment, the step of forming a first interconnect layer on the first surface of the stacking unit includes: forming a first organic dielectric layer on the first surface of the stacking unit; forming a first through hole in the first organic dielectric layer, wherein the first through hole exposes an end surface of the silicon via; and forming the first conductive circuit in the first through hole, wherein the first conductive circuit is connected to the silicon via.

[0016] In a specific embodiment, the step of forming the first organic dielectric layer on the first surface of the stacking unit includes: forming the first organic dielectric layer on the first surface of the stacking unit by a spin coating process.

[0017] In a specific embodiment, the step of forming the first through hole in the first organic dielectric layer includes: exposing and developing the first organic dielectric layer using a photolithography mask to form the first through hole.

[0018] In a specific embodiment, the step of forming the first conductive circuit in the first through hole includes: forming a first barrier layer covering the inner wall of the first through hole in the first through hole; filling the first through hole with a conductive material to form a first initial structure, wherein the first initial structure fills the first through hole and covers the surface of the first organic dielectric layer; and thinning the first initial structure to form the first conductive circuit.

[0019] In a specific embodiment, the step of forming the first conductive circuit in the first through hole further includes: thinning the first organic dielectric layer so that a surface of the first conductive circuit protrudes from a surface of the first organic dielectric layer.

[0020] In one specific embodiment, the step of forming a second interconnect layer on the second surface of the stacking unit includes: forming a second organic dielectric layer on the second surface of the stacking unit; forming a second through hole in the second organic dielectric layer, wherein the second through hole exposes the other end surface of the silicon via; and forming a second conductive circuit in the second through hole, wherein the second conductive circuit is connected to the silicon via.

[0021] In a specific embodiment, the step of forming the second organic dielectric layer on the second surface of the stacking unit includes: forming the second organic dielectric layer on the second surface of the stacking unit by a spin coating process.

[0022] In a specific embodiment, the step of forming the second through hole in the second organic dielectric layer includes: exposing and developing the second organic dielectric layer using a photolithography mask to form the second through hole.

[0023] In a specific embodiment, the step of forming the second conductive circuit in the second through hole includes: forming a second barrier layer covering the inner wall of the second through hole in the second through hole; filling the second through hole with a conductive material to form a second initial structure, wherein the second initial structure fills the second through hole and covers the surface of the second organic dielectric layer; and thinning the second initial structure to form the second conductive circuit.

[0024] In one embodiment, the step of forming the second conductive circuit in the second through hole further includes: thinning the second organic dielectric layer so that a surface of the second conductive circuit protrudes from a surface of the second organic dielectric layer.

[0025] In a specific embodiment, the steps of stacking a plurality of the stacking units along a first direction and bonding them together include: using plasma to activate the first interconnection layer and the second interconnection layer of the stacking unit that require a bonding process; performing a bonding process to bond the first interconnection layer of one of the two adjacent stacking units to the second interconnection layer of the other stacking unit.

[0026] In a specific embodiment, the step of performing the bonding process further includes: low temperature annealing.

[0027] In a specific embodiment, before the step of stacking and bonding a plurality of the stacking units along the first direction, the following step is also included: providing a substrate, and forming a third interconnection layer on the surface of the substrate where the stacking units need to be set, the third interconnection layer includes a third organic medium layer and a third conductive circuit arranged in the third organic medium layer, and the third conductive circuit is interconnected with the conductive structure in the substrate; the step of stacking and bonding a plurality of the stacking units along the first direction further includes: bonding the third interconnection layer to the second interconnection layer on the second surface of the bottommost stacking unit.

[0028] In a specific embodiment, in the step of providing a stacking unit, a fourth interconnection layer is formed on the second surface of the bottom stacking unit, and the fourth interconnection layer includes a first inorganic dielectric layer and a fourth conductive line arranged in the first inorganic dielectric layer; in the step of forming a second interconnection layer on the second surface of the stacking unit, the second interconnection layer is not formed on the second surface of the bottom stacking unit.

[0029] In a specific embodiment, in the step of forming the first interconnection layer on the first surface of the stacking unit, the first interconnection layer is not formed on the first surface of the topmost stacking unit, and the first surface of the topmost stacking unit is the substrate surface of the stacking unit.

[0030] In a specific embodiment, after the step of stacking and bonding the plurality of stacking units along the first direction, the method further includes: plastic packaging to form a plastic packaging body, wherein the plastic packaging body covers the stacking units.

[0031] A specific embodiment of the present invention also provides a three-dimensional stacked structure, comprising: a plurality of stacking units stacked along a first direction, the stacking unit comprising at least one chip, the stacking unit comprising a first surface and a second surface arranged opposite to each other; a bonding structure layer comprising a first interconnection layer and a second interconnection layer, the first interconnection layer being arranged on the first surface of one of the two adjacent stacking units, and the first interconnection layer comprising a first organic medium layer and a first conductive circuit arranged in the first organic medium layer, the second interconnection layer being arranged on the second surface of the other of the two adjacent stacking units, and the second interconnection layer comprising a second organic medium layer and a second conductive circuit arranged in the second organic medium layer, the first organic medium layer being connected to the second organic medium layer, and the first conductive circuit being connected to the second conductive circuit.

[0032] In a specific embodiment, the chip includes a through-silicon via, the first conductive circuit is connected to one end of the through-silicon via, and the second conductive circuit is connected to the other end of the through-silicon via.

[0033] In a specific embodiment, the stacking unit includes a plurality of chips stacked along the first direction, each chip includes a through-silicon via, and the through-silicon vias of all the chips are connected in sequence, the end faces of the through-silicon vias of the chips adjacent to the first surface of the stacking unit are connected to the first conductive circuit, and the end faces of the through-silicon vias of the chips adjacent to the second surface of the stacking unit are connected to the second conductive circuit.

[0034] In a specific embodiment, the stacking unit includes a plurality of chips stacked along the first direction, and two adjacent chips are connected via an inorganic hybrid bonding layer.

[0035] In a specific embodiment, the three-dimensional stacked structure further includes: a substrate; a third interconnection layer, arranged on the surface of the substrate, the third interconnection layer including a third organic dielectric layer and a third conductive circuit arranged in the third organic dielectric layer, and the third conductive circuit is interconnected with the conductive structure in the substrate; wherein the third organic dielectric layer is connected to the second organic dielectric layer on the second surface of the bottom stacking unit, and the third conductive circuit is connected to the second conductive circuit on the second surface of the bottom stacking unit.

[0036] In a specific embodiment, the second surface of the bottom stacking unit does not form the second interconnection layer, and the second surface of the bottom stacking unit is formed with a fourth interconnection layer, and the fourth interconnection layer includes a first inorganic dielectric layer and a fourth conductive line arranged in the first inorganic dielectric layer.

[0037] In a specific embodiment, the first surface of the stacking unit at the top layer is not formed with the first interconnection layer, and the first surface of the stacking unit at the top layer is the substrate surface of the stacking unit.

[0038] In a specific embodiment, the three-dimensional stacking structure further includes a plastic packaging body, and the plastic packaging body covers the stacking unit.

[0039] The manufacturing method of the three-dimensional stacking structure provided by the present invention adopts a first interconnection layer and a second interconnection layer having an organic dielectric layer as bonding layers between stacking units to perform organic hybrid bonding.

[0040] Compared to Figure 1 and Figure 2As for the bonding using micro-bumps shown, the distance between the stacking units of the three-dimensional stacking structure formed by the manufacturing method of the present invention, the key dimensions and spacing of the conductive structures in the conductive circuits of the interconnection layers are all small, so denser IO interconnections and more layers of stacking can be achieved. For example, the total height of chips with the same number of layers and the same specifications can be reduced by 15%, and the IO density is at least doubled. At the same time, organic hybrid bonding is used between the stacking units, and no plastic packaging material is required. The heat is conducted through the interconnection of the conductive circuits, and the heat dissipation effect is better. Through simulation comparison, the thermal resistance (Rjc) of the three-dimensional stacking structure using organic hybrid bonding is reduced by 50% compared with the three-dimensional stacking structure using micro-bumps.

[0041] Compared with the technology of using inorganic hybrid bonding between stacking units, the technology of using organic hybrid bonding between stacking units of the present invention has the following advantages:

[0042] The bonding interface of inorganic hybrid bonding requires multiple etchings, and photoresist protection glue needs to be applied according to the proportion during etching to form a through hole (Via). However, the bonding interface of the organic hybrid bonding provided by the present invention only requires photolithography to form a through hole (Via).

[0043] The organic dielectric layer used in organic hybrid bonding can directly replace the photoresist protective glue and can be directly sputtered and electroplated without removal, while inorganic hybrid bonding requires the removal of the photoresist protective glue.

[0044] In multi-layer hybrid bonding stacks, inorganic hybrid bonding requires multiple depositions to fill the gaps between adjacent chips (gapfill CVD) and grinding, while organic hybrid bonding only requires one final filling with plastic encapsulation material, reducing many process steps. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] To more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly describes the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0046] Figure 1 It is a schematic diagram of a three-dimensional stacking structure of an advanced package;

[0047] Figure 2 yes Figure 1 A magnified schematic diagram of area A in the middle;

[0048] Figure 3 1 is a schematic diagram of the steps of a method for manufacturing a three-dimensional stacked structure provided by a specific embodiment of the present invention;

[0049] Figure 4is a schematic diagram of a stacking unit provided in a method for manufacturing a three-dimensional stacking structure provided in one embodiment of the present invention;

[0050] Figure 5 Schematic diagram of exposing through-silicon vias in a method for manufacturing a three-dimensional stacked structure provided by one embodiment of the present invention;

[0051] Figure 6 is a schematic diagram of forming a first organic dielectric layer in a method for manufacturing a three-dimensional stacked structure provided by a specific embodiment of the present invention;

[0052] Figure 7 is a schematic diagram of forming a first through hole in the first organic dielectric layer in a method for manufacturing a three-dimensional stacked structure provided by one embodiment of the present invention;

[0053] Figure 8 is a schematic diagram of forming a first barrier layer covering the inner wall of the first through hole in the method for manufacturing a three-dimensional stacked structure provided by one embodiment of the present invention;

[0054] Figure 9 Schematic diagram of filling a conductive material in a method for manufacturing a three-dimensional stacked structure provided by one embodiment of the present invention;

[0055] Figure 10 is a schematic diagram of thinning the first initial structure in the method for manufacturing a three-dimensional stacked structure provided by a specific embodiment of the present invention;

[0056] Figure 11 is a schematic diagram of thinning the first organic dielectric layer in a method for manufacturing a three-dimensional stacked structure provided in one embodiment of the present invention;

[0057] Figure 12 1 is a schematic diagram of another exposed through-silicon via in a method for manufacturing a three-dimensional stacked structure provided by one embodiment of the present invention;

[0058] Figure 13 is a schematic diagram of forming a second interconnection layer in a method for manufacturing a three-dimensional stacked structure provided by a specific embodiment of the present invention;

[0059] Figure 14 This is a schematic diagram of a method for manufacturing a three-dimensional stacked structure provided by one embodiment of the present invention after cutting an initial unit;

[0060] Figure 15 This is a schematic diagram of a method for manufacturing a three-dimensional stacked structure provided by one embodiment of the present invention after bonding multiple stacking units;

[0061] Figure 16 This is a schematic diagram of a method for manufacturing a three-dimensional stacked structure after plastic packaging according to a specific embodiment of the present invention;

[0062] Figure 17 This is a schematic diagram after cutting in a method for manufacturing a three-dimensional stacked structure provided by one embodiment of the present invention;

[0063] Figure 18 is a schematic diagram of a three-dimensional stacking structure provided by a specific embodiment of the present invention;

[0064] Figure 19 is a schematic diagram of a stacking unit provided in a method for manufacturing a three-dimensional stacking structure provided in another specific embodiment of the present invention;

[0065] Figure 20 is a schematic diagram of forming a first interconnection layer and forming a second interconnection layer in a method for manufacturing a three-dimensional stacked structure provided by another specific embodiment of the present invention;

[0066] Figure 21 This is a schematic diagram of a method for manufacturing a three-dimensional stacked structure provided by another embodiment of the present invention after bonding multiple stacking units.

[0067] Figure 22 This is another schematic diagram of a method for manufacturing a three-dimensional stacked structure provided by another specific embodiment of the present invention after bonding multiple stacking units. DETAILED DESCRIPTION

[0068] The specific embodiments of the three-dimensional stacking structure and the manufacturing method thereof provided by the present invention are described in detail below with reference to the accompanying drawings.

[0069] Figure 3 This is a schematic diagram of the steps of a method for manufacturing a three-dimensional stacked structure provided by a specific embodiment of the present invention. Figure 3 The manufacturing method of the three-dimensional stacking structure includes the following steps: step S30, providing a stacking unit, wherein the stacking unit includes at least one chip, and the stacking unit includes a first surface and a second surface arranged opposite to each other; step S31, forming a first interconnection layer on the first surface of the stacking unit, wherein the first interconnection layer includes a first organic medium layer and a first conductive circuit arranged in the first organic medium layer; step S32, forming a second interconnection layer on the second surface of the stacking unit, wherein the second interconnection layer includes a second organic medium layer and a second conductive circuit arranged in the second organic medium layer; step S33, stacking a plurality of the stacking units along a first direction and bonding them together, wherein the first interconnection layer on the first surface of one of the two adjacent stacking units is bonded to the second interconnection layer on the second surface of the other stacking unit.

[0070] The manufacturing method of the three-dimensional stacked structure provided by the specific embodiment of the present invention uses the first interconnection layer and the second interconnection layer having the organic dielectric layer as bonding layers between the stacking units to perform organic hybrid bonding.

[0071] The following combination Figures 4 to 17 A method for manufacturing a three-dimensional stacked structure provided by a specific embodiment of the present invention is described in detail.

[0072] Figure 4 This is a schematic diagram of a stacking unit 400 provided in a method for manufacturing a three-dimensional stacked structure according to a specific embodiment of the present invention. Figure 4 In step S30 , a stacking unit 400 is provided. The stacking unit 400 includes at least one chip 410 (a dotted line is used to indicate a boundary between two chips 410 ). The stacking unit 400 includes a first surface 420 and a second surface 430 that are oppositely disposed.

[0073] In some specific embodiments, the stacking unit 400 includes an initial unit, the initial unit includes at least one wafer 440, the wafer 440 includes a plurality of the chips 410, the first surface of the initial unit serves as the first surface 420 of the stacking unit 400, and the second surface of the initial unit serves as the second surface 430 of the stacking unit 400. In this specific embodiment, Figure 4 As shown, the initial unit includes two wafers 440 stacked along a first direction D1, and two adjacent wafers 440 are connected by an inorganic hybrid bonding layer 450. Each wafer 440 includes a plurality of chips 410. Figure 4 In each of the wafers 440, two chips 410 are schematically shown, and the two chips 410 are arranged in parallel. In another specific embodiment, the initial unit includes four wafers 440 stacked along the first direction D1, and two adjacent wafers 440 are connected by an inorganic hybrid bonding layer 450, which can be referred to. Figure 18 .

[0074] The connection between two adjacent wafers 440 via the inorganic hybrid bonding layer 450 includes: the connection between the two adjacent wafers 440 via an inorganic dielectric layer and a conductive circuit disposed in the inorganic dielectric layer. In some specific embodiments, the chip 410 includes a through-silicon via 411, one end of which is connected to the conductive circuit and the other end extends into the substrate of the chip 410. In some specific embodiments, neither the first surface 420 nor the second surface 430 of the stacking unit 400 exposes the end surface of the through-silicon via 411 facing away from the inorganic hybrid bonding interface.

[0075] See also Figure 10In step S31, a first interconnect layer 500 is formed on the first surface 420 of the stacked unit 400. The first interconnect layer 500 includes a first organic dielectric layer and a first conductive line disposed in the first organic dielectric layer. Specifically, in this embodiment, the first interconnect layer 500 is formed on the first surface of the initial unit.

[0076] In some specific embodiments, the chip 410 includes a through silicon via 411, and the step of forming the first interconnect layer on the first surface 420 of the stacking unit 400 includes:

[0077] like Figure 5 , which is a schematic diagram of exposing TSVs 411 in a method for manufacturing a three-dimensional stacked structure according to one embodiment of the present invention, such that the end surfaces of the TSVs 411 are exposed to the first surface 420. Specifically, the stacking unit 400 is bonded to a first supporting plate 590, with the second surface 430 of the stacking unit 400 connected to the first supporting plate 590 and the first surface 420 facing away from the first supporting plate 590. The process of exposing the end surfaces of the TSVs 411 is performed from the first surface 420 of the stacking unit 400. In one embodiment, the stacking unit 400 includes a plurality of chips 410 stacked along the first direction D1, each chip 410 including a TSV 411, and the TSVs 411 of all chips 410 are sequentially connected. In the step of exposing the end surfaces of the TSVs 411 to the first surface 420, the end surfaces of the TSVs 411 of the chips 410 adjacent to the first surface 420 of the stacking unit 400 are exposed to the first surface 420.

[0078] In some specific embodiments, the method for exposing the end face of the TSV 411 to the first surface 420 includes: exposing the end face of the TSV 411 to the first surface 420 using a backside TSV reveal process. The backside TSV reveal process (BVR) includes the following steps: grinding the wafer 440, typically to a depth of 5-10 μm from the node of the TSV 411, to initially thin the back of the wafer 440 in preparation for exposing the TSV 411; dry etching: after grinding, dry etching the silicon to expose the TSV 411, forming a step height of approximately 5 μm; passivation: after silicon etching, passivating the TSV 411 using a dielectric layer stack to prevent oxidation or other external factors from affecting the TSV 411 and ensure its stable performance; and chemical mechanical polishing (CMP): performing chemical mechanical polishing (CMP) to remove excess surface material and expose the end face of the TSV 411 in preparation for subsequent redistribution layer (RDL) metallization.

[0079] After exposing the end face of the through silicon via 411, the first interconnection layer is formed, and the first conductive line is connected to the through silicon via 411. In some specific embodiments, the first interconnection layer is formed using a Damascene process, which specifically includes the following steps:

[0080] like Figure 6 , which is a schematic diagram of forming a first organic dielectric layer 501 in a method for manufacturing a three-dimensional stacked structure according to one embodiment of the present invention. The first organic dielectric layer 501 is formed on the first surface 420 of the stacking unit 400. In this step, the first organic dielectric layer 501 can be formed to a predetermined height by controlling process parameters. In some embodiments, a spin coating process is used to form the first organic dielectric layer 501 on the first surface 420 of the stacking unit 400. The first organic dielectric layer 501 can be a polyimide (PI) layer or other organic material layer, such as benzocyclobutene (BCB) or poly(p-phenylenebenzobisoxazole) (PBO).

[0081] like Figure 7 As shown, it is a schematic diagram of forming a first through hole 503 in the first organic dielectric layer 501 in the manufacturing method of the three-dimensional stacked structure provided by a specific embodiment of the present invention. The first through hole 503 is formed in the first organic dielectric layer 501, and the first through hole 503 exposes the end face of the silicon through hole 411.

[0082] In one specific embodiment, a photoresist mask is used to expose and develop the first organic dielectric layer 501 to form the first through-hole 503. Because the first organic dielectric layer 501 is an organic material, the exposure and development operations can be performed directly using the photoresist mask as a shield, eliminating the need to form a patterned photoresist protective layer on the surface of the first organic dielectric layer 501 and then use the photoresist protective layer as a mask to etch the first organic dielectric layer 501 to form the first through-hole 503. Furthermore, after forming the first through-hole 503, the first organic dielectric layer 501 does not need to be removed, as would be necessary if a photoresist protective layer were used to form the first through-hole 503. This manufacturing method significantly streamlines the process flow and reduces manufacturing costs.

[0083] like Figures 8 to 10 As shown, the first conductive circuit 502 is formed in the first through hole 503, and the first conductive circuit 502 is connected to the through silicon via 411. In some specific embodiments, the first conductive circuit 502 is formed by electroplating, sputtering, or other processes.

[0084] In one embodiment, the step of forming the first conductive circuit 502 in the first through hole 503 includes:

[0085] like Figure 8 FIG. 2 is a schematic diagram illustrating forming a first barrier layer 504 covering the inner wall of the first through-hole 503 in a method for manufacturing a three-dimensional stacked structure according to one embodiment of the present invention. The first barrier layer 504 is formed in the first through-hole 503 to cover the inner wall of the first through-hole 503. The first barrier layer 504 is used to prevent the subsequently formed conductive material from diffusing into the first organic dielectric layer 501, thereby preventing electromigration and short circuits. In some embodiments, the first barrier layer 504 may be a Ta / TaN composite layer. In this step, the first barrier layer 504 also covers the surface of the first organic dielectric layer 501.

[0086] like Figure 9 , which is a schematic diagram of filling a conductive material in a method for manufacturing a three-dimensional stacked structure according to one embodiment of the present invention. The conductive material is filled to form a first initial structure 900. The first initial structure 900 fills the first through-hole 503 and covers the surface of the first organic dielectric layer 501. In this step, the first initial structure 900 covers the surface of the first barrier layer 504. In some embodiments, the conductive material can be filled using processes such as electroplating or sputtering.

[0087] like Figure 10 , which is a schematic diagram of thinning the first initial structure 900 in a method for manufacturing a three-dimensional stacked structure according to a specific embodiment of the present invention, wherein the first initial structure 900 is thinned to form the first conductive circuit 502. The first initial structure 900 and the first barrier layer 504 on the surface of the first organic dielectric layer 501 are removed using a process such as chemical mechanical polishing until the surface of the first initial structure 900 is flush with the surface of the first organic dielectric layer 501. Only the first barrier layer 504 and the first initial structure 900 within the first through hole 503 remain, and the remaining first initial structure 900 serves as the first conductive circuit 502.

[0088] In some specific embodiments, the step of forming the first conductive circuit 502 in the first through hole 503 further includes: Figure 11Figure 2 shows a schematic diagram of thinning the first organic dielectric layer 501 in a method for manufacturing a three-dimensional stacked structure according to one embodiment of the present invention. Thinning the first organic dielectric layer 501 allows the surface of the first conductive trace 502 to protrude beyond the surface of the first organic dielectric layer 501, paving the way for subsequent bonding. In one embodiment, the first organic dielectric layer 501 can be thinned using an etching process. Adjusting the etching parameters can control the amount of thinning of the first organic dielectric layer 501.

[0089] Referring to step S32, after forming the first interconnect layer 500, a second interconnect layer 510 is formed on the second surface 430 of the stacked unit 400. The second interconnect layer 510 includes a second organic dielectric layer 511 and a second conductive trace 512 disposed in the second organic dielectric layer 511. Specifically, in this embodiment, the second interconnect layer 510 is formed on the second surface 430 of the initial unit.

[0090] In some specific embodiments, the chip 410 includes a through silicon via 411, and the step of forming the second interconnect layer 510 on the second surface 430 of the stacking unit 400 includes:

[0091] like Figure 12 , which is a schematic diagram of another method for exposing a TSV 411 in a method for manufacturing a three-dimensional stacked structure according to one embodiment of the present invention, wherein the end surface of the TSV 411 is exposed to the second surface 430. Specifically, the first supporting plate 590 is debonded to expose the second surface 430 of the stacking unit 400, and a second supporting plate 690 is bonded to the surface of the first interconnect layer 500, with the second surface 430 facing away from the second supporting plate 690. The process of exposing the end surface of the TSV 411 is performed from the second surface 430 of the stacking unit 400. In one embodiment, the stacking unit 400 includes a plurality of chips 410 stacked along the first direction D1, each chip 410 including a TSV 411, and the TSVs 411 of all chips 410 are sequentially connected. In the step of exposing the end surface of the TSV 411 to the second surface 430, the end surface of the TSV 411 of the chip 410 adjacent to the second surface 430 of the stacking unit 400 is exposed to the second surface 430. In some specific embodiments, the method of exposing the end surface of the TSV 411 to the second surface 430 includes: exposing the end surface of the TSV 411 to the second surface 430 using a backside TSV revealing process (BVR).

[0092] like Figure 13, which is a schematic diagram of forming a second interconnect layer 510 in a method for manufacturing a three-dimensional stacked structure according to one embodiment of the present invention. After exposing the end faces of the through-silicon vias 411, the second interconnect layer 510 is formed, and the second conductive traces 512 are connected to the through-silicon vias 411. In some embodiments, the second interconnect layer 510 is formed using a Damascene process. The method for forming the second interconnect layer 510 is the same as the method for forming the first interconnect layer 500, and specifically includes the following steps:

[0093] A second organic dielectric layer 511 is formed on the second surface 430 of the stacking unit 400. In this step, the second organic dielectric layer 511 is formed on the second surface 430 of the stacking unit 400 by a spin coating process.

[0094] A second through hole (not shown in the drawings) is formed in the second organic dielectric layer 511, exposing the other end surface of the through silicon via 411. In this step, the second organic dielectric layer 511 is exposed and developed using a photolithography mask to form the second through hole.

[0095] A second conductive trace 512 is formed in the second through-hole, connected to the through-silicon via 411. The steps of forming the second conductive trace 512 in the second through-hole include: forming a second barrier layer 514 covering the inner wall of the second through-hole; filling the second through-hole with a conductive material to form a second initial structure (not shown in the drawings); the second initial structure completely fills the second through-hole and covers the surface of the second organic dielectric layer 511; and thinning the second initial structure to form the second conductive trace 512.

[0096] In some specific embodiments, the step of forming the second conductive circuit 512 in the second through hole further includes: thinning the second organic dielectric layer 511 so that the surface of the second conductive circuit 512 protrudes from the surface of the second organic dielectric layer 511 .

[0097] After the second interconnection layer 510 is formed, the second supporting plate 690 is removed.

[0098] By repeating the above steps, a plurality of stacking units 400 having the first interconnection layer and the second interconnection layer disposed on the surface thereof can be formed.

[0099] In some specific embodiments, the above steps form the first interconnect layer 500 and the second interconnect layer 510 on the first surface 420 and the second surface 430 of the initial unit formed by the wafer 440, and the manufacturing method further includes: Figure 14, which is a schematic diagram of cutting an initial unit in a method for manufacturing a three-dimensional stacked structure provided by a specific embodiment of the present invention, wherein the initial unit is cut to form a plurality of independent stacked units 400 .

[0100] Figure 15 This is a schematic diagram of a method for manufacturing a three-dimensional stacked structure according to a specific embodiment of the present invention after bonding multiple stacking units 400. Figure 15 In step S33, multiple stacking units 400 are stacked and bonded together along a first direction D1, wherein the first interconnect layer 500 on the first surface 420 of one of two adjacent stacking units 400 is bonded to the second interconnect layer 510 on the second surface 430 of the other stacking unit 400. Specifically, the first organic dielectric layer 501 on the first surface 420 of one of the two adjacent stacking units 400 is bonded to the second organic dielectric layer 511 on the second surface 430 of the other of the two adjacent stacking units 400, and the first conductive trace 502 on the first surface 420 of one of the two adjacent stacking units 400 is bonded to the second conductive trace 512 on the second surface 430 of the other of the two adjacent stacking units 400, thereby forming an organic hybrid bonded structure. The number of stacking units 400 can be set according to the specific design of the three-dimensional stacking structure, and the number of stacking units 400 shown in the figures is for reference only.

[0101] In this organic hybrid bonding structure, the gap between the upper and lower stacking units 400, and the key dimensions and spacing of the conductive structures in the first conductive circuit 502 and the second conductive circuit 512 are all small, thereby enabling denser IO interconnection and more layers of stacking. In addition, the organic hybrid bonding does not require plastic encapsulation material filling, and heat is conducted through the interconnection between the first conductive circuit 502 and the second conductive circuit 512, resulting in better heat dissipation.

[0102] In some specific embodiments, the step of stacking and bonding the plurality of stacking units 400 along the first direction D1 includes:

[0103] Plasma activation is used to activate the first interconnect layer 500 and the second interconnect layer 510 of the stacked unit 400 where a bonding process is to be performed, thereby improving the surface properties of the first interconnect layer 500 and the second interconnect layer 510, activating their surface valence bonds, and enhancing bonding strength and reliability. Specifically, when two stacked units 400 need to be bonded, the first interconnect layer 500 on the first surface 420 of the first stacked unit 400 is activated, and the second interconnect layer 510 on the second surface 430 of the second stacked unit 400 is activated. In some specific embodiments, the first interconnect layer 500 and the second interconnect layer 510 of the stacked unit 400 where a bonding process is to be performed can be activated using plasma containing oxygen, nitrogen, argon, or a mixture of oxygen, nitrogen, and argon. In some specific embodiments, the activation effect can be improved by controlling parameters such as the plasma flow rate, RF power, processing time, and gas pressure.

[0104] After the activation treatment, a bonding process is performed to bond the first interconnect layer 500 of one of the two adjacent stacked units 400 to the second interconnect layer 510 of the other stacked unit 400. Specifically, the first organic dielectric layer 501 on the first surface 420 of one of the two adjacent stacked units 400 is bonded to the second organic dielectric layer 511 on the second surface 430 of the other of the two adjacent stacked units 400, and the first conductive trace 502 on the first surface 420 of one of the two adjacent stacked units 400 is bonded to the second conductive trace 512 on the second surface 430 of the other of the two adjacent stacked units 400. This bonding step can be performed in an ultra-high vacuum environment at a certain pressure and temperature.

[0105] The bonding process may also include low-temperature or high-temperature annealing. Specifically, heating to 150-450°C after bonding promotes the formation of covalent bonds between groups at the bonding interface, achieving a high-strength bond. In some embodiments, the bonding process may include low-temperature annealing (room temperature - 250°C).

[0106] In some specific embodiments, before the step of stacking the plurality of stacking units 400 along the first direction D1 and bonding them together, the following steps are further included:

[0107] A substrate 520 is provided, and a third interconnection layer 530 is formed on the surface of the substrate 520 where the stacking unit 400 is to be provided. The third interconnection layer 530 includes a third organic dielectric layer 531 and a third conductive line 532 provided in the third organic dielectric layer 531. The third conductive line 532 is interconnected with the conductive structure in the substrate 520, such as Figure 15 In one embodiment, the substrate 520 is disposed on a surface of a third supporting plate 790 , which may be a glass substrate. The third interconnect layer 530 is formed on a surface of the substrate 520 facing away from the third supporting plate 790 .

[0108] The substrate 520 may be an organic substrate, a glass substrate, a ceramic substrate, a silicon substrate, a composite substrate, a wafer, etc.

[0109] The step of stacking and bonding the plurality of stacking units 400 along the first direction D1 further includes bonding the third interconnection layer 530 to the second interconnection layer 510 of the second surface 430 of the bottom stacking unit 400, and then arranging other stacking units 400 on the bottom stacking unit 400, such as Figure 15 As shown. The third organic dielectric layer 531 is connected to the second organic dielectric layer 511, and the third conductive trace 532 is connected to the second conductive trace 512, forming an organic hybrid bonded structure. In this organic hybrid bonded structure, the gap between the bottom stacking unit 400 and the substrate 520, as well as the key dimensions and spacing of the conductive structures in the second conductive trace 512 and the third conductive trace 532 are all small, thereby enabling denser IO interconnection and more stacking layers. Furthermore, the organic hybrid bond does not require molding compound filling, and heat is conducted through the interconnection between the second conductive trace 512 and the third conductive trace 532, resulting in better heat dissipation.

[0110] In some specific embodiments, the first surface 420 of the topmost stacking unit 400 is not formed with the first interconnection layer 500, and the first surface 420 of the topmost stacking unit 400 is the substrate surface of the stacking unit 400, and the second interconnection layer 510 is formed on the second surface 430 of the topmost stacking unit 400, and the second interconnection layer 510 is used to form an organic hybrid bonding structure with the first interconnection layer 500 of the stacking unit 400 below, such as Figure 15 shown.

[0111] Figure 16 This is a schematic diagram of a method for manufacturing a three-dimensional stacked structure after plastic packaging according to a specific embodiment of the present invention. Figure 16 In step S34, the method for manufacturing a three-dimensional stacked structure provided by one embodiment of the present invention further includes: plastic encapsulation to form a plastic encapsulation body 540, wherein the plastic encapsulation body 540 covers the stacked units 400. In one embodiment, the substrate surface of the topmost stacked unit 400 is exposed to the plastic encapsulation body 540, and heat from the three-dimensional stacked structure can be conducted to the topmost stacked unit 400 through each conductive interconnect layer and dissipated through the substrate of the topmost stacked unit 400.

[0112] In some specific embodiments, a plurality of stacking structures are formed on the substrate, each of which is formed by stacking a plurality of stacking units 400. After the plastic packaging, a cutting process is performed between adjacent stacking structures to form a plurality of independent three-dimensional stacking structures. Figure 17 As shown, it is a schematic diagram after cutting in a manufacturing method of a three-dimensional stacked structure provided by a specific embodiment of the present invention, wherein the three-dimensional stacked structure includes a plurality of stacking units 400 stacked along a first direction D1, and a bonding structure layer 550 is provided between adjacent stacking units 400, and the bonding structure layer 550 includes the first interconnection layer 500 and the second interconnection layer 510.

[0113] The method for manufacturing a three-dimensional stacked structure provided in a specific embodiment of the present invention employs a first interconnect layer 500 and a second interconnect layer 510 comprising an organic dielectric layer as bonding layers between stacked units 400, performing organic hybrid bonding. This allows for denser IO interconnects and more stacked layers, while also improving the heat dissipation performance of the three-dimensional stacked structure. The method for manufacturing a three-dimensional stacked structure provided in a specific embodiment of the present invention has a simple process flow and relatively low requirements for bonding surface cleanliness.

[0114] In the above embodiment, the stacking unit 400 includes two chips 410 in the first direction D1. In another embodiment, as shown in FIG. Figure 18 As shown, it is a schematic diagram of a three-dimensional stacked structure provided by a specific embodiment of the present invention. The stacking unit 400 includes four chips 410 in the first direction D1, and adjacent chips 410 are connected by an inorganic hybrid bonding layer 450. The manufacturing method of the three-dimensional stacked structure can be referred to Figures 4 to 17 .

[0115] In some of the above specific embodiments, the stacking unit 400 includes an initial unit, which includes two wafers 440 stacked along a first direction D1, and two adjacent wafers 440 are connected by an inorganic hybrid bonding layer 450, such as Figure 4 After forming the first interconnection layer 500 on the first surface 420 of the initial unit and forming the second interconnection layer 510 on the second surface 430 of the initial unit, the initial unit is cut to form independent stacked units 400, as shown. Figure 14 After stacking a plurality of the stacking units 400 along the first direction D1 and bonding them together, a three-dimensional stacking structure is formed in which a plurality of chips 410 are stacked in the first direction D1. Figure 15In other specific embodiments, the stacking unit 400 is a wafer, and after a plurality of the stacking units 400 are stacked and bonded along the first direction D1, the formed three-dimensional stacking structure is a stacking structure in which a plurality of wafers are stacked in the first direction D1.

[0116] The following combination Figures 19 to 22 A method for manufacturing a three-dimensional stacked structure according to another embodiment of the present invention is described in detail. In this embodiment, the three-dimensional stacked structure is a stacked structure of multiple wafers in a first direction D1.

[0117] Figure 19 FIG. 4 is a schematic diagram of a stacking unit 400 provided in a method for manufacturing a three-dimensional stacking structure according to another embodiment of the present invention. Figure 19 In step S30 , a stacking unit 400 is provided. The stacking unit 400 includes at least one chip 410 . The stacking unit 400 includes a first surface 420 and a second surface 430 , which are opposite to each other. In this embodiment, the stacking unit 400 is a wafer, which includes a plurality of chips 410 .

[0118] In the three-dimensional stacking structure finally formed, the stacking unit 400 can be used as the stacking unit 400 of the bottom layer, the stacking unit 400 of the middle layer, and the stacking unit 400 of the top layer. Figure 19 As shown in part (a), when the stacking unit 400 is used as the bottom stacking unit 400, a fourth interconnection layer 560 is formed on the second surface 430 of the stacking unit 400. The fourth interconnection layer 560 includes a first inorganic dielectric layer 561 and a fourth conductive line 562 disposed in the first inorganic dielectric layer 561. The fourth conductive line 562 is connected to one end of the through silicon via 411, and the other end of the through silicon via 411 extends toward the interior of the stacking unit 400. Figure 19 As shown in part (b), when the stacking unit 400 serves as the stacking unit 400 of the middle layer and the stacking unit 400 of the top layer, the second surface 430 of the stacking unit 400 exposes the end face of the silicon via 411, and the silicon via 411 extends toward the interior of the stacking unit 400 and is not exposed to the first surface 420 of the stacking unit 400.

[0119] Figure 20 This is a schematic diagram of forming a first interconnection layer 500 and forming a second interconnection layer 510 in a method for manufacturing a three-dimensional stacked structure provided by another specific embodiment of the present invention. Figure 20In steps S31 and S32, a first interconnection layer 500 is formed on the first surface 420 of the stacking unit 400. The first interconnection layer 500 includes a first organic dielectric layer 501 and a first conductive line 502 disposed in the first organic dielectric layer 501. After the first interconnection layer 500 is formed, a second interconnection layer 510 is formed on the second surface 430 of the stacking unit 400. The second interconnection layer 510 includes a second organic dielectric layer 511 and a second conductive line 512 disposed in the second organic dielectric layer 511. The formation methods of the first interconnection layer 500 and the second interconnection layer 510 can be referred to. Figures 5 to 13 .

[0120] like Figure 20 As shown in part (a), when the stacking unit 400 is used as the bottom stacking unit 400, the first interconnection layer 500 is formed on the first surface 420 of the stacking unit 400, the second interconnection layer 510 is not formed on the second surface 430 of the stacking unit 400, and the second surface 430 of the stacking unit 400 has a fourth interconnection layer 560. Figure 20 As shown in part (b), when the stacking unit 400 is used as the stacking unit 400 of the middle layer, the first interconnection layer 500 is formed on the first surface 420 of the stacking unit 400, and the second interconnection layer 510 is formed on the second surface 430 of the stacking unit 400. Figure 20 As shown in part (c), when the stacking unit 400 serves as the topmost stacking unit 400, the second interconnection layer 510 is formed on the second surface 430 of the stacking unit 400, and the first interconnection layer 500 is not formed on the first surface 420 of the stacking unit 400. The first surface 420 of the stacking unit 400 is the substrate surface, and the silicon through-hole 411 is not exposed to the first surface 420.

[0121] Figure 21 FIG. 1 is a schematic diagram of a method for manufacturing a three-dimensional stacked structure according to another embodiment of the present invention after bonding multiple stacking units 400. Figure 22 This is another schematic diagram of a method for manufacturing a three-dimensional stacked structure according to another embodiment of the present invention after bonding multiple stacking units 400. Figure 21 、 Figure 22 In step S33, the plurality of stacking units 400 are stacked along the first direction D1 and bonded together, wherein the first interconnect layer 500 on the first surface 420 of one of two adjacent stacking units 400 is bonded to the second interconnect layer 510 on the second surface 430 of the other stacking unit 400. The bonding method can be referred to the description of the bonding method above.

[0122] In some specific embodiments, the three-dimensional stacked structure manufactured by the manufacturing method of the three-dimensional stacked structure provided by the present invention includes only two stacking units 400, such as Figure 21 As shown, one stacking unit 400 serves as the bottom stacking unit 400, and the other stacking unit 400 serves as the top stacking unit 400; in other specific embodiments, the three-dimensional stacking structure manufactured by the manufacturing method of the three-dimensional stacking structure provided by the present invention only includes three or more stacking units 400, such as Figure 22 As shown, at least one intermediate stacking unit 400 is provided between the bottommost stacking unit 400 and the topmost stacking unit 400. The number of intermediate stacking units 400 can be set according to the specific design of the three-dimensional stacking structure, and the number of intermediate stacking units 400 in the figure is only for illustration.

[0123] In this embodiment, organic hybrid bonding is performed between each wafer using a first interconnect layer 500 and a second interconnect layer 510 comprising an organic dielectric layer as bonding layers. Compared to inorganic hybrid bonding techniques used between stacked units 400, the present manufacturing method offers a simple process flow, low manufacturing costs, and relatively low requirements for bonding surface cleanliness. Bonding and annealing temperatures do not need to be set excessively high, which will not affect devices within the wafers, resulting in high reliability.

[0124] Based on the same inventive concept, a specific embodiment of the present invention further provides a three-dimensional stacked structure formed by the aforementioned manufacturing method.

[0125] like Figure 17 As shown, a three-dimensional stacked structure provided by a specific embodiment of the present invention includes: a plurality of stacking units 400 stacked along a first direction D1, wherein the stacking unit 400 includes at least one chip 410, and the stacking unit 400 includes a first surface 420 and a second surface 430 arranged opposite to each other; a bonding structure layer 550 including a first interconnection layer 500 and a second interconnection layer 510, wherein the first interconnection layer 500 is arranged on the first surface 420 of one of the two adjacent stacking units 400, and the first interconnection layer 500 includes a first organic dielectric layer 501 and a first conductive circuit 502 arranged in the first organic dielectric layer 501, and the second interconnection layer 510 is arranged on the second surface 430 of the other of the two adjacent stacking units 400, and the second interconnection layer 510 includes a second organic dielectric layer 511 and a second conductive circuit 512 arranged in the second organic dielectric layer 511, the first organic dielectric layer 501 is connected to the second organic dielectric layer 511, and the first conductive circuit 502 is connected to the second conductive circuit 512.

[0126] The three-dimensional stacked structure provided by the specific embodiment of the present invention uses the first interconnection layer 500 and the second interconnection layer 510 having an organic dielectric layer as the bonding structure layer 550. Figure 1 and Figure 2 As shown in the embodiment of the present invention, the gaps between the stacking units 400 of the three-dimensional stacked structure and the key dimensions and spacing of the conductive structures in the conductive circuits of the interconnection layer are relatively small. Therefore, denser IO interconnections and more layers of stacking can be achieved. For example, the total height of chips with the same number of layers and specifications can be reduced by 15%, and the IO density can be increased by at least 1 times. At the same time, organic hybrid bonding is used between the stacking units 400, and no plastic filling is required. The heat is conducted through the interconnection of the conductive circuits, and the heat dissipation effect is better. Through simulation comparison, the thermal resistance (Rjc) of the three-dimensional stacked structure using organic hybrid bonding is reduced by 50% compared with the three-dimensional stacked structure using microbumps.

[0127] Compared with the technology of using inorganic hybrid bonding between the stacking units 400, the three-dimensional stacking structure manufacturing process provided by the specific embodiment of the present invention is simple, has low manufacturing cost, and has relatively low requirements for the cleanliness of the bonding surface. The bonding and annealing temperatures do not need to be set too high, and will not affect the devices of the stacking unit 400. The three-dimensional stacking structure has high reliability.

[0128] The stacking unit 400 includes at least one chip 410. In a specific embodiment, the stacking unit 400 includes a plurality of chips 410 stacked along the first direction D1, and two adjacent chips 410 are connected by an inorganic hybrid bonding layer 450. Figure 17 As shown, the stacking unit 400 includes two chips 410 arranged along the first direction D1, and the two chips 410 are connected by an inorganic hybrid bonding layer 450. Figure 18 As shown, the stacking unit 400 includes four chips 410 arranged along the first direction D1 , and the four chips 410 are connected via an inorganic hybrid bonding layer 450 .

[0129] In a specific embodiment, the chip 410 includes a through silicon via 411, the first conductive line 502 is connected to one end of the through silicon via 411, and the second conductive line 512 is connected to the other end of the through silicon via 411. Figure 17As shown, the stacking unit 400 includes a plurality of chips 410 stacked along the first direction D1, each of the chips 410 includes a through-silicon via 411, and the through-silicon vias 411 of all the chips 410 are connected in sequence, the end faces of the through-silicon vias 411 of the chips 410 adjacent to the first surface 420 of the stacking unit 400 are connected to the first conductive circuit 502, and the end faces of the through-silicon vias 411 of the chips 410 adjacent to the second surface 430 of the stacking unit 400 are connected to the second conductive circuit 512.

[0130] The first interconnect layer 500 and the second interconnect layer 510 are both organic damascene structures formed using a damascene process. The first organic dielectric layer 501 and the second organic dielectric layer 511 can be layers of the same material or layers of different materials. The first organic dielectric layer 501 and the second organic dielectric layer 511 can be polyimide (PI) layers, or other organic material layers, such as benzocyclobutene (BCB) or poly(p-phenylenebenzobisoxazole) (PBO).

[0131] In one specific embodiment, a first barrier layer 504 is provided between the first organic dielectric layer 501 and the first conductive circuit 502, and a second barrier layer 514 is provided between the second organic dielectric layer 511 and the second conductive circuit 512. The first barrier layer 504 and the second barrier layer 514 are used to prevent metal particles in the first conductive circuit 502 from diffusing into the first organic dielectric layer 501 and metal particles in the second conductive circuit 512 from diffusing into the second organic dielectric layer 511, thereby avoiding electromigration and short circuit.

[0132] In a specific embodiment, the three-dimensional stacked structure further includes: a substrate 520; a third interconnection layer 530, which is arranged on the surface of the substrate 520, and the third interconnection layer 530 includes a third organic dielectric layer 531 and a third conductive circuit 532 arranged in the third organic dielectric layer 531, and the third conductive circuit 532 is interconnected with the conductive structure within the substrate 520; wherein the third organic dielectric layer 531 is connected to the second organic dielectric layer 511 of the second surface 430 of the bottom stacking unit 400, and the third conductive circuit 532 is connected to the second conductive circuit 512 of the second surface 430 of the bottom stacking unit 400, forming an organic hybrid bonding structure. In this organic hybrid bonding structure, the gap between the bottommost stacking unit 400 and the substrate 520, as well as the critical dimensions and spacing of the conductive structures in the second conductive traces 512 and third conductive traces 532, are all small. This allows for denser IO interconnection and more stacking layers. Furthermore, the organic hybrid bonding structure does not require molding compound, and heat dissipation is improved through the interconnection between the second conductive traces 512 and third conductive traces 532. The substrate 520 can be used to electrically connect the three-dimensional stacked structure to other devices. For example, the three-dimensional stacked structure is disposed on a printed circuit board, and the substrate 520 is used to electrically connect the three-dimensional stacked structure to the printed circuit board.

[0133] In a specific embodiment, the first surface 420 of the topmost stacking unit 400 is not formed with the first interconnection layer 500, and the first surface 420 of the topmost stacking unit 400 is the substrate surface of the stacking unit 400. The three-dimensional stacking structure can conduct heat to the topmost stacking unit 400 through the first conductive circuit 502 and the second conductive circuit 512, and dissipate heat through the substrate of the topmost stacking unit 400.

[0134] In a specific embodiment, the three-dimensional stacking structure further includes a plastic package 540, which covers the stacking units 400. The substrate surface of the topmost stacking unit 400 is exposed to the plastic package 540, which is beneficial to the heat dissipation of the three-dimensional stacking structure.

[0135] The three-dimensional stacking structure is a stacking structure in which multiple chips 410 are stacked in the first direction D1. In other specific embodiments, the three-dimensional stacking structure is a stacking structure in which multiple wafers are stacked in the first direction D1, that is, the stacking unit 400 is a wafer, and the wafer includes multiple chips 410. Figure 21 As shown, the three-dimensional stacking structure includes only two stacking units 400, as shown in FIG. Figure 22 As shown, the three-dimensional stacking structure includes three or more stacking units 400 .

[0136] In the three-dimensional stacking structure, the stacking unit 400 can serve as the stacking unit 400 at the bottom layer, the stacking unit 400 at the middle layer, and the stacking unit 400 at the top layer.

[0137] When the stacking unit 400 serves as the bottommost stacking unit 400, the second interconnect layer 510 is not formed on the second surface 430 of the stacking unit 400. Instead, a fourth interconnect layer 560 is formed on the second surface 430 of the bottommost stacking unit 400. The fourth interconnect layer 560 includes a first inorganic dielectric layer 561 and a fourth conductive trace 562 disposed in the first inorganic dielectric layer 561. The first surface 420 of the stacking unit 400 is formed with a first interconnect layer 500. The fourth conductive trace 562 is connected to one end of the through-silicon via 411, and the other end of the through-silicon via 411 is connected to the first conductive trace 502 of the first interconnect layer 500.

[0138] When the stacking unit 400 is used as a middle layer stacking unit 400, a first interconnection layer 500 is formed on the first surface 420 of the stacking unit 400, and a second interconnection layer 510 is formed on the second surface 430 of the stacking unit 400. One end of the through silicon via 411 is connected to the first interconnection layer 500, and the other end is connected to the second interconnection layer 510.

[0139] When the stacking unit 400 serves as the topmost stacking unit 400, a first interconnection layer 500 is formed on the first surface 420 of the stacking unit 400, and a second interconnection layer 510 is not formed on the second surface 430 of the stacking unit 400. The second surface 430 of the stacking unit 400 is the substrate surface, and one end of the through silicon via 411 is connected to the first interconnection layer 500, and the other end is not exposed to the second surface 430.

[0140] In this embodiment, the first interconnection layer 500 and the second interconnection layer 510 having an organic dielectric layer are used between each wafer as the bonding structure layer 550. Compared with the technology of using inorganic hybrid bonding between stacking units 400, the three-dimensional stacking structure of the present invention has high reliability.

[0141] It should be noted that the terms "including," "having," and their variations, as used in this document, are intended to cover non-exclusive inclusions. Terms such as "first," "second," and the like are used to distinguish similar items and are not necessarily used to describe a specific order or precedence, unless the context clearly indicates otherwise. Such usage should be understood to be interchangeable where appropriate. The term "one or more" may be used to describe a feature, structure, or characteristic in the singular, or in the plural, depending at least in part on the context, to describe a feature, structure, or combination of features. The term "based on" should be understood as not necessarily intended to express an exclusive set of factors, but may alternatively, also depending at least in part on the context, allow for the presence of other factors that are not necessarily explicitly described. Furthermore, the embodiments of the present invention and the features therein may be combined with one another, unless there is a conflict. Furthermore, descriptions of well-known components and technologies have been omitted from the above description to avoid unnecessary confusion regarding the concepts of the present invention. In each of the above embodiments, each embodiment focuses on its differences from the other embodiments, and reference may be made to the same or similar parts between the embodiments.

[0142] The above description is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for manufacturing a three-dimensional stacked structure, characterized in that: The steps include: Providing a stacking unit, the stacking unit comprising at least one chip, the stacking unit comprising a first surface and a second surface disposed opposite to each other; forming a first interconnection layer on the first surface of the stacking unit, wherein the first interconnection layer includes a first organic dielectric layer and a first conductive line disposed in the first organic dielectric layer; forming a second interconnection layer on the second surface of the stacking unit, wherein the second interconnection layer includes a second organic dielectric layer and a second conductive line disposed in the second organic dielectric layer; A plurality of the stacking units are stacked along a first direction and bonded together, wherein the first interconnection layer on the first surface of one of two adjacent stacking units is bonded together with the second interconnection layer on the second surface of the other stacking unit.

2. The method for manufacturing a three-dimensional stacked structure according to claim 1, wherein: In the step of providing a stacking unit, the stacking unit includes an initial unit, the initial unit includes at least one wafer, and the wafer includes a plurality of the chips; The step of forming a first interconnect layer on the first surface of the stacked unit includes: forming the first interconnect layer on the first surface of the initial unit; The step of forming a second interconnect layer on the second surface of the stacked unit includes: forming the second interconnect layer on the second surface of the initial unit; Before the step of stacking the plurality of stacking units along the first direction and bonding them together, the method further includes the following step: cutting the initial unit to form a plurality of independent stacking units.

3. The method for manufacturing a three-dimensional stacked structure according to claim 2, wherein: The initial unit includes a plurality of wafers stacked along the first direction, and two adjacent wafers are connected via an inorganic hybrid bonding layer.

4. The method for manufacturing a three-dimensional stacked structure according to claim 1, wherein: The chip includes a through silicon via, and the step of forming a first interconnection layer on the first surface of the stacking unit includes: exposing an end surface of the through silicon via to the first surface; forming the first interconnection layer, wherein the first conductive line is connected to the through silicon via; The step of forming a second interconnection layer on the second surface of the stacking unit includes: exposing the other end surface of the through silicon via to the second surface; forming the second interconnection layer, wherein the second conductive line is connected to the through silicon via.

5. The method for manufacturing a three-dimensional stacked structure according to claim 4, wherein: The stacking unit includes a plurality of chips stacked along the first direction, each chip includes a through-silicon via (TSV), and the TSVs of all the chips are sequentially connected. In the step of forming a first interconnect layer on the first surface of the stacking unit, end surfaces of the TSVs of the chips adjacent to the first surface of the stacking unit are exposed to the first surface. In the step of forming a second interconnection layer on the second surface of the stacking unit, end surfaces of through silicon vias of the chips adjacent to the second surface of the stacking unit are exposed to the second surface.

6. The method for manufacturing a three-dimensional stacked structure according to claim 4, wherein: The method of exposing one end surface of the through silicon via to the first surface and the other end surface of the through silicon via to the second surface includes: using a back side through silicon via exposure process to expose one end surface of the through silicon via to the first surface and the other end surface of the through silicon via to the second surface.

7. The method for manufacturing a three-dimensional stacked structure according to claim 4, wherein: The step of forming a first interconnect layer on the first surface of the stacking unit includes: forming a first organic dielectric layer on a first surface of the stacking unit; forming a first through hole in the first organic dielectric layer, wherein the first through hole exposes an end surface of the through silicon via; The first conductive circuit is formed in the first through hole, and the first conductive circuit is connected to the through silicon via.

8. The method for manufacturing a three-dimensional stacked structure according to claim 7, wherein: The step of forming a first organic medium layer on the first surface of the stacking unit includes: forming the first organic medium layer on the first surface of the stacking unit by a spin coating process.

9. The method for manufacturing a three-dimensional stacked structure according to claim 7, wherein: The step of forming the first through hole in the first organic dielectric layer includes: exposing and developing the first organic dielectric layer using a photolithography mask to form the first through hole.

10. The method for manufacturing a three-dimensional stacked structure according to claim 7, wherein: The step of forming the first conductive circuit in the first through hole includes: forming a first barrier layer in the first through hole, covering an inner wall of the first through hole; Filling the conductive material to form a first initial structure, wherein the first initial structure fills the first through hole, and covering the surface of the first organic medium layer; The first initial structure is thinned to form the first conductive line.

11. The method for manufacturing a three-dimensional stacked structure according to claim 7, wherein: The step of forming the first conductive circuit in the first through hole further includes: thinning the first organic dielectric layer so that a surface of the first conductive circuit protrudes from a surface of the first organic dielectric layer.

12. The method for manufacturing a three-dimensional stacked structure according to claim 4, wherein: The step of forming a second interconnect layer on the second surface of the stacking unit includes: forming a second organic medium layer on the second surface of the stacking unit; forming a second through hole in the second organic dielectric layer, wherein the second through hole exposes the other end surface of the through silicon via; A second conductive circuit is formed in the second through hole, and the second conductive circuit is connected to the through silicon via.

13. The method for manufacturing a three-dimensional stacked structure according to claim 12, wherein: The step of forming a second organic medium layer on the second surface of the stacking unit includes: forming the second organic medium layer on the second surface of the stacking unit by a spin coating process.

14. The method for manufacturing a three-dimensional stacked structure according to claim 12, wherein: The step of forming the second through hole in the second organic dielectric layer includes: exposing and developing the second organic dielectric layer using a photolithography mask to form the second through hole.

15. The method for manufacturing a three-dimensional stacked structure according to claim 12, wherein: The step of forming the second conductive circuit in the second through hole includes: forming a second barrier layer in the second through hole, covering the inner wall of the second through hole; Filling the conductive material to form a second initial structure, wherein the second initial structure fills the second through hole, and covering the surface of the second organic medium layer; The second initial structure is thinned to form the second conductive line.

16. The method for manufacturing a three-dimensional stacked structure according to claim 12, wherein: The step of forming the second conductive circuit in the second through hole further includes: thinning the second organic dielectric layer so that the surface of the second conductive circuit protrudes from the surface of the second organic dielectric layer.

17. The method for manufacturing a three-dimensional stacked structure according to claim 1, wherein: The steps of stacking a plurality of the stacking units along a first direction and bonding them together include: activating the first interconnect layer and the second interconnect layer of the stacking unit on which a bonding process needs to be performed by plasma; A bonding process is performed to bond the first interconnection layer of one of the two adjacent stacking units to the second interconnection layer of the other stacking unit.

18. The method for manufacturing a three-dimensional stacked structure according to claim 17, wherein: After the step of performing the bonding process, the step further includes: low temperature annealing.

19. The method for manufacturing a three-dimensional stacked structure according to claim 1, wherein: Before the step of stacking the plurality of stacking units along the first direction and bonding them together, the method further includes the following steps: Providing a substrate, and forming a third interconnection layer on a surface of the substrate where the stacking unit is to be disposed, the third interconnection layer comprising a third organic dielectric layer and a third conductive circuit disposed in the third organic dielectric layer, the third conductive circuit being interconnected with a conductive structure within the substrate; The step of stacking and bonding the plurality of stacking units along the first direction further includes bonding the third interconnection layer to the second interconnection layer on the second surface of the bottommost stacking unit.

20. The method for manufacturing a three-dimensional stacked structure according to claim 1, wherein: In the step of providing the stacking unit, a fourth interconnection layer is formed on the second surface of the bottommost stacking unit, the fourth interconnection layer including a first inorganic dielectric layer and a fourth conductive line provided in the first inorganic dielectric layer; In the step of forming a second interconnection layer on the second surface of the stacking unit, the second interconnection layer is not formed on the second surface of the bottommost stacking unit.

21. The method for manufacturing a three-dimensional stacked structure according to claim 20, wherein: In the step of forming the first interconnection layer on the first surface of the stacking unit, the first surface of the topmost stacking unit is not formed with the first interconnection layer, and the first surface of the topmost stacking unit is the substrate surface of the stacking unit.

22. The method for manufacturing a three-dimensional stacked structure according to claim 1, wherein: After the step of stacking the plurality of stacking units along the first direction and bonding them together, the method further comprises: Plastic packaging to form a plastic packaging body, wherein the plastic packaging body covers the stacking unit.

23. A three-dimensional stacked structure, characterized in that: include: A plurality of stacking units stacked along a first direction, each stacking unit comprising at least one chip, and each stacking unit comprising a first surface and a second surface opposite to each other; The bonding structure layer includes a first interconnection layer and a second interconnection layer, wherein the first interconnection layer is arranged on the first surface of one of the two adjacent stacking units, and the first interconnection layer includes a first organic dielectric layer and a first conductive circuit arranged in the first organic dielectric layer; the second interconnection layer is arranged on the second surface of the other of the two adjacent stacking units, and the second interconnection layer includes a second organic dielectric layer and a second conductive circuit arranged in the second organic dielectric layer; the first organic dielectric layer is connected to the second organic dielectric layer, and the first conductive circuit is connected to the second conductive circuit.

24. The three-dimensional stacked structure according to claim 23, characterized in that: The chip includes a through silicon via, the first conductive circuit is connected to one end of the through silicon via, and the second conductive circuit is connected to the other end of the through silicon via.

25. The three-dimensional stacked structure according to claim 23, characterized in that: The stacking unit includes a plurality of chips stacked along the first direction, each chip includes a through-silicon via, and the through-silicon vias of all the chips are connected in sequence, the end faces of the through-silicon vias of the chips adjacent to the first surface of the stacking unit are connected to the first conductive circuit, and the end faces of the through-silicon vias of the chips adjacent to the second surface of the stacking unit are connected to the second conductive circuit.

26. The three-dimensional stacked structure according to claim 23, characterized in that: The stacking unit includes a plurality of chips stacked along the first direction, and two adjacent chips are connected via an inorganic hybrid bonding layer.

27. The three-dimensional stacked structure according to claim 23, characterized in that: The three-dimensional stacked structure further includes: substrate; a third interconnection layer, disposed on the surface of the substrate, the third interconnection layer comprising a third organic dielectric layer and a third conductive circuit disposed in the third organic dielectric layer, the third conductive circuit being interconnected with the conductive structure in the substrate; The third organic dielectric layer is connected to the second organic dielectric layer on the second surface of the bottommost stacking unit, and the third conductive circuit is connected to the second conductive circuit on the second surface of the bottommost stacking unit.

28. The three-dimensional stacked structure according to claim 23, characterized in that The second surface of the bottom stacking unit is not provided with the second interconnection layer, and the second surface of the bottom stacking unit is provided with a fourth interconnection layer, which includes a first inorganic dielectric layer and a fourth conductive line arranged in the first inorganic dielectric layer.

29. The three-dimensional stacked structure according to claim 23, characterized in that The first interconnection layer is not formed on the first surface of the stacking unit at the top layer, and the first surface of the stacking unit at the top layer is the substrate surface of the stacking unit.

30. The three-dimensional stacked structure according to claim 23, wherein: The three-dimensional stacking structure further includes a plastic packaging body, which covers the stacking unit.

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