Hybrid bonding method based on regioselective atomic layer deposition technology

Abstract

The invention discloses a hybrid bonding method based on a regioselective atomic layer deposition technology, and belongs to the technical field of three-dimensional electronic packaging. The atomic layer deposition technology is adopted, multi-area and multi-spacing bonding can be carried out at the same time, and the method has wide size applicability. Interconnection layer bonding and dielectric layer bonding can be realized at low temperature without pressure, and damage to a bonding substrate caused by external mechanical force and high temperature during bonding is avoided. According to the process, when the interconnection layer and the dielectric layer are deposited, the micro defects of the to-be-bonded surface can be repaired, the requirements for the flatness and cleanliness of the to-be-bonded surface are low, and the influence of pollutants on the bonding quality is small. According to the invention, chemical mechanical polishing, plasma activation and other treatments do not need to be carried out on the to-be-bonded surface before bonding, the bonding process is simplified, and the method has a wide application prospect.

Description

Technical Field

[0001] The present invention relates to the technical field of three-dimensional electronic packaging, and in particular to a hybrid bonding method based on area-selective atomic layer deposition technology. Background Art

[0002] With the development of the Internet of Things, artificial intelligence, high-performance computing, and emerging technologies (autonomous driving, quantum computing, and photonic integration), the demand for low-power, high-density, high-performance, and high-reliability devices is growing. Hybrid bonding technology integrates semiconductors and devices (logic devices, memory, and image sensors) made of different materials into a single package to create multifunctional devices that meet these demands. Hybrid bonding simultaneously bonds dielectric layers and metal pads, utilizing optical alignment to ensure bonding accuracy and plasma activation to improve bond quality. However, incomplete cleaning of the bonding surface can leave residual particles or organic matter. During the bonding and annealing processes, rough bonding surfaces or uneven pressure and temperature can lead to interfacial voids. Furthermore, the mismatch in the thermal expansion coefficients of the dielectric layer and the metal pad can cause rapid temperature changes, leading to thermal stress concentration. This, combined with voids and contamination, can lead to delamination, desorption, and cracking, which can compromise bonding quality.

[0003] A Chinese invention patent with publication number CN114220783A discloses a hybrid bonding structure and a method for preparing the same. The hybrid bonding structure comprises first and second substrates disposed relative to each other and a bonding layer thereof, wherein the bonding layer comprises copper bonding points with a (110) preferred orientation. The hybrid bonding structure enhances the bonding strength and electrical connection between chips while also improving thermal stability and mechanical reliability. However, the preparation of the hybrid bonding structure involves complex processes such as photolithography, electroplating, polishing, plasma cleaning, and hot pressing bonding, requiring high-precision equipment and strict parameter control, posing challenges to process consistency, and is relatively expensive due to its reliance on specialized plating solutions and materials such as photoresist.

[0004] Chinese invention patent publication number CN116230631A discloses a method for preparing a metal interconnect structure, a metal interconnect structure, and a semiconductor component. The interconnect structure is formed by sequentially forming a barrier layer, a liner layer, a metal interconnect layer, and a cobalt layer within the interconnect grooves of a dielectric layer. However, the patent does not clearly define the bonding mechanism corresponding to the metal interconnect structure. When the metal interconnect structure is subsequently transferred for bonding, the cobalt layer is easily oxidized to form cobalt oxide, which hinders atomic diffusion at the cobalt-cobalt bonding interface, resulting in a decrease in bond strength and conductivity. Furthermore, the cobalt layer thickness and deposition cycles are limited to 30 nm and 300 times, respectively. In high-density interconnect structures with high aspect ratios or multi-layer stacks, more deposition cycles are often required to ensure uniform cobalt layer coverage.

[0005] Chinese invention patent publication number CN117877996A discloses a low-temperature, solid-state diffusion bonding process for nano-laminated Cu-Sn. By constructing a Cu / Sn / Cu / Sn / Cu / Sn / Cu micro-bumped laminate structure, the bonding temperature is reduced to 150-220°C by leveraging the melting point depression and size effects of nano-metals. This shortens the diffusion distance at the Sn-Cu interface, accelerates atomic diffusion, and controls the formation of intermetallic compounds. Depositing a nano-metal layer creates a highly active surface, which, combined with micro-bump pretreatment to prevent contamination, enables rapid, low-temperature, and low-damage bonding, improving production efficiency and reducing costs. However, nano-Sn has a lower melting point than conventional Sn (232°C), potentially melting and leaking during bonding, destroying the laminate structure. Nano-laminated layers easily form multiple Cu3Sn layers, and the tortuous diffusion paths during bonding can hinder long-range atomic migration. If the inert Au / Ag / Pt / Pd nanolayer deposited on the nano-metal layer is too thin, it is prone to cracking and failure, while if it is too thick, it can increase contact resistance.

[0006] In summary, hybrid bonding technology offers numerous advantages for simultaneously bonding dielectric layers and metal pads. However, existing hybrid bonding structures and fabrication methods, metal interconnect fabrication methods, and low-temperature solid-state diffusion bonding methods using nano-laminated layers present challenges such as complex processes, high costs, and the susceptibility of metal atoms on the bonding surface to oxidation. To fabricate highly reliable hybrid bonding structures, the development of novel hybrid bonding methods is urgently needed. Summary of the Invention

[0007] In view of the above-mentioned shortcomings of the existing technology, the present invention provides a hybrid bonding process that applies atomic layer deposition technology to reduce the impact of interface problems such as voids, contamination, and stress on bonding quality and bond structure reliability. To achieve the above-mentioned objectives, the present invention adopts the following technical solutions: A hybrid bonding method based on area-selective atomic layer deposition technology comprises the following steps: (1) Providing two substrates of the same size and shape, denoted as a first substrate and a second substrate; (2) Prepare a SiO2 dielectric layer on the substrate surface, spin-coat a photoresist, cover it with a patterned mask, and then perform photolithography exposure and development; (3) Patterned etching of the SiO2 dielectric layer to prepare blind vias, and magnetron sputtering to prepare metal pad arrays; (4) removing the photoresist and using ultraviolet nanoimprinting technology to prepare SiO2 support pillars and groove structures in the SiO2 dielectric layers of the first substrate and the second substrate, respectively; (5) combining the first substrate and the second substrate through the SiO2 support column and the groove structure, and then placing the combination in an atomic layer deposition chamber for regional selective metal interconnect layer deposition to achieve metal pad bonding; (6) Deposit a SiO2 dielectric layer in the atomic deposition chamber to fill the gaps in the assembly and complete hybrid bonding.

[0008] Preferably, in step (2), the SiO2 dielectric layer is formed by chemical vapor deposition; the thicknesses of the SiO2 dielectric layers of the first substrate and the second substrate are 1-10 µm and 1-5 µm, respectively.

[0009] Further preferably, the chemical vapor deposition method for preparing the SiO2 dielectric layer comprises the following steps: SiH4, O2 and N2 were used as Si source, oxidant and carrier gas, respectively, with flow rates of 50-200 sccm, 100-500 sccm and 100-500 sccm, respectively. The RF frequency and power were 13.56 MHz and 100-500 W, respectively. After the deposition was completed, the RF was stopped, the reaction gas was gradually turned off, and the carrier gas N2 was continued to be introduced to remove residual gas until the substrate cooled to room temperature.

[0010] Preferably, in step (2), after the SiO2 dielectric layer on the substrate surface is prepared, the substrate is annealed at 300-500°C for 30-90 min in a N2 environment to reduce defect density and residual stress.

[0011] Preferably, in step (3), the SiO2 dielectric layer on the substrate surface is pattern-etched using one of CF4, CHF3, and C4F8 gases, and the depth of the blind holes produced by etching is 0.4 to 2.5 μm.

[0012] Preferably, in step (3), the metal pad is cylindrical and is prepared by magnetron sputtering, with a diameter and thickness of 1-10 µm and 0.4-2.5 µm, respectively, and a spacing between the metal pads is 2-25 µm.

[0013] Further preferably, the preparation of the metal pad by magnetron sputtering comprises the following steps: The gas used for sputtering the metal target is Ar gas, the sputtering power and working pressure are 100~300 W and 2~5 mTorr, respectively, and the substrate temperature is 25~175 ℃. During sputtering, the distance between the metal target and the substrate is 50~150 mm, the Ar gas flow rate is 20~50 sccm, and the metal target is pre-sputtered to remove the surface oxide layer.

[0014] Preferably, in the step (3), before preparing the metal pad, a Ti boss with the same shape as the metal pad and a thickness of 50-200 nm can be prepared by magnetron sputtering in the blind hole of the SiO2 dielectric layer on the surface of the substrate as an adhesion layer to increase the adhesion between the metal pad and the substrate; in order to reduce internal stress and improve crystallinity, the substrate after the metal pad preparation is annealed at 150-300 ° C for 30-90 min in an N2 environment.

[0015] Preferably, in step (4), the prepared SiO2 support column and the groove structure match each other and are both cylindrical; the diameter and height of the SiO2 support column are 2~8 µm and 0.5~5 µm, respectively, and the diameter and depth of the groove structure are 2~8 µm and 0.4~4 µm, respectively.

[0016] Preferably, in step (4), the preparation process of the SiO2 support column and the groove structure includes the following steps: Deep ultraviolet lithography was used to fabricate the target structure on a quartz rigid substrate, followed by coating with an anti-sticking layer. PAK-01 liquid UV-curable resin was spin-coated on the surface of the SiO2 dielectric layer and then pre-baked at 80-100°C for 30-90 seconds to remove the solvent. The quartz rigid substrate was precisely aligned with the base, and a uniform pressure of 0.1-0.8 MPa was applied to tightly bond the substrate and resin. UV light was then transmitted through the mold to cure the resin, forming SiO2 support pillars or groove structures. The UV light wavelength and intensity were 365-405 nm and 10-100 mW / cm, respectively. 2 , the irradiation time is 10~60 s; the mold is slowly separated vertically, and the SiO2 dielectric layer is etched using one of CF4, CHF3, and C4F8 to transfer the substrate target structure to the SiO2 dielectric layer. O2-assisted etching is used to remove residual organic matter; finally, the substrate is soaked in acetone to strip off the UV-curable resin, and the substrate is rinsed with ultrapure water and blown dry with N2 to complete the preparation.

[0017] Preferably, in step (5) and step (6), the metal interconnect layer includes any one of Cu, Co, Pt, and Au, with a thickness of 0.2 to 11.2 µm; the deposition temperature is 100 to 200 °C; the assembly is not removed from the atomic deposition chamber after the metal interconnect layer deposition is completed, and a SiO2 dielectric layer is deposited after N2 purging and cleaning to fill the gaps in the assembly and complete hybrid bonding.

[0018] The substrates used in the above schemes can be made from Si wafers or Si cores commonly used in the art. When the substrate is made from a Si wafer, the size can be 2 inches, 4 inches, 6 inches, 8 inches, 10 inches, or 12 inches. When the substrate is made from Si cores, the shape can be square, trapezoidal, triangular, or any other shape.

[0019] Based on the above technical solutions, the design concept and principle of the present invention are as follows: This method utilizes atomic layer deposition (ALD) technology to provide atomically flat interface control. Through layer-by-layer deposition, film thickness can be precisely controlled to accommodate a wide range of bonding distances. Microscopic defects on the bonding surface can be repaired during deposition, and the flatness and cleanliness requirements for the bonding surface are relatively low. Chemical mechanical polishing and plasma activation treatment are not required before bonding, making the bonding process much simpler than traditional methods.

[0020] Furthermore, ALD technology offers exceptionally high step coverage and conformality, enabling multi-area and multi-pitch bonding without size limitations. This high step coverage and conformality enable seamless deposition of high-aspect-ratio trenches and holes, ensuring deposition continuity across the bonding interface.

[0021] In this process, atomic layer deposition technology has strong low-temperature process compatibility and integration capabilities. The deposition temperature of the interconnect layer and dielectric layer is only 100-200°C. There is no need to apply external mechanical force to promote bonding. No annealing is required after bonding, and no thermal damage will be caused to the substrate. The combined effects of thermal stress and external mechanical force can be avoided to cause warping or cracking of the substrate. It is suitable for multi-pitch bonding of multiple chips with different functions at the same time.

[0022] Compared with the prior art, the present invention has the following advantages and beneficial effects: The present invention provides a hybrid bonding method based on area-selective atomic layer deposition technology, which adopts atomic layer deposition technology to realize interconnect layer bonding and dielectric layer bonding. The bonding surface does not need to have high flatness and cleanliness. Microscopic defects of the bonding surface can be repaired during deposition, reducing the impact of contamination on bonding. The deposition bonding temperature is low to avoid thermal damage caused by high temperature. Multi-area and multi-spacing bonding can be performed simultaneously, and in principle there is no size restriction, which has broad application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A flow chart of hybrid bonding based on the area-selective atomic layer deposition technology provided by the present invention; Figure 2 Schematic diagram of the structure of the present invention after preparing a SiO2 dielectric layer on the surface of a substrate, spin-coating a photoresist, covering with a patterned mask, and performing exposure and development processes; wherein Fig. 2A is the first substrate, and Fig. 2B is the second substrate; Figure 3 Schematic diagram of the structure of the substrate after patterned etching of the SiO2 dielectric layer and magnetron sputtering to prepare the metal pad array provided by the present invention; wherein Fig. 3A represents the first substrate, and Fig. 3B represents the second substrate; Figure 4 Schematic diagram of the structure of the substrate after removing the photoresist provided by the present invention and using ultraviolet nanoimprint technology to prepare mutually matching SiO2 support columns and groove structures; wherein Fig. 4A represents the first substrate and Fig. 4B represents the second substrate.

[0024] Figure 5Fig. 5A shows a schematic diagram and a side view of the structure of the assembly formed by combining the substrate with the SiO2 support column and the groove structure provided by the present invention; and Fig. 5B shows a cross-sectional view of the assembly after metal pad deposition and bonding. Figure 6 FIG6A shows an X-ray diffraction pattern of the interconnect layer deposited between the metal pads of the assembly provided by the present invention; FIG6B shows a scanning electron microscope image of the cross-section of the bonding surface after depositing a SiO2 dielectric layer to fill the gaps in the assembly to achieve hybrid bonding; In the above figure: A1 represents the first substrate; A2 represents the SiO2 dielectric layer of the first substrate; A3 represents the second substrate; A4 represents the SiO2 dielectric layer of the second substrate; A5 represents the photoresist after spin coating, exposure and development on the surface of the SiO2 dielectric layer of the first substrate and the second substrate; A6 represents the metal pad array prepared by magnetron sputtering in the SiO2 dielectric layer of the first substrate and the second substrate; A7 represents the SiO2 support column prepared in the SiO2 dielectric layer of the first substrate; A8 represents the groove structure prepared in the SiO2 dielectric layer of the second substrate; A9 represents the interconnection layer deposited between the metal pads of the assembly. DETAILED DESCRIPTION

[0025] The present invention is further illustrated by way of examples below, but the present invention is not limited to the scope of the examples. Experimental methods in the following examples where specific conditions are not specified were performed according to conventional methods and conditions, or selected according to the product specifications.

[0026] Example 1 This embodiment provides a hybrid bonding method based on area selective atomic layer deposition technology, such as Figure 1 As shown in the flowchart, the steps are as follows: (1) Providing two substrates of the same size and shape, denoted as a first substrate and a second substrate; (2) Figure 2 Schematic diagram of the structure after preparing a SiO2 dielectric layer on the substrate surface, spin-coating photoresist, covering with a patterned mask, and performing exposure and development processes; The substrate is a square Si core with a side length of 5 mm and a thickness of 650 µm. The SiO2 dielectric layers of the first and second substrates are 6 µm and 4 µm thick, respectively, and are prepared by chemical vapor deposition. SiH4, O2, and N2 were used as the Si source, oxidant, and carrier gas, respectively, with flow rates of 100 sccm, 300 sccm, and 200 sccm, respectively. The RF frequency and power were 13.56 MHz and 300 W, respectively. After the deposition was completed, the RF was stopped, the reactive gases were gradually turned off, and the carrier gas N2 was continued to be introduced to purge residual gas until the substrate cooled to room temperature. The patterned photoresist, AZECI3000, was prepared on the SiO2 dielectric layer surfaces of the first and second substrates by spin coating, exposure, and development. The thickness of the photoresist was 2 µm. (3) Figure 3 Schematic diagram of the substrate structure after patterning the SiO2 dielectric layer and preparing the metal pad array by magnetron sputtering; The SiO2 dielectric layers of the first and second substrates were patterned with CF4. The resulting patterns consisted of arrayed circular blind vias with diameters of 5 µm and pitches of 20 µm, respectively. The difference was that the blind via depths in the SiO2 dielectric layer of the first substrate were 1.8 µm, while those in the second substrate were 0.8 µm. Magnetron sputtering was used to deposit an array of Cu pads to fill the arrayed circular vias. The Cu pads had a diameter of 5 µm and a thickness of 0.8 µm, respectively, with a pitch of 20 µm. A 99.999% pure Cu target was used for the sputtering. The Ar gas flow rate and substrate temperature were 30 sccm and 110 °C, respectively. The sputtering power and operating pressure were 200 W and 3 mTorr, respectively. (4) Figure 4 Schematic diagram of the substrate structure after UV nanoimprinting technology is used to prepare matching SiO2 support pillars and groove structures to remove the photoresist; The prepared SiO2 support column and groove structure match each other and are both cylindrical. The diameter and height of the SiO2 support column are 3 µm and 1 µm, respectively, and the diameter and depth of the groove structure are 3 µm and 0.8 µm, respectively. The specific preparation process is as follows: 1) Deep UV lithography is used to prepare the target structure on a hard quartz substrate, followed by coating with an anti-stick layer; 2) Spin-coat PAK-01 liquid UV-curable resin on the surface of the SiO2 dielectric layer and pre-bake at 90°C for 60 seconds to remove the solvent; 3) The quartz hard substrate was precisely aligned with the base, and a uniform pressure of 0.2 MPa was applied to tightly bond the substrate and the resin. The wavelength and energy of the light transmitted through the mold for 30 s were 365 nm and 30 mW / cm respectively. 2 UV light is used to cure the resin to form SiO2 support columns or groove structures; 4) Use CF4 to etch the SiO2 dielectric layer to transfer the substrate target structure to the SiO2 dielectric layer, and O2-assisted etching to remove residual organic matter; 5) Soaking the substrate in acetone to remove the UV-curable resin, rinsing with ultrapure water, and drying the substrate with nitrogen to complete the preparation; (5) Fig. 5A is a schematic diagram and side view of the structure after the substrate is combined to form an assembly through the SiO2 support column and the groove structure; Fig. 5B is a schematic cross-sectional view of the assembly after metal pad deposition and bonding; The Cu interconnect layer deposited between the metal pads has a thickness of 0.2 µm. The deposition temperature is 160 °C, and the inert carrier gas N2 flow rate is 300 sccm. The atomic layer deposition cycle is divided into two steps. The first step requires a Cu precursor Cu(acac)2 pulse for 3 seconds, an inert N2 purge for 4 seconds, an oxidant H2O pulse for 3 seconds, and an inert N2 purge for 4 seconds. The first step is repeated three times before the second step. The second step is a reducing agent HQ pulse for 2 seconds and an inert N2 purge for 3 seconds. The thickness of the Cu interconnect layer deposited after each deposition cycle is about 2.1 Å. (6) The thickness of the SiO2 dielectric layer used to fill the voids in the assembly is 0.2 µm, the deposition temperature is 175 °C, the plasma power is 100 W, and the inert carrier gas N2 flow rate is 200 sccm; the atomic layer deposition cycle is: Si source precursor 3DMAS pulse for 3 s, inert N2 purge for 10 s, plasma O2 pulse for 5 s, inert N2 purge for 10 s; the thickness of the deposited SiO2 dielectric layer after each deposition cycle is about 1.8 Å; Fig. 6A is an X-ray diffraction pattern of the interconnect layer deposited between the metal pads of the assembly, and Fig. 6B is a scanning electron microscope image of the cross-section of the bonding surface after the SiO2 dielectric layer is deposited to fill the voids in the assembly and achieve hybrid bonding. The results show that the Cu interconnect layer has a (111) preferred orientation, the bonding quality of the interconnect layer and the dielectric layer is good, and there is no void at the bonding interface.

[0027] Example 2 In this example, shear strength testing was conducted on the hybrid-bonded Si core particles prepared using area-selective atomic layer deposition in Example 1 at 25°C in an air atmosphere. The test results were compared with the shear strengths reported in the literature for hybrid bonding of wafers or core particles using different processes, as shown in Table 1.

[0028] Table 1: Comparison of shear strength between the hybrid bonded Si core particles prepared in Example 1 and the existing hybrid bond technology

[0029] Comparing the results in Table 1, we can see that among References 1 to 5, Reference 1 achieves the highest shear strength, at 22 MPa. The hybrid-bonded Si core particles produced in this embodiment achieve a shear strength of 32 MPa, significantly higher than those reported in existing processes and a 45% improvement over Reference 1, which achieved the highest shear strength.

[0030] In summary, the present invention uses atomic layer deposition technology to achieve interconnect layer bonding and dielectric layer bonding, with low requirements for bonding surface flatness and cleanliness; multi-area and multi-spacing bonding can be performed simultaneously, and in principle there is no size restriction. This process can repair microscopic defects on the bonding surface during deposition and reduce the impact of contamination on bonding. The deposition bonding temperature of the present invention is low, which can avoid thermal damage caused by high temperature. The present invention solves many defects of existing processes and has broad application prospects.

[0031] The above describes in detail the preferred embodiments of the present invention. It should be understood that those skilled in the art can make numerous modifications and variations based on the concepts of the present invention without inventive effort. Therefore, any technical solutions that can be derived by those skilled in the art through logical analysis, reasoning, or limited experimentation based on the concepts of the present invention and the prior art should be within the scope of protection defined by the claims.

Claims

1. A hybrid bonding method based on area selective atomic layer deposition technology, characterized in that: The steps include: (1) Providing two substrates of the same size and shape, denoted as a first substrate and a second substrate; (2) Prepare a SiO2 dielectric layer on the substrate surface, spin-coat a photoresist, cover it with a patterned mask, and then perform photolithography exposure and development; (3) Patterned etching of the SiO2 dielectric layer to prepare blind vias, and magnetron sputtering to prepare metal pad arrays; (4) removing the photoresist and using ultraviolet nanoimprinting technology to prepare SiO2 support pillars and groove structures in the SiO2 dielectric layers of the first substrate and the second substrate, respectively; (5) combining the first substrate and the second substrate through the SiO2 support column and the groove structure, and then placing the combination in an atomic layer deposition chamber for regional selective metal interconnect layer deposition to achieve metal pad bonding; (6) Deposit a SiO2 dielectric layer in the atomic deposition chamber to fill the gaps in the assembly and complete hybrid bonding.

2. The hybrid bonding method based on area-selective atomic layer deposition technology according to claim 1, characterized in that: In the step (2), the SiO2 dielectric layer is formed by chemical vapor deposition; the thickness of the SiO2 dielectric layer of the first substrate and the second substrate are 1-10 μm and 1-5 μm respectively.

3. The hybrid bonding method based on area selective atomic layer deposition technology according to claim 2, characterized in that: The chemical vapor deposition method for preparing the SiO2 dielectric layer comprises the following steps: SiH4, O2 and N2 were used as Si source, oxidant and carrier gas, respectively, with flow rates of 50-200 sccm, 100-500 sccm and 100-500 sccm, respectively. The RF frequency and power were 13.56 MHz and 100-500 W, respectively. After the deposition was completed, the RF was stopped, the reaction gas was gradually turned off, and the carrier gas N2 was continued to be introduced to remove residual gas until the substrate cooled to room temperature.

4. The hybrid bonding method based on area-selective atomic layer deposition technology according to claim 1, characterized in that: In the step (2), after the SiO2 dielectric layer on the substrate surface is prepared, the substrate is annealed at 300-500°C for 30-90 min in a N2 environment.

5. The hybrid bonding method based on area-selective atomic layer deposition technology according to claim 1, characterized in that: In the step (3), the SiO2 dielectric layer on the substrate surface is patterned and etched using one of CF4, CHF3, and C4F8 gases, and the depth of the etched blind holes is 0.4 to 2.5 μm; The metal pads are cylindrical and prepared by magnetron sputtering. The diameter and thickness are 1~10 μm and 0.4~2.5 μm, respectively. The metal pad spacing is 2~25 μm.

6. The hybrid bonding method based on area selective atomic layer deposition technology according to claim 5, characterized in that: The magnetron sputtering method for preparing the metal pad comprises the following steps: The gas used for sputtering the metal target is Ar gas, the sputtering power and working pressure are 100~300 W and 2~5 mTorr, respectively, and the substrate temperature is 25~175 ℃. During sputtering, the distance between the metal target and the substrate is 50~150 mm, the Ar gas flow rate is 20~50 sccm, and the metal target is pre-sputtered to remove the surface oxide layer.

7. The hybrid bonding method based on area-selective atomic layer deposition technology according to claim 1, characterized in that: In the step (3), before preparing the metal pad, a Ti boss with a shape identical to that of the metal pad and a thickness of 50 to 200 nm is prepared by magnetron sputtering in a blind hole of the SiO2 dielectric layer on the surface of the substrate as an adhesion layer; the substrate after the metal pad preparation is annealed at 150 to 300 ° C in an N2 environment for 30 to 90 min.

8. The hybrid bonding method based on area-selective atomic layer deposition technology according to claim 1, characterized in that: In the step (4), the SiO2 support column and the groove structure match each other and are both cylindrical; the diameter and height of the SiO2 support column are 2~8 μm and 0.5~5 μm, respectively, and the diameter and depth of the groove structure are 2~8 μm and 0.4~4 μm, respectively.

9. The hybrid bonding method based on area selective atomic layer deposition technology according to claim 1, characterized in that: In step (4), the preparation process of the SiO2 support column and groove structure includes the following steps: Deep ultraviolet lithography was used to fabricate the target structure on a quartz rigid substrate, followed by coating with an anti-sticking layer. PAK-01 liquid UV-curable resin was spin-coated on the surface of the SiO2 dielectric layer and then pre-baked at 80-100°C for 30-90 seconds to remove the solvent. The quartz rigid substrate was precisely aligned with the base, and a uniform pressure of 0.1-0.8 MPa was applied to tightly bond the substrate and resin. Ultraviolet light was then transmitted through the mold to cure the resin, forming SiO2 support pillars or groove structures. The UV light wavelength and intensity were 365-405 nm and 10-100 mW / cm, respectively. 2 , the irradiation time is 10~60 s; the mold is slowly separated vertically, and the SiO2 dielectric layer is etched using one of CF4, CHF3, and C4F8 to transfer the substrate target structure to the SiO2 dielectric layer. O2-assisted etching is used to remove residual organic matter; finally, the substrate is soaked in acetone to strip off the UV-curable resin, and the substrate is rinsed with ultrapure water and blown dry with N2 to complete the preparation.

10. The hybrid bonding method based on area-selective atomic layer deposition technology according to claim 1, characterized in that: In the steps (5) and (6), the metal interconnection layer includes any one of Cu, Co, Pt, and Au, and has a thickness of 0.2 to 11.2 μm; the deposition temperature is 100 to 200 °C; the assembly is not removed from the atomic deposition chamber after the metal interconnection layer deposition is completed, and a SiO2 dielectric layer is deposited after N2 purging and cleaning to fill the gaps in the assembly and complete hybrid bonding.

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