Method for suppressing zero crossing point current distortion of interleaving parallel totem pole PFC charger

Abstract

The invention discloses a method for suppressing zero crossing point current distortion of an interleaving parallel totem pole PFC charger, and belongs to the technical field of chargers. According to the method, two stages are divided at an alternating-current voltage zero crossing point, soft start is performed on upper and lower switch tubes of a high-frequency bridge arm respectively, and a current peak caused by sudden change of a duty ratio is avoided; meanwhile, a current loop controller is adopted to output signals to control a power frequency switching tube, and phase delay caused by a power inductor is compensated. Simulation results show that the method enables the total input current THD to be reduced by 1.51%, improves the power factor, does not need extra hardware, reduces the cost, is easy to implement, and is suitable for the field of medium and high power chargers.

Description

Technical Field

[0001] The present invention belongs to the technical field of chargers and relates to a method for suppressing zero-crossing current distortion of an interleaved parallel totem pole PFC (Power Factor Correction) charger. Background Art

[0002] In recent years, new energy vehicles, primarily electric vehicles, have experienced rapid development, and the number of electric vehicles in my country has rapidly increased. Charging electric vehicles has become a hot topic. Chargers typically employ a two-stage design. The front-stage AC / DC converter must implement power factor correction and output a stable DC voltage to the downstream circuit. The totem pole bridgeless PFC circuit is currently the mainstream circuit due to its advantages, including fewer components in the power circuit, low conduction losses, high efficiency, and low common-mode noise. The interleaved parallel totem pole PFC charger topology builds on this design by adding an inductor and a switching leg, creating a structure where two full-bridge circuits share a single power-frequency leg. This topology divides the input current, reducing current stress and cost on the switching components. When operating, the input current is the sum of the inductor currents of the two switching ripples, which are 180° out of phase. This reduces the peak-to-peak ripple of the input current, doubles the ripple frequency, and reduces harmonic content. This improves the power factor and reduces input current harmonics and EMI. Because the body diode of traditional Si MOSFETs has large reverse recovery losses during turn-off, they are usually only suitable for discontinuous conduction mode (DCM) and critical conduction mode (CRM). However, with the increasing popularity of third-generation wide-bandgap semiconductors, the fast recovery characteristics of the body diode of SiC MOSFETs have enabled interleaved parallel totem-pole PFC chargers to adopt the continuous conduction mode (CCM) of the inductor current in medium and high power applications, achieving higher efficiency.

[0003] While interleaved parallel totem-pole PFC chargers offer numerous advantages, they also suffer from inductor current distortion at the input voltage zero-crossing point in CCM operation, severely impacting the input current THD and power factor correction. To address this issue, the paper (Xue L, Shen Z, Boroyevich D, et al. GaN-based high-frequency totem-pole bridgeless PFC design with digital implementation [C] / / Applied Power Electronics Conference & Exposition. IEEE, 2015. DOI: 10.1109 / APEC.2015.7104435.) investigated the causes of zero-crossing current distortion and proposed a solution that reserves transmission delay for the low-frequency bridge leg and uses digital dithering to increase the equivalent resolution of the high-frequency bridge leg to improve the minimum pulse limit. The literature (Zhang B, Lin Q, Shimada Y, et al. Analysis and reduction method of conducted noise inGaN HEMTs based totem-pole bridgeless PFC converter[C] / / Power Electronics &Motion Control Conference. IEEE, 2016. DOI:10.1109 / IPEMC.2016.7512298.) adds an additional set of capacitor bridge arms and auxiliary circuits, and absorbs current spikes by controlling the additional circuits at the zero-crossing point, which increases the cost of emergency design. The paper (Fan WT, Yeung SC, Chung SH. Optimized hybrid PWM scheme for mitigating zero-crossing distortion in totem-pole bridgeless PFC[C] / / 2018 IEEE Applied Power Electronics Conference and Exposition (APEC). IEEE, 2018. DOI:10.1109 / APEC.2018.8341299.) proposes a hybrid pulse-width modulation scheme that dynamically changes the switching signal of the switching tube at the zero-crossing point according to six different bridge arm midpoint voltage conditions to reduce current distortion.

[0004] However, for the technical problem of zero-crossing current distortion in interleaved parallel totem-pole PFC chargers, the existing solutions are generally too complicated, resulting in a significant increase in costs. There is an urgent need for a simple and easy method that does not require additional hardware circuits to solve the above technical problem. Summary of the Invention

[0005] The purpose of the present invention is to provide a method for suppressing zero-crossing current distortion in an interleaved parallel totem-pole PFC charger. Based on an in-depth analysis of the operating principle of the interleaved parallel totem-pole PFC charger circuit in CCM mode and the reasons why the total input current is distorted at the zero-crossing point, a zero-crossing optimization scheme is proposed. This scheme soft-starts the high-frequency bridge arm switches by dividing the AC voltage into two different stages at the zero-crossing point, and uses the output signal of the current loop controller in a dual closed-loop control system instead of the input voltage signal to control the switching of the power-frequency bridge arm switches. Compared with other existing zero-crossing optimization schemes, the optimization scheme proposed in the present invention does not require additional hardware circuits, saving costs, and the control algorithm is easier to implement and more reliable. SIMULINK simulation results show that this control strategy effectively reduces current distortion at the zero-crossing point, improves the waveform quality of the total input current, reduces the total voltage difference (THD) by 1.51%, and improves the full-load power factor (PF) value and efficiency of the system. The objectives of the present invention are achieved through the following specific technical solutions.

[0006] A method for suppressing zero-crossing current distortion in an interleaved parallel totem-pole PFC charger is disclosed. The circuit topology of the interleaved parallel totem-pole PFC charger includes two sets of high-frequency bridge arms, one set of power-frequency bridge arms, and two power inductors. The high-frequency bridge arms include upper and lower switching tubes, and the switching tubes of the two sets of high-frequency bridge arms both use SiC MOSFETs. The power-frequency bridge arms include two power-frequency switching tubes, each using Si MOSFETs. Two power inductors are connected in series with the two sets of high-frequency bridge arms, and the current ripple phase of the two inductors is 180 degrees apart. The method includes: dividing the control stage at the zero-crossing point of the AC input voltage into two stages, soft-starting the upper and lower switching tubes of the high-frequency bridge arms, respectively; and using the output signal of the current loop controller as the control signal of the power-frequency switching tube to compensate for the phase delay caused by the power inductor. The method provided by the present invention, through a targeted control strategy, not only utilizes the reverse recovery characteristics of SiC MOSFETs to adapt to the CCM mode, but also suppresses zero-crossing distortion through two-stage soft start and phase compensation, thereby reducing the total input current THD and improving the power factor.

[0007] Furthermore, the two control stages are specifically: From t0 to t1: the lower switch tubes of one of the high-frequency bridge arms are controlled to turn on at a preset small duty cycle, and the corresponding upper switch tubes are turned off until the duty cycle of the lower switch tube transitions to the actual operating duty cycle; From t1 to t2: the upper switch tube of the high-frequency bridge arm is controlled to be turned on with a preset small duty cycle, and the corresponding switch tube of the power-frequency bridge arm is turned on until the duty cycle of the upper switch tube transitions to the actual working duty cycle.

[0008] By soft-starting the upper and lower tubes of the high-frequency bridge arm in stages, sudden duty cycle changes during the positive and negative half-cycle switching are avoided, positive and negative current spikes are suppressed, and the zero-crossing current transition is smoothed.

[0009] Furthermore, the initial value of the preset small duty cycle is 0.1-0.3, and the actual operating duty cycle is reached within 5-10 switching cycles through a linear increase. The duty cycle is slowly adjusted to reduce current surges, further reduce distortion, and ensure dynamic response speed.

[0010] Furthermore, the current loop controller is the inner loop controller in a dual closed-loop voltage and current control system. Its output signal is a duty cycle signal corresponding to the bridge arm midpoint voltage, with the same polarity as the bridge arm midpoint voltage. This duty cycle signal, with the same polarity as the bridge arm midpoint voltage, is used as the switching criterion for the power-frequency switching transistors, accurately compensating for phase shifts caused by power inductors and avoiding current spikes caused by bus voltage during the delay period.

[0011] Furthermore, the two high-frequency bridge arms and the power-frequency bridge arm each form two independent boost circuits, with the control signals of the two boost circuits 180° out of phase. This staggered parallel structure shunts the input current, reducing current stress on the switching devices. The combined total input current ripple is reduced, and zero-crossing control further reduces harmonic content.

[0012] Furthermore, at time t3-t4, when the AC voltage transitions from the positive half-cycle to the negative half-cycle, the switches in all high-frequency and power-frequency bridge arms are turned off, and the integral value of the current loop controller is cleared. This prevents excessive duty cycle output caused by controller integral accumulation, prevents reverse current spikes caused by energy backflow, and further optimizes zero-crossing distortion.

[0013] Furthermore, the AC input voltage zero-crossing point is determined by determining if its absolute value is less than a preset threshold value, which is 5 to 10 V. Accurately identifying the zero-crossing interval ensures that soft-start and phase compensation strategies are only effective during distortion-prone intervals, avoiding impacts on circuit stability during normal operation.

[0014] Furthermore, the output signal of the current loop controller is logically conditioned to directly drive the power-frequency switching tube. The conditioning logic is as follows: when the output signal is positive, the lower switching tube in the power-frequency bridge arm is turned on; when the output signal is negative, the upper switching tube in the power-frequency bridge arm is turned on. This achieves synchronized switching of the power-frequency switching tube and the high-frequency bridge arm, eliminating the additional bus voltage action time caused by phase delay and fundamentally suppressing delay-induced current distortion.

[0015] Furthermore, the total duration of the t0-t1 and t1-t2 phases is 50-100 μs and does not exceed 1 / 10 of half a power frequency cycle, thereby ensuring distortion suppression while preventing excessively long transition times from affecting the circuit's dynamic response and output voltage stability.

[0016] Furthermore, the interleaved parallel totem-pole PFC charger operates in continuous conduction mode (CCM), with the two power inductors having equal inductance values ​​of 50-100 μH. This makes it suitable for medium- and high-power applications. The equal inductance ensures symmetrical superposition of the two current ripples, reducing the total input current ripple. Zero-crossing control is also used to further optimize THD.

[0017] Compared to existing technologies, this invention offers the following beneficial technical advantages: It eliminates the need for additional auxiliary circuitry, saving costs; the control algorithm is easier to implement, and reliability is enhanced. It effectively suppresses zero-crossing current distortion, reduces input current THD, and improves power factor, making it suitable for high-efficiency, high-power-density charging equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is the circuit topology diagram of the interleaved parallel totem pole PFC charger.

[0019] Figure 2 This is a graph showing the change in duty cycle of a high-frequency switching tube.

[0020] Figure 3 It is the voltage and current dual closed-loop control algorithm diagram.

[0021] Figure 4 This is a schematic diagram of the cause of current spikes.

[0022] Figure 5 It is the equivalent model of the converter and the vector diagram of input voltage, current and bridge arm midpoint voltage.

[0023] Figure 6 It is a schematic diagram of the zero-crossing optimization solution of the present invention.

[0024] Figure 7 This is a schematic diagram of the optimized control flow.

[0025] Figure 8 This is a schematic diagram of the experimental circuit.

[0026] Figure 9 This is the total input current waveform before optimization.

[0027] Figure 10 This is the total input current waveform after optimization.

[0028] Figure 11This is the current THD analysis result diagram before optimization.

[0029] Figure 12 This is the current THD analysis result diagram after optimization. DETAILED DESCRIPTION

[0030] The following is a clear and complete description of the technical solution of the present invention in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present invention.

[0031] In the description of the present invention, it should be understood that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "back," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like, indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate description and simplify the present invention. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance, quantity, or position.

[0032] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediate medium; and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0033] The circuit topology of the interleaved parallel totem pole PFC charger is as follows: Figure 1As shown, Q1-Q4 are high-frequency switches, and S1 and S2 are power-frequency switches. To ensure that the interleaved parallel totem-pole PFC charger circuit can be used in high-power applications and achieve high efficiency even in CCM mode, the switches Q1-Q4 in the high-frequency bridge arm typically use wide-bandgap semiconductor devices with no reverse recovery issues, such as SiC MOSFETs. The switches S1 and S2 in the power-frequency bridge arm use conventional Si MOSFETs. The two high-frequency bridge arms of this circuit can be equivalent to two independent boost circuits with the power-frequency bridge arm. Each boost circuit is independently controlled and has no coupling relationship with the other. The two inductor current ripples differ by half a carrier cycle, resulting in a total input current ripple that is less than or equal to the single-phase inductor current ripple.

[0034] When the circuit is working, in the positive half cycle of the input voltage, the lower switch tubes Q2 and Q4 of the two high-frequency bridge arms are defined as the main control switch tubes, the upper bridge arm switch tubes Q1 and Q3 are used as freewheeling tubes, and the lower switch tube S2 of the power frequency bridge arm remains on. The upper and lower tube drive signals of the same bridge arm are complementary and leave a dead zone; similarly, in the negative half cycle of the circuit, the upper switch tubes Q1 and Q3 of the two high-frequency bridge arms are defined as the main control switch tubes, the lower bridge arm switch tubes Q2 and Q4 are used as freewheeling tubes, and the upper switch tube S1 of the power frequency bridge arm remains on. This working mode causes the duty cycle values ​​of the high-frequency tubes Q1~Q4 to be discontinuous within a power frequency cycle, and have a large span at the zero crossing point of the input voltage. Taking the lower switch tube Q2 of the first high-frequency bridge arm as an example, its duty cycle diagram within a complete power frequency cycle of the grid voltage is shown as follows. Figure 2 As shown in Figure 1, switch Q2 functions as a main current controller during the positive half-cycle of the grid voltage and as a freewheeling current controller during the negative half-cycle. When the grid voltage crosses zero from the positive half-cycle to the negative half-cycle, the duty cycle of switch S2 drops sharply from nearly 1 to near 0. This operating characteristic can lead to zero-crossing distortion of the total input current.

[0035] In terms of control algorithm, the instantaneous direct current control algorithm in CCM mode consists of a double closed loop consisting of a voltage outer loop and a current inner loop, so it is also called a double closed loop control algorithm. Its control structure is as follows: Figure 3 This algorithm has the advantages of fast dynamic response, small grid-side input current harmonics, and stable DC-side output voltage. Currently, this control algorithm is widely used in interleaved parallel totem-pole PFC charger circuits.

[0036] In CCM operation mode, the interleaved parallel totem pole PFC charger circuit will generate a current spike at the grid voltage zero crossing point. The main reasons are as follows:

[0037] Reason 1: The current spike caused by the sudden change of duty cycle caused by the switching of the main control switch tube in the positive and negative half cycles, such as Figure 4 shown.

[0038] During the positive and negative half-cycles of the input AC voltage, the upper and lower switches Q1 and Q2 of the high-frequency bridge arm alternately function as the main control switches. This functional switching causes a discontinuity in the high-frequency switch duty cycle near the AC voltage zero-crossing point. For example, at the instant the input AC voltage changes from positive to negative, Q2's duty cycle abruptly changes from 1 to 0. Due to the functional switching, Q1, the freewheeling transistor, also experiences a sudden change in duty cycle from 0 to 1. Because the power-frequency bridge arm uses a standard Simos transistor, its reverse recovery time is relatively long. At the same time, the voltage across the parasitic capacitance of upper switch S1 is still the DC bus voltage. When switch Q1 is suddenly turned on with a duty cycle close to 1, the voltage applied to the power inductor includes not only the input AC voltage but also the DC bus voltage across parasitic capacitance C1. However, in the actual control loop, the voltage parameter used for calculation is still only the AC input voltage, resulting in a large positive spike in the current waveform.

[0039] When the circuit enters the negative half-cycle, during the dead time of the power-frequency bridge arm, the upper and lower tubes of the high-frequency bridge arm will be turned on in a complementary manner. When the lower tube Q1 is turned off and the upper tube Q2 is turned on with a duty cycle of 1-D, although the duty cycle is very small, the AC input voltage is near the zero point at this time, and the normal inductor current cannot be established. At this time, part of the energy on the DC bus capacitor will flow through the inductor and back into the input end. When this backflow energy passes through the inductor, it will generate a current opposite to the input voltage, resulting in a negative current spike on the inductor.

[0040] Reason 2: The voltage drop caused by the power inductor and the current spike caused by the phase deviation.

[0041] When considering the influence of power inductance, the equivalent model of the circuit is as follows Figure 5 As shown on the left. The difference between the midpoint voltage of the high-frequency bridge arm and the power-frequency bridge arm is V ab It can be expressed as:

[0042] Where V ab Represents the midpoint voltage between the first high-frequency bridge arm and the power-frequency bridge arm, in V; V in Represents the input grid voltage, unit is V; θ represents the phase deviation caused by the power inductor, IL represents the power inductor current, unit is A.

[0043] In this case, the input voltage V in , inductor current IL and bridge arm midpoint voltage V ab The relationship diagram is as follows Figure 5 As shown on the right. Figure 5 It can be seen that near the zero-crossing point of the AC input voltage, the input voltage V in will be equal to the bridge arm midpoint voltage Vab There will be a phase difference θ. If the traditional voltage and current dual closed-loop control strategy is used, and the input voltage polarity is used as the signal to judge the switching of the power frequency switch tube, the switching signal of the low-frequency bridge arm will lag behind the switching signal of the high-frequency bridge arm. During this delay time t d Internal bus voltage V bus It will act additionally on the inductor, generating a current spike of the magnitude shown in the following formula.

[0044]

[0045] Where, I peak Represents the peak value of the distorted current, in A; V bus Represents the output bus voltage, in V; t d represents the delay time of the switching signal lag, in seconds; L represents the power inductance, in μH.

[0046] Based on the above in-depth analysis of the causes of zero-crossing current distortion in the interleaved parallel totem pole PFC charger, the present invention proposes an optimization scheme based on soft start of high-frequency switching tubes at zero-crossing points and combined with phase delay compensation control of the bridge arm midpoint voltage. The specific implementation method is as follows: Figure 6 shown.

[0047] Before optimization, all bridge arm switches were off during this time. After optimization, when the AC voltage crosses zero, switch Q2 is turned on with a very small duty cycle, while switch Q1 is turned off. After several cycles, at t1, switch Q2 expands to its actual duty cycle, D. During this time, switch S1 completes reverse recovery, and the drain-source voltage of switch S2 slowly decreases to zero, suppressing the current spike caused by the sudden turn-on of switch Q2.

[0048] From t1 to t2: Before optimization, after switch Q2's soft-start completes, switch Q1, acting as a synchronous rectifier, turns on in a complementary fashion. After optimization, at t1, switch Q1 is soft-started, and switch S2 is simultaneously turned on. By t2, the duty cycle of switch Q1 reaches a true 1-D value. Because reverse recovery of switch S1 has already completed at this point, arm shoot-through is eliminated. The soft-start operation of synchronous rectifier switch Q1 mitigates current backflow caused by a large potential difference between the AC input voltage and the DC bus voltage. When the duty cycle of switch Q1 is low, the on-time is short, minimizing the generation of significant reverse current. This suppresses negative current spikes in the inductor caused by the bus voltage.

[0049] Time t2~t3: normal operation time period of the positive half cycle of the power frequency cycle; Between t3 and t4, before the AC input voltage transitions from the positive half-cycle to the negative half-cycle, all switches are turned off. Simultaneously, before the negative half-cycle begins, the controller's integral value must be cleared to prevent excessively high integral accumulation, which could lead to an excessively high duty cycle. While a soft-start strategy for switches sacrifices some current at the zero-crossing point, it effectively suppresses the resulting spikes.

[0050] At the same time, based on the previous analysis, we can know that the bridge arm midpoint voltage V ab It is the most reasonable to use it as the switching signal of the power frequency switch tube. However, in the actual circuit, the bridge arm midpoint voltage V ab It is a DC square wave signal containing a large number of harmonics. It is difficult to obtain accurately and will increase the hardware cost. In the voltage and current dual closed-loop control model proposed in the previous analysis, the signal output by the current loop controller is the bridge arm midpoint duty cycle d ab It can be expressed as:

[0051] Where, d ab Represents the duty cycle of the midpoint voltage between the first high-frequency bridge arm and the power-frequency bridge arm; V bus Represents the output bus voltage, in V; V ab Represents the midpoint voltage between the first high-frequency bridge arm and the power-frequency bridge arm, in V; V in Represents the input grid voltage, in V; θ represents the phase deviation caused by the power inductor.

[0052] From the above formula, we can see that the polarity of the signal is related to the bridge arm midpoint voltage V ab The polarity is consistent, so the current loop controller output signal can be used instead of the input voltage V in As the judgment standard for the power-frequency switch drive signal, the optimized control block diagram is shown in Figure 7. Since all gate signals of the switch are based on the control loop output of the current inner loop, phase delay and current spikes are effectively suppressed.

[0053] In order to verify the effectiveness of the method for suppressing zero-crossing current distortion provided by the present invention, a 6.6kW staggered parallel totem pole PFC charger circuit was constructed in MATLAB / SIMULINK simulation software for simulation experiments. The input voltage was set to 220V, 50Hz AC, the output DC bus voltage range was 400-600V, and the switching frequency was set to 100kHz. The simulation experimental circuit is shown in Figure 1. Figure 8 shown.

[0054] The total input current waveform IL before and after applying the optimization scheme is as follows: Figure 9 、 Figure 10 shown.

[0055] Comparative Analysis Figure 9 、 Figure 10 It can be seen that when the traditional control strategy is adopted, there will be obvious current distortion at the zero-crossing point, and the current waveform is not sinusoidal. After adopting the zero-crossing optimization scheme proposed in this invention, there is no obvious current distortion at the zero-crossing point, the transition is smoother, and the quality of the current waveform is improved. The total harmonic distortion (THD) and power factor (PF) of the current under the two schemes are shown as follows: Figure 11 、 Figure 12 As shown in Table 1.

[0056] Table 1 Total input current THD and system power factor PF before and after optimization

[0057] Depend on Figure 11 、 Figure 12 From the comparative analysis of Table 1, it can be seen that the method provided by the present invention is used to suppress the distortion of the current at the zero-crossing point, which can significantly reduce the total THD value of the input current, improve the quality of the current waveform, and help to improve the PF value of the entire system, thereby achieving a better power factor correction effect.

[0058] Although the embodiments of the present invention have been shown and described above, it should be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art may make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention without departing from the principles and intent of the present invention. The scope of protection of the present invention is defined by the claims and their equivalents.

Claims

1. A method for suppressing zero-crossing current distortion in an interleaved parallel totem-pole PFC charger. The circuit topology of the interleaved parallel totem-pole PFC charger includes two sets of high-frequency bridge arms, one set of power-frequency bridge arms, and two power inductors. The high-frequency bridge arms include upper and lower switching transistors, and the switching transistors of the two sets of high-frequency bridge arms are both SiC MOSFETs. The power-frequency bridge arm includes two power-frequency switching transistors, each of which is Si MOSFET. Two power inductors are connected in series with the two sets of high-frequency bridge arms, and the current ripples of the two inductors are 180° out of phase. The method is characterized in that: The method includes: dividing the control phase into two stages at the zero-crossing point of the AC input voltage, soft-starting the upper and lower switches of the high-frequency bridge arm respectively; and using the output signal of the current loop controller as the control signal of the power frequency switch to compensate for the phase delay caused by the power inductor.

2. The method according to claim 1, characterized in that The two control stages are specifically: From t0 to t1: the lower switch tubes of one of the high-frequency bridge arms are controlled to turn on at a preset small duty cycle, and the corresponding upper switch tubes are turned off until the duty cycle of the lower switch tube transitions to the actual operating duty cycle; From t1 to t2: the upper switch tube of the high-frequency bridge arm is controlled to be turned on with a preset small duty cycle, and the corresponding switch tube of the power-frequency bridge arm is turned on until the duty cycle of the upper switch tube transitions to the actual working duty cycle.

3. The method according to claim 2, characterized in that The initial value of the preset small duty cycle is 0.1-0.3, and the actual working duty cycle is reached within 5-10 switching cycles in a linear increasing manner.

4. The method according to claim 1, wherein The current loop controller is an inner loop controller in the voltage-current dual closed-loop control, and its output signal is a duty cycle signal corresponding to the bridge arm midpoint voltage, and the polarity of the signal is consistent with the polarity of the bridge arm midpoint voltage.

5. The method according to claim 1, wherein The two groups of high-frequency bridge arms and the industrial frequency bridge arm respectively constitute two independent Boost circuits, and the control signals of the two Boost circuits have a phase difference of 180°.

6. The method according to claim 2, characterized in that At time t3~t4 when the AC voltage transitions from the positive half cycle to the negative half cycle, the switch tube drivers of all high-frequency bridge arms and power-frequency bridge arms are turned off, and the integral value of the current loop controller is cleared.

7. The method according to claim 1, characterized in that The basis for judging the zero-crossing point of the AC input voltage is that the absolute value of the input voltage is less than a preset threshold, and the preset threshold is 5~10V.

8. The method according to claim 4, characterized in that The output signal of the current loop controller directly drives the power frequency switch tube after logic conditioning. The conditioning logic is: when the output signal is positive, the switch tube at the lower power frequency bridge arm is controlled to be turned on; when the output signal is negative, the switch tube at the upper power frequency bridge arm is controlled to be turned on.

9. The method according to claim 2, characterized in that The total duration of the t0-t1 and t1-t2 phases is 50-100 μs and does not exceed 1 / 10 of half a power frequency cycle.

10. The method according to claim 1, characterized in that The interleaved parallel totem pole PFC charger operates in a continuous conduction mode, and the inductance values ​​of the two power inductors are equal, both 50-100 μH.

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