Multiphase filter STFT resource optimization method based on time multiplexing constant multiplication

Abstract

The invention relates to a multiphase filter STFT resource optimization method based on time multiplexing constant multiplication, and belongs to the technical field of signal time frequency analysis. Comprising a Tm-SCM optimization method and / or a Tm-MCM optimization method; the Tm-SCM optimization method comprises the following steps: generating a DAG; carrying out matrix modeling; matrix selection based on a genetic algorithm; carrying out matrix merging and time multiplexing DAG generation; the Tm-MCM optimization method comprises the steps of matrix selection and time multiplexing. According to the method, a hardware circuit can be conveniently generated by re-optimizing window function coefficients of different types and lengths, so that the window functions are quickly switched and upgraded, the limitation that the window functions of the traditional architecture are fixed and difficult to change is broken through, and the resource overhead of constant multiplication is reduced while the real-time performance is ensured.

Description

Technical Field

[0001] The invention relates to a STFT resource optimization method based on time multiplexing constant multiplication, and belongs to the technical field of signal time-frequency analysis. Background Art

[0002] The short-time Fourier transform (STFT) is a fundamental tool for signal time-frequency analysis. Its hardware implementation typically adopts two architectures: the traditional FFT-based architecture and the polyphase filter-based architecture. The FFT-based architecture directly performs the FFT on the data within a sliding window to obtain the spectrum. Each window shift involves re-multiplying the window and recalculating the FFT. This approach is simple to implement, but in scenarios with high overlap, it involves significant repetitive computations and low hardware resource utilization. Furthermore, FFT processing requires a single buffer of data for the entire window length, impacting real-time performance and latency. Furthermore, switching window functions or lengths lacks flexibility. The polyphase filter architecture combines the sliding window and FFT into a filter bank, achieving equivalent frequency band decomposition. This architecture avoids repetitive computations for STFTs with a fixed overlap ratio, improving efficiency. However, the trade-off is the need for numerous constant coefficient multiplications (corresponding to the window function coefficients) in the filter implementation, often consuming significant multiplier resources (LUTs / registers or DSP units). Current traditional implementations typically allocate a single multiplier for each window coefficient or use a lookup table, which incurs significant resource overhead when the window length is long. Attempting to reuse fewer multipliers using time-division multiplexing introduces additional control and timing complexity, increasing design difficulty and potential delays. Consequently, existing STFT architectures are limited in terms of hardware resources, flexibility, and latency. Either they consume too much resources to be efficiently implemented on FPGAs / ASICs, or they reduce resources at the expense of system throughput or increase design complexity. The implementation of window function multipliers presents a bottleneck—reducing the resource overhead of these constant multiplication operations while ensuring real-time performance is a pressing issue facing existing technologies.

[0003] Therefore, it is urgent to propose a polyphase filter STFT resource optimization method based on time-reuse constant multiplication to solve the above technical problems. Summary of the Invention

[0004] To solve the above problems, a polyphase filter STFT resource optimization method based on time-reuse constant multiplication is provided. A brief summary of the present invention is provided below to provide a basic understanding of certain aspects of the present invention. It should be understood that this summary is not an exhaustive summary of the present invention. It is not intended to identify key or important parts of the present invention, nor is it intended to limit the scope of the present invention.

[0005] The technical solution of the present invention: A polyphase filter STFT resource optimization method based on time multiplexing constant multiplication, including: a Tm-SCM optimization method and / or a Tm-MCM optimization method; The Tm-SCM optimization method includes the following steps: DAG generation; Matrix modeling; Matrix selection based on genetic algorithm; Matrix merging and time-multiplexed DAG generation; The Tm-MCM optimization method includes: matrix selection and time multiplexing.

[0006] Preferably: the Tm-SCM optimization method is based on the Tm-SCM architecture, the Tm-SCM architecture includes a first delay module, a Tm-SCM module and a first FFT module, the output ends of the four groups of Tm-SCMs set for parallel processing are connected to the first FFT module, and the input ends of the three groups of Tm-SCMs are respectively provided with a delay module; the input signal x[n] enters the corresponding first delay module for delay adjustment, and the timing of the signal input is matched through the timing delay. The input sequence is decomposed into multiple parallel subsequences according to the phase through the Tm-SCM module, and the single-channel input is converted into four parallel signals. The four sub-signals perform FFT operations in parallel in the first FFT module.

[0007] Preferably, the DAG graph generation includes the following steps: exhaustively enumerating possible displacement and configurations, expressing them as DAGs, and selecting the optimal DAG by comparing the performance of different DAGs.

[0008] Preferably: Matrix modeling includes the following steps: Each DAG is systematically converted to a matrix representation to facilitate extensive analysis and manipulation; each node of the DAG corresponds one-to-one to the row and column indices of an upper triangular matrix, and elements in the matrix are explicitly represented as shift and addition operations.

[0009] Preferably, the matrix selection based on the genetic algorithm comprises the following steps: Randomly sample chromosomes from the matrix; generational cycles; Assess fitness; sort and retain the elite; offspring generation; Update population; Termination condition: output "no", return to the generation loop, output "yes", continue; Returns the optimal solution.

[0010] Preferably: matrix union and time multiplexing DAG generation include the following steps: Independent DAGs representing constants are merged into a Tm-SCM DAG by identifying and sharing common arithmetic operations. Overlapping intermediate nodes are identified across different DAGs. These common shift operations are implemented only once, and their outputs are multiplexed to dynamically power multiple subsequent arithmetic paths at different clock cycles. A multiplexer unit selects the appropriate intermediate node based on timing signals to achieve hardware multiplexing.

[0011] Preferably, the MCM architecture includes an MCM module, a second delay module, and a second FFT, wherein one path of the MCM module is directly connected to the second FFT, and three paths of the MCM module are each connected to the second FFT through a corresponding second delay module; the input signal x[n] enters the MCM module and is decomposed into four parallel subsequences, and the decomposed multi-path signals are time-sequenced by the second delay module to achieve parallel input.

[0012] Preferably: the Tm-MCM optimization method is based on the Tm-MCM architecture, which includes a Tm-MCM module, a third delay module and a third FFT. The number of Tm-MCM modules is two groups, two paths of one group of Tm-MCM modules are connected to the third FFT through corresponding third delay modules, one path of another group of Tm-MCM modules is directly connected to the third FFT, and the other path of another group of Tm-MCM modules is connected to the third FFT through corresponding third delay modules; the input signal x[n] enters the Tm-MCM module and is decomposed into four parallel subsequences, and the decomposed multi-path signals are timed by the third delay module to realize parallel input.

[0013] Preferably: in the Tm-MCM optimization process method, the selected matrix: each selected DAG is the result of the GA-based selection described previously, specifically selected to minimize hardware resources; Time multiplexing: Individual DAGs are then merged into a unified time-multiplexed DAG. The unified DAG uses multiplexers to dynamically select the intermediate shift and addition / subtraction operations required for different clock cycles, thereby maximizing the reuse of hardware resources. By strategically using multiplexers to control the input of intermediate nodes, multiple multiplication paths can share resources across time periods.

[0014] The present invention has the following beneficial effects: 1. In terms of hardware resources, compared with traditional direct multiplication implementation, the Tm-SCM / Tm-MCM architecture can significantly reduce the total number of adders and achieve a reduction in overall circuit area.

[0015] 2. In terms of delay and throughput, the method of the present invention supports balancing hardware resources and computational delay by adjusting the time multiplexing depth, ensuring that the delay is controlled within an acceptable range while meeting the real-time requirements of the system; the polyphase filter STFT itself has a pipeline parallel characteristic, and after combining with time scheduling, it can still ensure continuous output spectrum without affecting the time-frequency resolution under high overlap.

[0016] 3. In terms of the flexibility of window functions, due to the use of a multiplication structure generated based on an algorithm, the present invention can easily re-optimize and generate hardware circuits for window function coefficients of different types and lengths, thereby realizing rapid switching and upgrading of window functions. This breaks through the limitation of traditional architectures where window functions are fixed and difficult to change, ensuring real-time performance while reducing the resource overhead of these constant multiplication operations.

[0017] 4. The resource optimization method provided by the present invention is very suitable for applications such as radar signal processing, speech feature extraction, and electronic warfare spectrum analysis that require high-overlap real-time STFT. In the above-mentioned fields, it can achieve high-performance time-frequency transformation at a lower hardware cost, thereby improving the overall system efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A framework diagram for optimizing the STFT resources of a polyphase filter based on time-multiplexed constant multiplication, including: (a) Tm-SCM-based window function architecture for polyphase filter STFT; (b) MCM window-based architecture for polyphase filter STFT; (c) Tm-MCM window-based architecture for the polyphase filter STFT.

[0019] Figure 2 Flowchart of the framework for Tm-SCM structure optimization design.

[0020] Figure 3 Flowchart for the incorporation of Tm-MCM structure optimization results.

[0021] Figure 4 Sliding window segmentation and spectrum transformation in STFT.

[0022] Figure 5 Timing analysis and parameter selection for a Tm-MCM architecture with four channels. DETAILED DESCRIPTION

[0023] To make the objectives, technical solutions, and advantages of the present invention more clearly apparent, the present invention is described below using specific embodiments shown in the accompanying drawings. However, it should be understood that these descriptions are merely illustrative and are not intended to limit the scope of the present invention. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present invention.

[0024] Specific implementation method 1: Combination Figure 1-5 This embodiment describes a method for optimizing the resources of a polyphase filter STFT based on time-multiplexed constant multiplication. In this embodiment, any one or more of the Tm-SCM (time-multiplexed-single constant multiplier) architecture, the Tm-MCM (time-multiplexed-multiple constant multiplier) architecture, and the MCM (multiple constant multiplier) architecture are embedded in the windowing module of the STFT (polyphase filter) architecture. If the original general architecture mentioned above exists in the original STFT, the new architecture is used to replace the original architecture. The Tm-SCM architecture, the Tm-MCM architecture, and the MCM architecture can be processed in parallel or individually, including: a Tm-SCM optimization method and / or a Tm-MCM optimization method; like Figure 2 As shown, the Tm-SCM optimization method includes the following steps: Step 11: DAG graph generation; Step 12: Matrix modeling; Step 13: Matrix selection based on genetic algorithm; Step 14: Matrix merging and time-multiplexing DAG graph generation; like Figure 3 As shown, the Tm-MCM optimization method includes: selecting a matrix and time multiplexing.

[0025] Specific implementation method 2: Combination Figure 1-5 The present embodiment is described. The present embodiment is a multi-phase filter STFT resource optimization method based on time multiplexing constant multiplication. The Tm-SCM optimization method is based on the Tm-SCM architecture. The Tm-SCM architecture includes a first delay module, a Tm-SCM module and a first FFT module. The output ends of the four groups of Tm-SCMs set for parallel processing are connected to the first FFT module, and the input ends of the three groups of Tm-SCMs are respectively provided with a delay module; the input signal x[n] enters the corresponding first delay module for delay adjustment, and the timing of the signal input is matched by the timing delay. The input sequence is decomposed into multiple parallel subsequences according to the phase through the Tm-SCM module, and the single input is converted into four parallel signals. The decomposed four signals are windowed, and the four sub-signals perform FFT operations in parallel in the first FFT module; the FFT module is a 4-way parallel FFT, and the delay module is z -kr , k=1,2,3; In the optimization method of Tm-SCM architecture, two Tm-CM-based architectures are used for the window function unit of the polyphase filter STFT: Tm-based SCM and Tm-MCM-based designs, both of which are effective alternatives to general multipliers; Figure 1 (a) The original universal multiplier in the polyphase filter STFT architecture is replaced by the Tm-SCM; since the coefficients of the original universal multiplier are the window function coefficients of the polyphase filter, the coefficients replaced by the Tm-SCM are the same; in the polyphase filter structure, not all window functions are used for each channel, but only a part of them; for example, in a structure with parallelism P, each channel has only N / P window function coefficients, which greatly reduces the parameters selected by the Tm-SCM; this design can achieve high parallelism and high throughput, significantly reducing the hardware overhead generated by using multiple universal multipliers; it is worth noting that the proposed structure can complete the calculation within one clock cycle, thereby basically keeping the existing delay unchanged; therefore, the Tm-SCM method provides a resource-efficient multiplication scheme while retaining the original parallel throughput of the polyphase filter STFT.

[0026] Specific implementation method three: Combination Figure 1-5 This embodiment describes a method for optimizing the STFT resources of a polyphase filter based on time-multiplexed constant multiplication. Step 11: generating an independent DAG graph includes the following steps: exhaustively enumerating possible shift-and-add configurations, representing them as DAGs, and selecting the optimal DAG (directed acyclic graph) by comparing the performance of different DAGs. That is, each target constant is optimally converted into multiple DAG representations through a comprehensive inspection of exhaustive optimal solutions. For each constant (e.g., 111 or 118), there may be multiple optimal shift-and-add configurations, such as 111 = 16×7−1 or 128−17, each of which exhibits a different hardware implementation. The problem is converted into a Boolean satisfiability (SAT) instance, thereby utilizing N. Fiege, M. Kumm, and P. Zipf, "Bit-level optimization of constant multiplication using Boolean satisfiability," IEEE Circuits and Systems I: Formal Paper. A powerful SAT solver proposed in 2023. It is able to enumerate all optimal solutions instead of a single optimal solution, generating a large number of equally efficient DAGs for each constant; the large number of enumerations ensures comprehensive exposure of the possible optimal hardware topologies for subsequent optimization steps.

[0027] Specific implementation method four: Combination Figure 1-5 This embodiment describes the polyphase filter STFT resource optimization method based on time multiplexing constant multiplication in this embodiment. Step 12: Matrix modeling includes the following steps: Each DAG is systematically converted to a matrix representation to facilitate extensive analysis and manipulation. In particular, each node of the DAG corresponds one-to-one to the row and column indices of an upper triangular matrix, and the elements in the matrix explicitly represent shift and addition operations. For example, the element {16,-1} indicates that the addition node has two different inputs; the first input is shifted by 4 bits (equivalent to multiplication by 16), while the second input is directly subtracted. A zero element indicates that there is no direct connection between the nodes. Figure 2 The constant w in 12 = 111 as an example, the matrix is ​​constructed as follows; 12 = 111 The first DAG is modeled as the matrix: (4) Here, the element {1, 16} explicitly encodes the operation of node 17 as 1×1+1×16 = 17, while {−1} represents subtraction from node 128 to obtain node 111. To expand the solution space, the matrix performs scaling operations to maintain arithmetic equivalence. Entries like {16, −1} can be scaled to an equivalent form, such as {1, −0.0625}, enabling additional design trade-offs between hardware complexity and operation accuracy.

[0028] Specific implementation method five: Combination Figure 1-5 This embodiment describes the polyphase filter STFT resource optimization method based on time multiplexing constant multiplication in this embodiment. Step 13 of the genetic algorithm-based matrix selection includes the following steps: Step 131: Randomly sample P chromosomes from the matrix M; Step 132: Generation cycle (1 to G); Step 133: Evaluate fitness: calculate using matrix M; Step 134: sort and retain the elite: retain the first ef·P chromosomes; Step 135: Offspring generation: parent generation selection crossover and mutation; Step 136: Update the population: merge the elites and the new offspring; Step 137: Termination condition: Maximum number of generations (G) or stagnation (S); output "No", return to step 132 generation loop, output "Yes", and continue; Step 138: Return the optimal solution: the selected matrix M; A genetic algorithm (GA) is used to select the best matrix from the expansion candidates; e.g. Figure 2As shown in the figure, GA first randomly initializes a population of matrix combinations; each combination (individual) contains a matrix selected from each matrix group; the fitness of each individual is evaluated by first merging the matrices in the combination into a unified matrix, and then analyzing the hardware resources of the combination (including the number of adders, multiplexer complexity, and critical path delay); individuals are sorted according to fitness, and elite solutions are retained to maintain the best results between generations; new candidate solutions are generated through genetic operations (such as crossover and mutation) to ensure diversity in the solution space; this iterative process continues until the algorithm converges or reaches the specified termination criterion; In each iteration of the genetic algorithm, the combination that produces the lowest hardware resource consumption is continuously tracked and updated; at termination, the optimal matrix combination identified by the algorithm is converted back to a hardware-compatible DAG representation through an inverse transformation, ensuring that the final selected matrix directly corresponds to an efficient hardware topology.

[0029] Specific implementation method six: combination Figure 1-5 This embodiment describes the polyphase filter STFT resource optimization method based on time-multiplexed constant multiplication in this embodiment. Step 14 of matrix union and time-multiplexed DAG generation includes the following steps: Independent DAGs representing constants (e.g., 111, 118, 124, 127) are merged into a single Tm-SCM DAG by identifying and sharing common arithmetic operations. First, overlapping intermediate nodes are identified across different DAGs, such as nodes that perform the same shift (e.g., multiplication by 16, 4, or 128). Then, these common shift operations are implemented only once, and their outputs are multiplexed to dynamically power multiple subsequent arithmetic paths at different clock cycles. Multiplexer (MUX) units select appropriate intermediate nodes based on timing signals to achieve hardware multiplexing. As a result, the merged time-multiplexed DAG efficiently utilizes minimal adder resources and reduces multiplexer complexity, forming an optimized hardware topology suitable for FPGA or ASIC implementation.

[0030] Specific implementation method seven: combination Figure 1-5 This embodiment describes a method for optimizing STFT resources of a polyphase filter based on time-multiplexed constant multiplication. The MCM window architecture includes an MCM module, a second delay module, and a second FFT. One path of the MCM module is directly connected to the second FFT, and three paths of the MCM module are each connected to the second FFT via a corresponding second delay module. An input signal x[n] enters the MCM module and is decomposed into four parallel subsequences. The decomposed four-path signal is windowed, and the decomposed multi-path signal is time-sequenced by the second delay module to achieve parallel input. Based on the windowing of constant multipliers (non-time multiplexing), the delay module is placed at the end, and some multiplexers are added to the windowing architecture based on Tm-SCM to obtain the constant multiplier structure. Figure 1 As shown in (b), this option replaces the Tm-SCM unit in each channel with a single combined constant multiplier core; this core generates all the required window coefficient products in one clock cycle, so each channel can read its result without additional latency; since one block now serves all P channels, the duplicate constant multiplier logic disappears, resulting in a significant reduction in adders, shifters, and multiplexers; this results in an increase in register resources used for storage in the module output section, and the savings become more significant as the level of parallelism increases.

[0031] Specific implementation method eight: combination Figure 1-5 The present embodiment is described. The present embodiment is a method for optimizing polyphase filter STFT resources based on time multiplexing constant multiplication. The Tm-MCM optimization method is based on a Tm-MCM window architecture. The Tm-MCM architecture includes a Tm-MCM module, a third delay module, and a third FFT. There are two groups of Tm-MCM modules. Two paths of one group of Tm-MCM modules are connected to the third FFT through corresponding third delay modules, one path of another group of Tm-MCM modules is directly connected to the third FFT, and another path of another group of Tm-MCM modules is connected to the third FFT through corresponding third delay modules. The first, second, and third FFTs can be the same FFT or different FFTs. The input signal x[n] enters the Tm-MCM module and is decomposed into four parallel subsequences. The decomposed four-path signals are windowed. The decomposed multi-path signals are time-sequenced by the third delay module to achieve parallel input. Time-division multiplexing MCM windows. To reduce the impact of delays and multiplexers in the MCM window architecture, the proposed Tm-MCM window architecture is shown in Figure 1(c). Unlike the fully parallel MCM method that generates all window outputs in each clock cycle, Tm-MCM schedules the generation of different constant products in time. At the same time, it utilizes the inherent multi-output characteristics of MCM so that multiple channels can be served simultaneously in each time slot. Therefore, the Tm-MCM module avoids the resource overhead of generating all window function coefficients at once, which is particularly beneficial for longer window lengths. Compared with the Tm-SCM design, the dual (or multi) channel capacity of the Tm-MCM structure allows more multiplications to be shared at the hardware level. Therefore, it achieves fewer adders and registers. By dividing the window coefficients into small sets and scheduling them into alternating time slots, Tm-MCM achieves a good balance between throughput and resource utilization, solving the problem that when the window coefficient list is long, the adder tree inside the fully parallel constant multiplier becomes deeper, extending the critical path and reducing the cost of FPGA or ASIC. This reduces the maximum achievable clock frequency on the target. It also addresses the issue of the core having to issue all coefficient products in every cycle. If the overlap rate is less than 100%, many of these product results will be discarded in the FFT stage, so the hardware will still consume power for useless work. This reduces resource waste and implementation complexity. Time multiplexing MCM window principle: such as Figure 4 As shown, the STFT architecture for a serial input discrete signal x[n] with a sliding window function w[n] is defined as: (1) in, is the rotation factor; N is the number of FFT points and the window length; the parameter R is the window shift step; P = N / R indicates the number of parallel channels; the operator F{·} represents the discrete Fourier transform (DFT) operation on the N-point sequence, which maps the time domain signal to its corresponding frequency domain representation; According to (1), the window signal is defined as: (2) where r is the frame (or block) index, n represents the sample index within each frame of length N, and, assuming m = rR + n, m is the absolute sample index over the entire signal; thus, the windowed signal can be rewritten as: (3) This property states that the window repeats with a period N and is symmetric about n = N / 2; such periodic and symmetric windows are often used to ensure continuity at frame boundaries and to simplify the overlap-add process in time-frequency analysis; to illustrate this more clearly, assume N = 32 and R = 4; thus, for a particular sample x[m], the window coefficients involved become w[m], w[m+4], w[m+8], w[m+12], which is obtained by substituting the periodic property w[n] = w[n+N] into the expression for w[m−rR]; in this case, each consecutive frame index r increases by 4 in the parameter of w[·], resulting in four window values ​​for the same x[m]; therefore, each absolute sample x[m] participates in exactly four constant multiplications, regardless of its corresponding frame r; due to this symmetric property, as Figure 5 As shown, it is observed that the required time-multiplexed window function coefficients are shared between the two channels; the coefficients required for each channel are reused by its mirror channel (CH1↔CH4 and CH2↔CH3) after a fixed delay; therefore, only eight different window function sample products need to be generated every four cycles; these products are listed in the table below, which divides them into two groups a[n] and b[n], corresponding to the first and second outputs of the dual-output multiplier core respectively; The present invention further introduces a window architecture based on Tm-MCM. The detailed parameter selection process and timing scheduling are described in this paper. It is crucial to determine which window coefficients correspond to each specific sample of the input signal x[n]. In terms of hardware resources, the number of LUTs and registers required to implement STFT window multiplication is significantly reduced, and the use of scarce DSP multiplier cores is avoided as much as possible. For example, compared with traditional direct multiplication implementations, the Tm-SCM / Tm-MCM architecture can significantly reduce the total number of adders, thereby reducing the overall circuit area. In terms of the flexibility of window functions, due to the use of a multiplication structure generated based on an algorithm, the present invention can easily re-optimize and generate hardware circuits for window function coefficients of different types and lengths, thereby realizing rapid switching and upgrading of window functions, breaking through the limitations of traditional architectures where window functions are fixed and difficult to change.

[0032] Specific implementation method nine: Combination Figure 1-5 This embodiment describes a polyphase filter STFT resource optimization method based on time-multiplexed constant multiplication. In the Tm-MCM optimization process, the optimization procedure previously described for the Tm-SCM scenario is also directly applicable to the Tm-MCM method. Due to the inherent dual-output structure of the MCM, there are some minor differences. Figure 3 The final optimization results of the Tm-MCM scenario are illustrated, showing the optimized DAG with the corresponding constants selected after the genetic algorithm-based selection (the selected constants are the same as before); like Figure 3 The upper half of the dotted box shows the selection matrix: each selected DAG is the GA-based selection result described previously, specifically selected to minimize hardware resources.

[0033] Time multiplexing: These individual DAGs are then merged into a unified time-multiplexed DAG, e.g. Figure 3 As shown in the dashed box in the lower half, this unified DAG utilizes multiplexers to dynamically select the intermediate shift and addition / subtraction operations required for different clock cycles, thereby maximizing hardware resource reuse. By strategically using multiplexers to control intermediate node inputs, multiple multiplication paths can share resources across time periods, significantly reducing the number of adders and multiplexers required. The resulting unified Tm-MCM structure provides efficient resource optimization for FPGA or ASIC implementation. The method of the present invention supports balancing hardware resources and computational delay by adjusting the time multiplexing depth, ensuring that the delay is controlled within an acceptable range while meeting the real-time requirements of the system; the polyphase filter STFT itself has a pipeline parallel characteristic, and after combining with time scheduling, it can still ensure continuous output spectrum without affecting the time-frequency resolution under high overlap.

[0034] Example 1: The present invention realizes resource optimization of STFT window function multiplication operation through the following technical solutions.

[0035] like Figure 1 As shown in Figure 2, three proposed STFT hardware structures based on constant multipliers are shown: 1. Tm-SCM Architecture: A time-multiplexed single-constant multiplication architecture is proposed. A directed acyclic graph (DAG) is used to represent fixed-coefficient multiplication, decomposing constant multiplication into addition and shift operations. DAG analysis extracts shareable addition operations, enabling an efficient single-constant multiplication circuit architecture to replace traditional multipliers. This architecture utilizes a combination of shift registers and adders to eliminate hardware multipliers and supports time-division multiplexing: the same shift-add unit can multiply a series of input samples by the same constant over multiple clock cycles. Through pipeline control, a compact Tm-SCM module can perform multiple data multiplications sequentially in time, reducing the number of parallel multipliers.

[0036] 2. MCM architecture: A shared operation structure for multiple constant multiplication (MCM) is proposed. For the multiple sets of constant coefficients involved in the window, the present invention integrates multiple constant multiplication operations into a unified addition network. By utilizing the common shift-addition part generated by different constant combinations, the common calculation parts of multiple multiplications are merged to eliminate redundancy. The MCM architecture is equivalent to a customized arithmetic circuit for a specific set of constants (such as a window coefficient set), which completes the product calculation of all constants in the set and the input data at one time. Compared with implementing multiplication for each constant separately, the MCM network greatly reduces the number of adders, thereby reducing LUT and logic consumption.

[0037] 3. Tm-MCM Architecture: Building on this foundation, the present invention further proposes a time-multiplexed multi-constant multiplication architecture, combining time multiplexing with the MCM architecture. Leveraging the symmetry and periodicity of window function coefficients (e.g., the center-symmetry of Hann and Blackman window function coefficients), a multiplication network is designed whose output can be dynamically scheduled across multiple clock cycles. Tm-MCM distributes computational tasks in the time domain, enabling a single adder network to generate different coefficient products in different cycles, thus achieving time sharing for multiplication of multiple constants. For example, for a symmetric window coefficient pair, a single computation module only needs to compute the symmetric coefficient products in both odd and even frames to cover the entire window operation. The Tm-MCM architecture leverages the MCM's advantage of merging shared operations and further reduces hardware duplication through time division multiplexing, enabling the same hardware to perform multiplication operations with different constants at different times, minimizing resource waste. This architecture outputs window product results sequentially over several clock cycles, enabling the completion of the entire window multiplication operation with minimal hardware overhead while meeting system throughput requirements. Figure 2 A timing diagram showing this structure is shown.

[0038] like Figure 2 and Figure 3As shown, the optimization process for Tm-SCM and Tm-MCM is demonstrated using a 32-point Hanning window as an example. This invention provides a structure search and optimization framework based on DAG representation and matrix analysis for automatically generating the aforementioned multiplication structure. By representing constant multiplication operations as DAGs and equivalent matrix forms, a SAT solver and genetic algorithm are used to search and optimize multiple possible DAG structure combinations. This framework can evaluate the resource consumption of different combination schemes, efficiently screen out globally optimal or suboptimal DAG merging schemes through constraint solving and evolutionary optimization, and synthesize the results into corresponding hardware circuits. In other words, this invention uses formal methods to automatically explore the optimal implementation of Tm-SCM / MCM / Tm-MCM structures, minimizing resource usage such as adders and shift registers while ensuring output correctness. This optimization design process can be customized for resource optimization for different window function coefficient sets, making the method of this invention widely applicable and scalable.

[0039] Using a Kintex-7 series FPGA as the hardware platform, a 32-point STFT example was implemented, in which the window multiplication optimization module proposed in this invention was applied. First, a window function, such as a Blackman window or a Hann window, was selected, with a length of 32 and symmetric properties. In a traditional polyphase filter STFT architecture, the window multiplication portion typically requires 32 multipliers (16 multipliers are required to exploit symmetry) to multiply each input sample by the corresponding window coefficient. This embodiment, however, uses the method of this invention to generate the corresponding time-multiplexed window multiplication module, replacing the existing multiplier array.

[0040] Specifically, for the selected 32-point window function coefficients, the DAG optimization design framework of the present invention is used to generate a resource-optimized Tm-SCM structure. This structure uses a shift register and adder network to implement fixed-constant multiplication, without using a DSP multiplication unit. Through appropriate pipeline and scheduling control, the single constant multiplication module sequentially accepts each sample value in the window in each clock cycle, performs window multiplication operations, and then outputs them. Because the Blackman window coefficients are symmetric about the center, this embodiment further adopts Tm-MCM architecture optimization: the symmetric coefficient pairs are combined and calculated by the same addition network, and paired product results are output in adjacent clock cycles. In this way, a compact Tm-MCM module can complete the window product calculation of a pair of symmetric samples within two clock cycles, and the complete processing of 32 samples can be completed in only 16 clock cycles (the window multiplication operation of one frame of STFT is completed in 16 clock cycles). Comprehensive experimental results demonstrate that, when implemented on a Kintex-7 FPGA, this window multiplication module achieves 32-point Blackman window multiplication using only a small number of LUTs and register resources, without any DSP48 cores. Compared to traditional implementations, this approach saves over 50% of lookup table resources. With the addition of the present invention's window function module, the entire 32-point STFT structure can operate stably at the designed clock frequency, continuously outputting a 32-point FFT spectrum in real time with minimal pipeline delay overhead between each frame output, thus verifying the effectiveness and superiority of the present method on actual hardware.

[0041] If other window functions (such as Hann window) or different window lengths are used, the method of the present invention is also applicable. By re-inputting the corresponding window coefficient set into the optimization framework, a corresponding new Tm-SCM or Tm-MCM multiplier structure can be generated. In another embodiment, we replace the window function with a 32-point Hann window and use the Tm-MCM architecture to generate an optimized multiplier network. The comprehensive results also show a significant resource saving effect while ensuring the correctness of the STFT output. It can be seen that the method of the present invention has the ability to adaptively optimize different window functions and can be widely used in various digital signal processing systems that require low-resource, high-performance STFT calculations; The resource optimization method provided by the present invention is very suitable for scenarios requiring high-overlap real-time STFT, such as radar signal processing, speech feature extraction, and electronic warfare spectrum analysis. In the above-mentioned fields, high-performance time-frequency transformation can be achieved at a lower hardware cost, thereby improving the overall system efficiency.

[0042] It should be noted that in the above embodiments, as long as the technical solutions are not contradictory, they can be permuted and combined. Those skilled in the art can exhaust all possibilities based on the mathematical knowledge of permutations and combinations. Therefore, the present invention will no longer describe the technical solutions after permutations and combinations one by one, but it should be understood that the technical solutions after permutations and combinations have been disclosed by the present invention.

[0043] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A polyphase filter STFT resource optimization method based on time-multiplexed constant multiplication, characterized by: include: Tm-SCM optimization method and / or Tm-MCM optimization method; The Tm-SCM optimization method includes the following steps: DAG generation; Matrix modeling; Matrix selection based on genetic algorithm; Matrix merging and time-multiplexed DAG generation; The Tm-MCM optimization method includes: matrix selection and time multiplexing.

2. The polyphase filter STFT resource optimization method based on time multiplexing constant multiplication according to claim 1, characterized in that: The Tm-SCM optimization method is based on the Tm-SCM architecture, which includes a first delay module, a Tm-SCM module and a first FFT module. The output ends of the four groups of Tm-SCMs set for parallel processing are connected to the first FFT module, and the input ends of the three groups of Tm-SCMs are respectively provided with a delay module. The input signal x[n] enters the corresponding first delay module for delay adjustment, and the timing of the signal input is matched through the timing delay. The input sequence is decomposed into multiple parallel subsequences according to the phase through the Tm-SCM module, and the single input is converted into four parallel signals. The four sub-signals perform FFT operations in parallel in the first FFT module.

3. The polyphase filter STFT resource optimization method based on time multiplexing constant multiplication according to claim 2, characterized in that: DAG graph generation includes the following steps: Exhaust possible displacement and addition configurations, represent them as DAGs, and select the optimal DAG by comparing the performance of different DAGs.

4. The method for optimizing polyphase filter STFT resources based on time-multiplexed constant multiplication according to claim 3, characterized in that: Matrix modeling involves the following steps: Each DAG is systematically converted to a matrix representation to facilitate extensive analysis and manipulation; each node of the DAG corresponds one-to-one to the row and column indices of an upper triangular matrix, and elements in the matrix are explicitly represented as shift and addition operations.

5. The method for optimizing polyphase filter STFT resources based on time-multiplexed constant multiplication according to claim 4, characterized in that: The matrix selection based on genetic algorithm includes the following steps: Randomly sample chromosomes from the matrix; generational cycles; Assess fitness; sort and retain the elite; offspring generation; Update population; Termination condition: Output "No" to return to the generation loop, output "Yes" to continue; Returns the optimal solution.

6. The method for optimizing polyphase filter STFT resources based on time-multiplexed constant multiplication according to claim 5, characterized in that: Matrix union and time-multiplexed DAG generation include the following steps: Independent DAGs representing constants are merged into a Tm-SCM DAG by identifying and sharing common arithmetic operations; Overlapping intermediate nodes are identified across different DAGs. These common shift operations are implemented only once, and their outputs are multiplexed to dynamically power multiple subsequent arithmetic paths at different clock cycles. The multiplexer unit selects the appropriate intermediate node based on the timing signal to achieve hardware multiplexing.

7. The method for optimizing polyphase filter STFT resources based on time-multiplexed constant multiplication according to any one of claims 1 to 6, characterized in that: The MCM architecture includes an MCM module, a second delay module, and a second FFT. One path of the MCM module is directly connected to the second FFT, and three paths of the MCM module are each connected to the second FFT through a corresponding second delay module. The input signal x[n] enters the MCM module and is decomposed into four parallel subsequences. The decomposed multi-path signals are time-sequenced by the second delay module to achieve parallel input.

8. The method for optimizing polyphase filter STFT resources based on time-multiplexed constant multiplication according to claim 7, characterized in that: The Tm-MCM optimization method is based on the Tm-MCM architecture, which includes a Tm-MCM module, a third delay module, and a third FFT. The Tm-MCM modules are divided into two groups. Two paths of the Tm-MCM modules in one group are connected to the third FFT through corresponding third delay modules, one path of the Tm-MCM modules in the other group is directly connected to the third FFT, and the other path of the Tm-MCM modules in the other group is connected to the third FFT through corresponding third delay modules. The input signal x[n] enters the Tm-MCM module and is decomposed into four parallel subsequences. The decomposed multi-path signals are timed by the third delay module to achieve parallel input.

9. The method for optimizing polyphase filter STFT resources based on time-multiplexed constant multiplication according to claim 8, characterized in that: In the Tm-MCM optimization process method, the selected matrix: Each selected DAG is the result of the GA-based selection described previously, specifically selected to minimize hardware resources. Time multiplexing: Individual DAGs are then merged into a unified time-multiplexed DAG. The unified DAG uses multiplexers to dynamically select the intermediate shift and addition / subtraction operations required for different clock cycles, thereby maximizing the reuse of hardware resources. By strategically using multiplexers to control the input of intermediate nodes, multiple multiplication paths can share resources across time periods.

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