Anti-nuclear radiation reinforced level conversion circuit for high-voltage SOI half-bridge driver

Abstract

The invention discloses an anti-nuclear radiation reinforced level conversion circuit for a high-voltage SOI half-bridge driver. A pulse generation circuit generates two narrow pulse signals to a transient dose rate reinforced high-voltage level conversion circuit. The instantaneous dose rate reinforcement resistant high-voltage level transfer circuit provides low-voltage-to-high-voltage pulse input and transmits the low-voltage-to-high-voltage pulse input to the total dose reinforcement resistant pulse filter circuit; the pulse filter circuit capable of resisting total dose reinforcement filters noise signals generated in the switching process of the LDMOS device and transmits the filtered signals to the RS trigger circuit capable of resisting total dose reinforcement; the neutron reinforcement resisting undervoltage detection circuit is used for generating an undervoltage detection signal and transmitting the undervoltage detection signal to the total dose reinforcement resisting RS trigger circuit; and the RS trigger circuit capable of resisting total dose reinforcement identifies the undervoltage detection signal and restores the two narrow pulse signals generated by the pulse generation circuit into wide pulse signals at the same time. The anti-radiation characteristic of the improved circuit is greatly improved.

Description

Technical Field

[0001] The invention belongs to the field of analog integrated circuit design and integrated systems, specifically a level conversion circuit with nuclear radiation hardening for high-voltage SOI half-bridge drivers. Background Art

[0002] With the advancement of microelectronics, space, nuclear, and strategic weapons technologies, a large number of advanced electronic devices are required in artificial satellites, spacecraft, nuclear facilities, and nuclear weapons systems. However, electronic components in advanced electronic devices operating in radiation environments, such as space and nuclear radiation, can suffer varying degrees of radiation damage, degrading their parameters and performance, and ultimately leading to failure of the entire device. Currently, MOSFET and IGBT drive systems are widely used in aerospace-grade equipment, but they still cannot meet the radiation hardening design requirements for high-voltage power drivers. This makes it difficult to meet the urgent needs of automated control systems and servo motor drives in aerospace applications. Summary of the Invention

[0003] The purpose of the present invention is to overcome the above-mentioned shortcomings of the prior art and provide a level conversion circuit for a high-voltage SOI half-bridge driver with nuclear radiation hardening. The development of the present invention can realize a hardened design for total dose resistance, neutron injection resistance, and transient dose rate resistance in a single driver circuit, so that the functional performance of the device after the three types of irradiation meet the system application.

[0004] In the present invention, the narrow pulse generating circuit with total dose reinforcement generates two narrow pulse signals through logical operations and transmits them to the high-voltage level transfer circuit with instantaneous dose rate reinforcement. The high-voltage level transfer circuit with instantaneous dose rate reinforcement undertakes the function of transferring the low-voltage domain logic control signal to the high-side floating voltage domain logic control signal. The signal waveform of the narrow pulse generating circuit is converted into a narrow pulse signal corresponding to its rising edge and falling edge, and then the low-voltage narrow pulse signal is converted into two high-voltage pulse signals through the level shift core circuit. The obtained signal is then shaped and noise is filtered out by the pulse filtering circuit with total dose reinforcement, and then converted into a square wave signal by the RS trigger circuit with total dose reinforcement. The RS trigger circuit with total dose reinforcement not only realizes the function of restoring the pulse wave to a square wave, but also realizes the judgment function of the fault logic. When the undervoltage detection circuit with neutron reinforcement emits an undervoltage fault, the RS trigger circuit with total dose reinforcement will maintain the output at a constant low level.

[0005] The technical solution adopted by the present invention is a level conversion circuit with nuclear radiation hardening for a high-voltage SOI half-bridge driver, comprising a narrow pulse generation circuit with total dose hardening, a high-voltage level transfer circuit with instantaneous dose rate hardening, a pulse filtering circuit with total dose hardening, and an RS trigger circuit with total dose hardening, which are connected in sequence. The RS trigger circuit with total dose hardening is also connected to an undervoltage detection circuit with neutron hardening; wherein:

[0006] The narrow pulse generating circuit with total dose hardening is used to provide narrow pulse input to the high voltage level transfer circuit with transient dose rate hardening;

[0007] The high-voltage level transfer circuit with transient dose rate reinforcement is used to provide a low-voltage to high-voltage narrow pulse input, which is transmitted to the pulse filtering circuit with total dose reinforcement;

[0008] The pulse filter circuit with total dose hardening is used to filter the noise signal generated during the turn-on and turn-off process of the LDMOS device in the high-voltage level shift circuit with transient dose rate hardening, to prevent false triggering when the amplitude of the noise signal reaches the trigger threshold, and at the same time transmit the filtered signal to the RS trigger circuit with total dose hardening;

[0009] The undervoltage detection circuit with neutron hardening is used to generate an undervoltage detection signal to prevent the power supply voltage from being too low, and at the same time transmit the over-voltage and under-voltage detection signal to the RS trigger circuit with total dose hardening;

[0010] The RS trigger circuit with total dose hardening recognizes the undervoltage detection signal and simultaneously restores a pair of two-path narrow pulse signals generated by the pulse generating circuit into a single wide pulse signal.

[0011] The narrow pulse generating circuit for total dose hardening includes: a first narrow pulse generating branch and a second narrow pulse generating branch having two identical circuits, wherein the circuit connection relationship includes: the input end is connected to the output end through a NOT gate NOT1, two parallel MOS transistors (M1, M2), a Schmitt trigger SMT1, a NOR gate NOR1, a NOT gate NOT5, and a NOT gate NOT6 in sequence; the second input end of the NOT gate NOR1 is also connected to the output end of the NOT gate NOT1;

[0012] The source of the PMOS transistor M1 is connected to the power supply, the drain is respectively connected to the drain of the NMOS transistor M2 and one end of the Schmitt trigger SMT1, and the gate is connected to one end of the NOT gate NOT1; the gate of the NMOS transistor M2 is connected to one end of the NOT gate NOT1, and the source is connected to the ground via the resistor R1; the output end of the NOT gate NOT1 of the first narrow pulse branch is also connected to the input end of the second narrow pulse branch;

[0013] The output ends of the first narrow pulse branch and the second narrow pulse branch are respectively connected to two input ends (IN1, IN2) of a high-voltage level transfer circuit reinforced against transient dose rate.

[0014] The high-voltage level transfer circuit with transient dose rate hardening includes:

[0015] The source of NMOS transistor MH1 is connected to ground via resistor R6, its drain is connected to the drain of PMOS transistor P1, and its gate is connected to input IN1. The source and gate of NMOS transistor MH2 are connected to one end of resistor R7, its drain is connected to the gate of PMOS transistor P1, and the other end of resistor R7 is connected to ground. The source of NMOS transistor MH3 is connected to ground via resistor R8, its drain is connected to the drain of PMOS transistor P2, and its gate is connected to input IN2.

[0016] The source of the PMOS transistor P1 is connected to the power supply, the gate is connected to the gate of the PMOS transistor P2, and one drain is connected to the power supply via diodes D2 and D1 in sequence. Another drain is connected to the power supply via resistor R4. The drain of the PMOS transistor P1 is also connected to the input terminal IN2 of the pulse filter circuit for total dose hardening via a NOT gate NOT10.

[0017] The source of the PMOS transistor P2 is connected to the power supply, the gate is connected to the power supply via diodes D4 and D3 in sequence, and the other gate is connected to the power supply via resistor R4. The drain is connected to the power supply via diodes D6 and D5 in sequence, and the other drain is connected to the power supply via resistor R5. The drain of the PMOS transistor P2 is also connected to the input terminal IN1 of the pulse filter circuit for total dose hardening via a NOT gate NOT9.

[0018] The pulse filter circuit for total dose reinforcement includes a first narrow pulse filter branch and a second narrow pulse filter branch with the same circuits. The circuit connection relationship includes:

[0019] The input terminal IN1 of the pulse filter circuit for total dose hardening is connected to the gate of the PMOS tube M5 and the gate of the NMOS tube M10 respectively. The source of the PMOS tube M5 is connected to the power supply, and the drain is connected to the drain of the NMOS tube M10. The source of the NMOS tube M10 is connected to the ground via the resistor R9.

[0020] The drain of the PMOS transistor M5 is connected to the gate of the PMOS transistor M6 and the gate of the NMOS transistor M11 respectively. The source of the PMOS transistor M6 is connected to the power supply, and the drain is connected to the drain of the NMOS transistor M11. The source of the NMOS transistor M11 is connected to the ground via the resistor R10.

[0021] The drain of the PMOS transistor M6 is connected to the gate of the PMOS transistor M7 and the gate of the NMOS transistor M12 respectively. The source of the PMOS transistor M7 is connected to the power supply, and the drain is connected to the drain of the NMOS transistor M12 via the resistor R23. The source of the NMOS transistor M12 is connected to the ground via the resistor R11. The drain of the NMOS transistor M12 is also connected to the ground via the capacitor C1 and the resistor R12.

[0022] The drain of the NMOS tube M12 is connected to the gate of the PMOS tube M8, the gate of the PMOS tube M15, the gate of the NMOS tube M14, and the gate of the NMOS tube M13 respectively;

[0023] The source of the PMOS transistor M8 is connected to the power supply, and the drain is connected to the source of the PMOS transistor M15; the drain of the PMOS transistor M15 is connected to the drain of the NMOS transistor M14; the source of the NMOS transistor M14 is connected to the drain of the NMOS transistor M13, and the source of the NMOS transistor M13 is connected to the ground via the resistor R13;

[0024] The drain of the PMOS transistor M15 is also connected to the gate of the PMOS transistor M16 and the gate of the NMOS transistor M17 respectively; the source of the PMOS transistor M16 is connected to the drain of the PMOS transistor M8, and the drain is connected to the ground via the resistor R14; the source of the NMOS transistor M17 is connected to the source of the PMOS transistor M15, and the drain is connected to the power supply;

[0025] The drain of the PMOS transistor M15 is also connected to the gates of the PMOS transistor M19 and the NMOS transistor M18 respectively; the source of the PMOS transistor M19 is connected to the power supply, and the drain is connected to the output terminal OUT1; the source of the NMOS transistor M18 is connected to the ground via the resistor R15, and the drain is connected to the output terminal OUT1.

[0026] The RS trigger circuit with total dose hardening includes: a NAND gate NAND1 and a NAND gate NAND2;

[0027] The first input terminal of the NAND gate NAND1 is connected to the UVLO input terminal, the second input terminal of the NAND gate NAND1 is connected to the R input terminal, the third input terminal of the NAND gate NAND1 is connected to the output terminal of the NAND gate NAND2, the first input terminal of the NAND gate NAND2 is connected to the output terminal of the NAND gate NAND1, the second input terminal of the NAND gate NAND2 is connected to the S input terminal, and the output terminal of the NAND gate NAND2 is output as the final output terminal.

[0028] The neutron-hardened undervoltage detection circuit includes:

[0029] The power supply is connected to the positive input terminal of the comparator COMP1 through the resistor R25. The other end of the resistor R25 is connected to the ground through the resistor R26 and the resistor R27 in sequence. The output end of the comparator COMP1 is connected to the UVLO end of the RS trigger 104 with total dose hardening through the NAND gate NOT11 and the NAND gate NOT12 in sequence. The output end of the NAND gate NOT12 is also connected to the gate of the NMOS transistor M33. The source of the NMOS transistor M33 is connected to the ground, and the drain of the NMOS transistor M33 is connected to the resistors R26 and R27.

[0030] The present invention has the following beneficial effects and advantages:

[0031] The circuit developed by this invention achieves a robust design for total dose, neutron injection, and transient dose rate resistance in a single driver circuit, ensuring that the device's functional performance meets system requirements after all three types of irradiation. This invention significantly differs from conventional level-shifting circuits in high-voltage half-bridge drivers, significantly improving the circuit's radiation resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 The figure is a schematic diagram of a level conversion circuit structure with nuclear radiation hardening for a high-voltage SOI half-bridge driver according to the present invention.

[0033] Figure 2 Schematic diagram of the narrow pulse generation circuit structure for total dose hardening.

[0034] Figure 3 Schematic diagram of a high-voltage level-shifting circuit structure hardened against transient dose rates.

[0035] Figure 4 Schematic diagram of the pulse filter circuit structure for total dose hardening.

[0036] Figure 5 Schematic diagram of the neutron-hardened undervoltage detection circuit structure.

[0037] Figure 6 Schematic diagram of the RS trigger circuit structure with total dose hardening.

[0038] Figure 7 Output waveform for instantaneous dose rate irradiation test.

[0039] Figure 8 These are the effects under different radiation conditions.

[0040] Among them, 100 is a narrow pulse generating circuit for total dose hardening; 101 is a narrow pulse generating circuit for total dose hardening; 102 is a pulse filtering circuit for total dose hardening; 103 is an undervoltage detection circuit for neutron hardening; 104 is an RS trigger circuit for total dose hardening. DETAILED DESCRIPTION

[0041] To make the above-mentioned objects, features, and advantages of the present invention more readily apparent, the specific implementation methods of the present invention are described in detail below with reference to the accompanying drawings. The following description sets forth many specific details to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways than those described herein, and those skilled in the art may make similar modifications without departing from the scope of the invention. Therefore, the present invention is not limited to the specific implementation methods disclosed below.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art of the art to which the present invention pertains. The terms used in the specification of the invention herein are for the purpose of describing specific embodiments only and are not intended to limit the present invention.

[0043] The circuit of the present invention improves the influence of the total dose effect on the high-voltage half-bridge driver circuit; improves the influence of the neutron effect on the high-voltage half-bridge driver circuit; and improves the influence of the instantaneous dose rate effect on the high-voltage half-bridge driver circuit.

[0044] like Figure 1 The figure shows a nuclear radiation hardened level conversion circuit for a high-voltage SOI half-bridge driver according to the present invention. The circuit comprises a total-dose hardened narrow pulse generation circuit 100, a transient-dose-rate hardened high-voltage level shifting circuit 101, a total-dose hardened pulse filtering circuit 102, and a total-dose hardened RS trigger circuit 104, which are connected in sequence. The total-dose hardened RS trigger circuit 104 is also connected to a neutron-hardened undervoltage detection circuit 103.

[0045] The narrow pulse generating circuit 100 with total dose hardening is used to provide a narrow pulse input to the high voltage level transfer circuit 101 with transient dose rate hardening;

[0046] The high-voltage level shifting circuit 101 with transient dose rate hardening is used to provide a low-voltage to high-voltage narrow pulse input, which is transmitted to the pulse filtering circuit 102 with total dose hardening;

[0047] The pulse filter circuit 102 with total dose hardening is used to filter the noise signal generated during the turn-on and turn-off process of the LDMOS device in the high-voltage level shifter circuit 101 with transient dose rate hardening, to prevent false triggering when the amplitude of the noise signal reaches the trigger threshold, and at the same time transmit the filtered signal to the RS trigger circuit 104 with total dose hardening;

[0048] The undervoltage detection circuit 103 with neutron hardening is used to generate an undervoltage detection signal to prevent the power supply voltage from being too low, and at the same time transmit the over-voltage and under-voltage detection signal to the RS trigger circuit 104 with total dose hardening;

[0049] The total dose hardened RS trigger circuit 104 identifies the undervoltage detection signal and simultaneously restores a pair of two narrow pulse signals generated by the pulse generating circuit into a single wide pulse signal.

[0050] like Figure 2 As shown, in the above-mentioned nuclear radiation hardened level conversion circuit structure for a high-voltage SOI half-bridge driver, the narrow pulse generating circuit 100 with total dose hardening includes a PMOS transistor M1, a PMOS transistor M3, an NMOS transistor M2, an NMOS transistor M4, a resistor R1, a resistor R2, a NOT gate NOT1, a NOT gate NOT2, a NOT gate NOT3, a NOT gate NOT4, a NOT gate NOT5, a NOT gate NOT6, a NOT gate NOT7, a NOT gate NOT8, a Schmitt trigger SMT1, SMT2, and a NOR gate NOR1, NOR2.

[0051] The source of the PMOS transistor M1 is connected to the power supply, the drain is connected to the source of the NMOS transistor M2, the drain is connected to one end of the Schmitt trigger SMT1, the gate is connected to one end of the NOT gate NOT1, and one end of the NOT gate NOT1 is connected to the input. The gate of the NMOS transistor M2 is connected to one end of the NOT gate NOT1, the source is connected to one end of the resistor R1, the other end of the resistor R1 is connected to ground, the other end of the Schmitt trigger SMT1 is connected to one end of the NOT gate NOT3, the other end of the NOT gate NOT3 is connected to the input of the NOR gate NOR1, the other input of the NOR gate NOR1 is connected to the gate of the PMOS transistor M1, the output of the NOR gate NOR1 is connected to the input of the NOT gate NOT5, the output of the NOT gate NOT5 is connected to the input of the NOT gate NOT6, and the output of the NOT gate NOT6 is connected to IN1 of the high-voltage level shifter circuit 101 with transient dose rate hardening. The source of the PMOS transistor M3 is connected to the power supply, the drain is connected to the drain of the NMOS transistor M4, the drain is connected to one end of the Schmitt trigger SMT2, the gate is connected to one end of the NOT gate NOT2, and one end of the NOT gate NOT2 is connected to the NOT gate NOT1. The gate of the NMOS transistor M4 is connected to one end of the NOT gate NOT2, the source is connected to one end of the resistor R2, the other end of the resistor R2 is connected to ground, the other end of the Schmitt trigger SMT2 is connected to one end of the NOT gate NOT4, the other end of the NOT gate NOT4 is connected to the input of the NOR gate NOR2, the other input of the NOR gate NOR2 is connected to the gate of the PMOS transistor M3, the output of the NOR gate NOR2 is connected to the input of the NOT gate NOT7, the output of the NOT gate NOT7 is connected to the input of the NOT gate NOT8, and the output of the NOT gate NOT8 is connected to IN2 of the high-voltage level shifter circuit 101 with transient dose rate hardening.

[0052] When the narrow pulse generating circuit 100 is in operation, it generates two offset square waves, and then performs a logical operation of OR and NON on the two square waves to generate the required pulse signal. The pulse delay is determined by the RC circuit delay, the Schmitt trigger delay, and the inverter delay. The output narrow pulse signal is transmitted to the high-voltage level transfer circuit (101) with enhanced resistance to transient dose rate. Since the on-resistance of the N-tube decreases and the on-resistance of the P-tube increases after radiation, the N-tube is often connected in series and the P-tube is connected in parallel in device selection. The switching threshold VM is the point where the input is equal to the output. In general, VM is at the midpoint of the voltage swing, so that the low-level noise tolerance and the high-level noise tolerance have similar values. Since PMOS and NMOS devices have different sensitivities to total dose radiation, the radiation conditions have different effects on the turn-on thresholds of the two devices. By modifying the ratio of the PMOS and NMOS devices in the circuit, the switching threshold VM is reduced, thereby offsetting the effect of the total dose on the switching characteristics.

[0053] like Figure 3 As shown, the high-voltage level shifting circuit 101 with enhanced transient dose rate resistance includes a diode D1, a diode D2, a diode D3, a diode D4, a diode D5, a diode D6, a PMOS transistor P1, a PMOS transistor P2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, an NMOS transistor MH1, an NMOS transistor MH2, an NMOS transistor MH3, and NOT gates NOT9 and NOT10.

[0054] The source of the NMOS transistor MH1 is connected to one end of the resistor R6, the drain is connected to the drain of the PMOS transistor P1, the gate is connected to the input IN1, and the other end of the resistor R6 is connected to the ground. The source and gate of the NMOS transistor MH2 are connected to one end of the resistor R7, the drain is connected to the gate of the PMOS transistor P1, and the other end of the resistor R6 is connected to the ground. The source of the NMOS transistor MH3 is connected to one end of the resistor R8, the drain is connected to the drain of the PMOS transistor P2, the gate is connected to the input IN2, and the other end of the resistor R8 is connected to the ground. The source of the PMOS transistor P1 is connected to the power supply, and the gate is connected to the gate of the PMOS transistor P2. The source of the PMOS transistor P2 is connected to the power supply, and the gate is connected to one end of the resistor R4. One end of the diode D1 is connected to the power supply, and the other end is connected to one end of the diode D2. The diode D2 The other end is connected to one end of the resistor R3, the other end of the resistor R3 is connected to the power supply, one end of the diode D3 is connected to the power supply, the other end is connected to one end of the diode D4, the other end of the diode D4 is connected to one end of the resistor R4, the other end of the resistor R4 is connected to the power supply, one end of the diode D5 is connected to the power supply, the other end is connected to one end of the diode D6, the other end of the diode D6 is connected to one end of the resistor R5, the other end of the resistor R5 is connected to the power supply, the input end of the NOT gate NOT9 is connected to the drain of the PMOS tube P2, the output end of the NOT gate NOT9 is connected to the input end IN1 of the pulse filter circuit 102 with anti-total dose hardening, the input end of the NOT gate NOT10 is connected to the drain of the PMOS tube P1, and the output end of the NOT gate NOT10 is connected to the input end IN2 of the pulse filter circuit 102 with anti-total dose hardening.

[0055] The high-voltage level-shifting circuit 101, with its transient dose rate hardening, converts the input signal waveform into narrow pulse signals corresponding to its rising and falling edges. The low-side narrow pulse signal is then converted into two high-side pulse signals through a core level-shifting circuit. It transmits the logic control signal from the low-voltage region of the high-side channel to the high-voltage region to generate the floating gate control signal. The core component in this circuit is a high-voltage LDMOS device. During the high-voltage level-shifting process, transient dose rate effects can induce transient photocurrents, causing excessive current in the high-voltage LDMOS device and resulting in thermal damage. A resistor is introduced at the source end of the high-current branch of the high-voltage tube to provide transient current limiting, preventing device burnout caused by transient high currents.

[0056] like Figure 4As shown, the pulse filter circuit 102 with total dose reinforcement includes PMOS tube M5, PMOS tube M6, PMOS tube M7, PMOS tube M8, PMOS tube M9, PMOS tube M16, PMOS tube M15, NMOS tube M10, NMOS tube M11, NMOS tube M12, NMOS tube M13, NMOS tube M14, NMOS tube M17, NMOS tube M18, resistor R9, resistor R10, resistor R11, resistor R12, resistor R13, resistor R14, resistor R 15. Resistor R23, PMOS transistor M19, PMOS transistor M20, PMOS transistor M21, PMOS transistor M22, PMOS transistor M23, PMOS transistor M30, PMOS transistor M28, NMOS transistor M24, NMOS transistor M25, NMOS transistor M26, NMOS transistor M27, NMOS transistor M31, NMOS transistor M32, NMOS transistor M29, resistor R16, resistor R17, resistor R18, resistor R19, resistor R20, resistor R21, resistor R22, resistor R24;

[0057] The gate of the PMOS tube M5 is connected to the input, the source is connected to the power supply, and the drain is connected to the drain of the PMOS tube M10. The gate of the NMOS tube M10 is connected to the input, the source is connected to one end of the resistor R9, and the other end of the resistor R9 is connected to the ground. The gate of the PMOS tube M6 is connected to the drain of the PMOS tube M5, the source is connected to the power supply, and the drain is connected to the drain of the PMOS tube M11. The gate of the NMOS tube M11 is connected to the drain of the NMOS tube M10, the source is connected to one end of the resistor R10, and the other end of the resistor R10 is connected to the ground. The gate of the PMOS tube M7 is connected to the drain of the PMOS tube M6, the source is connected to the power supply, and the drain is connected to one end of the resistor R23. The other end of the resistor R23 is connected to the drain of the PMOS tube M12. The gate of 12 is connected to the drain of NMOS tube M11, the source is connected to one end of resistor R11, the other end of resistor R11 is connected to ground, the gate of PMOS tube M8 is connected to one end of capacitor C1, one end of capacitor C1 is connected to the drain of NMOS tube M12, and the other end is connected to one end of resistor R12, the other end of resistor R12 is connected to ground, the source of PMOS tube M8 is connected to ground, the drain is connected to the source of PMOS tube M15, the drain is connected to the gate of PMOS tube M15 and the gate of NMOS tube M14, the drain is connected to the gate of PMOS tube M15 and the gate of NMOS tube M13, the drain of PMOS tube M15 is connected to the drain of NMOS tube M14, the source of NMOS tube M14 is connected to the drain of NMOS tube M13, and NMOS tube M1 The source of the PMOS transistor M16 is connected to one end of the resistor R13, the other end of the resistor R13 is connected to the ground, the source of the PMOS transistor M16 is connected to the drain of the PMOS transistor M8, the gate of the PMOS transistor is connected to the gate of the NMOS transistor M17, the gate of the PMOS transistor M16 is connected to the drain of the PMOS transistor M15, the drain of the PMOS transistor M16 is connected to one end of the resistor R14, the other end of the resistor R14 is connected to the ground, the gate of the NMOS transistor M17 is connected to the drain of the NMOS transistor M14, the drain of the NMOS transistor M17 is connected to the power supply, the source of the NMOS transistor M17 is connected to the drain of the NMOS transistor M14, the gate of the PMOS transistor M9 is connected to the drain of the NMOS transistor M15, the source is connected to the power supply, the drain of the PMOS transistor M9 is connected to the drain of the NMOS transistor M18, and the NMOS transistor M19 is connected to the NMOS transistor M20. The gate of the OS transistor M18 is connected to the drain of the NMOS transistor M15, and the source is connected to one end of the resistor R15, the other end of the resistor R15 is connected to the ground. The drain of the NMOS transistor M18 is connected to the R end of the RS trigger circuit 104 with total dose hardening. The gate of the PMOS transistor M19 is connected to the input, the source is connected to the power supply, and the drain is connected to the drain of the PMOS transistor M24. The gate of the NMOS transistor M24 is connected to the input, the source is connected to one end of the resistor R16, and the other end of the resistor R16 is connected to the ground. The gate of the PMOS transistor M20 is connected to the drain of the PMOS transistor M19, the source is connected to the power supply, and the drain is connected to the drain of the PMOS transistor M25. The gate of the NMOS transistor M25 is connected to the drain of the NMOS transistor M24, and the source is connected to one end of the resistor R17.The other end of resistor R17 is connected to ground, the gate of PMOS tube M21 is connected to the drain of PMOS tube M20, the source is connected to the power supply, the drain is connected to one end of resistor R24, the other end of resistor R24 ​​is connected to the drain of PMOS tube M26, the gate of NMOS tube M26 is connected to the drain of NMOS tube M25, the source is connected to one end of resistor R18, the other end of resistor R18 is connected to ground, the gate of PMOS tube M22 is connected to one end of capacitor C2, one end of capacitor C2 is connected to the drain of NMOS tube M26 The other end is connected to one end of the resistor R19, the other end of the resistor R19 is connected to the ground, the source of the PMOS tube M22 is connected to the ground, the drain is connected to the source of the PMOS tube M28, the drain is connected to the gate of the PMOS tube M28 and the gate of the NMOS tube M29, the drain is connected to the gate of the PMOS tube M28 and the gate of the NMOS tube M27, the drain of the PMOS tube M28 is connected to the drain of the NMOS tube M29, the source of the NMOS tube M29 is connected to the drain of the NMOS tube M27, and the NMOS tube The source of M27 is connected to one end of the resistor R20, the other end of the resistor R20 is connected to the ground, the source of the PMOS tube M30 is connected to the drain of the PMOS tube M22, the gate of the PMOS tube is connected to the gate of the NMOS tube M31, the gate of the PMOS tube M30 is connected to the drain of the PMOS tube M28, the drain of the PMOS tube M30 is connected to one end of the resistor R21, the other end of the resistor R21 is connected to the ground, the gate of the NMOS tube M31 is connected to the drain of the NMOS tube M29, and the drain of the NMOS tube M31 is connected to the ground. The source of the NMOS transistor M31 is connected to the drain of the NMOS transistor M29, the gate of the PMOS transistor M23 is connected to the drain of the NMOS transistor M29, the source is connected to the power supply, the drain of the PMOS transistor M23 is connected to the drain of the NMOS transistor M32, the gate of the NMOS transistor M32 is connected to the drain of the NMOS transistor M28, the source is connected to one end of the resistor R22, the other end of the resistor R22 is connected to ground, and the drain of the NMOS transistor M32 is connected to the S end of the RS trigger circuit 104 with total dose hardening.

[0058] The pulse filter circuit 102 with anti-total dose reinforcement is mainly composed of a filter and a Schmitt trigger. When the pulse input is less than the fixed pulse width, it can be filtered out. When a noise pulse comes, the M8 tube will be turned on to charge the capacitor, thereby transmitting the noise input signal to the next-level module. When filtering the noise, the charged capacitor voltage can be made so that the subsequent device cannot be reversed. After filtering, the signal is passed to the RS trigger circuit 104 with anti-total dose reinforcement. The pulse filter circuit 102 with anti-total dose reinforcement adopts methods such as increasing the source resistance to address the threshold voltage change, reserving the drive margin, and adjusting the VM value to complete the anti-total dose reinforcement design.

[0059] like Figure 5As shown, the neutron-hardened undervoltage detection circuit 103 includes a resistor R25, a resistor R26, a resistor R27, an NMOS transistor M33, a comparator COMP1, a NOT gate NOT11, and a NOT gate NOT12;

[0060] One end of the resistor R25 is connected to the power supply, and the other end is connected to the input of the comparator COMP1. One end of the resistor R26 is connected to the other end of the resistor R25, and the other end is connected to the resistor R27. The other end of the resistor R27 is connected to ground. The output end of the comparator COMP1 is connected to the input of the NOT gate NOT11. The output of the NOT gate NOT11 is connected to the input of the NOT gate NOT12. The output of the NOT gate NOT12 is connected to the gate of the NMOS transistor M33. The source of the NMOS transistor M33 is connected to ground. The drain of the NMOS transistor M33 is connected to one end of the resistor R27. The gate of the NMOS transistor M33 is connected to the UVLO end of the RS trigger circuit 104 with total dose hardening.

[0061] The driving circuit may cause functional errors and increased failure rate due to undervoltage. Therefore, in order to ensure the normal operation of the circuit, it is necessary to adopt an undervoltage detection circuit 103 with neutron resistance reinforcement. When the power supply voltage drops below the protection voltage designed by the undervoltage protection module, the gate control signal of the power tube will be forced to turn off until the power supply voltage returns to the set voltage value. The undervoltage protection releases the fault signal and the circuit resumes normal operation. When the error signal comes, the signal is transmitted to the RS trigger circuit 104 with total dose reinforcement. A bipolar circuit is used in the undervoltage protection circuit to generate a voltage reference comparison point. MOS devices are less sensitive to neutron injection, and the reinforcement method for bipolar devices mainly uses the method of compressing the base width.

[0062] like Figure 6 As shown, the total dose hardened RS trigger circuit 104 includes a NAND gate NAND1 and a NAND gate NAND2;

[0063] The first input terminal of the NAND gate NAND1 is connected to the UVLO input terminal, the second input terminal of the NAND gate NAND1 is connected to the R input terminal, the third input terminal of the NAND gate NAND1 is connected to the output terminal of the NAND gate NAND2, the first input terminal of the NAND gate NAND2 is connected to the output terminal of the NAND gate NAND1, the second input terminal of the NAND gate NAND2 is connected to the S input terminal, and the output terminal of the NAND gate NAND2 is output as the final output terminal.

[0064] When a valid narrow pulse signal appears at the R and S terminals of the RS flip-flop circuit 104, the flip-flop switches state as long as the pulse width meets the trigger's minimum response time. Even after the pulse disappears, the bistable structure maintains its output, converting the transient pulse into a sustained level. The circuit also achieves total dose hardening by increasing the source resistance to account for threshold voltage variations, reserving drive margin, and adjusting the VM value.

[0065] The signal capture during the instantaneous dose rate irradiation test of the circuit is carried out, and the test data is plotted into a scatter plot. When the instantaneous photocurrent signal arrives, the output waveform instantly generates a narrow pulse electrical signal, and returns to normal after the instantaneous photocurrent signal ends. The output waveform is as follows Figure 7 The circuit was selected for dynamic irradiation test, and the test data was recorded. The sample was subjected to cobalt source irradiation test, neutron irradiation test, and instantaneous dose irradiation test. During the test, the power supply current did not change significantly. The output waveform of the driving circuit was observed online. The output waveform is shown as follows: Figure 8 shown.

[0066] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should be regarded as within the scope of protection of the present invention.

Claims

1. A radiation-hardened level shifter circuit for a high-voltage SOI half-bridge driver, characterized in that: The invention comprises a narrow pulse generating circuit (100) with a total dose reinforcement, a high voltage level transfer circuit (101) with a transient dose rate reinforcement, a pulse filtering circuit (102) with a total dose reinforcement, and an RS trigger circuit (104) with a total dose reinforcement, which are connected in sequence. The RS trigger circuit (104) with a total dose reinforcement is further connected to an undervoltage detection circuit (103) with a neutron reinforcement; wherein: The narrow pulse generating circuit (100) with total dose hardening is used to provide a narrow pulse input to the high-voltage level transfer circuit (101) with instantaneous dose rate hardening; The high-voltage level transfer circuit (101) with transient dose rate reinforcement is used to provide a low-voltage to high-voltage narrow pulse input, which is transmitted to the pulse filtering circuit (102) with total dose reinforcement; The pulse filter circuit (102) with total dose hardening is used to filter noise signals generated during the opening and closing processes of the LDMOS device in the high-voltage level transfer circuit (101) with instantaneous dose rate hardening, to prevent false triggering when the amplitude of the noise signal reaches the trigger threshold, and to transmit the filtered signal to the RS trigger circuit (104) with total dose hardening; The undervoltage detection circuit (103) with neutron resistance reinforcement is used to generate an undervoltage detection signal to prevent the power supply voltage from being too low, and at the same time transmit the overvoltage and undervoltage detection signal to the RS trigger circuit (104) with total dose reinforcement; The total dose hardened RS trigger circuit (104) identifies an undervoltage detection signal and simultaneously restores a pair of two-path narrow pulse signals generated by a pulse generating circuit (100) into a single wide pulse signal.

2. The radiation-hardened level shifter circuit for a high-voltage SOI half-bridge driver according to claim 1, wherein: The total dose hardening resistant narrow pulse generating circuit (100) comprises: a first narrow pulse generating branch and a second narrow pulse generating branch of two identical circuits, wherein the circuit connection relationship comprises: the input end is connected to the output end through a NOT gate NOT1, two parallel MOS tubes (M1, M2), a Schmitt trigger SMT1, a NOR gate NOR1, a NOT gate NOT5, and a NOT gate NOT6 in sequence; the second input end of the NOT gate NOR1 is also connected to the output end of the NOT gate NOT1; The source of the PMOS transistor M1 is connected to the power supply, the drain is respectively connected to the drain of the NMOS transistor M2 and one end of the Schmitt trigger SMT1, and the gate is connected to one end of the NOT gate NOT1; the gate of the NMOS transistor M2 is connected to one end of the NOT gate NOT1, and the source is connected to the ground via the resistor R1; the output end of the NOT gate NOT1 of the first narrow pulse branch is also connected to the input end of the second narrow pulse branch; The output ends of the first narrow pulse branch and the second narrow pulse branch are respectively connected to two input ends (IN1, IN2) of a high-voltage level transfer circuit (101) reinforced against transient dose rate.

3. The radiation-hardened level shifter circuit for a high-voltage SOI half-bridge driver according to claim 1, wherein: The high-voltage level transfer circuit (101) with transient dose rate reinforcement includes: The source of NMOS transistor MH1 is connected to ground via resistor R6, its drain is connected to the drain of PMOS transistor P1, and its gate is connected to input IN1. The source and gate of NMOS transistor MH2 are connected to one end of resistor R7, its drain is connected to the gate of PMOS transistor P1, and the other end of resistor R7 is connected to ground. The source of NMOS transistor MH3 is connected to ground via resistor R8, its drain is connected to the drain of PMOS transistor P2, and its gate is connected to input IN2. The source of the PMOS tube P1 is connected to the power supply, the gate is connected to the gate of the PMOS tube P2, one drain is connected to the power supply via diodes D2 and D1 in sequence, and the other drain is connected to the power supply via resistor R4; the drain of the PMOS tube P1 is also connected to the input terminal IN2 of the pulse filter circuit (102) for total dose reinforcement via a NOT gate NOT10; The source of the PMOS tube P2 is connected to the power supply, one path of the gate is connected to the power supply via diodes D4 and D3 in sequence, another path of the gate is connected to the power supply via resistor R4, one path of the drain is connected to the power supply via diodes D6 and D5 in sequence, and another path of the drain is connected to the power supply via resistor R5; the drain of the PMOS tube P2 is also connected to the input terminal IN1 of the pulse filter circuit (102) for total dose reinforcement via a NOT gate NOT9.

4. The radiation-hardened level shifter circuit for a high-voltage SOI half-bridge driver according to claim 1, wherein: The pulse filter circuit (102) for total dose reinforcement includes a first narrow pulse filter branch and a second narrow pulse filter branch, both of which have the same circuits. The circuit connection relationship includes: The input terminal IN1 of the pulse filter circuit (102) with total dose reinforcement is connected to the gate of the PMOS tube M5 and the gate of the NMOS tube M10 respectively, the source of the PMOS tube M5 is connected to the power supply, the drain is connected to the drain of the NMOS tube M10, and the source of the NMOS tube M10 is connected to the ground via the resistor R9; The drain of the PMOS transistor M5 is connected to the gate of the PMOS transistor M6 and the gate of the NMOS transistor M11 respectively. The source of the PMOS transistor M6 is connected to the power supply, and the drain is connected to the drain of the NMOS transistor M11. The source of the NMOS transistor M11 is connected to the ground via the resistor R10. The drain of the PMOS transistor M6 is connected to the gate of the PMOS transistor M7 and the gate of the NMOS transistor M12 respectively. The source of the PMOS transistor M7 is connected to the power supply, and the drain is connected to the drain of the NMOS transistor M12 via the resistor R23. The source of the NMOS transistor M12 is connected to the ground via the resistor R11. The drain of the NMOS transistor M12 is also connected to the ground via the capacitor C1 and the resistor R12. The drain of the NMOS tube M12 is connected to the gate of the PMOS tube M8, the gate of the PMOS tube M15, the gate of the NMOS tube M14, and the gate of the NMOS tube M13 respectively; The source of the PMOS transistor M8 is connected to the power supply, and the drain is connected to the source of the PMOS transistor M15; the drain of the PMOS transistor M15 is connected to the drain of the NMOS transistor M14; the source of the NMOS transistor M14 is connected to the drain of the NMOS transistor M13, and the source of the NMOS transistor M13 is connected to the ground via the resistor R13; The drain of the PMOS transistor M15 is also connected to the gate of the PMOS transistor M16 and the gate of the NMOS transistor M17 respectively; the source of the PMOS transistor M16 is connected to the drain of the PMOS transistor M8, and the drain is connected to the ground via the resistor R14; the source of the NMOS transistor M17 is connected to the source of the PMOS transistor M15, and the drain is connected to the power supply; The drain of the PMOS transistor M15 is also connected to the gates of the PMOS transistor M19 and the NMOS transistor M18 respectively; the source of the PMOS transistor M19 is connected to the power supply, and the drain is connected to the output terminal OUT1; the source of the NMOS transistor M18 is connected to the ground via the resistor R15, and the drain is connected to the output terminal OUT1.

5. The radiation-hardened level shifter circuit for a high-voltage SOI half-bridge driver according to claim 1, wherein: The total dose hardened RS trigger circuit (104) comprises: a NAND gate NAND1 and a NAND gate NAND2; The first input terminal of the NAND gate NAND1 is connected to the UVLO input terminal, the second input terminal of the NAND gate NAND1 is connected to the R input terminal, the third input terminal of the NAND gate NAND1 is connected to the output terminal of the NAND gate NAND2, the first input terminal of the NAND gate NAND2 is connected to the output terminal of the NAND gate NAND1, the second input terminal of the NAND gate NAND2 is connected to the S input terminal, and the output terminal of the NAND gate NAND2 is output as the final output terminal.

6. The radiation-hardened level shifter circuit for a high-voltage SOI half-bridge driver according to claim 1, wherein: The neutron-hardened undervoltage detection circuit (103) comprises: The power supply is connected to the positive input terminal of the comparator COMP1 through the resistor R25. The other end of the resistor R25 is connected to the ground through the resistor R26 and the resistor R27 in sequence. The output end of the comparator COMP1 is connected to the UVLO end of the RS trigger 104 with total dose hardening through the NAND gate NOT11 and the NAND gate NOT12 in sequence. The output end of the NAND gate NOT12 is also connected to the gate of the NMOS transistor M33. The source of the NMOS transistor M33 is connected to the ground, and the drain of the NMOS transistor M33 is connected to the resistors R26 and R27.

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