High-precision low-latency analog-to-digital converter offset error low-overhead digital calibration method

Abstract

The application discloses a high-precision low-delay analog-digital converter (ADC) low-overhead digital calibration method, and relates to the technical field of integrated circuit design.The method comprises the following steps: obtaining a bit weight matrix and an error vector according to the output of the ADC; performing amplification on the bit weight matrix to obtain a minimum segmentation matrix; performing least square on the error vector according to the minimum segmentation matrix to obtain a calibration weight vector; and performing calibration on the output of the ADC according to the minimum segmentation matrix and the calibration weight vector.The bit weight matrix is amplified to obtain the minimum segmentation matrix, and the minimum segmentation calibration is realized based on the minimum segmentation matrix; and the calibration precision is improved by increasing the number of calibration weights.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design technology, specifically relating to a high-precision, low-delay analog-to-digital converter offset error low-overhead digital calibration method. Background Technology

[0002] Analog-to-digital converter (ADC) bit weight calibration is a technique used to compensate for ADC errors and improve accuracy. It is primarily used to correct bit weight deviations in converters such as Successive Approximation Analog-to-Digital Converters (SAR ADCs), Capacitive Digital-to-Analog Converters (CDACs), and Current-Swept DACs (Digital-to-Analog Converters). These deviations are typically caused by process mismatches, parasitic effects, or environmental factors, and severely impact the ADC's linearity and effective number of bits.

[0003] Bit weight calibration can only perform linear calibration for capacitor mismatch errors. Due to the presence of parasitic capacitance, capacitor mismatch errors are non-linear; therefore, traditional bit weight calibration struggles to calibrate non-linear errors caused by parasitic capacitance. Bit weight calibration typically relies on accurate estimation of the capacitor mismatch error at each bit in the analog-to-digital converter (ADC) to generate effective calibration weights, thereby achieving precise correction of the ADC output. However, in actual calibration processes, limitations imposed by thermal noise interference and the physical characteristics of the manufacturing process and devices make error estimation difficult to achieve completely accurate results, leading to certain deviations in the bit weight calibration results. Summary of the Invention

[0004] To address the aforementioned problems in the existing technology, this invention provides a high-precision, low-delay analog-to-digital converter offset error and low-overhead digital calibration method. The technical problem to be solved by this invention is achieved through the following technical solution:

[0005] This invention provides a high-precision, low-delay analog-to-digital converter offset error and low-overhead digital calibration method, comprising:

[0006] Step 1: Obtain the bit weight matrix and error vector based on the output of the analog-to-digital converter;

[0007] Step 2: Expand the bit weight matrix to obtain the minimum segmented matrix;

[0008] Step 3: Perform least squares on the error vector based on the minimum piecewise matrix to obtain the calibration weight vector;

[0009] Step 4: Calibrate the output of the analog-to-digital converter according to the minimum segmentation matrix and the calibration weight vector.

[0010] In one embodiment of the present invention, step 1 includes:

[0011] Step 1.1: Sample the binary digital code vector output by the analog-to-digital converter to obtain the bit weight matrix;

[0012] Step 1.2: Perform sine fitting on the actual decimal output code vector of the analog-to-digital converter to estimate the ideal decimal output code vector of the analog-to-digital converter. Based on the actual decimal output code vector and the ideal decimal output code vector, obtain the error vector.

[0013] In one embodiment of the present invention, the bit weight matrix is ​​represented as:

[0014] ;

[0015] in, The number of samples taken. The number of bits in the analog-to-digital converter. For the first The binary digit code vector of each sample, , , For the first The first sample in the binary code vector A digit code.

[0016] In one embodiment of the present invention, the error vector is represented as:

[0017] ;

[0018] in, For the error vector, This is the actual decimal output code vector. This is the ideal decimal output code vector.

[0019] In one embodiment of the present invention, step 2 includes:

[0020] Step 2.1: Invert the binary bits of the column vector with the most significant bit in the bit weight matrix to obtain the corresponding transformed column vector;

[0021] Step 2.2: Combine the transformed column vector with the bit weight matrix to obtain the minimum segmented matrix.

[0022] In one embodiment of the present invention, the minimum piecewise matrix is ​​represented as:

[0023] ;

[0024] in, It is the minimum piecewise matrix. To transform column vectors, This is the bit weight matrix. , It is the column vector of the most significant bit in the bit weight matrix.

[0025] In one embodiment of the present invention, in step 3, the calibration weight vector is represented as:

[0026] ;

[0027] in, To calibrate the weight vector, It is the minimum piecewise matrix. For the error vector, This indicates the matrix transpose.

[0028] In one embodiment of the present invention, in step 4, the output of the analog-to-digital converter is calibrated according to the following formula:

[0029] ;

[0030] in, This is the calibrated decimal output code vector. This is the actual decimal output code vector. It is the minimum piecewise matrix. To calibrate the weight vector.

[0031] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0032] This invention presents a high-precision, low-delay analog-to-digital converter offset error and low-overhead digital calibration method. It expands the bit weight matrix to obtain a minimum piecewise matrix, and performs minimum piecewise calibration based on this minimum piecewise matrix. This invention improves calibration accuracy by increasing the number of calibration weights. Increasing the calibration weights allows for a more accurate estimation of the nonlinear component of the capacitor mismatch model because it makes the linear estimation closer to the nonlinear error, thus achieving more precise calibration. Increasing the calibration weights also reduces the error in estimating the mismatched capacitance, thereby improving calibration accuracy.

[0033] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of a high-precision, low-delay analog-to-digital converter offset error and low-overhead digital calibration method provided in an embodiment of the present invention;

[0035] Figure 2 This is a flowchart of the ADC error calibration process using minimum segment calibration and bit weight calibration provided in this embodiment of the invention;

[0036] Figure 3 This is a comparison chart of the spectra of uncalibrated, bit-weighted calibrated, and minimum segmented calibrated samples provided in an embodiment of the present invention;

[0037] Figure 4 This is a histogram of the signal-to-noise ratio (SNDR) and spurious dynamic range (SFDR) before and after calibration in Monte Carlo simulation using the method of this invention. Detailed Implementation

[0038] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following describes in detail, with reference to the accompanying drawings and specific embodiments, a high-precision, low-delay analog-to-digital converter offset error and low-overhead digital calibration method proposed according to the present invention.

[0039] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a more in-depth and concrete understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the technical solutions of the present invention.

[0040] This invention provides a high-precision, low-latency analog-to-digital converter (ADC) offset error low-overhead digital calibration method. It significantly improves calibration results by slightly increasing calibration weights. Specifically, it improves the matrix structure in the bit-weighted calibration method and introduces a small number of additional calibration weights, thereby significantly improving the accuracy of ADC error calibration. This method effectively enhances the accuracy and robustness of calibration results while maintaining low computational complexity. This invention can improve the calibration accuracy of various ADC error calibration methods, such as least-squares sine fitting and filtering / least-squares optimization. Furthermore, this method is applicable to ADCs with binary weight structures as well as those with non-binary weight structures, demonstrating strong versatility and adaptability.

[0041] Please see Figure 1 , Figure 1 This is a schematic diagram of a high-precision, low-delay analog-to-digital converter offset error and low-overhead digital calibration method provided in an embodiment of the present invention, as shown below. Figure 1 As shown, the high-precision, low-delay analog-to-digital converter offset error low-overhead digital calibration method of this invention includes the following steps:

[0042] Step 1: Obtain the bit weight matrix and error vector based on the output of the analog-to-digital converter.

[0043] Optionally, step 1 includes:

[0044] Step 1.1: Sample the binary digital code vector output by the analog-to-digital converter to obtain the bit weight matrix.

[0045] In this embodiment, the number of samples is assumed to be... The number of bits in an ADC Therefore, the bit weight matrix formed by the sampled samples is expressed as:

[0046] ;

[0047] in, The number of samples taken. The number of bits in the analog-to-digital converter. For the first The binary digit code vector of each sample, , , For the first The first sample in the binary code vector digit code It is generally represented by binary 0 and 1.

[0048] The matrix form of the bit weight matrix can be expressed as:

[0049] .

[0050] Step 1.2: Perform sine fitting on the actual decimal output code vector of the analog-to-digital converter to estimate the ideal decimal output code vector of the analog-to-digital converter. Based on the actual decimal output code vector and the ideal decimal output code vector, obtain the error vector.

[0051] In this embodiment, the actual decimal output code vector of the ADC obtained by sampling is defined as follows: , , , Indicates the first The actual decimal output code of the next sample. .

[0052] The default input sinusoidal signal has a precision far exceeding the resolution of the ADC, thus allowing the ideal decimal output code vector of the ADC to be obtained. It can be viewed as an ideal sine wave. Based on this, the actual decimal output code vector of the ADC can be used to... By performing sine fitting, the corresponding ideal decimal output code vector is estimated. , It can be represented as: , Indicates the first Ideal decimal output code after subsampling. .

[0053] The error vector refers to the difference between the actual decimal output code vector of the ADC and the ideal decimal output code vector of the ADC. In this embodiment, the error vector is represented as:

[0054] ;

[0055] in, For the error vector, This is the actual decimal output code vector. This is the ideal decimal output code vector.

[0056] Error vector It can be represented as: , ,in ， Indicates the first Error extracted from each sample.

[0057] It is understandable that the actual decimal output code vector of the ADC With bit weight matrix The key is as follows:

[0058] ;

[0059] in, The weight vector of the ADC. , , Indicates the first Each weight, If it is a binary ADC, then .

[0060] Step 2: Expand the positional weight matrix to obtain the minimum segmented matrix.

[0061] Optionally, step 2 includes:

[0062] Step 2.1: Invert the column vector of the most significant bit in the bit weight matrix according to the binary bits to obtain the corresponding transformed column vector;

[0063] In this embodiment, let the transformed column vector be , specifically, , , To make the bit weight matrix In D M-1 The result is obtained by changing 0 to 1 and 1 to 0. , , Bit weight matrix A column vector of the most significant bit (MSB) in the byte order. Where, if... In If it is 1, then the corresponding In It is 0, and conversely, if In If it is 0, then the corresponding In The value is 1.

[0064] By Perform a linear transformation to obtain :

[0065] .

[0066] Step 2.2: Combine the transformed column vector with the bit weight matrix to obtain the minimum piecewise matrix.

[0067] In this embodiment, the minimum piecewise matrix is ​​represented as:

[0068] ;

[0069] in, It is the minimum piecewise matrix. To transform column vectors, This is the bit weight matrix. , It is the column vector of the most significant bit in the bit weight matrix.

[0070] For example, an 8-bit ADC outputs 12 decimal digits as... Taking binary weights as an example, its corresponding bit weight matrix and the minimum piecewise matrix obtained after amplification As shown below:

[0071] .

[0072] Step 3: Perform least squares on the error vector based on the minimum piecewise matrix to obtain the calibration weight vector.

[0073] In this embodiment, the calibration weight vector is represented as:

[0074] ;

[0075] in, To calibrate the weight vector, It is the minimum piecewise matrix. For the error vector, This indicates the matrix transpose.

[0076] Calibration weight vector It can be represented as: ,in, Representing the The calibration weight corresponding to the bit. , This indicates the increased calibration weight. In That is, the calibration weight vector corresponding to bit weight calibration. .

[0077] Step 4: Calibrate the output of the analog-to-digital converter based on the minimum segmentation matrix and the calibration weight vector.

[0078] In this embodiment, the output of the analog-to-digital converter is calibrated according to the following formula:

[0079] ;

[0080] in, This is the calibrated decimal output code vector. This is the actual decimal output code vector. It is the minimum piecewise matrix. To calibrate the weight vector.

[0081] In practical applications, after storing and locking the calibration weight vector, the ADC output can be directly calibrated during subsequent sampling. The corresponding minimum piecewise matrix is ​​obtained from the ADC output. Using the minimum piecewise matrix and calibration weight vector Decimal output code vector of ADC By performing calibration, the calibrated ADC decimal output code vector can be obtained. , , , Indicates the first The decimal output code of a calibrated ADC.

[0082] The high-precision, low-latency analog-to-digital converter offset error low-overhead digital calibration method of the present invention expands the bit weight matrix to obtain a minimum segmented matrix, and performs minimum segment calibration based on this minimum segmented matrix. Compared with existing bit weight calibration, the minimum segment calibration of the present invention has the following advantages:

[0083] (1) Traditional bit weight calibration methods can usually only compensate for linear errors caused by capacitor mismatch, and the calibration accuracy is significantly limited when facing nonlinear error models. The minimum piecewise calibration method proposed in this invention can more accurately approximate the nonlinear part of the capacitor mismatch error, thereby achieving effective correction of the nonlinear error source. In this way, the overall calibration accuracy of the ADC is significantly improved, which is especially suitable for application scenarios with high error control accuracy requirements in high-resolution ADC systems.

[0084] (2) Traditional bit weight calibration usually relies on the accurate estimation of the capacitance mismatch error of each bit in the ADC in order to generate the corresponding calibration weight, thereby effectively correcting the ADC output. However, in the actual calibration process, due to the influence of thermal noise interference and the physical limitations of the device, it is impossible to achieve a completely accurate estimation of the capacitance mismatch error, which leads to a certain error in the calibration weight. This invention introduces additional calibration weights, which can compensate for the uncertainty in error estimation to a certain extent and effectively improve the overall calibration accuracy.

[0085] Furthermore, the effectiveness of the method of the present invention will be illustrated through specific examples. The minimum segment calibration method is applied to ADC error calibration based on least squares sine fitting, and the results are compared and analyzed with the calibration results obtained by the same method using bit weight calibration.

[0086] Please see Figure 2 , Figure 2This is a flowchart of ADC error calibration using minimum segment calibration and bit weight calibration provided in an embodiment of the present invention. The left figure is a flowchart of ADC error calibration based on least squares sine fitting using minimum segment calibration, and the right figure is a flowchart of ADC error calibration based on least squares sine fitting using bit weight calibration.

[0087] like Figure 2 As shown, the ADC error calibration based on least squares sinusoidal fitting using minimum piecewise calibration includes the following steps:

[0088] S1: Generate a high-precision signal source with a signal amplitude of Amp and a signal frequency of... f in The single-tone sine wave signal is obtained and the high-precision single-tone sine wave signal is input into the ADC;

[0089] S2: Obtain the ADC output digital code vector by quantizing the input signal over a period of time using the ADC. Sum of weights matrix ;

[0090] S3: Because the default input sinusoidal signal has a much higher accuracy than the ADC resolution, the output of the ADC under ideal conditions can be... It can be viewed as an ideal sine wave. Based on this, the actual decimal output code vector of the ADC can be used to... By performing sine fitting, the corresponding ideal decimal output code vector is estimated. ;

[0091] S4: Through calculation Obtain the error vector ;

[0092] S5: For bit weight matrix Amplification yields the minimum piecewise matrix. ,make ,in , ,in To make the bit weight matrix In The result is obtained by changing 0 to 1 and 1 to 0; let , , Bit weight matrix A column vector of the most significant bit (MSB). This can be achieved by... Perform a linear transformation to obtain Then With bit weight matrix Combining these steps yields the minimum piecewise matrix. ;

[0093] .

[0094] S6: For the error vector The calibration weight vector is obtained by performing least squares. ;

[0095] .

[0096] S7: After storing and locking the calibration weight vector, the ADC output can be directly calibrated during subsequent sampling. The corresponding minimum piecewise matrix is ​​obtained through the ADC output. Using the minimum piecewise matrix and calibration weight vector The actual decimal output code vector of the ADC By performing calibration, the decimal output code vector of the ADC can be obtained. , , , It can be represented as: , Indicates the first The decimal output code of a calibrated ADC.

[0097] like Figure 2 As shown, the ADC error calibration based on least-squares sinusoidal fitting using bit-weight calibration includes the following steps:

[0098] S1: Generate a high-precision signal source with a signal amplitude of Amp and a signal frequency of... f in The single-tone sine wave signal is then input into the ADC.

[0099] S2: Obtain the ADC output digital code vector by quantizing the input signal over a period of time using the ADC. Sum of weights matrix ;

[0100] S3: Because the default input sinusoidal signal has a much higher accuracy than the ADC resolution, the output of the ADC under ideal conditions can be... It can be viewed as an ideal sine wave. Based on this, the actual decimal output code vector of the ADC can be used to... By performing sine fitting, the corresponding ideal decimal output code vector is estimated. ;

[0101] S4: Through calculation Obtain the error vector ;

[0102] S5: For the error vector The calibration weight vector is obtained by performing least squares. ;

[0103] ;

[0104] in, , Representing the The calibration weight corresponding to the bit. .

[0105] S6: After storing and locking the calibration weights, the ADC output can be directly calibrated during subsequent sampling. The corresponding bit weight matrix can be obtained from the ADC output. Using the bit weight matrix and calibration weight vector The actual decimal output code vector of the ADC By performing calibration, the calibrated decimal output code vector can be obtained. , , , , Indicates the first The decimal output code of a calibrated ADC.

[0106] The proposed minimum segment calibration method was simulated and verified in MATLAB. The simulation object was a 24-bit SAR ADC, and its calibration performance was evaluated under the conditions of a 5% relative error per unit capacitance, a sampling sequence length of 1024 bits, and a calibration bit depth of 15 bits. The sampling frequency was set during the simulation. f s = 2MHz, input signal frequency f in = 68.4 kHz. The traditional bit-weight calibration method and the minimum segment calibration method proposed in this invention were respectively applied to the ADC error correction process based on least squares sine fitting to compare the performance differences between the two in terms of calibration accuracy.

[0107] Please see Figure 3 , Figure 3 This is a comparison chart of the spectra of uncalibrated, bit-weighted calibrated, and minimum segmented calibrated spectra provided by an embodiment of the present invention. Figure 3As shown, in the uncalibrated state, the system's signal-to-noise ratio (SNR) is 103.9 dB, signal-to-noise ratio (SNDR) is 103.8 dB, effective number of bits (ENOB) is 17.0 bit, spurious dynamic range (SFDR) is 110.6 dB, and total harmonic distortion (THD) is -125.4 dB. After bit-weighted calibration, the SNR increases to 123.4 dB, the SNDR to 123.3 dB, the ENOB to 20.2 bits, the SFDR to 140.2 dB, and the THD to -139.0 dB. Minimum segment calibration further improves performance, achieving an SNR of 137.6 dB, an SNDR of 137.6 dB, an ENOB increase to 22.6 bits, an SFDR increase to 150.8 dB, and a further reduction in THD to -162.1 dB. These results demonstrate that the proposed minimum segment calibration method significantly outperforms traditional calibration techniques and has a significant advantage in improving the overall performance of the analog-to-digital converter.

[0108] Please see Figure 4 And Table 1, Figure 4 This is a histogram of SNDR and SFDR before and after calibration in Monte Carlo simulation using the method of this invention. Table 1 is a comparison table of SNDR and SFDR before and after calibration in Monte Carlo simulation using the design of this invention.

[0109] Table 1

[0110]

[0111] Figure 4 Table 1 shows the histograms and statistical parameters of SNDR and SFDR before and after 2000 Monte Carlo simulations under the above conditions, for both bit-weighted calibration and minimum segmentation calibration. Compared to uncalibrated, bit-weighted calibration and minimum segmentation calibration improved the average SNDR by 19.35 dB and 34.63 dB, respectively, and the SFDR by 24.2 dB and 39.62 dB, respectively. Simulation results show that, compared to the bit-weighted calibration method, minimum segmentation calibration improves SNDR and SFDR by 15.28 dB and 15.42 dB, respectively. Furthermore, the standard deviations of SNDR and SFDR for minimum segmentation calibration are significantly lower than those for bit-weighted calibration. In conclusion, minimum segmentation calibration has superior calibration capability and results in a more stable ADC after calibration compared to bit-weighted small-segmentation calibration.

[0112] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes said element.

[0113] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0114] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A high-precision, low-delay analog-to-digital converter offset error and low-overhead digital calibration method, characterized in that, include: Step 1: Obtain the bit weight matrix and error vector based on the output of the analog-to-digital converter; Step 2: Expand the bit weight matrix to obtain the minimum segmented matrix; Step 2 includes: Step 2.1: Invert the binary bits of the column vector with the most significant bit in the bit weight matrix to obtain the corresponding transformed column vector; Step 2.2: Combine the transformed column vector with the bit weight matrix to obtain the minimum piecewise matrix; the minimum piecewise matrix is ​​represented as: ； in, It is the minimum piecewise matrix. To transform column vectors, This is the bit weight matrix. , It is the column vector of the most significant bit in the bit weight matrix; Step 3: Perform least squares on the error vector based on the minimum piecewise matrix to obtain the calibration weight vector; Step 4: Calibrate the output of the analog-to-digital converter according to the minimum segmentation matrix and the calibration weight vector.

2. The high-precision, low-delay analog-to-digital converter offset error low-overhead digital calibration method according to claim 1, characterized in that, Step 1 includes: Step 1.1: Sample the binary digital code vector output by the analog-to-digital converter to obtain the bit weight matrix; Step 1.2: Perform sine fitting on the actual decimal output code vector of the analog-to-digital converter to estimate the ideal decimal output code vector of the analog-to-digital converter. Based on the actual decimal output code vector and the ideal decimal output code vector, obtain the error vector.

3. The high-precision, low-delay analog-to-digital converter offset error low-overhead digital calibration method according to claim 2, characterized in that, The bit weight matrix is ​​represented as follows: ； in, The number of samples collected. The number of bits in the analog-to-digital converter. For the first The binary digit code vector of each sample, , , For the first The first sample in the binary code vector A digit code.

4. The high-precision, low-delay analog-to-digital converter offset error low-overhead digital calibration method according to claim 2, characterized in that, The error vector is represented as: ； in, For the error vector, This is the actual decimal output code vector. This is the ideal decimal output code vector.

5. The high-precision, low-delay analog-to-digital converter offset error low-overhead digital calibration method according to claim 1, characterized in that, In step 3, the calibration weight vector is represented as: ； in, To calibrate the weight vector, It is the minimum piecewise matrix. For the error vector, This indicates the matrix transpose.

6. The high-precision, low-delay analog-to-digital converter offset error low-overhead digital calibration method according to claim 1, characterized in that, In step 4, the output of the analog-to-digital converter is calibrated according to the following formula: ； in, This is the calibrated decimal output code vector. This is the actual decimal output code vector. It is the minimum piecewise matrix. To calibrate the weight vector.

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