Semiconductor device and method of manufacturing the same

Abstract

The application provides a semiconductor device and a preparation method thereof. The device comprises a substrate having a first surface, the substrate having a first doping type; a plurality of source region structures spaced in the substrate, a second surface of the source region structure being in the first surface; a gate structure on the first surface and covering part of the surface of the plurality of source region structures; an anti-static structure on a side of the gate structure away from the substrate, in a direction of the substrate pointing to the gate structure, the anti-static structure comprising a plurality of first doping layers and second doping layers stacked alternately, the first doping layer having a second doping type, and the second doping layer having the first doping type. The static electricity current is released through the anti-static structure, the gate oxide layer of the gate structure is protected, the gate oxide layer is ensured not to be broken down under high static voltage, the anti-static ability of the trench gate structure is improved, and thus the problem of low gate anti-static breakdown ability of the semiconductor device in the related art is solved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor device and a method for fabricating the same. Background Technology

[0002] Power MOSFETs, characterized by low forward voltage drop, high switching speed, and easy gate control, have become an important semiconductor device in power electronics applications. The gate electrostatic discharge (ESD) capability of a power MOSFET is directly related to the chip area and the thickness of the gate oxide layer. SiC MOSFETs, limited by material and process characteristics, have small chip areas, thin gate oxide layers, and poor gate ESD breakdown capability. As the application of SiC MOSFETs becomes more widespread, new SiC MOSFETs with high ESD capabilities are constantly emerging. However, these new SiC MOSFETs exhibit higher switching losses under high-frequency operating conditions, and their gates are easily broken down.

[0003] The information disclosed above in the background section is only intended to enhance the understanding of the background art of the art described herein. Therefore, the background art may contain certain information that does not constitute prior art known to those skilled in the art in this country. Summary of the Invention

[0004] The main objective of this application is to provide a semiconductor device and its fabrication method to solve the problem of low gate electrostatic discharge resistance in existing semiconductor devices.

[0005] To achieve the above objectives, according to one aspect of this application, a semiconductor device is provided, comprising: a substrate having a first surface, the substrate having a first doping type; a plurality of source region structures spaced apart in the substrate, the second surfaces of the source region structures being located in the first surface; a gate structure located on the first surface and covering a portion of the surfaces of the plurality of source region structures; and an antistatic structure located on a side of the gate structure away from the substrate, in a direction from the substrate to the gate structure, the antistatic structure comprising a plurality of staggered first doped layers and second doped layers, the first doped layers having a second doping type and the second doped layers having the first doping type.

[0006] Optionally, the antistatic structure further includes a third doped layer, which is located on the outermost side of the antistatic structure along the direction from the substrate to the gate structure. The third doped layer has the first doping type and the doping concentration of the third doped layer is different from that of the second doped layer.

[0007] Optionally, the third doped layer includes a first sub-doped layer and a second sub-doped layer, wherein the second sub-doped layer is located on the outermost side of the antistatic structure along the direction from the substrate to the gate structure, the first sub-doped layer is located on the side of the second sub-doped layer closer to the substrate, the doping concentration of the second sub-doped layer is higher than the doping concentration of the first sub-doped layer, and the doping concentration of the first sub-doped layer is lower than the doping concentration of the second doped layer.

[0008] Optionally, the first source region structure in the source region structure includes: a first well region, a first doped region, and a second doped region, wherein the side surface of the first well region closest to the gate structure is in contact with the gate structure, the first doped region, and the second doped region, respectively, and the first well region has the second doping type; in a first direction, the first doped region is in contact with the first well region and the second doped region, the first doped region has the first doping type, the first direction forms an angle with the direction of the substrate pointing to the gate structure, and the second doped region has the second doping type.

[0009] Optionally, the semiconductor device further includes an insulating layer located on both sides of the gate structure and the antistatic structure in a first direction, wherein the first source region structure in the source region structure has a first doped region and a second doped region, the insulating layer covers the first doped region, the first doped region has the first doping type, the second doped region has the second doping type, and the first direction forms an angle with the direction of the substrate pointing to the gate structure.

[0010] Optionally, the semiconductor device further includes an anode metal layer and a cathode metal layer, wherein the anode metal layer covers the antistatic structure, the insulating layer, and a portion of the source region structure; and the cathode metal layer is located on the side of the substrate opposite to the first surface.

[0011] Optionally, the projections of the first doped layer and the second doped layer onto the first surface overlap with the projection of the gate structure onto the first surface.

[0012] According to another aspect of this application, a method for fabricating a semiconductor device is provided. The method includes: providing a substrate having a first surface and a first doping type; forming a plurality of source region structures spaced apart in the substrate, with second surfaces of the source region structures located in the first surface; forming a gate structure on the first surface, the gate structure covering portions of the surfaces of the plurality of source region structures; and forming an antistatic structure on a side of the gate structure opposite to the substrate, wherein, in a direction from the substrate to the gate structure, the antistatic structure includes a plurality of interleaved first doped layers and second doped layers, the first doped layers having a second doping type and the second doped layers having the first doping type.

[0013] Optionally, the step of forming a plurality of source region structures includes: performing a first ion implantation at intervals in the substrate to form a plurality of first well regions, the first well regions having the second doping type; performing a second ion implantation in each of the plurality of first well regions to form a plurality of first doped regions, the first doped regions and the first well regions each having a surface located in the first surface, the first doped regions having the first doping type; performing a third ion implantation in one of the first doped regions to form a second doped region, the first doped region being in contact with the first well region and the second doped region in a first direction, the second doped region having the second doping type, the first direction forming an angle with the direction of the substrate pointing to the gate structure.

[0014] Optionally, the step of forming the antistatic structure includes: alternately depositing the materials of the first doped layer and the second doped layer on the side of the pre-gate structure away from the substrate to form a first doped pre-layer and a second doped pre-layer; performing an etching process on the first doped pre-layer, the second doped pre-layer and the pre-gate structure to obtain the first doped layer, the second doped layer and the gate structure, wherein the first doped layer covers the gate structure.

[0015] Applying the technical solution of this application, the semiconductor device of this application includes a substrate, multiple source region structures, a gate structure, and an anti-static structure. The formation of the anti-static structure on top of the gate structure enhances the gate's anti-static capability. The anti-static structure comprises alternating layers of first and second doped layers, with opposite doping types. Multiple PN junction structures are formed between the multiple first and second doped layers. When the gate voltage exceeds a safety threshold, the multiple PN junctions conduct, and current flows through the anti-static structure to release the electrostatic current. This protects the gate oxide layer of the gate structure, ensuring that the gate oxide layer is not broken down under high electrostatic voltage, thus improving the anti-static capability of the trench gate structure and solving the problem of low gate electrostatic breakdown capability in related technologies. Attached Figure Description

[0016] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0017] Figure 1 A cross-sectional structural schematic diagram of a first semiconductor device according to an embodiment of this application is shown;

[0018] Figure 2 A cross-sectional structural schematic diagram of a second semiconductor device according to an embodiment of this application is shown;

[0019] Figure 3 A cross-sectional structural schematic diagram of a third semiconductor device according to an embodiment of this application is shown;

[0020] Figure 4 A schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of this application is shown;

[0021] Figure 5 This diagram shows a cross-sectional structure of the substrate after the formation of the first well region in a semiconductor device fabrication method.

[0022] Figure 6 It shows in Figure 5 A schematic cross-sectional view of the substrate after the formation of the first doped region in the first well region formed in the matrix;

[0023] Figure 7 It shows in Figure 6 A schematic cross-sectional view of the substrate after the formation of the second doped region within the first doped region;

[0024] Figure 8 It shows in Figure 7A schematic diagram of the cross-sectional structure of the substrate after the pre-gate structure and pre-antistatic structure are formed on the substrate;

[0025] Figure 9 It shows the Figure 8 A schematic diagram of the cross-sectional structure of the substrate after etching the pre-gate structure and pre-antistatic structure.

[0026] The above figures include the following reference numerals:

[0027] 10. Substrate; 11. Substrate; 12. Epitaxial layer; 20. Source region structure; 21. First source region structure; 22. Second source region structure; 211. First well region; 212. First doped region; 213. Second doped region; 30. Gate structure; 31. Gate oxide layer; 32. Gate; 300. Pre-gate structure; 310. Pre-gate oxide layer; 320. Pre-gate; 40. Antistatic structure; 41. First doped layer; 410. First doped pre-layer; 42. Second doped layer; 420. Second doped pre-layer; 43. Third doped layer; 431. First sub-doped layer; 432. Second sub-doped layer; 50. Insulating layer; 60. Anode metal layer; 70. Cathode metal layer. Detailed Implementation

[0028] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0029] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0030] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of the invention described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0031] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.

[0032] As described in the background section, existing SiC MOS devices are limited by material and process characteristics, resulting in small chip area, thin gate oxide layer, and poor gate electrostatic discharge (ESD) immunity. With the increasingly widespread application of SiC MOS devices, new SiC MOS devices with high ESD immunity are constantly emerging. However, these new SiC MOS devices exhibit high switching losses under high-frequency operating conditions, and their gates are easily broken down. To address the problem of low gate ESD immunity in existing semiconductor devices, embodiments of this application provide a semiconductor device and its fabrication method.

[0033] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0034] According to one embodiment of this application, a semiconductor device is provided, such as... Figures 1 to 3 As shown, it includes: a substrate 10 having a first surface and a first doping type; a plurality of source region structures 20 spaced apart in the substrate 10, with a second surface of the source region structures 20 located in the first surface; a gate structure 30 located on the first surface and covering a portion of the surface of the plurality of source region structures 20; and an antistatic structure 40 located on the side of the gate structure 30 away from the substrate 10. In the direction from the substrate 10 to the gate structure 30, the antistatic structure 40 includes a plurality of staggered first doped layers 41 and second doped layers 42, the first doped layers 41 having a second doping type and the second doped layers 42 having a first doping type.

[0035] By forming an anti-static structure on top of the gate structure, the gate electrostatic discharge (ESD) capability of semiconductor devices can be improved. This anti-static structure comprises alternating layers of first and second doped layers with opposite doping types. Multiple PN junctions are formed between the multiple first and second doped layers. When the gate voltage exceeds a safety threshold, these PN junctions conduct. Utilizing the reverse breakdown characteristic of PN junctions, electrostatic energy can be rapidly discharged when the preset ESD voltage threshold is exceeded, thus protecting the gate oxide layer from damage. Current flowing through the anti-static structure releases the electrostatic current, protecting the gate oxide layer and ensuring it does not break down under high ESD voltages, thereby improving the ESD capability of the trench gate structure. Furthermore, when the number of stacked first and second doped layers is not limited to two (PNPN or PNPNPN), the structure can be either PNPN or PNPNPN. When the gate voltage exceeds the preset threshold, it can quickly conduct, discharging excess electrostatic energy and protecting the gate oxide layer from damage. This semiconductor device solves the problem of low gate ESD breakdown capability in related technologies.

[0036] The aforementioned source region structure is formed by ion implantation from the first surface into the substrate. After the source region structure is formed, the portion of the first surface with the source region structure becomes the second surface of the source region structure, while the portion of the first surface without the source region structure remains the first surface of the substrate. The second surface and the first surface are located on the same surface, but with different divisions. The upper surface of the source region structure is divided into the second surface, while the upper surface of the substrate without the source region structure is divided into the first surface.

[0037] In the above embodiments, such as Figures 1 to 3 As shown, the gate structure 30 includes a gate oxide layer 31 and a gate 32. The gate oxide layer 31 is located on the substrate 10, and the gate 32 is located on the side of the gate oxide layer 31 facing away from the substrate 10. The gate 32 can be made of polysilicon with N-type doping, and the gate oxide layer 31 can be made of silicon dioxide with a thickness of 30nm-60nm. The gate structure 30 is used for gate signal transmission. By controlling the thickness of the gate oxide layer, efficient control of the channel can be achieved. Reasonable adjustment of the gate structure not only reduces the switching time but also improves the radiation resistance of the device and enhances the reliability of the device.

[0038] Because of their high channel mobility, conventional silicon semiconductor devices typically have thicker gate oxide layers, generally 90-120 nm. In contrast, semiconductor devices, with their lower channel mobility, usually have thinner gate oxide layers to ensure lower channel resistance. This means that conventional silicon semiconductor devices do not require special gate electrostatic discharge (ESD) protection to achieve high gate ESD tolerance. Therefore, the ESD structure of silicon semiconductor devices typically protects the entire device structure rather than just the gate. The ESD structure in this application primarily aims to improve the ESD rating of the gate structure.

[0039] In the above embodiments, the substrate material can be silicon carbide, which allows the device to have high thermal conductivity and high breakdown field strength, making it suitable for manufacturing high-performance devices that can operate under high temperature and high pressure environments. Figures 1 to 3 As shown, the substrate 10 includes a substrate 11 and an epitaxial layer 12. The doping concentration of the substrate 11 is higher than that of the epitaxial layer 12. The higher doping concentration of the substrate 11 can increase the depth of the depletion layer, thereby increasing the reverse breakdown voltage and reducing the risk of device breakdown. Furthermore, the substrate 11 can absorb carriers from the epitaxial layer 12, further reducing the on-resistance. The lower doping concentration of the epitaxial layer 12 can provide greater carrier mobility when the device is turned on, thereby reducing the on-resistance.

[0040] In the above embodiments, the first and second doped layers are relatively thin and meet the withstand voltage requirements of the PN junction under the target ESD level (similar in principle to a Zener diode), thus improving the electrostatic discharge (ESD) level of the gate. When the first and second doped layers are relatively thin, soft breakdown is possible. When the instantaneous voltage is too high (or when the gate voltage exceeds the safe range), the PNP transistor will directly conduct, and due to the low energy, it will not damage the device. Furthermore, the integrated NPNP structure (where the first N is the gate) will be turned on, and the current will be released through the PN junction, protecting the gate oxide layer from breakdown and improving the ESD resistance of the trench gate structure.

[0041] In the above embodiments, the first doping type can be N-type doping or P-type doping, and the second doping type can be P-type doping or N-type doping. For example, the first doping type is N-type doping and the second doping type is P-type doping, or the first doping type is P-type doping and the second doping type is N-type doping. The N-type doping element can be any one of pentavalent elements, including phosphorus (P), arsenic (As), and antimony (Sb), and the P-type doping element can be any one of trivalent elements, including boron (B), aluminum (Al), and gallium (Ga). This application does not impose specific limitations.

[0042] In some alternative implementations, such as Figure 2 and Figure 3As shown, the antistatic structure 40 also includes a third doped layer 43, which is located on the outermost side of the antistatic structure 40 along the direction from the substrate 10 to the gate structure 30. The third doped layer 43 has a first doping type, and the doping concentration of the third doped layer 43 is different from that of the second doped layer 42. Figure 2 Based on the NPNP structure, the addition of an N-type third doped layer 43 increases the voltage drop at the antistatic structure 40, resulting in a larger threshold voltage that can smoothly drive the gate oxide layer 31 to turn on, thus enabling the semiconductor device to conduct. This avoids the situation where the voltage drop generated by the NPNP structure is too small, and the resulting threshold voltage is insufficient to turn on the gate oxide layer 31, thus preventing the gate oxide layer 31 from forming a channel with the source structure 20 and the semiconductor device from conducting. Furthermore, by using different doping concentrations of the third doped layer 43 and the second doped layer 42, the concentration of the third doped layer 43 can be reasonably set, resulting in more comprehensive performance of the entire device.

[0043] In some alternative implementations, such as Figure 2 and Figure 3 As shown, the third doped layer 43 includes a first sub-doped layer 431 and a second sub-doped layer 432. The second sub-doped layer 432 is located on the outermost side of the antistatic structure 40 along the direction from the substrate 10 to the gate structure 30. The first sub-doped layer 431 is located on the side of the second sub-doped layer 432 closer to the substrate 10. The doping concentration of the second sub-doped layer 432 is higher than that of the first sub-doped layer 431, and the doping concentration of the first sub-doped layer 431 is lower than that of the second sub-doped layer 432. Placing the lower-concentration first sub-doped layer 431 on the side of the second sub-doped layer 432 closer to the substrate 10 can increase the resistance at the antistatic structure 40, thereby increasing the voltage drop and raising the threshold voltage to enable the device to turn on smoothly. Placing the higher-concentration second sub-doped layer 432 on the outermost side of the antistatic structure 40 will allow it to contact the metal electrode of the subsequent device, reducing the contact resistance and enabling the gate structure 30 to have lower switching power consumption in high-resistance or high-frequency applications.

[0044] In the above embodiments, the doping concentration of the first sub-doped layer can vary with different threshold voltages and electrostatic discharge (ESD) requirements, resulting in different thicknesses and doping concentrations. Therefore, during normal operation (excluding ESD voltage surges and operating at normal voltage), electrical isolation between the gate and source can be guaranteed, ensuring the effectiveness of the threshold voltage and the integrity of the gate control capability.

[0045] In some alternative implementations, such as Figure 3As shown, the first source region structure 21 in the source region structure includes: a first well region 211, a first doped region 212, and a second doped region 213. The surface of the first well region 211 closest to the gate structure 30 contacts the gate structure 30, the first doped region 212, and the second doped region 213, respectively. The first well region 211 has a second doping type. In the first direction X, the first doped region 212 contacts the first well region 211 and the second doped region 213. The first doped region 212 has a first doping type. The first direction X forms an angle with the direction from the substrate 10 to the gate structure 30. The second doped region 213 has a second doping type. A complex multi-region doping mode is adopted, wherein the first well region 211 is P-type, the first doped region 212 is N-type, and the second doped region 213 is P-type. The doping concentration of the second doped region 213 is higher than that of the first well region 211. The contact between the second doped region 213 and the source metal of the device can reduce the source electrode contact resistance and improve the carrier efficiency.

[0046] Furthermore, parasitic transistors exist in semiconductor devices. For example, an NPN parasitic transistor can be formed by an N-type substrate, a P-type first well region, and an N-type first doped region beneath the gate structure. When the voltage and current in these regions reach certain conditions, the parasitic transistor may enter a conducting state, forming a self-sustaining current path; this process is known as latch-up. The introduction of a second doped region can act as a "circuit breaker" in this current path. When the voltage difference between the source and drain reaches a certain threshold, the PN junction formed by the second doped region and the N-type first doped region will undergo reverse breakdown, allowing current to flow and breaking the self-sustaining current path. This design ensures that even under extreme conditions, the device can safely release additional current through a safe path, preventing latch-up and protecting the overall safety and performance of the device. Figure 3 As shown, the source region structure of the device also includes a second source region structure 22, which includes a first doped region 212 and a first well region 211, but does not include a third doped region.

[0047] The junction depth of the first well region can be 0.7-1.5 μm, and the doping concentration can be 10. 18 -10 19 cm 2 This helps to carry higher voltages and avoids internal short circuits or avalanche breakdown under high voltage. The junction depth of the first doped region is typically 0.1-0.4 μm, and the doping concentration can be 10⁻⁶. 19This reduces the source-substrate contact resistance, thereby reducing source losses during device conduction, accelerating carrier movement, reducing switching time, and lowering switching losses. The junction depth of the second doped region can be greater than or equal to that of the first doped region, with a junction depth of 0.7-1.5 μm. This allows for better formation of an effective PN junction with the N-type first doped region, controlling the current path and preventing short circuits or latch-up effects.

[0048] In some alternative implementations, such as Figures 1 to 3 As shown, the semiconductor device also includes an insulating layer 50, which is located on both sides of the gate structure 30 and the antistatic structure 40 in the first direction X. The first source region structure 21 in the source region structure 20 has a first doped region 212 and a second doped region 213. The insulating layer 50 covers the first doped region 212, which has a first doping type, and the second doped region 213 has a second doping type. The first direction X forms an angle with the direction from the substrate 10 to the gate structure 30. By setting the first doped region 212 in the first source region structure 21 to not contact the electrode, the current of the parasitic transistor will flow through the second doped region 213. In this way, the second doped region 213 can minimize the risk of latch-up in the device. The insulating layer strengthens the electrical isolation between the sides of the antistatic structure 40 and the electrode, which can improve the stability of the device during long-term use.

[0049] In the above optional embodiments, the insulating layer can be made of materials such as silicon dioxide, silicon nitride, aluminum oxide, and aluminum nitride, and the thickness can be 0.3-0.8 μm. This application does not make specific limitations.

[0050] In some alternative implementations, such as Figures 1 to 3 As shown, the semiconductor device also includes an anode metal layer 60 and a cathode metal layer 70, wherein the anode metal layer 60 covers the antistatic structure 40, the insulating layer 50, and part of the source region structure 20; the cathode metal layer 70 is located on the side of the substrate 10 opposite to the first surface. Figure 3 As shown, an ohmic contact is formed between the anode metal layer 60 and the third doped layer 43, and an ohmic contact is also formed between the anode metal layer 60 and the second doped region 213, improving current flow efficiency. The arrangement of the anode metal layer 60 and the cathode metal layer 70 can improve the electrode contact efficiency of the semiconductor device, while ensuring charge balance of the device in different operating modes. The anode metal layer 60 covers the third doped layer 43 and part of the source region structure 20, providing a low-impedance path for the device and accelerating the electrostatic discharge of the antistatic structure 40. The cathode metal layer 70 is placed on the other side of the substrate 10, which can enhance the heat dissipation capacity of the device, reduce the operating temperature, and extend the device life.

[0051] In the above embodiments, the materials of the anode metal layer and the cathode metal layer can be any one or more of Ni, Cu, Ag, Mo, Ta and Au, and this application does not make any specific limitation.

[0052] In some alternative implementations, the projections of the first and second doped layers on the first surface overlap with the projection of the gate structure on the first surface. This allows the first doped layer, the second doped layer, and the gate structure to be formed using a single photomask during device fabrication, saving costs and process steps.

[0053] The overlapping first and second doped layers in the semiconductor device proposed in this application may have more overlaps, not limited to those shown in the figure, and the total thickness of the final device may be 30-200 μm.

[0054] According to another embodiment of this application, a method for fabricating a semiconductor device is provided. Figure 4 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of this application. For example... Figure 4 As shown, the semiconductor device is prepared using a fabrication method, which includes:

[0055] Step S1: Provide a substrate having a first surface and a first doping type;

[0056] Specifically, the substrate includes a substrate and an epitaxial layer. The doping concentration of the substrate is higher than that of the epitaxial layer. The high doping concentration of the substrate can increase the depth of the depletion layer, thereby increasing the reverse breakdown voltage and reducing the risk of device breakdown. In addition, the substrate can also absorb charge carriers from the epitaxial layer, further reducing the on-resistance.

[0057] Step S2: Multiple source region structures are formed at intervals in the substrate, with the second surface of the source region structure located in the first surface;

[0058] Specifically, the source region structure includes a first source region structure and a second source region structure. The first source region structure includes a first well region, a first doped region, and a second doped region, while the second source region structure includes a first well region and a first doped region. The source region structure can regulate the current flow of the device, and the inclusion of a second doped region in the first source region structure can also prevent latch-up effects.

[0059] Step S3: A gate structure is formed on the first surface, and the gate structure covers part of the surface of multiple source region structures.

[0060] Specifically, the gate structure includes a gate oxide layer and a gate. The gate oxide layer can be made of silicon dioxide and has a thickness of 30nm-60nm. The gate can be made of polysilicon and can be used for gate signal transmission.

[0061] Step S4: An antistatic structure is formed on the side of the gate structure away from the substrate. In the direction from the substrate to the gate structure, the antistatic structure includes a plurality of staggered first doped layers and second doped layers. The first doped layer has a second doping type and the second doped layer has a first doping type.

[0062] Specifically, the first and second doped layers are relatively thin and meet the withstand voltage requirements of the PN junction under the target ESD level, which can improve the electrostatic discharge level of the gate.

[0063] The semiconductor device prepared according to the above method has an antistatic structure. This structure comprises alternating layers of first and second doped layers with opposite doping types. Multiple PN junctions are formed between the multiple first and second doped layers. When the gate voltage exceeds a safety threshold, these PN junctions conduct. Utilizing the reverse breakdown characteristic of PN junctions, electrostatic energy can be rapidly discharged when the preset electrostatic voltage threshold is exceeded, thus protecting the gate oxide layer from damage. Current flowing through the antistatic structure releases the electrostatic current, protecting the gate oxide layer and ensuring it is not broken down under high electrostatic voltage. This improves the antistatic capability of the trench gate structure. Furthermore, when the number of stacked layers of the first and second doped layers is more than two (PNPN or PNPNPN), the structure can be either PNPN or PNPNPN. When the gate voltage exceeds the preset threshold, it can quickly conduct, discharging excess electrostatic energy and protecting the gate oxide layer from damage. This semiconductor device solves the problem of low gate electrostatic breakdown capability in related technologies.

[0064] In some alternative implementations, the step of forming multiple source region structures includes: such as Figure 5 As shown, a plurality of first well regions 211 are formed by spaced first ion implantation in the substrate 10. The first well regions 211 have a second doping type; the second doping type can be P-type. The first well regions help to spatially isolate the source region and the gate, reducing lateral leakage current. The substrate 10 includes a substrate 11 and an epitaxial layer 12, and the plurality of first well regions 211 are formed in the epitaxial layer 12. Figure 6 As shown, multiple first doped regions 212 are formed by second ion implantation in multiple first well regions 211. Both the first doped regions 212 and the first well regions 211 have surfaces located in a first surface, and the first doped regions 212 have a first doping type. Further N-type ion implantation is performed in the P-type first well regions to form first doped regions. The introduction of the N-type first doped regions reduces the resistance between the source and the channel, while maintaining good isolation from the well regions, thus enhancing the device's conductivity and electrical isolation. Figure 7As shown, a third ion implantation is performed in one of the first doped regions 212 to form a second doped region 213. In the first direction X, the first doped region 212 contacts the first well region 211 and the second doped region 213. The second doped region 213 has a second doping type. The first direction X forms an angle with the direction of the substrate 10 pointing towards the gate structure. By performing P-type ion implantation in the first doped region (N-type) to form the second doped region, the device can safely release additional electrostatic current under extreme conditions, preventing latch-up effects. The source region structure with the first doped region 212, the second doped region 213, and the first well region 211 is the first source region structure 21, and the other is the second source region structure 22.

[0065] In some alternative implementations, the step of forming the antistatic structure includes: such as Figure 8 As shown, materials of the first doped layer and the second doped layer are alternately deposited on the side of the pre-gate structure 300 away from the substrate 10 to form a first doped pre-gate layer 410 and a second doped pre-gate layer 420; the pre-gate structure 300 includes a pre-gate oxide layer 310 and a pre-gate layer 320. The multiple layers of the first doped pre-gate layer 410 and the second doped pre-gate layer 420 form a PNPN structure (more layers can be formed to form a structure similar to PNPNPNPN). As an anti-static structure, the PNPN structure can quickly conduct when the gate voltage reaches a preset ESD threshold (e.g., ±2000V), protecting the gate oxide layer from electrostatic damage.

[0066] like Figure 9 As shown, the first doped pre-layer, the second doped pre-layer, and the pre-gate structure are etched in one step to obtain the first doped layer 41, the second doped layer 42, and the gate structure 30 (the gate structure 30 includes the gate oxide layer 31 and the gate 32). The first doped layer 41 covers the gate structure 30. Using a single photomask and a single etching process, the gate structure 30 and the antistatic structure 40 can be formed simultaneously, saving process steps and reducing costs.

[0067] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0068] The semiconductor device and its fabrication method proposed in the above embodiments of this application can achieve the following technical effects:

[0069] 1) The semiconductor device of this application forms an anti-static structure on top of the gate structure to improve the gate anti-static capability of the semiconductor device. The anti-static structure has alternating layers of first and second doped layers with opposite doping types. Multiple PN junction structures are formed between the multiple first and second doped layers. When the gate voltage exceeds a safety threshold, the multiple PN junctions conduct. Utilizing the reverse breakdown characteristic of PN junctions, when the preset electrostatic voltage threshold is exceeded, electrostatic energy can be quickly discharged, thereby protecting the gate oxide layer from damage. Current flowing through the anti-static structure releases the electrostatic current, protecting the gate oxide layer of the gate structure and ensuring that the gate oxide layer is not broken down under high electrostatic voltage, thus improving the anti-static capability of the trench gate structure. Furthermore, when the number of stacked layers of the first and second doped layers is more than two, the structure can be PNPN or PNPNPN. When the gate voltage exceeds the preset threshold, it can quickly conduct, discharging excess electrostatic energy and protecting the gate oxide layer from damage. The above-described semiconductor device solves the problem of low gate electrostatic breakdown capability in related technologies.

[0070] 2) This application incorporates a second doped region within one of the source regions of a semiconductor device. This allows a PN junction to be formed between the second and first doped regions. When the instantaneous voltage is too high, the device can release electrostatic current through the safe path of the PN junction conduction, preventing latch-up. The inclusion of a third doped region not only prevents the device from failing to turn on due to a low threshold voltage but also reduces the contact resistance with the electrodes, thereby lowering the device's switching losses.

[0071] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A semiconductor device, characterized by, The semiconductor device comprises: a substrate having a first surface, the substrate having a first doping type; a plurality of source region structures spaced apart in the substrate, a second surface of the source region structures being in the first surface; a gate structure on the first surface and covering part of the surfaces of the plurality of source region structures; an antistatic structure on a side of the gate structure facing away from the substrate in a direction of the substrate pointing to the gate structure, the antistatic structure comprising a plurality of interleaved first doping layers and second doping layers, the first doping layers having a second doping type, the second doping layers having the first doping type, the antistatic structure further comprising a third doping layer on an outermost side of the antistatic structure in the direction of the substrate pointing to the gate structure, the third doping layer having the first doping type, the third doping layer having a doping concentration different from a doping concentration of the second doping layers, the third doping layer comprising a first sub-doping layer and a second sub-doping layer, wherein the second sub-doping layer is on the outermost side of the antistatic structure in the direction of the substrate pointing to the gate structure, the first sub-doping layer is on a side of the second sub-doping layer close to the substrate, the doping concentration of the second sub-doping layer is higher than the doping concentration of the first sub-doping layer, the doping concentration of the first sub-doping layer is lower than the doping concentration of the second doping layers, and the first sub-doping layer is in contact with the second doping layers.

2. The semiconductor device according to claim 1, wherein The first source region structure of the source region structures comprises: a first well region, a first doping region, and a second doping region, wherein a side surface of the first well region close to the gate structure is in contact with the gate structure, the first doping region, and the second doping region respectively, the first well region has the second doping type; 3. The semiconductor device of claim 1, wherein in a first direction, the first doping region is in contact with the first well region and the second doping region, the first doping region has the first doping type, the first direction has an angle with the direction of the substrate pointing to the gate structure, and the second doping region has the second doping type.

4. The semiconductor device according to claim 3, wherein The semiconductor device further comprises an insulating layer on both sides of the gate structure and the antistatic structure in a first direction, the first source region structure of the source region structures has a first doping region and a second doping region, the insulating layer covers the first doping region, the first doping region has the first doping type, and the second doping region has the second doping type, the first direction has an angle with the direction of the substrate pointing to the gate structure. The semiconductor device further comprises an anode metal layer and a cathode metal layer, wherein the anode metal layer covers the antistatic structure, the insulating layer, and part of the source region structures; 5. The semiconductor device of claim 1, wherein the cathode metal layer is on a side of the substrate facing away from the first surface.

6. A method of manufacturing a semiconductor device, characterized by Projections of the first doping layers and the second doping layers on the first surface overlap with a projection of the gate structure on the first surface. The preparation method is used for preparing the semiconductor device of any one of claims 1 to 5, and the preparation method comprises: A substrate is provided, the substrate has a first surface, the substrate has a first doping type; A plurality of source region structures are formed in the substrate at intervals, a second surface of the source region structure is located in the first surface; A gate structure is formed on the first surface, the gate structure covers part of the surface of a plurality of the source region structures; An antistatic structure is formed on a side of the gate structure facing away from the substrate, in a direction of the substrate pointing to the gate structure, the antistatic structure comprises a plurality of first doping layers and second doping layers stacked alternately, the first doping layer has a second doping type, the second doping layer has the first doping type, the antistatic structure further comprises a third doping layer, the third doping layer is located at the outermost side of the antistatic structure in the direction of the substrate pointing to the gate structure, the third doping layer has the first doping type, the doping concentration of the third doping layer is different from that of the second doping layer, the third doping layer comprises a first sub-doping layer and a second sub-doping layer, wherein the second sub-doping layer is located at the outermost side of the antistatic structure in the direction of the substrate pointing to the gate structure, the first sub-doping layer is located on a side of the second sub-doping layer close to the substrate, the doping concentration of the second sub-doping layer is higher than that of the first sub-doping layer, and the doping concentration of the first sub-doping layer is lower than that of the second doping layer.

7. The production method according to claim 6, wherein The step of forming a plurality of source region structures comprises: A first ion implantation is performed in the substrate at intervals to form a plurality of first well regions, the first well region has the second doping type; A second ion implantation is performed in each of the plurality of first well regions to form a plurality of first doping regions, the first doping region and the first well region both have a surface located in the first surface, and the first doping region has the first doping type; A third ion implantation is performed in one of the first doping regions to form a second doping region, in a first direction, the first doping region is in contact with the first well region and the second doping region, the second doping region has the second doping type, and the first direction has an angle with the direction of the substrate pointing to the gate structure.

8. The preparation method according to claim 6, characterized in that, The step of forming an antistatic structure comprises: The material of the first doping layer and the material of the second doping layer are alternately deposited on a side of a preliminary gate structure facing away from the substrate to form a first doping preliminary layer and a second doping preliminary layer; A first doping preliminary layer, a second doping preliminary layer and a preliminary gate structure are subjected to an etching treatment to obtain the first doping layer, the second doping layer and the gate structure, and the first doping layer covers the gate structure.

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