Optical computing chip with vertical micro-lens structure and wafer-level intelligent manufacturing method thereof

Abstract

The application discloses a vertical micro-mirror structure optical computing chip and a wafer-level intelligent manufacturing method thereof, and relates to the field of optical computing chips.The optical computing chip comprises a plurality of optical modulators and a plurality of quantum logic gates, and the optical modulators are provided with interference light paths based on vertical micro-mirrors, so that optical modulation is realized; the quantum logic gates construct stable light paths through the mirrors provided by the vertical micro-mirrors, realize interference by means of a beam splitter, and perform Hadamard transformation by a wave plate at the entrance or exit of a target light path, so that optical computing is realized; a deep-groove beam splitter or a deep-wall beam splitter is used as the beam splitter, the silicon walls in the deep-wall beam splitter are provided with a predetermined included angle perpendicular to the two side walls of the substrate, and the deep-groove beam splitter is manufactured in the following manner: a deep groove pattern is photoetched on the surface of a single-crystal silicon wafer; the deep groove with the predetermined angle is etched by deep etching and the side walls are smoothed; an optical thin film is deposited in the deep groove; the shape of the deep-groove beam splitter is photoetched and etched by deep etching, and the side walls are smoothed; and an optical antireflection film is grown on the vertical side walls.

Description

Technical Field

[0001] This invention relates to the fields of integrated circuits, optoelectronics, advanced packaging and digital manufacturing, and in particular to a vertical micromirror structure optical computing chip and its wafer-level intelligent manufacturing method. Background Technology

[0002] As semiconductor processes advance to the sub-10 nanometer scale, integrated circuits face two fundamental challenges: first, signal delay and crosstalk caused by metal interconnects have outpaced the performance improvement of transistors, becoming the primary bottleneck restricting computing power growth; second, while 3D stacked packaging can increase integration density, it also leads to a surge in heat flux density per unit area. Against this backdrop, optical computing has emerged as a transformative technological approach. Silicon-based photonics technology relies on a mature microelectronics manufacturing system, integrating components such as lasers, modulators, waveguides, and detectors on silicon substrates to construct a fully functional link for optical signal generation, transmission, and modulation. Its core lies in using photons to replace electrons for data transmission and processing. Compared to electrons, photons have no rest mass, and different wavelengths of light can be used for simultaneous multi-channel communication, resulting in greater bandwidth, higher speed, and stronger resistance to electromagnetic interference, thus overcoming the physical limitations of electrical interconnects. However, silicon-based photonics technology still faces challenges in industrialization: mainstream solutions rely on SOI (silicon-on-insulator) substrates to construct waveguide structures, but SOI materials are expensive and have compatibility barriers with bulk silicon integrated circuit processes, which greatly increases the difficulty of heterogeneous integration; in addition, the edge roughness during silicon waveguide etching will cause significant light scattering loss, which seriously restricts device performance, yield and integration scale. Summary of the Invention

[0003] To address the issues of complex processes in traditional silicon-based photonics technology and the disadvantages of horizontal micromirrors in MEMS (Micro-Electro-Mechanical Systems) for horizontal optical path transmission and control, the purpose of this application is to provide an optical computing chip with a vertical micromirror structure and its wafer-level intelligent manufacturing method.

[0004] According to a first aspect of the embodiments of this application, this application proposes an optical computing chip with a vertical micromirror structure, including several optical modulators and several quantum logic gates. The optical modulators are configured with interference optical paths based on the vertical micromirrors to achieve optical modulation. The quantum logic gates construct stable optical paths through mirrors configured with the vertical micromirrors, use beam splitters to achieve interference, and perform Hadamard transformation by waveplates at the entrance or exit of the target optical path to achieve optical computing.

[0005] The quantum logic gate employs a deep trench beamsplitter or a deep-wall beamsplitter as the beamsplitter. In the deep-wall beamsplitter, the silicon walls are perpendicular to the two sidewalls of the substrate and are set at a predetermined angle. The deep trench beamsplitter is manufactured as follows: a deep trench pattern is photolithographically etched on the surface of a single-crystal silicon wafer; a deep trench with a predetermined angle is etched using a deep etching method and the sidewalls are smoothed; an optical thin film is deposited in the deep trench; the shape of the deep trench beamsplitter is photolithographically etched and the sidewalls are smoothed; and an optical antireflection film is grown on the vertical sidewalls.

[0006] Furthermore, the adjustable interferometer arm in the optical modulator is manufactured using thermo-optical modulation and voltage modulation as follows: an insulating layer is deposited on the surface of a single-crystal silicon wafer; a heavily doped substrate region is formed by ion implantation and annealing; a metal layer is deposited and annealed to form a substrate region electrode with ohmic contact properties; a gate electrode is formed on the surface-deposited insulating layer; a vertical structure is deeply etched on the single-crystal silicon wafer and the sidewalls are smoothed to form a vertical micromirror; and an optical antireflection film is deposited on the surface of the vertical micromirror.

[0007] Furthermore, the tunable interferometer arm in the optical modulator is modulated using a PN junction and is manufactured in the following manner:

[0008] Vertical sidewalls are etched and smoothed on the surface of a single-crystal silicon wafer using a deep etching method to form several vertical micromirrors. The surface of the vertical micromirrors is patterned using spray coating or two-photon lithography. The vertical sidewalls are doped and annealed to form P-regions, N-regions, P+ regions, and N+ regions. Electrodes are grown and an optical antireflection film is grown on the surface of the vertical micromirrors to form tunable interference arms based on a comb-type PN junction modulation structure.

[0009] Furthermore, the quantum logic gate also includes a metal grating polarizer, which is manufactured in the following ways: photolithography and vertical deep etching are performed on a single-crystal silicon wafer to form a nanograting or nanopillar, and metal is deposited to form a metal grating; or grating gaps are printed on the vertical sidewalls after vertical deep etching and sidewall smoothing using two-photon printing, the sidewalls are patterned using spray adhesive and photolithography and metal is deposited, and the resist is removed to obtain a metal grating; or the patterning is performed using spray adhesive and photolithography, metal is deposited and the resist is removed, and the metal in the gaps is etched away using the grayscale milling function of focused ion beam etching to obtain a metal grating.

[0010] Furthermore, the quantum logic gate also includes a grating waveplate, which is manufactured in the following ways: etching a grating periodic structure on the vertical sidewalls after deep vertical etching and sidewall smoothing using a grayscale milling function of deep reactive ion etching or focused ion beam etching, and depositing metal to form a waveplate with a reflective metal grating structure; or manufacturing a grating periodic structure on the vertical sidewalls after deep vertical etching and sidewall smoothing using a two-photon printing method, and depositing metal to form a waveplate with a reflective metal grating structure.

[0011] Furthermore, the quantum logic gate also includes a collimating lens, which is manufactured by two-photon printing additive manufacturing of the vertical sidewalls after sidewall smoothing, or by focused ion beam etching and milling.

[0012] Furthermore, both the optical modulator and the quantum logic gate also include a reflector, which is manufactured by etching vertical sidewalls using a deep etching method and smoothing them to form a vertical micromirror, and depositing an optical anti-reflection film on the surface of the vertical micromirror.

[0013] Furthermore, the optical computing chip also includes a spectrometer, in which light emitted by a laser epitaxially grown on a single-crystal silicon wafer or through heterogeneous integration passes through a vertical aperture to a vertical concave mirror, and is then reflected by a beam splitter to split light of different wavelengths into different angles. The light is then reflected back to the vertical concave mirror and focused at different positions for detection by a detector.

[0014] Furthermore, a blazed grating is used as the beam-splitting element, and the blazed grating is manufactured in the following manner:

[0015] Serrated grooves are made on a vertical micromirror after vertical deep etching and sidewall smoothing using additive or subtractive manufacturing methods, and a metal layer is deposited to form a blazed grating.

[0016] According to a second aspect of the embodiments of this application, this application also proposes a wafer-level smart manufacturing method for a system-on-a-chip, the system-on-a-chip including an optical computing chip with a vertical micromirror structure as described in the first aspect, the method comprising:

[0017] At the system level, the wafer is divided into optical computing units, electrical computing units, storage units, control units, and power supply units, and a wafer-level system architecture is formed through system-level modeling.

[0018] Based on the aforementioned wafer-level system architecture, the optoelectronic synergistic functional structure of the optical computing unit and the electrical computing unit is designed.

[0019] Under the optoelectronic collaborative functional architecture, the optoelectronic interconnect network is designed. Adaptive routing algorithm is used to reduce blocking latency, redundant interconnect design is used to achieve automatic switching of backup path in case of failure, and dynamic voltage regulation is used to reduce idle power consumption.

[0020] In the context of optoelectronic on-chip interconnect networks, an artificial intelligence mapping model between manufacturing parameters and device performance is established. Automatic routing is performed according to functional requirements, and the on-chip system routing layout under multi-physics coupling conditions is simulated. If the simulation results do not meet the requirements, the on-chip interconnect network is optimized based on the simulation results and then simulated again until the requirements are met.

[0021] Construct a global perception layer, establish data on integrated circuit manufacturing equipment, cleanroom environment, and microelectronic materials, build a multi-dimensional mapping digital manufacturing model, combine the wiring layout design of the on-chip system with the digital manufacturing model to drive the microelectronic process line, and complete the manufacturing of optoelectronic integrated systems.

[0022] In this process, the chip's process parameters are tested in real time, and the drift of equipment parameters is extracted in real time. Dynamic closed-loop control is implemented by combining the test results and equipment parameters to predict, compensate, and dynamically adjust the device performance in advance, and optimize the on-chip system routing layout design.

[0023] The technical solutions provided by the embodiments of this application may include the following beneficial effects:

[0024] This invention utilizes high-temperature, dry, or wet methods to smooth the sidewalls of deeply etched silicon vias, forming a vertical micromirror structure with a roughness of less than 1 nm. This allows for the fabrication of a deep trench beamsplitter, which exhibits higher reliability than single-crystal silicon thin-film beamsplitters. Based on the deep trench beamsplitter, various optical modulators and quantum logic gates can be further constructed, realizing a spatial light optical computing chip structure beyond macroscopic spatial optics and silicon-based optoelectronics. Compared to silicon-based optoelectronics, this invention not only features a simpler process but also exhibits lower light transmission loss in air compared to silicon waveguides, making it suitable for large-scale integration.

[0025] This invention also proposes a wafer-level intelligent manufacturing method for a system-on-a-chip (SoC) incorporating the aforementioned optical computing chip. This method forms a top-down, end-to-end manufacturing process from architecture to design to manufacturing to testing and feedback, thereby comprehensively improving the design and manufacturing efficiency of wafer-level optoelectronic SoCs.

[0026] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0027] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0028] Figure 1 The diagram shows the manufacturing process of the DC voltage modulated MZI adjustable interference arm of the MOS structure, where (a-1)-(f-1) are the top views of the wafer for each process, (a-2)-(f-2) are the front views of the wafer for each process, and (a-3)-(f-3) are the cross-sectional views of the wafer for each process.

[0029] Figure 2 The diagram shows a DC voltage modulated MZI adjustable interference arm of a MOS structure, where (a)-(d) are schematic diagrams of the substrate electrode and the gate electrode being set at different positions.

[0030] Figure 3 The diagram shows the manufacturing process of the adjustable interference arm of the comb-type PN junction modulation structure, where (a) is a schematic diagram of the wafer after sidewall doping and (b) is a schematic diagram of the wafer after the growth of electrodes and antireflection film.

[0031] Figure 4 The diagram shows the manufacturing process flow chart of the deep trench beam splitter, where (a-1)-(e-1) are the wafer top views of each process, and (a-2)-(e-2) are the wafer cross-sectional views of each process.

[0032] Figure 5 The diagram shows a schematic of a metal grating polarizer based on a vertical micromirror, where (a) is a nano-grating or nano-pillar vertical grating, (b) is a nano-grating or nano-pillar vertical grating with added substrate structure, (c) is a reflective vertical metal grating waveplate, and (d) is a reflective horizontal metal grating waveplate.

[0033] Figure 6 The diagram shows a blazed grating spectrometer based on a vertical micromirror, where (a) is a blazed grating, (b) is a spectrometer, (c) and (d) are two structural configurations for deflecting the blazed grating using a MEMS electrostatic actuator, (e) and (f) are two structural configurations for deflecting the blazed grating using a comb-type electrostatic drive structure, (g) is a slit-type vertical aperture, and (h) is a circular aperture-type vertical aperture.

[0034] Figure 7 The diagram shows a schematic of a vertical micromirror-based optical computing chip, where (a) is a schematic of an MZI (Micro-Zen Array), (b) is a schematic of a Michelson interferometer, (c) is a schematic of a two-bit quantum logic gate, and (d) is a schematic of a system-on-a-chip.

[0035] Figure 8 The diagram shows the structure of a deep-wall beam splitter, where (a) is a three-dimensional structural diagram of a frustum-shaped deep-wall beam splitter, (b) is a top view of a frustum-shaped deep-wall beam splitter, (c) is a top view of a single-side-wall coating of a frustum-shaped deep-wall beam splitter, (d) is a top view of a single-side-wall coating of a cuboid-shaped deep-wall beam splitter, (e) is a top view of a double-side-wall coating of a frustum-shaped deep-wall beam splitter, and (f) is a top view of a double-side-wall coating of a cuboid-shaped deep-wall beam splitter.

[0036] Figure 9 The diagram shows a flowchart of a wafer-level intelligent manufacturing method for a vertical micromirror structure optical computing chip.

[0037] Figure reference numerals: 1. Single-crystal silicon wafer; 2. Insulating layer; 3. Substrate region; 4. Substrate region electrode; 5. Gate electrode; 6. Vertical structure; 7. Anti-reflection coating; 8. Deep trench; 9. Optical thin film; 10. Vertical sidewall; 11. Optical anti-reflection coating; 12. Metal grating; 13. Substrate structure; 14. Reflective metal grating waveplate; 15. Grating periodic structure; 16. Blazed grating; 17. Laser; 18. Vertical aperture; 19. First vertical concave mirror; 20. Second vertical concave mirror; 21. Detector; 22. Vertical cantilever beam; 23. Rear vertical stationary plate; 24. Front vertical stationary plate; 25. Moving electrode plate; 26. First stationary plate; 27. Second stationary plate; 28. Third stationary plate; 29. ​​Fourth stationary plate; 30. Slit; 31. Circular aperture structure; 32. First beam splitter; 33. First interferometer arm; 34. Second beam splitter; 35. Second interferometer arm; 36. Second interferometer arm; 37. Second interferometer arm. 7. Third beam splitter 38. Third reflector 39. First detector 40. Third interferometer arm 41. Fourth reflector 42. First half beam splitter 43. Second half beam splitter 44. Third half beam splitter 45. Fourth half beam splitter 46. First third beam splitter 47. Second third beam splitter 48. Third third beam splitter 49. First reflective metal grating half-wave plate 50. Second reflective metal grating half-wave plate 51. First collimating lens 52. Second collimating lens 53. Third collimating lens 54. Fourth collimating lens 55. Laser 56. On-chip optical computing chip 57. Second detector 58. Electrical signal processing chip 59. Adapter board 60. Circuit board 61. Power supply module 62. Deep wall beam splitter 63. Transmission sidewall optical anti-reflection coating 64. Reflection sidewall optical thin film 65. Detailed Implementation

[0038] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application.

[0039] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0040] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0041] This application provides a vertical micromirror structure optical computing chip, including several optical modulators and several quantum logic gates. Optical modulation is achieved by setting the interference optical path in the optical modulators based on the vertical micromirrors. The quantum logic gates construct a stable optical path through vertically positioned mirrors, utilize beam splitters to achieve classical and non-classical interference, and perform Hadamard transformation by waveplates at the entrance / exit of the target optical path, thereby realizing optical computing. The quantum logic gates employ deep trench beam splitters or deep-wall beam splitters as the beam splitters. In the deep-wall beam splitter, the silicon walls are perpendicular to the two sidewalls of the substrate and set at a predetermined angle. The deep trench beam splitter is manufactured as follows: a deep trench pattern is photolithographically etched on the surface of a single-crystal silicon wafer; deep trenches with a predetermined angle are etched using a deep etching method and the sidewalls are smoothed; an optical thin film is deposited in the deep trench; the shape of the deep trench beam splitter is photolithographically etched and the sidewalls are smoothed; and an optical antireflection film is grown on the vertical sidewalls.

[0042] The optical computing chip with a vertical micromirror structure is an on-chip optical system composed of devices such as optical modulators and quantum logic gates. In specific implementations, the optical modulator can be an intensity modulator, phase modulator, polarization modulator, etc., all of which can realize optical phase modulation function through vertical micromirrors. The following embodiments will be described in detail using a Mach-Zehnder modulator as an example. The Mach-Zehnder modulator includes a Mach-Zehnder interferometer (MZI) tunable interferometer arm, a deep trench beamsplitter, and a mirror. The optical path is organized by the deep trench beamsplitter, mirror, and other components, and optical phase modulation is realized by the MZI tunable interferometer arm. The quantum logic gate is used to realize the basic logical operations in quantum computing. Taking the two-bit controlled-NOT (CNOT) quantum logic gate as an example, it includes a deep trench beamsplitter, a mirror, a beamsplitter, and a waveplate. A stable optical path is constructed by a vertically set mirror. Classical and non-classical interference is realized by the deep trench beamsplitter, and the Hadamard transformation is performed by the waveplate at the entrance / exit of the target optical path, finally completing the controlled-NOT quantum logic operation.

[0043] Vertical micromirrors innovatively construct three-dimensional optical structures and key optical components perpendicular to the wafer plane directly on a single-crystal silicon wafer using a high-precision deep etching process. After smoothing the sidewalls, the surface roughness can be controlled to within 1 nanometer, meeting the stringent requirements of optical interfaces. Compared to traditional horizontal micromirrors in Micro-Opto-Electro-Mechanical Systems (MOEMS), this technology eliminates the need for subsequent alignment and micro-assembly processes, enabling the direct fabrication of vertical optical components on a silicon-based plane and achieving complete horizontally integrated optical paths.

[0044] Examples 1-4 and 6 illustrate the structure and manufacturing steps of key optical components based on vertical micromirrors, respectively. Example 5 illustrates an optical computing chip and optoelectronic integrated system composed of key optical components. Example 7 illustrates the design and collaborative intelligent manufacturing method of a wafer-level optoelectronic integrated system, forming a top-down end-to-end manufacturing method from architecture to design to manufacturing to testing and feedback.

[0045] Example 1

[0046] MZIs are the most basic structural unit in optical computing. MZIs achieve linear matrix operations by adjusting the phase difference between two interferometer arms, utilizing the interference effect of light. This application, based on a MOS (Metal-Oxide Semiconductor) structure, modulates the refractive index of the vertical micromirrors in the tunable interferometer arms of the MZI via electrical or thermal modulation, thereby changing the interference phase of the two beams of light. This embodiment uses the structure and manufacturing process of the vertical micromirrors in the tunable interferometer arms of the MZI as an example to provide a method for manufacturing an optical computing chip. However, the application scenarios of this invention are not limited to the given example and can also be applied to other scenarios involving the fabrication of MZIs using vertical micromirrors with different structures and principles.

[0047] like Figure 1 As shown, the fabrication steps of the DC voltage modulated MZI adjustable interferometer arm of the MOS structure are as follows:

[0048] S11: First, on single-crystal silicon wafer 1 ( Figure 1 In the (a-1), (a-2), and (a-3) layers, an insulating layer 2 is deposited on the surface. The material of the insulating layer includes, but is not limited to, one or more high dielectric constant materials such as silicon dioxide, silicon nitride, and hafnium oxide. Then, photolithography and etching are used to remove part of the insulating layer to expose the silicon substrate. Figure 1 (b-1), (b-2), (b-3) in the text.

[0049] S12: Heavily doped substrate region 3 is formed by ion implantation and annealing. Figure 1 (c-1), (c-2), (c-3) in the text.

[0050] S13: Deposit a metal layer and anneal it to form an ohmic contact substrate electrode 4 on substrate region 3, and form a gate electrode 5 on the surface-deposited insulating layer 2. Figure 1 (d-1), (d-2), (d-3) in the middle.

[0051] S14: Deeply etch vertical structure 6 onto single-crystal silicon wafer 1 and smooth the sidewalls to create a good optical plane and an electrical vertical plane, i.e., a vertical micromirror. Figure 1 (e-1), (e-2), (e-3) in the text.

[0052] A vertical structure with a depth greater than 100 micrometers, a perpendicularity better than 90°±0.3°, and an initial sidewall roughness better than 50 nanometers was etched on the upper surface of a single-crystal silicon wafer using a deep etching process.

[0053] Sidewall smoothing of the vertical structure 6 can be achieved through methods including, but not limited to, low-flow dry etching, low-concentration wet chemical etching, reducing the alternation cycle between etching and protection processes, gas cluster ion beam etching, focused ion beam etching and milling, ion beam etching, and chemical mechanical polishing of the sidewalls based on hard mask metal protection. As an embodiment of the invention, it is preferable to use a solution of less than 5 wt.% low-concentration potassium hydroxide (KOH) or tetramethylammonium hydroxide (TMAH), 10 wt.%~30 wt.% isopropanol, and deionized water to etch the aforementioned deep-etched silicon vias, resulting in a vertical structure 2 with a sidewall roughness of less than 5 nm, serving as a good optical and electrical vertical plane. As another embodiment of the invention, it is preferable to use one or more steps of low-flow sulfur hexafluoride (SF6), argon plasma, oxygen plasma, and xenon difluoride (XeF2) for post-etching of the vertical structure, with the gas flow rate generally below 30 sccm, resulting in a vertical structure 6 with a sidewall roughness of less than 1 nm.

[0054] S15: Deposit and pattern an optical antireflection film on the surface of the vertical micromirror, retaining only the antireflection film 7 on the sidewalls of the vertical micromirror while removing the optical antireflection film on the upper surface. Figure 1 (f-1), (f-2), (f-3) in the middle.

[0055] It should be noted that the substrate electrode 4 and gate electrode 5 of the adjustable interference arm of the DC voltage modulated MZI in the MOS structure can be configured in various ways according to the actual depletion layer electric field distribution requirements. The substrate electrode 4 can be located on the upper surface ( Figure 2 (a) and (b) in the text can also be fabricated on the lower surface using double-polished silicon wafers and double-sided processes. Figure 2 (c) and (d) in the text); the gate electrode 5 can be located at the top of the vertical micromirror ( Figure 2(a) and (c) in the text can also be a ring structure. Figure 2 (b) and (d) in the text.

[0056] It should be noted that the structure of thermo-optically modulated MZI is similar to that of voltage-modulated MZI, but the electrode material is preferably titanium nitride. The essence of the thermo-optic effect is that the dielectric constant of the material changes with temperature, leading to a change in refractive index. Therefore, the refractive index of the vertical micromirror of the tunable interferometer arm can be changed by heating titanium nitride, thereby changing the interference phase of the two beams. The ring electrode structure is also suitable for thermo-optically modulated MZI.

[0057] It should be noted that the aforementioned voltage-modulated and thermo-optically modulated MZIs are both MOS structures. However, compared to MOS-structured MZIs, PN junction modulation allows the bias voltage to directly control the carrier concentration in the depletion or injection region. However, unlike silicon waveguides, vertical micromirrors typically have depths of tens or even hundreds of micrometers. Directly implanting ions tens of micrometers vertically downwards into a silicon vertical micromirror is extremely difficult. If only the sidewalls (XZ plane) of the vertical micromirror are implanted, the doping depth is limited and may not be sufficient to completely cover the entire modulation phase. Therefore, this invention proposes a comb-type PN junction modulation structure with adjustable interference arms to meet the needs of different application scenarios. First, the surface of the vertical micromirror, after deep vertical etching and sidewall smoothing, is patterned using spray coating or two-photon lithography. Then, the vertical sidewalls are doped and annealed to form P-regions, N-regions, P+ regions, and N+ regions. The sidewall doping methods include, but are not limited to, tilted-angle ion implantation and plasma doping (PLAD). Figure 3 (a)); Finally, an electrode is grown and preferably atomic layer deposition (ALD) is performed to grow an antireflection film 7 on the surface of the vertical micromirror. Figure 3 (b) in the middle.

[0058] Example 2

[0059] Another application of optical computing is quantum computing. This embodiment provides a method for manufacturing a deep trench beam splitter to achieve more reliable quantum logic gates. However, the application scenarios of this invention are not limited to the example given, and can also be applied to other scenarios involving the manufacture of beam splitters.

[0060] S21: First, on single-crystal silicon wafer 1 ( Figure 4The surfaces of (a-1) and (a-2) are photolithographically patterned to form deep trenches; then, deep trenches 8 with a certain angle are etched using a deep etching method; finally, the sidewalls of the deep trenches are smoothed, and the smoothing methods include, but are not limited to, high-temperature annealing, low-flow dry etching, low-concentration wet chemical etching, reducing the alternation cycle of etching and protection processes, gas cluster ion beam etching, focused ion beam etching milling, ion beam etching, and chemical mechanical polishing of the sidewalls based on hard mask metal protection, etc. Figure 4 (b-1) and (b-2) in the middle.

[0061] S22: Deposit an optical thin film 9 in the deep trench 8. Methods for depositing the optical thin film include, but are not limited to, physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc. To achieve a higher aspect ratio for the deep trench filling, atomic layer deposition is preferred. The deposited optical thin film includes, but is not limited to, one or more of silicon dioxide, silicon nitride, aluminum oxide, titanium dioxide, etc. Figure 4 (c-1) and (c-2) in the middle.

[0062] S23: First, the outline of the deep trench beam splitter is photolithographically and deeply etched; then, the outline of the deep trench beam splitter is smoothed to obtain the vertical sidewall 10 of the deep trench beam splitter. Figure 4 (d-1) and (d-2) in the middle.

[0063] S24: Preferably, an optical antireflective coating 11 is grown on the vertical sidewall 10 of the deep trench beam splitter using ALD. Figure 4 (e-1) and (e-2) in the middle.

[0064] Since the optical thin film filling the deep trench plays a splitting role in the deep trench beam splitter, while the outer side of the deep trench is a single crystal silicon that can provide mechanical support, the length, thickness and depth dimensions are usually greater than or equal to 100 micrometers. In contrast, the thickness of a deep-etched single crystal silicon thin film used directly as a beam splitter is usually less than or equal to 5 micrometers to avoid severe Fabry-Perot interference. Therefore, the deep trench beam splitter has higher reliability than the single crystal silicon thin film beam splitter.

[0065] Example 3

[0066] Polarizers and half-wave plates are important optical components. Besides the deep trench structure described in Example 2, polarizers based on vertical micromirrors can also be implemented using grating structures. Gratings can be classified into transmission gratings and reflection gratings.

[0067] Figure 5Figure (a) shows a schematic diagram of a transmissive grating polarizer based on a vertical micromirror. First, a nanograting or nanopillar is photolithographically etched and vertically deep into a single-crystal silicon wafer. Then, metal is deposited using a physical vapor deposition method to form a metal grating 12. When unpolarized light is incident on the metal grating, its electric field component can be decomposed into two orthogonal directions: transverse electric polarization (TE polarization) and transverse magnetic polarization (TM polarization). TE polarized light is strongly suppressed and almost cannot be transmitted; while TM polarized light can be transmitted efficiently, forming highly linearly polarized output light. Compared with traditional horizontal metal grating polarizers, the metal grating polarizer based on a vertical micromirror proposed in this invention not only has a spatial dimension structure suitable for the optical system requirements on vertical micromirrors, but also, because the vertical grating is supported at the bottom, there is no need to set a substrate support structure in the optical path direction, thereby reducing losses and simplifying the model by eliminating the need to consider the equivalent medium.

[0068] Figure 5 While the nanogratings or nanopillars shown in (a) have many advantages, they also suffer from relatively low structural strength, making them suitable only for non-high-vibration environments. For high-vibration environments, substrate structure 13 can be added, but in this case, equivalent medium theory needs to be considered, such as... Figure 5 As shown in (b) above. There are various methods for its manufacturing process. This invention provides two feasible methods as examples, but manufacturing this structure using other methods should not be considered a new method. Method 1: First, the grating gap is printed using two-photon printing on the vertical sidewall after deep vertical etching and sidewall smoothing; then, the back side of the vertical sidewall is protected by spraying adhesive and photolithography, exposing only the side with the grating gap; finally, metal is deposited using physical vapor deposition (PVD) and the resist is stripped away to remove the resist and metal on the back side of the vertical sidewall, as well as the grating gap and metal printed using two-photon printing, resulting in the vertical metal grating polarizer. Method 2: First, the back side of the vertical sidewall is protected by spraying adhesive and photolithography, exposing only the front side; then, metal is deposited using physical vapor deposition (PVD) and the resist is stripped away to remove the resist and metal on the back side of the vertical sidewall, retaining only the metal on the front side of the vertical sidewall; finally, the metal of the grating gap is etched away using the grayscale milling function of focused ion beam etching, resulting in the vertical metal grating polarizer.

[0069] Half-wave plates and quarter-wave plates can be manufactured using reflective metal grating structures. Their working principle is to introduce a specific phase difference into the TE / TM polarization components during reflection by combining the grating groove depth and the material. Figure 5(c) shows a reflective metal grating waveplate based on a vertical micromirror. There are various methods for its fabrication. This invention provides two feasible methods as embodiments; however, fabricating this structure using other methods should not be considered a new method. Method 1: First, a grating periodic structure is etched onto the vertical sidewalls after deep vertical etching and sidewall smoothing using a grayscale milling function of deep reactive ion etching or focused ion beam etching; then, metal is deposited to form a reflective metal grating waveplate 14. Method 2: First, a grating periodic structure is fabricated on the vertical sidewalls after deep vertical etching and sidewall smoothing using a two-photon printing method; then, metal is deposited to form a reflective metal grating waveplate 14.

[0070] It should be noted that the two manufacturing methods for wave plates have their own characteristics, meeting the needs of different application scenarios. Method one uses subtractive manufacturing to produce an all-silicon structure wave plate, which has better structural stability. Method two uses additive manufacturing to produce a wave plate, which offers greater flexibility in spatial structure design; its grating periodic structure can be rotated at any angle on the vertical sidewalls parallel to the XZ plane to achieve different angles with the Z-axis. For example, Figure 5 If the structure in (c) is manufactured using method two, the angle between its grating periodic structure 14 and the Z-axis is 0°; while Figure 5 The structure in (d) is that the angle between the grating periodic structure 15 and the Z-axis is 90°.

[0071] Example 4

[0072] Example 3 illustrates the structure and manufacturing method of key vertical micromirror-based grating polarizers and waveplates in optical computing chips. Gratings can also serve as spectroscopic elements in spectrometers. This example uses a blazed grating based on a vertical micromirror to illustrate the structure of an on-chip spectrometer. A blazed grating is a reflective grating composed of a set of sawtooth grooves. Through its sawtooth groove structure and blaze angle design, the blazed grating shifts the single-slit diffraction principal maximum from the zeroth order to the target diffraction order, solving the energy dispersion problem of traditional gratings.

[0073] Figure 6 (a) shows a schematic diagram of a blazed grating based on a vertical micromirror structure. The blazed grating 16 can be made by subtractive manufacturing methods such as deep etching or focused ion beam etching on the vertical sidewall after deep vertical etching and sidewall smoothing, and then depositing a metal layer; or it can be made by additive manufacturing methods such as two-photon printing on the vertical sidewall after deep vertical etching and sidewall smoothing, and then depositing a metal layer.

[0074] Figure 6Figure (b) shows a schematic diagram of an on-chip spectrometer based on a blazed grating with a vertical micromirror structure. Its working principle is as follows: light emitted from a laser 17, epitaxially grown on a single-crystal silicon wafer or heterogeneously integrated, passes through a vertical aperture 18 to a first vertical concave mirror 19, and is then reflected by a blazed grating 16 to split light of different wavelengths into different angles. The light is then reflected by a second vertical concave mirror 20, which focuses the light of different wavelengths at different positions for detection by a detector 21.

[0075] It should be noted that wavelength selection can usually be achieved by deflecting the blazed grating 16. For the angle deflection of the blazed grating 16 based on the vertical micromirror structure, it can be achieved by loading it onto a typical MEMS electrostatic actuator structure. Figure 6 The structure shown in (c) is to fabricate the blazed grating 16 on the vertical cantilever beam 22 to form a moving electrode plate, and to achieve the angular deflection of the blazed grating 16 by applying a static voltage between the rear vertical fixed electrode plate 23 and the vertical cantilever beam 22. Figure 6 The structure shown in (d) is a blazed grating 16 fabricated on a vertical cantilever beam 22, with a rear vertical fixed plate 23 and a front vertical fixed plate 24 respectively set in front of and behind the moving plate. The angle deflection of the blazed grating can be achieved by changing the voltage polarity. Figure 6 (e) and Figure 6 Figure (f) shows a schematic diagram of the blazed grating 16 and the vertical concave mirror 20 fabricated on a comb-type electrostatic drive structure. The comb-type electrostatic drive structure consists of a moving electrode plate 25 and independent first fixed electrode plates 26, 27, 28, and 29. When the moving electrode plate 25 is connected to the negative terminal of the power supply voltage and the fixed electrode plates 26 and 27 are connected to the positive terminal of the power supply voltage, the moving electrode plate 25 drives the blazed grating 16 and the vertical concave mirror 20 to deflect to the left; when the moving electrode plate 25 is connected to the negative terminal of the power supply voltage and the fixed electrode plates 28 and 29 are connected to the positive terminal of the power supply voltage, the moving electrode plate 25 drives the blazed grating 16 and the vertical concave mirror 20 to deflect to the right.

[0076] It should be noted that the vertical aperture 18 can be either a slit type or a circular aperture type. Figure 6 The slit-type vertical aperture shown in (g) can be achieved by first creating the slit 30 using a vertical deep etching method, and then depositing a metal layer on the slit surface. Figure 6 The circular aperture vertical aperture shown in (h) can be achieved by printing a circular aperture structure 31 on the vertical sidewall or the bottom of a single-crystal silicon wafer using a two-photon printing method, and then depositing a metal layer on the slit surface. Furthermore, Figure 6The on-chip spectrometer in (b) uses a blazed grating to diffract and disperse polychromatic light, separating and focusing light of different wavelengths in space to measure spectral intensity. However, this does not mean that the core dispersive element can only use a blazed grating; it can also be a vertical prism manufactured using vertical deep etching and sidewall smoothing processes, or a vertical prism manufactured based on additive manufacturing methods such as two-photon printing.

[0077] Example 5

[0078] Example 1 illustrates the structure and manufacturing process of the vertical micromirror with an MZI tunable interferometer arm for optical computing provided by this invention. Examples 2 and 3 respectively illustrate the deep trench beam splitter and the reflective metal grating half-wave plate based on the vertical micromirror, key optical components in the CNOT gate for quantum computing provided by this invention. This example will illustrate how these key optical components are assembled into an optical computing chip on a single-crystal silicon wafer.

[0079] Figure 7 Figure (a) shows a schematic diagram of MZI. A beam of light ① illuminates the first beam splitter 32. A reflected beam ② passes through the first reflector 33, and the light ③ passes through the first interferometer arm 34 to reach the second beam splitter 35, with a path of ①-②-③. A transmitted beam ④ passes through the second interferometer arm 36 and the light ⑤ of the second reflector 37 to reach the third beam splitter 35, with a path of ①-④-⑤. The two beams ③ and ⑤ interfere at the third beam splitter 35 to form interference light ⑥. The first interferometer arm 34 and the second interferometer arm 36 can be one of the electrically tunable or thermally tunable interferometer arms of the MOS structure or PN junction structure described in Embodiment 1.

[0080] Figure 7 Figure (b) shows a schematic diagram of an embodiment applying the adjustable interferometer arm from Example 1 and the deep trench beam splitter from Example 2 to a Michelson interferometer. One beam of light ① illuminates the third beam splitter 38, one beam is reflected to the third mirror 39 and then transmitted through the third beam splitter 38 to the detector 40, with the path being ①-②-③-④; the other beam of light is transmitted through the third interferometer arm 41, illuminates the fourth mirror 42, is reflected back, and is reflected through the third beam splitter 38 to the first detector 40, with the path being ①-⑤-⑥-⑦-⑧-⑨. The third interferometer arm 41 can be one of the electrically adjustable or thermally adjustable interferometer arms with a MOS structure or a PN junction structure as described in Example 1.

[0081] It should be noted that, Figure 7 (a) and Figure 7(b) in this example only illustrates the MZI and Michelson interferometers commonly used in optical computing. The method of forming an on-chip optical system on a single-crystal silicon wafer by combining interferometer arms with vertical structures and deep trench beam splitters is also applicable to other types of interferometers such as Fabry interferometers and Sagnac interferometers.

[0082] Figure 7 Figure (c) shows the schematic diagram of a two-bit controlled-not-agnostic (CNOT) quantum logic gate based on the deep trench beam splitter described in Example 2 and the reflective metal grating half-wave plate described in Example 3. In the CNOT gate, the first half-beam splitter 43 and the second half-beam splitter 44 constitute a MZI, and the control bit is input into this MZI. The third half-beam splitter 45 and the fourth half-beam splitter 46 constitute another MZI, and the target bit is input into this MZI. After the control bit performs conditional phase control on the target bit using the first third-third beam splitter 47, the second third-third beam splitter 48, and the third third-third beam splitter 49, the control bit is output after phase adjustment by the first reflective metal grating half-wave plate 50, and the target bit is output after phase adjustment by the second reflective metal grating half-wave plate 51. The CNOT gate is also equipped with a first collimating lens 52, a second collimating lens 53, a third collimating lens 54, and a fourth collimating lens 55. These lenses are formed by two-photon printing additive manufacturing or grayscale milling and cutting manufacturing on the vertical sidewalls after sidewall polishing, and are used to ensure beam collimation and mode matching.

[0083] Figure 7 Figure (d) shows a schematic diagram of an on-chip system based on vertical micromirror-based optical computing chip and electrical chip wafer-level integration. Light emitted from laser 56, epitaxially grown on a single-crystal silicon wafer or heterogeneously integrated, passes through on-chip optical computing chip 57 based on vertical micromirror to a second detector 58, is converted into an electrical signal, and integrated with electrical signal processing chip 59 on adapter board 60. Multiple adapter boards and computing chips can be integrated on circuit board 61, and vertical short-distance power supply is achieved through bottom power supply module 62.

[0084] Example 6

[0085] As a simplified form of deep trench beam splitter, the deep-wall beam splitter in this embodiment can be used to simplify the process in situations where high-precision control of the beam splitting ratio is not required. Generally, it is difficult to etch a vertical silicon wall structure with a thickness less than or equal to the wavelength onto a silicon wafer using vertical deep etching. For example, if the dimensions of the vertical silicon wall are 300 micrometers long (X direction), 200 micrometers deep (Z direction), and less than or equal to 1 micrometer thick (Y direction), although a specific ratio of reflected and transmitted light can be achieved by designing an appropriate incident light angle according to the Fresnel equation, the reliability is poor. The silicon wall is prone to breakage due to its thinness, leading to device failure. If the thickness is increased to several times the wavelength, such as 5 micrometers to 20 micrometers, the two sidewalls of the silicon wall (parallel to the XZ planes) form parallel plates, resulting in multi-beam Fabry-Perot interference. This makes the beam splitting effect a superposition of the Fresnel equation and Fabry-Perot interference. To eliminate Fabry-Perot interference, the two sidewalls of the silicon wall perpendicular to the substrate can be set at a certain angle (this angle can be obtained by comprehensively considering Fresnel's equations, Fabry-Perot interference, and total internal reflection, preferably 1.5°), forming a frustum-shaped deep-wall beam splitter 63 (e.g. Figure 8 As shown in (a)), its top view is trapezoidal (as shown in the figure). Figure 8 As shown in (b) in the figure), the Fabry interference between the first and second reflections can be eliminated.

[0086] Although the above method eliminates Fabry-Perot interference between the primary and secondary reflections, the intensity loss due to the secondary reflection not entering the primary reflection path should be considered a system loss. To eliminate Fabry-Perot interference without significant system loss, an ALD method can preferably be used to deposit a transmission sidewall optical antireflection film 64 (e.g., ...) on the transmission sidewall of the deep-wall beam splitter 63. Figure 8 (as shown in (c)). This method is applicable not only to frustum-shaped deep-walled beam splitters but also to cuboid-shaped deep-walled beam splitters (such as...). Figure 8 As shown in (d)). Depending on actual needs, additional elements can be added to the reflecting surface of the frustum-shaped beam splitter (such as...). Figure 8 (as shown in (e)) and the reflector of the cuboid deep-wall beam splitter (as shown in (e)). Figure 8 As shown in (f), the reflective sidewall optical film 65 is preferably deposited using the ALD method. The transmissive sidewall optical antireflective film 64 and the reflective sidewall optical film 65 can be the same or different, depending on the actual requirements.

[0087] It should be noted that, Figure 8 The angles and dimensions shown are for illustrative purposes only. When designing angles for actual use, in addition to comprehensively considering Fresnel equations and Fabry-Perot interference to achieve interference-free beam splitting, it is also necessary to consider avoiding total internal reflection.

[0088] Example 7

[0089] Large-scale optoelectronic integrated on-chip systems have complex structures and processes, therefore, design and manufacturing processes require collaborative optimization, such as... Figure 9 As shown, this embodiment proposes a smart manufacturing method for design-technology co-optimization (DTCO) for optical computing chips and optoelectronic integrated systems with vertical micromirror structures. The method mainly includes: wafer-level system modeling, optoelectronic co-architecture design, on-chip interconnect network simulation design, automatic routing and multi-physics coupling simulation optimization, and digital twin manufacturing steps.

[0090] S61: Wafer-level system modeling. At the system level, the wafer is divided into optical computing units, electrical computing units, storage units, control units, and power supply units. A complete wafer-level system architecture is formed through system-level modeling.

[0091] S62: Optoelectronic Co-working Architecture Design. Under the wafer-level system architecture established in S61, the co-working structure of the core optical computing unit and electrical computing unit is designed, comprehensively considering top-level optoelectronic co-working functional architectures such as standardized interfaces, software-defined networks, hierarchical topology, and joint scheduling mechanisms.

[0092] S63: Simulation Design of Optoelectronic Interconnect Network. The design of the optoelectronic interconnect network established in S62, under the optoelectronic collaborative functional architecture, includes using adaptive routing algorithms to reduce blocking latency, implementing automatic switching to backup paths during faults through redundant interconnect design, and reducing idle power consumption through dynamic voltage regulation, thereby realizing the optoelectronic interconnect network.

[0093] S64: Automatic routing and multiphysics coupling simulation optimization. Based on the optoelectronic on-chip interconnect network completed in S63, an artificial intelligence mapping model of manufacturing parameters and device performance is established. Automatic routing is performed according to functional requirements, and the on-chip system routing layout under multiphysics coupling conditions (optical, electrical, thermal, etc.) is further simulated. If the simulation results do not fully meet the requirements, the optoelectronic on-chip interconnect network is optimized based on the results. Through repeated iterative optimization, the design result achieves the overall optimal performance.

[0094] S65: Digital Twin Manufacturing. First, a global perception layer is constructed to establish data on integrated circuit manufacturing equipment, cleanroom environment, and microelectronic materials. Then, a multi-dimensional mapping digital manufacturing model is constructed. Furthermore, combining the on-chip system wiring layout design completed in S64 with the digital manufacturing model to drive the microelectronic process line, the manufacturing of optoelectronic integrated systems is completed.

[0095] In this process, the chip's process parameters are tested in real time, and the drift of equipment parameters is also extracted in real time. Dynamic closed-loop control is implemented by combining the test results and equipment parameters to predict, compensate, and dynamically adjust the device performance in advance. The system-on-chip routing layout design in S64 is optimized to further improve system performance.

[0096] It is important to note that, unlike the real-time testing of chip process parameters during the manufacturing process of traditional silicon photonics and CMOS integrated circuits, the online real-time testing of process parameters for optoelectronic integrated on-chip systems with vertical micromirror structures includes not only measurements such as thin film thickness, sheet resistance, and etching depth of planar structures, but also the morphology measurement of on-chip spatial optical systems using confocal optical profilometers to ensure the normal functioning of the on-chip optical systems.

[0097] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein.

[0098] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. An optical computing chip of vertical micro-mirror structure, characterized in that, The optical modulator comprises a plurality of optical modulators and a plurality of quantum logic gates, and the optical modulators are arranged based on vertical micro-mirrors to set interference optical paths of the optical modulators to realize optical modulation; the quantum logic gates are constructed by mirrors of the vertical micro-mirrors to set stable optical paths, interference is realized by a beam splitter, and Hadamard transformation is performed by a wave plate at an entrance or an exit of a target optical path to realize optical calculation. The quantum logic gate adopts a deep trench beam splitter or a deep wall beam splitter as the beam splitter, the silicon wall of the deep wall beam splitter is arranged at a predetermined angle with respect to two side walls of the substrate, and the deep trench beam splitter is manufactured by the following method: performing photoetching on a surface of a single crystal silicon wafer to form a pattern of a deep trench; performing deep etching to form the deep trench with a predetermined angle and performing side wall smoothing; depositing an optical film in the deep trench; performing photoetching and deep etching to form an outer shape of the deep trench beam splitter and performing side wall smoothing; and growing an optical anti-reflection film on the vertical side wall.

2. The photonic computing chip of claim 1, wherein, The adjustable interference arm in the optical modulator adopts thermal light modulation or voltage modulation, and is manufactured by the following method: depositing an insulating layer on a surface of a single crystal silicon wafer; forming a heavily doped substrate region by ion implantation and annealing; depositing a metal layer and annealing to form a substrate region electrode with ohmic contact properties; forming a gate electrode on the insulating layer on the surface; performing deep etching on the single crystal silicon wafer and performing side wall smoothing to form a vertical micro-mirror; An optical anti-reflection film is deposited on the surface of the vertical micro-mirror.

3. The photonic computing chip of claim 1, wherein, The adjustable interference arm in the optical modulator adopts PN junction modulation, and is manufactured by the following method: The vertical micro-mirror is formed by the following method: performing deep etching on a surface of a single crystal silicon wafer to form vertical side walls and performing side wall smoothing; performing patterning on the surface of the vertical micro-mirror by spraying glue or two-photon photoetching; doping the vertical side walls and annealing to form P regions, N regions, P+ regions and N+ regions; growing an electrode and growing an optical anti-reflection film on the surface of the vertical micro-mirror to form an adjustable interference arm based on a comb-tooth type PN junction modulation structure.

4. The photonic computing chip of claim 1, wherein, The quantum logic gate further comprises a metal grating polarizer, and the metal grating polarizer is manufactured by the following method: performing photoetching and vertical deep etching to form a nano-grid or a nano-pillar on a single crystal silicon wafer, depositing a metal to form a metal grid; or performing photoetching and vertical deep etching and side wall smoothing on the vertical side wall, printing a grating gap by using two-photon, patterning the side wall by spraying glue and photoetching, and depositing a metal to obtain a metal grid by peeling off the glue; or patterning by spraying glue and photoetching, depositing a metal, and peeling off the glue, etching away the metal in the gap by using a gray-scale milling function of a focused ion beam etching to obtain a metal grid.

5. The photonic computing chip of claim 1, wherein, The quantum logic gate further comprises a grating wave plate, and the grating wave plate is manufactured by the following method: etching a grating period structure on the vertical side wall after vertical deep etching and side wall smoothing by using deep reactive ion etching or a gray-scale milling function of a focused ion beam etching, and depositing a metal to form a wave plate of a reflective metal grating structure; or manufacturing a grating period structure on the vertical side wall after vertical deep etching and side wall smoothing by using a two-photon printing method, and depositing a metal to form a wave plate of a reflective metal grating structure.

6. The photonic computing chip of claim 1, wherein, The quantum logic gate further comprises a collimating lens, which is manufactured by two-photon printing additive manufacturing on the vertical sidewall after smoothing the sidewall, or focused ion beam milling subtractive manufacturing.

7. The photonic computing chip of claim 1, wherein, The light modulator and the quantum logic gate further comprise a mirror, which is manufactured by etching vertical sidewalls and smoothing to form a vertical micro-mirror, and depositing an optical enhancement film on the surface of the vertical micro-mirror.

8. The photonic computing chip of claim 1, wherein, The optical computing chip further comprises a spectrometer, in which the light emitted by the laser manufactured by epitaxial growth on a single crystal silicon wafer or by hetero-integration passes through a vertical diaphragm to a vertical concave mirror, is reflected to a light splitting element to split the light of different wavelengths into different angles, is reflected to a vertical concave mirror and is focused on different positions by a detector.

9. The photonic computing chip of claim 8, wherein, A blazed grating is used as the light splitting element, which is manufactured by: Making a zigzag groove on the vertical micro-mirror after vertical etching and sidewall smoothing, depositing a metal layer, and forming a blazed grating.

10. A wafer-level intelligent manufacturing method of a system on a chip, characterized by, The on-chip system comprises the optical computing chip with the vertical micro-mirror structure of any one of claims 1-9, and the method comprises: Dividing the wafer into optical computing units, electrical computing units, storage units, control units and power supply units at the system level, and forming a wafer-level system architecture through system-level modeling; Designing the photoelectric synergistic function structure of the optical computing units and the electrical computing units based on the wafer-level system architecture; Designing the photoelectric on-chip interconnection network under the photoelectric synergistic function architecture, wherein an adaptive routing algorithm is used to reduce blocking delay, a redundant interconnection design is used to automatically switch to a backup path in case of failure, and dynamic voltage adjustment is used to reduce idle power consumption; Under the photoelectric on-chip interconnection network, an artificial intelligence mapping model of manufacturing parameters and device performance is established, automatic routing is performed according to functional requirements, and the on-chip system routing layout under multi-physical field coupling conditions is simulated, wherein if the simulation result does not meet the requirements, the on-chip interconnection network is optimized according to the simulation result and simulated again until the requirements are met; A global perception layer is constructed, data of integrated circuit manufacturing equipment, super-clean room environment and microelectronic materials are established, a multi-dimensional mapping digital manufacturing model is constructed, the routing layout design of the on-chip system is combined, and the microelectronic process line is driven by the digital manufacturing model to complete the manufacturing of the photoelectric integrated system; In the manufacturing process, the process parameters of the chip are tested in real time, the drift of the equipment parameters is extracted in real time, the test results and the equipment parameters are combined to implement dynamic closed-loop control, the device performance is predicted, compensated and dynamically feedback adjusted in advance, and the on-chip system routing layout design is optimized.

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