Array substrate and manufacturing method thereof, display panel and display device

Abstract

The invention discloses an array substrate and a manufacturing method thereof, a display panel and a display device. The array substrate comprises a substrate, and a signal line, a buffer layer, an active layer, a gate insulating layer, a gate layer, a protective layer and an electrode layer which are arranged on the substrate, the buffer layer is provided with a first through hole penetrating through the buffer layer, and the signal line is overlapped with the first through hole; the active layer is divided into a first conductor part, a semiconductor part and a second conductor part which are continuous, the end, away from the semiconductor part, of the first conductor part is provided with a lap joint part, the orthographic projection of the lap joint part on the substrate is located in the orthographic projection of the first through hole on the substrate, and the lap joint part is in lap joint with a signal line located at the bottom of the first through hole; the conductive structure is arranged on the same layer as any conductive layer on one side, far away from the substrate, of the active layer; the conductive structure is overlapped with the first through hole, and the conductive structure is electrically connected with the signal line and the upper surface of the lap joint part at least in the first through hole.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate and a manufacturing method thereof, a display panel and a display device. Background Art

[0002] In recent years, with the improvement of product resolution and refresh rate, parasitic capacitance on the metal layer of data lines has become an important factor restricting the improvement of resolution and refresh rate of high-end LCD display products.

[0003] To solve the problem of large parasitic capacitance in display products based on oxide transistors, the data line metal layer is usually placed downward. However, in array substrates based on oxide transistors, placing the data line metal layer downward either results in a low aperture ratio or poor electrical connection between the active layer in the oxide transistor and the data line, affecting the display effect.

[0004] Therefore, how to simultaneously improve the aperture ratio of pixels in the array substrate and the poor electrical properties between the active layer and the data lines has become a technical problem that needs to be solved urgently. Summary of the Invention

[0005] Embodiments of the present invention provide an array substrate and a manufacturing method thereof, a display panel, and a display device to solve the above-mentioned problems existing in the prior art.

[0006] In a first aspect, to solve the above technical problems, an embodiment of the present invention provides an array substrate, comprising:

[0007] A base substrate, and a signal line, a buffer layer, an active layer, a gate insulating layer, a gate layer, a protective layer, and an electrode layer on the base substrate; the buffer layer has a first through hole extending through the buffer layer, and the signal line overlaps the first through hole; the active layer is divided into a continuous first conductor portion, a semiconductor portion, and a second conductor portion; an end of the first conductor portion away from the semiconductor portion has an overlapping portion, the overlapping portion having an orthographic projection of the base substrate located within the orthographic projection of the first through hole on the base substrate, and overlapping the signal line located at the bottom of the first through hole;

[0008] A conductive structure is arranged in the same layer as any conductive layer located on the side of the active layer away from the base substrate; the conductive structure overlaps with the first through hole, and the conductive structure electrically connects the signal line and the upper surface of the overlapping portion at least in the first through hole.

[0009] In a possible implementation manner, the conductive layer is the gate layer;

[0010] The gate insulating layer includes a residual structure covering a sidewall of the first through hole portion, wherein the residual structure does not overlap with the first conductor portion;

[0011] The conductive structure includes a first portion, a second portion, and a third portion that are continuously arranged; the first portion is in direct contact with the residual structure, the second portion is in direct contact with the signal line in the first through hole, and the third portion is in direct contact with the first conductor portion; wherein the third portion overlaps with a portion of the first conductor portion in the first through hole, and overlaps with a portion of the first conductor portion outside the first through hole and on a side of the buffer layer away from the base substrate.

[0012] In a possible implementation manner, the conductive layer is the gate layer;

[0013] The gate insulating layer has a second through hole extending through the gate insulating layer, the second through hole overlapping the first through hole, the conductive structure electrically connecting the signal line and the first conductor portion in a region where the first through hole and the second through hole overlap; the signal line overlaps the second through hole;

[0014] The overlapping portion and the signal line partially overlap in the second through hole; the conductive structure electrically connects the signal line and the upper surface of the overlapping portion in the second through hole.

[0015] In a possible implementation manner, the conductive layer is located in the electrode layer;

[0016] A third through hole is provided at a position corresponding to the first through hole, at least penetrating the protective layer; the overlapping portion is overlapped on the signal line located in the third through hole; and the conductive structure electrically connects the signal line and the upper surface of the overlapping portion in the third through hole.

[0017] In a possible implementation manner, an orthographic projection of the third through hole on the base substrate is located within an orthographic projection of the first through hole on the base substrate, and the third through hole passes through the protective layer;

[0018] Alternatively, the third through hole overlaps with the first through hole, and the third through hole is closer to the semiconductor portion than the first through hole, and the third through hole passes through the gate insulating layer and the protection layer.

[0019] In a possible implementation manner, the second conductor portion is reused as a pixel electrode, the conductive layer is a common electrode layer, and the protective layer is a first insulating layer.

[0020] In one possible implementation manner, the electrode layer includes:

[0021] a common electrode layer, located on a side of the protective layer away from the base substrate;

[0022] a second insulating layer, located on a side of the common electrode layer away from the base substrate;

[0023] A pixel electrode layer is located on a side of the second insulating layer away from the base substrate; the pixel electrode layer includes a pixel electrode, and has a fourth through hole penetrating the protective layer and the second insulating layer at a position corresponding to the second conductor portion, the pixel electrode extends into the fourth through hole and is electrically connected to the second conductor portion; the pixel electrode does not overlap with the common electrode layer.

[0024] In one possible implementation manner, the protective layer includes:

[0025] a first insulating layer, located on a side of the gate layer away from the substrate;

[0026] The resin layer is located between the first insulating layer and the common electrode layer.

[0027] In a possible implementation manner, the conductive layer is the pixel electrode layer, and the third through hole also passes through the second insulating layer;

[0028] Alternatively, the conductive layer is the common electrode layer.

[0029] In a possible implementation manner, the array substrate further includes a light shielding structure provided on the same layer as the signal line;

[0030] The orthographic projection of the semiconductor portion on the base substrate is located within the orthographic projection of the light shielding structure on the base substrate.

[0031] In one possible implementation manner, the signal line includes:

[0032] Data cable;

[0033] The active layer is a metal oxide semiconductor.

[0034] In a second aspect, an embodiment of the present invention provides a method for manufacturing an array substrate, comprising:

[0035] providing a substrate;

[0036] A signal line, a buffer layer, an active layer, a gate insulating layer, a gate layer, a protective layer and an electrode layer are formed on one side of the base substrate; wherein the buffer layer has a first through hole penetrating the buffer layer, and the signal line overlaps with the first through hole; the active layer is divided into a continuous first conductor portion, a semiconductor portion and a second conductor portion, and the first conductor portion has an overlapping portion at one end away from the semiconductor portion, the overlapping portion is located within the orthographic projection of the first through hole on the base substrate, and overlaps with the signal line located at the bottom of the first through hole; the array substrate also includes a conductive structure, which is arranged on the same layer as any conductive layer located on the side of the active layer away from the base substrate, the conductive structure overlaps with the first through hole, and the conductive structure electrically connects the signal line and the upper surface of the overlapping portion at least within the first through hole.

[0037] In one possible implementation, forming the active layer, the gate insulating layer, and the gate layer includes:

[0038] forming an original active layer on a side of the buffer layer away from the base substrate; one end of the original active layer extends to the bottom of the first through hole and is deposited on the surface of the portion of the signal line exposed in the first through hole;

[0039] forming a gate insulating layer and a gate layer in sequence on a side of the original active layer away from the substrate;

[0040] The original active layer is semiconductorized to obtain the active layer.

[0041] In a possible implementation manner, the conductive layer is the gate layer, and a gate insulating layer and a gate layer are sequentially formed on a side of the original active layer away from the base substrate, including:

[0042] Depositing an original gate insulating layer on a side of the original active layer away from the substrate;

[0043] Etching the original gate insulating layer at a position corresponding to the first through hole to obtain a second through hole penetrating the original gate insulating layer, wherein the second through hole overlaps with the first through hole, and the signal line and the overlapping portion are located in a region where the second through hole overlaps with the first through hole; wherein the original gate insulating layer having the second through hole serves as the gate insulating layer;

[0044] Depositing the original gate layer on a side of the gate insulation layer away from the substrate;

[0045] The original gate layer is patterned to obtain the gate layer and a conductive structure covering the second through hole and the overlapping region of the second through hole.

[0046] In a possible implementation manner, the conductive layer is the common electrode layer, and forming a protective layer and an electrode layer includes:

[0047] After the original active layer is semiconductorized, a protective layer is formed on a side of the gate layer away from the base substrate;

[0048] At a position corresponding to the first through hole, at least the protective layer is etched to obtain a third through hole that at least penetrates the protective layer, so that the signal line and the overlapping portion are located in the third through hole;

[0049] A common electrode layer and the conductive structure are formed on a side of the protection layer away from the base substrate.

[0050] One possible implementation method for forming a protective layer and an electrode layer includes:

[0051] After the original active layer is semiconductorized, the protective layer, the common electrode layer and the second gate insulating layer are sequentially formed on a side of the gate layer away from the base substrate;

[0052] At a position corresponding to the first through hole, at least the protective layer and the second insulating layer are etched to obtain a third through hole that at least penetrates the protective layer and the second insulating layer, so that the signal line and the overlapping portion are located in the third through hole;

[0053] A pixel electrode layer and the conductive structure are formed on a side of the second insulating layer away from the base substrate.

[0054] In a possible implementation manner, the gate insulating layer is patterned, and the original active layer is semiconductorized to obtain the active layer, comprising:

[0055] The original active layer is semiconductorized by hydrogen ion diffusion to obtain the active layer; wherein the original gate insulating layer serves as the gate insulating layer.

[0056] In a possible implementation manner, the gate insulating layer is patterned using the gate layer as a hard mask, and the original active layer is semiconductorized to obtain the active layer, comprising:

[0057] The active layer is semiconductorized by ion doping or plasma diffusion to obtain the active layer.

[0058] In a third aspect, an embodiment of the present invention provides a display panel, including:

[0059] A color filter substrate and the array substrate as described in the first aspect are arranged opposite to each other;

[0060] The liquid crystal layer is located between the color filter substrate and the array substrate.

[0061] In a fourth aspect, an embodiment of the present invention provides a display device comprising the display panel as described in the third aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] Figure 1 Shown is a structural schematic diagram of an array substrate;

[0063] Figure 2 A process diagram of manufacturing an array substrate;

[0064] Figure 3 A process diagram for forming a gate insulating layer, a connecting portion, and a gate layer;

[0065] Figure 4 is a structural schematic diagram of another array substrate;

[0066] Figure 5 A partial process diagram of another array substrate;

[0067] Figure 6 is a structural schematic diagram of another array substrate;

[0068] Figure 7 A schematic structural diagram of the connection position between an active layer and a data line provided by an embodiment of the present invention;

[0069] Figure 8 A schematic diagram of the distribution of doping particles in an active layer provided by an embodiment of the present invention;

[0070] Figure 9 A schematic structural diagram of an array substrate provided by an embodiment of the present invention;

[0071] Figure 10 A schematic structural diagram of another array substrate provided by an embodiment of the present invention;

[0072] Figure 11 A schematic structural diagram of another array substrate provided by an embodiment of the present invention;

[0073] Figure 12 A schematic structural diagram of another array substrate provided by an embodiment of the present invention;

[0074] Figure 13 A schematic structural diagram of another array substrate provided by an embodiment of the present invention;

[0075] Figure 14 A schematic structural diagram of another array substrate provided by an embodiment of the present invention;

[0076] Figure 15-16 A schematic structural diagram of another array substrate provided by an embodiment of the present invention;

[0077] Figure 17 and Figure 18 A schematic structural diagram of another array substrate provided by an embodiment of the present invention;

[0078] Figure 19 and Figure 20 A schematic structural diagram of another array substrate provided by an embodiment of the present invention;

[0079] Figure 21 A flowchart of a method for manufacturing an array substrate provided by an embodiment of the present invention;

[0080] Figure 22 A schematic diagram of manufacturing an array substrate provided by an embodiment of the present invention;

[0081] Figure 23 A schematic diagram of forming an active layer according to an embodiment of the present invention;

[0082] Figure 24 A schematic diagram of forming a gate insulating layer and a gate layer provided by an embodiment of the present invention;

[0083] Figure 25 A schematic diagram of forming a common electrode layer and a conductive structure is provided for an embodiment of the present invention;

[0084] Figure 26 A schematic diagram of forming a pixel electrode layer and a conductive structure provided by an embodiment of the present invention.

[0085] Reference numerals:

[0086] Substrate 1, signal line 2, buffer layer 3, active layer 4, gate insulating layer 5, gate layer 6, protective layer 7, electrode layer 8, conductive structure 9, connection structure 62, light shielding structure 2z, first conductor portion 41, semiconductor portion 42, second conductor portion 43, overlapping portion 41a, first through hole H1, second through hole H2, third through hole H3, fourth through hole H4, fifth through hole H5, residual structure 61, first portion 91, second portion 92, third portion 93;

[0087] Original active layer 04 , original gate insulating layer 05 , original gate layer 06 , first insulating layer PVX1 , resin layer Resin, second insulating layer PVX2 , common electrode layer COM, pixel electrode layer PIX, pixel electrode P. DETAILED DESCRIPTION

[0088] Embodiments of the present invention provide an array substrate and a manufacturing method thereof, a display panel, and a display device to solve the above-mentioned problems existing in the prior art.

[0089] It should be understood that the specific structural and functional details disclosed in the embodiments of the present invention are merely representative and are for the purpose of describing exemplary embodiments of the present application. However, the present application can be implemented in many alternative forms and should not be construed as being limited to the embodiments set forth herein.

[0090] In the description of the present application, it should be understood that the terms "center", "lateral", "up", "down", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present application, unless otherwise specified, "multiple" means two or more. In addition, the term "including" and any variations thereof are intended to cover non-exclusive inclusions.

[0091] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0092] The terms used in this application are intended only to describe specific embodiments and are not intended to limit exemplary embodiments. Unless the context clearly indicates otherwise, the singular forms "a", "an", "an item" used herein are also intended to include the plural. It should also be understood that the terms "comprise" and / or "include" used herein specify the presence of stated features, integers, steps, operations, units and / or components, and do not exclude the presence or addition of one or more other features, integers, steps, operations, units, components and / or combinations thereof.

[0093] In the embodiments of the present invention, the term "and / or" simply describes an association relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. Furthermore, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0094] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention will be further described below with reference to the accompanying drawings and examples. However, the example embodiments can be implemented in various forms and should not be understood as being limited to the embodiments described herein; on the contrary, these embodiments are provided to make the present invention more comprehensive and complete, and to fully convey the concepts of the example embodiments to those skilled in the art. The same figure marks in the figures represent the same or similar structures, and their repeated descriptions will be omitted. The words expressing position and direction described in the present invention are all explained with reference to the accompanying drawings as examples, but changes can be made as needed, and the changes made are all included in the scope of protection of the present invention. The drawings of the present invention are only used to illustrate the relative position relationship and do not represent the true proportion.

[0095] It should be noted that specific details are set forth in the following description to facilitate a full understanding of the present invention. However, the present invention can be implemented in a variety of ways different from those described herein, and those skilled in the art can make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below. The subsequent description of the specification is a preferred embodiment of the present application, but the description is for the purpose of illustrating the general principles of the present application and is not intended to limit the scope of the present application. The scope of protection of the present application shall be determined as defined by the appended claims.

[0096] In the related art, in order to solve the problem of large parasitic capacitance of display products based on oxide transistors, the metal layer of the data line 2' is usually placed downward, such as Figure 1 The figure shows a schematic diagram of the structure of an array substrate. The array substrate includes: a base substrate 1, a data line 2' and a light shielding structure 2z arranged on the same layer on one side of the base substrate 1, a buffer layer 3 located on the side of the data line 2' away from the base substrate 1, an active layer 4' located on the side of the buffer layer 3 away from the base substrate 1, a gate insulating layer 5 located on the side of the active layer 4' away from the base substrate 1, a gate layer 6 and a connecting portion 9' located on the side of the gate insulating layer 5 away from the base substrate 1, the connecting portion 9' being connected to the data line 2' through a via in the insulating layer, a protective layer 7 located on the side of the gate layer away from the base substrate 1, and a protective layer 7 including a gate layer 6 located on the side of the gate insulating layer 5 away from the base substrate 1. A first insulating layer (denoted as PVX1) on one side of the board 1 and a resin layer (denoted as Resin) located on the side of the first insulating layer PVX1 away from the base substrate 1; a common electrode layer (denoted as COM) located on the side of the resin layer Resin away from the base substrate 1, a second insulating layer (denoted as PVX2) located on the side of the common electrode layer COM away from the base substrate 1, and a pixel electrode layer (denoted as PIX) located on the side of the second insulating layer PVX2 away from the base substrate 1. The pixel electrode layer PIX is overlapped with the active layer 4' through a through hole that passes through the second insulating layer PVX2 to the active layer 4'.

[0097] See Figure 2 The following is a process diagram of manufacturing an array substrate. The specific manufacturing process is as follows:

[0098] S11: depositing a first metal layer on one side of the base substrate 1 and patterning the first metal layer to obtain a data line 2 ′ and a light shielding structure 2 z;

[0099] S12: forming a buffer layer 3, an original active layer 04', and an original gate insulating layer 05 in sequence on the side of the data line 2' and the light shielding structure 2z away from the base substrate 1;

[0100] S13: depositing a second metal layer on a side of the original gate insulating layer 05 away from the base substrate 1, and patterning the second metal layer and the original gate insulating layer 05 to obtain a gate insulating layer 5, a gate layer 6 and a connecting portion 9';

[0101] See Figure 3 The process diagram for forming the gate insulating layer, the connecting portion and the gate layer is as follows:

[0102] S131: dry-etching the original gate insulating layer 05 and the buffer layer 3 to form a through hole penetrating the original gate insulating layer 05 and the buffer layer 3 at a position corresponding to the data line 2'. The through hole covers the overlapping portion of the original active layer 04' and the data line 2'.

[0103] During dry etching, since plasma is used for dry etching, the portion of the original active layer 04 ′ overlapping with the through hole will be conductive.

[0104] S132 : depositing a second metal layer on a side of the original gate insulating layer 05 away from the base substrate 1 , and patterning the second metal layer to obtain a gate layer 6 and a connecting portion 9 ′.

[0105] At this time, the connection portion 9 ′ is connected to the conductive portion of the original active layer 04 ′.

[0106] S133 : using the gate layer 6 and the connecting portion 9 ′ as a hard mask, etching the original gate insulating layer 05 over a large area to obtain a gate insulating layer 5 .

[0107] S14: Conductorize the portion of the original active layer 04' that is not covered by the connecting portion 9' and the gate layer 6, so as to obtain an active layer 4'. The active layer 4' includes a first portion 41' connected to the connecting portion 9', a second portion 43' connected to the pixel electrode layer PIX, and a semiconductor portion 42' located between the first portion 41' and the second portion 43'; wherein the first portion 41' and the second portion 43' are conductorized, and the semiconductor portion 42' is not conductorized; the semiconductor portion 42' constitutes a channel region of the transistor, the first portion 41' and the connecting portion 9' can be regarded as the first electrode of the transistor, the second portion 43' can be regarded as the second electrode of the transistor, and the portion of the gate layer 6 overlapping with the semiconductor portion 42' can be regarded as the gate of the transistor.

[0108] At this time, all portions of the active layer 4 ′ not covered by the gate layer 6 are conductive, so that the first portion 41 ′ and the second portion 43 ′ are electrically connected to the semiconductor portion 42 ′.

[0109] Figure 3 Where a is the size of the via in the original gate insulating layer 05, and b is the minimum distance from the via in the original gate insulating layer 05 to the transistor's channel c. This minimum distance ensures transistor device characteristics and prevents plasma from diffusing into channel c during dry etching of the via in the original gate insulating layer 05, which could affect transistor stability. d and e are contained within the via in the original gate insulating layer 05. d ensures that the connection portion 9' overlaps the original active layer 04', while e ensures that the right side of the connection portion 9' does not overlap the original gate insulating layer 05, ensuring that data signals can be transmitted to the transistor's channel c through the connection portion 9' and the first portion 41'.

[0110] like Figure 4 The figure shows another structural diagram of an array substrate. If the right side of the connecting portion 9' overlaps with the original gate insulating layer 05, the size of the via hole in the original gate insulating layer 05 is Figure 3 The a in Figure 4 When A in , A does not contain e, assuming Figure 4 The right side of the middle connecting portion 9' overlaps with the original gate insulating layer 05 at the corresponding position e. Please refer to the subsequent processing flow Figure 5 This is a partial process diagram of another array substrate.

[0111] S133': using the patterned second metal layer as a hard mask, etching the original gate insulating layer 05 over a large area to obtain a gate insulating layer 5, wherein a portion at position e in the gate insulating layer 5 is covered by the connecting portion 9'.

[0112] S14': The portion of the original active layer 04' not covered by the connecting portion 9' and the gate layer 6 is conductorized. At this time, the portion of the original active layer 04' corresponding to position e is covered by the connecting portion 9', so that the portion of the active layer 4' corresponding to position e cannot be conductorized and is in a high-resistance state. This causes the connecting portion 9' to be unable to form a good electrical connection with the channel c through the first portion 41', affecting the switching characteristics of the transistor. Therefore, the right side of the connecting portion 9' cannot overlap with the original gate insulating layer 05.

[0113] S15: On the side of the connection portion 9 ′ and the gate layer 6 away from the base substrate 1 , a protection layer 7 , a resin layer Resin, a common electrode layer COM, a second insulating layer PVX2 and a pixel electrode layer PIX are sequentially formed, and the pixel electrode layer PIX is electrically connected to the active layer 4 ′.

[0114] When the right side of the connecting portion 9' cannot overlap with the original gate insulating layer 05, the above solution requires that the through hole of the original gate insulating layer 05 must include d and e, which will reduce the pixel aperture ratio and pixel density of the display product, and also cause parasitic capacitance between the data line 2' and other metals.

[0115] In order to reduce the size of the through hole of the original gate insulating layer 05, it is possible to use Figure 6 The scheme shown, Figure 6 This is a structural diagram of another array substrate. Figure 6 The through hole corresponding to the data line 2' only penetrates the buffer layer 3, allowing the active layer 4' to be connected to the data line 2' through this through hole, so that there is no need Figure 3 d and e in the figure, thereby minimizing the size of the through hole in the original gate insulating layer 05 corresponding to the data line 2' and improving the aperture ratio.

[0116] However, Figure 6 The active layer 4' and the data line 2' in the solution cannot form a good electrical contact. The inventors found that: since the first portion 41' connected to the data line 2' needs to be conductive, the doping ions or dry etching plasma or hydrogen (H) ions that make the active layer 4' conductive may only be injected near the upper surface of the active layer 4' (such as Figure 7 At A' shown in Figure 7 Schematic diagram of the structure of the active layer and the data line overlap position provided by an embodiment of the present invention), the active layer 4' can be made completely conductive near the top; of course, by increasing the energy, dose and other process parameters during injection, doping ions or dry etching plasma or H ions can be injected into the active layer 4' near the middle layer (such as Figure 7 C shown in FIG), or even injected into the vicinity of the lower surface of the active layer 4' (as shown below Figure 7B shown); however, due to the blocking effect of the atoms of the active layer 4' themselves, the farther away from the upper surface of the active layer 4' and the closer to the lower surface of the active layer 4', the less the number of doped ions or dry-etched Plasma or H ions injected, that is, the number of doped ions or dry-etched Plasma or H ions injected near the upper surface of the active layer 4' will be much higher than that near the lower surface of the active layer 4'. This makes it possible that when the upper surface of the active layer 4' is fully conductive, the lower surface of the active layer 4' may not be conductive, as shown below Figure 8 FIG. 1 is a schematic diagram showing the distribution of doping particles in an active layer provided by an embodiment of the present invention. Figure 8 The material used for the active layer 4' is indium gallium zinc oxide (IGZO).

[0117] It can be seen that when the active layer 4' is connected downward to the data line 2', the active layer 4' and the data line 2' may not form good electrical contact because the lower surface of the active layer 4' is not conductive, which directly affects the display effect of the product.

[0118] To solve the above problems, embodiments of the present invention provide an array substrate and a manufacturing method thereof, a display panel, and a display device, which are described in detail below with reference to the accompanying drawings.

[0119] See Figure 9 A schematic structural diagram of an array substrate provided in an embodiment of the present invention includes:

[0120] A base substrate 1, and a signal line 2, a buffer layer 3, an active layer 4, a gate insulating layer 5, a gate layer 6, a protective layer 7, and an electrode layer 8 on the base substrate 1; the buffer layer 3 has a first through hole H1 that penetrates the buffer layer 3, and the signal line 2 overlaps with the first through hole H1; the active layer 4 is divided into a continuous first conductor portion 41, a semiconductor portion 42, and a second conductor portion 43, and an end of the first conductor portion 41 away from the semiconductor portion 42 has an overlapping portion 41a, the orthographic projection of the overlapping portion 41a on the base substrate 1 is located within the orthographic projection of the first through hole H1 on the base substrate, and overlaps with the signal line 2 located at the bottom of the first through hole H1;

[0121] The signal line 2 can be a signal line 2 in the source and drain layer, such as a data line. The material used for the active layer 4 is a semi-transparent metal oxide, such as indium gallium tin oxide (IGTO), indium gallium zinc oxide (IGZO), zinc oxynitride (ZnON), indium gallium zinc oxysulfide (IGZSO), etc.

[0122] Conductive structure 9 is disposed in the same layer as any conductive layer located on the side of active layer 4 away from substrate 1. Conductive structure 9 overlaps first through-hole H1 and electrically connects signal line 2 and the upper surface of overlap portion 41a at least within first through-hole H1. "In the same layer" means formed using the same process, not without a step.

[0123] like Figure 10 As shown, it is a structural diagram of another array substrate provided by an embodiment of the present invention. When the gate layer 6 is located on the side of the active layer 4 close to the base substrate 1, the conductive layer is the electrode layer 8; Figure 9 As shown, when the gate layer 6 is located on the side of the active layer 4 away from the base substrate 1 , the conductive layer may be the gate layer 6 or the electrode layer 8 .

[0124] For example, Figure 9 In the example, the signal line 2 is a data line, the gate layer 6 is located on the side of the active layer 4 close to the base substrate 1, and the conductive layer is the gate layer 6 (that is, the conductive structure 9 and the gate layer 6 are formed by the same process). As an example, since the first conductor portion 41 of the active layer 4 extends into the first through hole H1, the overlapping portion 41a is used to cover and overlap a portion of the data line located at the bottom of the first through hole H1, and the conductive structure 9 is used to electrically connect the data line not covered by the overlapping portion 41a and the upper surface of the overlapping portion 41a in the first through hole H1. In this way, the via image opened in the gate insulating layer 5 corresponding to the first through hole H1 before the conductive structure 9 is formed can be avoided. Figure 3 The pixel aperture ratio is reduced by including d and e, and the conductive structure 9 can be used to directly connect the data line and the upper surface of the overlapping portion 41a to improve the conductivity of the data line and the active layer 4, thereby improving the conductivity of the overlapping portion 41a between the data line and the active layer 4 while improving the pixel aperture ratio.

[0125] In the embodiment provided by the present invention, since the signal line 2 and the upper surface of the overlapping portion 41a in the active layer 4 are electrically connected by the conductive structure 9 in the first through hole H1, and the upper surface of the active layer 4 is rich in conductive particles after being conductorized, not only can the resistance between the signal line 2 and the overlapping portion 41a of the active layer 4 be effectively reduced, but the pixel aperture ratio can also be improved, thereby simultaneously improving the conductivity and pixel aperture ratio of the active layer 4 and the data line (signal line 2 of the source and drain layer) in the array substrate with the source and drain layer underneath.

[0126] Please continue to see Figure 9 , the conductive layer is a gate layer 6;

[0127] The gate insulating layer 5 includes a residual structure 61 covering a portion of the sidewall of the first through hole H1 . The residual structure 61 does not overlap with the first conductor portion 41 . The formation of the residual structure 61 can be found in the subsequent description of the manufacturing method and will not be repeated here.

[0128] The conductive structure 9 includes a first portion 91, a second portion 92, and a third portion 93, which are arranged continuously. The first portion 91 directly contacts the residual structure 61, the second portion 92 directly contacts the signal line 2 in the first through-hole H1, and the third portion 93 directly contacts the first conductor portion 41. The third portion 93 overlaps the portion of the first conductor portion 41 within the first through-hole H1 and also overlaps the portion of the first conductor portion 41 outside the first through-hole H1 on the side of the buffer layer 3 away from the base substrate 1. In other words, the third portion 93 extends from the surface of the overlapping portion 41a along the sidewall of the first through-hole H1 toward the semiconductor portion 42 to the outside of the first through-hole H1, covering a small portion of the first conductor portion 41 outside the first through-hole H1.

[0129] Since the second portion 92 in the conductive structure 9 is in direct contact with the signal line 2 in the first through hole H1, the third portion 93 is in direct contact with the first conductor portion 41, and the third portion 93 extends from the surface of the overlapping portion 41a along the side wall of the first through hole H1 to the semiconductor portion 42 to the outside of the first through hole H1, covering a small part of the first conductor portion 41 outside the first through hole H1, so that the gate insulation layer 5 is not covered in the area where the third portion 93 overlaps with the first conductor portion 41, and the conductive structure 9 can be effectively electrically connected to the first conductor portion 41 and the signal line 2 in the first through hole H1, thereby improving the conductivity of the active layer 4 and the data line (the signal line 22 of the source and drain layer) in the array substrate with the source and drain layer underneath.

[0130] See Figure 11 This is a structural diagram of another array substrate provided by an embodiment of the present invention, wherein the array substrate further includes a light shielding structure 2z provided on the same layer as the signal line 2;

[0131] The orthographic projection of the semiconductor portion 42 on the base substrate 1 is located within the orthographic projection of the light shielding structure 2 z on the base substrate 1 .

[0132] By setting a shading structure 2z on the same layer as the signal line 2 and allowing the semiconductor part 42 to have its orthographic projection on the base substrate 1 located within the shading structure 2z, the shading structure 2z can be used to prevent light from entering the semiconductor part 42 (i.e., the channel region of the transistor), thereby preventing light from affecting the performance of the transistor and improving the stability of the transistor. The shading structure 2z and the signal line 2 can also be formed using the same mask, thereby improving the stability of the transistor without increasing the process.

[0133] See Figure 12 This is a schematic structural diagram of another array substrate provided by an embodiment of the present invention, wherein the conductive layer is a gate layer 6;

[0134] The gate insulating layer 5 has a second through hole H2 that penetrates the gate insulating layer 5. The second through hole H2 overlaps with the first through hole H1. The conductive structure 9 electrically connects the signal line 2 and the first conductor portion 41 in the region where the first through hole H1 and the second through hole H2 overlap. The signal line 2 overlaps with the second through hole H2.

[0135] The overlapping portion 41 a and the signal line 2 partially overlap in the second through hole H2 ; the conductive structure 9 electrically connects the signal line 2 and the upper surface of the overlapping portion 41 a in the second through hole H2 .

[0136] The overlapping portion 41a overlaps with a portion of the signal line 2 in the area where the first through hole H2 overlaps with the second through hole H2, and the conductive structure 9 directly contacts the first conductor portion 41 and the signal line 2 respectively in the area where the first through hole H2 overlaps with the second through hole H2, and the conductive structure 9 extends along the first conductor portion 41 toward the semiconductor portion outside the first through hole and inside the second through hole. In this way, the conductive structure 9 has no contact with the gate insulating layer 5 in the area where the first conductor portion 41 is located, thereby preventing the appearance of an unconducted portion in the first conductor portion 41 and reducing the conductivity of the first conductor portion 41.

[0137] In the embodiment provided by the present invention, by arranging the conductive structure 9 and the gate layer 6 in the same layer, the depth of the through hole between the gate layer 6 and the data line can be reduced, thereby improving the flatness of the array substrate; and at a position corresponding to the first through hole H1, a second through hole H2 is arranged through the gate insulating layer 5, so that the second through hole H2 overlaps with the first through hole H1, and the conductive structure 9 is in direct contact with the signal line 2 and the first conductor portion 41 in the area where the second through hole H2 overlaps with the first through hole H1, which can not only make the signal line 2 and the first conductor portion 41 have good conductivity, but also further improve the flatness of the array substrate, and when the gate layer 6 is patterned, the active layer 4 can also be over-etched.

[0138] The electrode layer 8 at least includes a common electrode layer COM, such as Figure 11 and Figure 12 The electrode layer 8 may include a common electrode layer COM, which is located on a side of the protective layer 7 away from the base substrate 1;

[0139] The second insulating layer PVX2 is located on a side of the common electrode layer COM away from the base substrate 1;

[0140] The pixel electrode layer PIX is located on the side of the second insulating layer PVX2 away from the base substrate 1; the pixel electrode layer PIX includes a pixel electrode (denoted as P), and has a fourth through hole H4 penetrating the protective layer 7 and the second insulating layer PVX2 at a position corresponding to the second conductor portion 43. The pixel electrode P extends into the fourth through hole H4 and is electrically connected to the second conductor portion 43; the pixel electrode P has no overlap with the common electrode layer COM.

[0141] Figure 11and Figure 12 The film layers of the common electrode layer COM and the pixel electrode layer PIX can also be interchanged. The pixel electrode layer PIX is set on the side of the common electrode layer COM away from the base substrate 1, and the opposite common electrode layer COM is set on the side of the pixel electrode layer PIX away from the base substrate 1. This can make the distance between the pixel electrode layer PIX and the gate layer 6 larger, and better prevent parasitic capacitance from being generated between the pixel electrode layer PIX and the gate layer 6.

[0142] like Figure 13 As shown is a structural schematic diagram of another array substrate provided by an embodiment of the present invention. The electrode layer 8 may also have only a common electrode layer COM. In this case, the pixel electrode P is arranged on the same layer as the active layer 4, and the second semiconductor portion 42 in the active layer 4 is reused as the pixel electrode P. This can reduce the thickness of the array substrate, and the pixel electrode P and the active layer 4 can be formed through a mask process, thereby realizing the lightweight and thinning of the display product and saving process and cost.

[0143] See Figure 14 A structural schematic diagram of another array substrate provided in an embodiment of the present invention, wherein the array substrate further includes a connecting structure 62, which is arranged in the same layer as the gate layer 6 and is located on the surface of the second conductor portion 43; the protective layer 7 and the second insulating layer PVX2 have a fourth through hole H4 exposing the connecting structure 62 at a position corresponding to the connecting structure 62, and the pixel electrode P is electrically connected to the connecting structure 62 through the fourth through hole H4, so that the connecting structure 62 electrically connects the pixel electrode P and the second conductor portion 43, thereby improving the flatness of the second insulating layer PVX2, and thereby improving the flatness of the pixel electrode layer PIX.

[0144] See Figure 15-16 This is a structural diagram of another array substrate provided by an embodiment of the present invention. The conductive layer may also be the electrode layer 8. In this case, the conductive structure 9 is provided on the same layer as the electrode layer 8.

[0145] A third through hole H3 is provided at a position corresponding to the first through hole H1, which penetrates at least the protective layer 7. As shown in FIG15 , when the gate insulating layer 5 is patterned with the gate layer 6 as a hard mask, the third through hole H3 penetrates the protective layer 7. Figure 16 When the gate insulating layer 5 is not patterned, the third through hole H3 penetrates the gate insulating layer 5 and the protective layer 7. The overlapping portion 41a of the first conductor portion 41 overlaps the signal line 2 located within the third through hole H3; the conductive structure 9 electrically connects the signal line 2 and the upper surface of the overlapping portion 41a within the third through hole H3.

[0146] like Figure 15 and Figure 16 As shown, the electrode layer 8 only includes the common electrode layer COM, and the conductive layer is the common electrode layer COM; the second conductor portion 43 is reused as the pixel electrode P, and the protective layer 7 is the first insulating layer PVX1.

[0147] When the electrode layer 8 includes a common electrode layer COM and a pixel electrode layer PIX, the conductive layer is one of the common electrode layer COM and the pixel electrode layer PIX; taking the electrode layer 8 including the common electrode layer COM and the pixel electrode layer PIX as an example, Figure 17 and Figure 18 FIG2 is a structural diagram of another array substrate provided by an embodiment of the present invention, wherein the conductive layer is the common electrode layer COM, and the conductive structure 9 is provided on the same layer as the common electrode layer COM; Figure 17 The middle gate insulating layer 5 is patterned using the gate layer 6 as a hard mask. The orthographic projection of the third through hole H3 on the base substrate 1 is located within the orthographic projection of the first through hole H1 on the base substrate 1 . The third through hole H3 penetrates the protective layer 7 . Figure 18 The middle gate insulating layer 5 is not patterned, the third through hole H3 overlaps the first through hole H1, and the third through hole H3 is closer to the semiconductor portion 42 than the first through hole H1, and the third through hole H3 passes through the protective layer 7 and the gate insulating layer 5. Figure 19 and Figure 20 FIG2 is a schematic structural diagram of another array substrate provided by an embodiment of the present invention, wherein the conductive layer is the pixel electrode layer PIX, the conductive structure 9 is provided on the same layer as the pixel electrode layer PIX, and the third through hole H3 also penetrates the second insulating layer PVX2; Figure 19 The middle gate insulating layer 5 is patterned using the gate layer 6 as a hard mask, and the third through hole H3 penetrates the protective layer 7 and the second insulating layer PVX2, so that the signal line 2 and the overlapping portion 41a are in direct contact with the conductive structure 9 in the third through hole H3; Figure 20 The middle gate insulating layer 5 is not patterned, and the third through hole H3 penetrates the gate insulating layer 5, the protective layer 7 and the second insulating layer PVX2, so that the signal line 2 and the overlapping portion 41a are in direct contact with the conductive structure 9 at the third through hole H3.

[0148] Please continue to see Figures 17-20 , protective layer 7, comprising:

[0149] The first insulating layer PVX1 is located on a side of the gate layer 6 away from the substrate 1;

[0150] The resin layer Resin is located between the first insulating layer PVX1 and the common electrode layer COM.

[0151] In the embodiment provided by the present invention, when the electrode layer 8 includes a pixel electrode layer PIX and a common electrode layer COM, by setting the protective layer 7 to a film layer composed of a first insulating layer PVX1 and a resin layer Resin, the distance between the pixel electrode P and the gate layer 6 can be increased, thereby reducing the generation of parasitic capacitance.

[0152] Based on the same inventive concept, an embodiment of the present invention provides a flowchart of a method for manufacturing an array substrate, see Figure 21A flowchart of a method for manufacturing an array substrate provided in an embodiment of the present invention, the method comprising:

[0153] S21: providing a substrate;

[0154] S22: A signal line, a buffer layer, an active layer, a gate insulating layer, a gate layer, a protective layer and an electrode layer are formed on one side of the base substrate; wherein the buffer layer has a first through hole penetrating the buffer layer, and the signal line overlaps with the first through hole; the active layer is divided into a continuous first conductor portion, a semiconductor portion and a second conductor portion, and an end of the first conductor portion away from the semiconductor portion has an overlapping portion, the overlapping portion is located within the orthographic projection of the first through hole on the base substrate, and overlaps with the signal line located at the bottom of the first through hole; the array substrate also includes a conductive structure, which is arranged on the same layer as any conductive layer located on the side of the active layer away from the base substrate, the conductive structure overlaps with the first through hole, and the conductive structure is electrically connected to the signal line and the upper surface of the overlapping portion at least within the first through hole.

[0155] See Figure 22 A schematic diagram of manufacturing an array substrate provided by an embodiment of the present invention, taking the conductive layer as a gate layer as an example, in which the conductive structure and the gate layer are provided on the same layer:

[0156] S31 : depositing a source-drain electrode layer on one side of the base substrate 1 , and patterning the source-drain electrode layer to obtain a signal line 2 .

[0157] If a light shielding structure 2z is also provided on the source and drain electrode layer, the signal line 2 and the light shielding structure 2z will be obtained simultaneously after the source and drain electrode layer is patterned. The signal line 2 may be a data line.

[0158] S32: depositing a buffer layer 3 on a side of the signal line 2 away from the base substrate 1, and etching the buffer layer 3 at a position corresponding to the data line to obtain a first through hole H1 penetrating the buffer layer 3, so that the signal line 2 overlaps with the first through hole H1.

[0159] S33: forming an active layer 4, a gate insulating layer 5 and a gate layer 6 on a side of the buffer layer 3 away from the substrate 1;

[0160] The structures of the active layer 4 , the gate insulating layer 5 and the gate layer 6 can be found in the above description of the array substrate, and will not be described in detail here.

[0161] S34 : forming a protection layer 7 and an electrode layer 8 in sequence on a side of the gate layer 6 away from the base substrate 1 .

[0162] The electrode layer 8 may include a common electrode layer COM, or a common electrode layer COM and a pixel electrode layer PIX; when the electrode layer 8 includes the common electrode layer COM, the protective layer 7 is a first insulating layer PVX1; when the electrode layer 8 includes the common electrode layer COM and the pixel electrode layer PIX, the protective layer 7 includes a first insulating layer PVX1 and a resin layer Resin located on the first insulating layer PVX1 away from the base substrate 1.

[0163] In the embodiment provided by the present invention, a first through hole H1 exposing the signal line 2 is formed in the buffer layer 3, the overlapping portion 41a in the active layer 4 overlaps a portion of the signal line 2 in the first through hole H1, and a conductive structure 9 arranged in the same layer as the gate layer 6 or the electrode layer 8 is used in the first through hole H1 to electrically connect the overlapping portion 41a and the upper surface of the signal line 2, thereby improving the conductivity of the active layer 4 and the signal line 2 and the pixel aperture ratio of the array substrate.

[0164] In some embodiments, the active layer, the gate insulating layer, and the gate layer may be formed by the following methods:

[0165] An original active layer is formed on a side of the buffer layer away from the substrate; one end of the original active layer extends to the bottom of the first through hole and is deposited on the surface of the portion of the signal line exposed in the first through hole;

[0166] forming a gate insulating layer and a gate layer in sequence on a side of the original active layer away from the substrate;

[0167] The original active layer is semiconductorized to obtain an active layer.

[0168] See Figure 23 A schematic diagram of forming an active layer provided in an embodiment of the present invention, taking the conductive structure and the gate layer as an example:

[0169] S331: forming an original active layer 04 on a side of the buffer layer 3 away from the base substrate 1; one end of the original active layer 04 extends to the bottom of the first through hole H1 and is deposited on the surface of a portion of the signal line 2 in the first through hole H1;

[0170] S332: depositing an original gate insulating layer 05 on a side of the original active layer 04 away from the substrate 1;

[0171] S333: etching the original gate insulating layer 05 at a position corresponding to the first through hole H1 to obtain a fifth through hole H5 penetrating the original gate insulating layer 05, so that a portion of the original active layer 04 covering the first through hole H1 overlaps with the fifth through hole H5;

[0172] Since plasma dry etching is used when etching the original insulating layer to form the fifth through hole H5 , the active layer 4 in the fifth through hole H5 is conductive. The conductive portion is indicated by denser dot filling in the figure.

[0173] S334: depositing an original gate layer 06 on a side of the original gate insulating layer 05 away from the substrate 1;

[0174] S335: Patterning the original gate layer 06 to obtain a gate layer 6 and a conductive structure 9;

[0175] S336: patterning the original gate insulating layer 05 using the gate layer 6 as a hard mask to obtain a gate insulating layer 5;

[0176] S337: Conducting the original active layer 04 to obtain an active layer 4 including a first conductor portion 41 , a semiconductor portion 42 and a second conductor portion 43 ; wherein the portion of the first conductor portion 41 overlapping the surface of the signal line 2 serves as an overlapping portion 41 a .

[0177] Since the gate insulating layer 5 is obtained by patterning the original gate insulating layer 05 with the gate layer 6 as a hard mask, the first conductor portion 41 and the second conductor portion 43 are not covered by the gate insulating layer 5. Therefore, the first conductor portion 41 and the second conductor portion 43 can be conductively converted by ion doping or plasma diffusion.

[0178] In another embodiment, the conductive layer is a gate layer, the conductive structure and the gate layer are provided in the same layer, and a gate insulating layer and a gate layer are sequentially formed on a side of the original active layer away from the substrate. This can also be achieved by the following methods:

[0179] Depositing an original gate insulating layer on a side of the original active layer away from the substrate;

[0180] Etching the original gate insulating layer at a position corresponding to the first through hole to obtain a second through hole penetrating the original gate insulating layer, wherein the second through hole overlaps with the first through hole, and the signal line and the overlapping portion are located in the region where the second through hole overlaps with the first through hole; wherein the original gate insulating layer having the second through hole serves as the gate insulating layer;

[0181] Depositing an original gate layer on a side of the gate insulating layer away from the substrate;

[0182] The original gate layer is patterned to obtain the gate layer and a conductive structure covering the overlapping area of ​​the second through hole and the first through hole.

[0183] See Figure 24 A schematic diagram of forming a gate insulating layer and a gate layer provided in an embodiment of the present invention.

[0184] S331-S335 and Figure 23 The steps are the same and will not be repeated here.

[0185] S336 ′: Conducting the original active layer 04 to obtain an active layer 4 including a first conductor portion 41 , a semiconductor portion 42 and a second conductor portion 43 ; wherein the portion of the first conductor portion 41 overlapping the surface of the signal line 2 serves as an overlapping portion 41 a .

[0186] Since the gate insulating layer 5 is not patterned, most of the original active layer 04 is covered by the gate insulating layer 5 , so the active layer 4 can be semiconductorized by hydrogen ion diffusion.

[0187] In some embodiments, the conductive layer is a common electrode layer, and the formation of the protective layer and the electrode layer can be achieved by the following methods:

[0188] After the original active layer is semiconductorized, a protective layer is formed on the side of the gate layer away from the substrate;

[0189] At a position corresponding to the first through hole, at least the protective layer is etched to obtain a third through hole that at least penetrates the protective layer, so that the signal line and the overlapping portion are located in the third through hole;

[0190] A common electrode layer and a conductive structure are formed on a side of the protection layer away from the base substrate.

[0191] See Figure 25 A schematic diagram of forming a common electrode layer and a conductive structure is provided for an embodiment of the present invention.

[0192] S41: After the original active layer 04 is semiconductorized, a protective layer 7 is deposited on the side of the gate layer 6 away from the base substrate 1;

[0193] Figure 25 Since the second conductor portion 43 is reused as the pixel electrode P, the protection layer 7 is composed of the first insulating layer PVX1.

[0194] S42: etching the protective layer 7 at a position corresponding to the first through hole H1 to obtain a third through hole H3 penetrating the protective layer 7, so that the signal line 2 and the overlapping portion 41a are exposed in the third through hole H3;

[0195] S43: depositing an ITO layer on the side of the protective layer 7 away from the base substrate 1;

[0196] S44: patterning the ITO layer to obtain a common electrode layer COM and a conductive structure 9 overlapping the third through hole H3.

[0197] If the electrode layer 8 includes a pixel electrode layer PIX and a common electrode layer COM, and the common electrode layer COM and the conductive structure 9 are provided in the same layer, the common electrode layer COM and the conductive structure 9 are formed in the same manner as described above and will not be described again.

[0198] In other embodiments, the conductive structure and the pixel electrode are disposed in the same layer to form a protective layer and an electrode layer, which can be achieved by the following methods:

[0199] After the original active layer is semiconductorized, a protective layer, a common electrode layer, and a second insulating layer are sequentially formed on the side of the gate layer away from the substrate;

[0200] At a position corresponding to the first through hole, at least the protective layer and the second insulating layer are etched to obtain a third through hole that penetrates at least the protective layer and the second insulating layer, so that the signal line and the overlapping portion are located in the third through hole;

[0201] A pixel electrode layer and a conductive structure are formed on a side of the second insulating layer away from the base substrate.

[0202] See Figure 26 A schematic diagram of forming a pixel electrode layer and a conductive structure provided by an embodiment of the present invention.

[0203] S51: After the original active layer 04 is semiconductorized, a protective layer 7, a common electrode layer COM and a second insulating layer PVX2 are sequentially formed on the side of the gate layer 6 away from the base substrate 1;

[0204] S52: Etching the protective layer 7 and the second insulating layer PVX2 at a position corresponding to the first through hole H1 and a position corresponding to the second conductor portion 43 to obtain a third through hole H3 overlapping with the first through hole H1 and a fourth through hole H4 overlapping with the second conductor portion 43. The signal line 2 and the connector 42 are located in the third through hole H3.

[0205] S53: depositing an ITO layer on a side of the second insulating layer PVX2 away from the substrate 1;

[0206] S54: patterning the ITO layer to obtain a pixel electrode layer PIX and a conductive structure 9 covering the third through hole H3.

[0207] Based on the same inventive concept, an embodiment of the present invention provides a display panel, including:

[0208] The color filter substrate and the array substrate as described above are arranged opposite to each other; the structure of the array substrate can be found in the description of the array substrate side, which will not be repeated here.

[0209] The liquid crystal layer is located between the color filter substrate and the array substrate.

[0210] Based on the same inventive concept, an embodiment of the present invention provides a display device, which includes the display panel as described above.

[0211] The display device may be a liquid crystal display, a liquid crystal display screen, a liquid crystal television or other display device, or may be a mobile device such as a mobile phone, a tablet computer, or a notebook.

[0212] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0213] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. An array substrate, characterized in that: include: A base substrate, and a signal line, a buffer layer, an active layer, a gate insulating layer, a gate layer, a protective layer, and an electrode layer on the base substrate; the buffer layer has a first through hole extending through the buffer layer, and the signal line overlaps the first through hole; the active layer is divided into a continuous first conductor portion, a semiconductor portion, and a second conductor portion; an end of the first conductor portion away from the semiconductor portion has an overlapping portion, the overlapping portion having an orthographic projection of the base substrate located within the orthographic projection of the first through hole on the base substrate, and overlapping the signal line located at the bottom of the first through hole; A conductive structure is arranged in the same layer as any conductive layer located on the side of the active layer away from the base substrate; the conductive structure overlaps with the first through hole, and the conductive structure electrically connects the signal line and the upper surface of the overlapping portion at least in the first through hole.

2. The array substrate according to claim 1, wherein: The conductive layer is the gate layer; The gate insulating layer includes a residual structure covering a sidewall of the first through hole portion, wherein the residual structure does not overlap with the first conductor portion; The conductive structure includes a first portion, a second portion, and a third portion that are continuously arranged; the first portion is in direct contact with the residual structure, the second portion is in direct contact with the signal line in the first through hole, and the third portion is in direct contact with the first conductor portion; wherein the third portion overlaps with a portion of the first conductor portion in the first through hole, and overlaps with a portion of the first conductor portion outside the first through hole and on a side of the buffer layer away from the base substrate.

3. The array substrate according to claim 1, wherein: The conductive layer is the gate layer; The gate insulating layer has a second through hole extending through the gate insulating layer, the second through hole overlapping the first through hole, the conductive structure electrically connecting the signal line and the first conductor portion in a region where the first through hole and the second through hole overlap; the signal line overlaps the second through hole; The overlapping portion and the signal line partially overlap in the second through hole; the conductive structure electrically connects the signal line and the upper surface of the overlapping portion in the second through hole.

4. The array substrate according to claim 1, wherein: The conductive layer is located on the electrode layer; A third through hole is provided at a position corresponding to the first through hole, at least penetrating the protective layer; the overlapping portion is overlapped on the signal line located in the third through hole; and the conductive structure electrically connects the signal line and the upper surface of the overlapping portion in the third through hole.

5. The array substrate according to claim 4, wherein: The orthographic projection of the third through hole on the base substrate is located within the orthographic projection of the first through hole on the base substrate, and the third through hole passes through the protective layer; Alternatively, the third through hole overlaps with the first through hole, and the third through hole is closer to the semiconductor portion than the first through hole, and the third through hole passes through the gate insulating layer and the protection layer.

6. The array substrate according to any one of claims 1 to 5, wherein: The second conductor portion is multiplexed as a pixel electrode, the conductive layer is a common electrode layer, and the protective layer is a first insulating layer.

7. The array substrate according to claim 4 or 5, wherein: The electrode layer comprises: a common electrode layer, located on a side of the protective layer away from the base substrate; a second insulating layer, located on a side of the common electrode layer away from the base substrate; A pixel electrode layer is located on a side of the second insulating layer away from the base substrate; the pixel electrode layer includes a pixel electrode, and has a fourth through hole penetrating the protective layer and the second insulating layer at a position corresponding to the second conductor portion, the pixel electrode extends into the fourth through hole and is electrically connected to the second conductor portion; the pixel electrode does not overlap with the common electrode layer.

8. The array substrate according to claim 7, wherein: The protective layer comprises: a first insulating layer, located on a side of the gate layer away from the substrate; The resin layer is located between the first insulating layer and the common electrode layer.

9. The array substrate according to claim 7, wherein: The conductive layer is the pixel electrode layer, and the third through hole also passes through the second insulating layer; Alternatively, the conductive layer is the common electrode layer.

10. The array substrate according to any one of claims 1 to 5, wherein: The array substrate further includes a light shielding structure provided on the same layer as the signal line; The orthographic projection of the semiconductor portion on the base substrate is located within the orthographic projection of the light shielding structure on the base substrate.

11. The array substrate according to any one of claims 1 to 5, wherein: The signal line includes: Data cable; The active layer is a metal oxide semiconductor.

12. A method for manufacturing an array substrate, characterized in that: include: providing a substrate; A signal line, a buffer layer, an active layer, a gate insulating layer, a gate layer, a protective layer and an electrode layer are formed on one side of the base substrate; wherein the buffer layer has a first through hole penetrating the buffer layer, and the signal line overlaps with the first through hole; the active layer is divided into a continuous first conductor portion, a semiconductor portion and a second conductor portion, and the first conductor portion has an overlapping portion at one end away from the semiconductor portion, the overlapping portion is located within the orthographic projection of the first through hole on the base substrate, and overlaps with the signal line located at the bottom of the first through hole; the array substrate also includes a conductive structure, which is arranged on the same layer as any conductive layer located on the side of the active layer away from the base substrate, the conductive structure overlaps with the first through hole, and the conductive structure electrically connects the signal line and the upper surface of the overlapping portion at least within the first through hole.

13. A display panel, characterized in that: include: A color filter substrate and an array substrate according to any one of claims 1 to 11, which are arranged opposite to each other; The liquid crystal layer is located between the color filter substrate and the array substrate.

14. A display device, characterized in that: Comprising the display panel as claimed in claim 13.

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