Multi-chip integrated photoelectric sensor and manufacturing method thereof, ft test method

Abstract

This invention discloses a multi-chip integrated photoelectric sensor and its manufacturing method and FT testing method, belonging to the field of integrated circuit technology. The multi-chip integrated photoelectric sensor includes an image sensor chip with a photosensitive area and an edge area on its front side. A light-transmitting component is disposed on the photosensitive area to filter out interference light, and multiple front-side pads are provided in the edge area for electrical signal transmission. A light source chip has a light-emitting area on its top and a first bottom pad and a second bottom pad on its bottom, which are respectively connected to the two front-side pads of the image sensor chip. An RDL (Reconstructed Distribution Layer) wiring layer penetrates the image sensor chip to transmit electrical signals from the front side to the back side. By directly chip-bonding the light source chip to the surface of the CMOS image sensor, the size of the product in the X, Y, and Z directions is greatly reduced, meeting the size requirements of end products.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a multi-chip integrated photoelectric sensor and its manufacturing method and FT test method. Background Technology

[0002] Multi-chip integrated optical sensors, in addition to a CIS (CMOS Image Sensor) image sensor, also integrate a light-emitting source chip. Typically, such multi-chip integrated optical sensors use a PCB substrate as the carrier board. Both the CIS chip and the light-emitting source chip are mounted on the PCB substrate via die bonding, and the pads of the CIS chip and the light-emitting source chip are connected to the pads of the PCB substrate using a wire bonding process. Figure 1 The existing photoelectric sensor 100 shown has the following limitations in its packaging:

[0003] Since the PCB substrate 102 is used as a carrier board with a certain thickness in the Z direction, and the carrier board requires metal plate making and protective layer, and the warpage of the carrier board needs to be considered to facilitate the high yield and stability of the packaging process mass production, the carrier board must have a certain thickness to support it.

[0004] The Y direction is perpendicular to the paper surface. The PCB substrate 102 needs to consider the size of the light source chip 108, the size of the CIS chip 106, the wire bond 104 bonding space, and the support of the optical packaging cover plate 103 in the X and Y directions.

[0005] Furthermore, the light source chip 108 and the CIS chip 106 are mostly standardized products, and can only be packaged and integrated using the PCB substrate 102 as a carrier, which makes further miniaturization impossible.

[0006] Figure 1 The provided packaging solution uses PCB substrate 102 as the carrier board. After packaging, due to the varying degrees of warping of the entire board, FT (Final Test) testing usually involves first cutting the entire board into individual products, and then placing the individual products into the test socket for testing, which results in relatively low testing efficiency.

[0007] It should be noted that the information disclosed in the background section of this invention is intended only to enhance the understanding of the general background of this invention, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0008] The purpose of this invention is to provide a multi-chip integrated photoelectric sensor and its manufacturing method and FT testing method, so as to solve the problem that multi-chip integrated optical sensors cannot meet the miniaturization requirements.

[0009] To address the aforementioned technical problems, this invention provides a multi-chip integrated photoelectric sensor, comprising:

[0010] An image sensor chip has a photosensitive area and an edge area on its front side. A light-transmitting component is provided on the photosensitive area to filter out interference light. The edge area is provided with multiple front pads, including a first front pad and a second front pad, for connection to the bottom pad of the light source chip.

[0011] A light source chip, wherein a light-emitting area is provided on the top of the light source chip and a first bottom pad and a second bottom pad are provided on the bottom, for communicating with the first front pad and the second front pad of the image sensor respectively;

[0012] The RDL reconstructed wiring layer extends through the image sensor chip to transmit electrical signals from the front pads of the image sensor chip to the back.

[0013] A cover plate structure is disposed on the edge area to protect the front side of the image sensor chip.

[0014] Preferably, the surface of the first bottom pad is connected to the surface of the first front pad of the image sensor chip, the surface of the second bottom pad is connected to the surface of the second front pad of the image sensor chip, and the second front pad exports electrical signals to the back side of the image sensor chip through TSV (Through Silicon Via) technology, and a BGA / LGA pad is formed on the back side of the image sensor chip.

[0015] Preferably, the RDL reconstructed wiring layer is connected to the BGA / LGA pad at one end on the back of the image sensor chip, and an internal insulating layer is provided between the RDL reconstructed wiring layer and the image sensor chip, and a surface insulating layer is also provided on the end of the RDL reconstructed wiring layer on the back of the image sensor chip.

[0016] Preferably, the light-transmitting component is a filter or a lens, and the cover plate structure is a plurality of columns disposed on the edge area.

[0017] Preferably, an organic film is attached to the BGA / LGA pads.

[0018] A method for manufacturing a multi-chip integrated photoelectric sensor includes the following steps:

[0019] An image sensor chip and a light source chip are provided. The front side of the image sensor chip has a photosensitive area and an edge area. The edge area is provided with a plurality of front pads. The front pads include a first front pad, a second front pad, and other front pads for the connection of electrical signals. The top of the light source chip is provided with a light-emitting area, and the bottom has a first bottom pad and a second bottom pad.

[0020] The first and second front pads of the image sensor chip are connected to the first and second bottom pads of the light source chip to form an electrical signal connection between the two chips.

[0021] A light-transmitting component is provided on the photosensitive area to filter out interfering light;

[0022] A substrate is provided, the substrate is etched to form an opening that is adapted to the photosensitive area and the light source chip, and the side of the substrate with the opening is pressed against the front side of the image sensor chip to form a cover plate structure.

[0023] Thin the back side of the image sensor chip to the required thickness;

[0024] Using the TSV process, an RDL reconstruction wiring layer is formed in the image sensor chip to transmit electrical signals from the front side of the image sensor chip to the back side.

[0025] Preferably, the edge region is provided with a first front pad, a second front pad, and other metal layer pads. The first bottom pad, the second bottom pad, and the first front pad and the second front pad of the image sensor chip are connected to each other using Ag Paste (silver paste), ACA / ACP (anisotropic conductive adhesive), or ACF (anisotropic conductive film) through chip bonding process or SMT assembly, followed by reflow soldering process.

[0026] Preferably, setting a light-transmitting component on the photosensitive area includes: setting a filter on the photosensitive area by a chip bonding process, or fabricating a lens on the photosensitive area.

[0027] Preferably, forming the RDL reconstruction wiring layer in the image sensor chip using the TSV process includes:

[0028] Through-silicon vias are formed on the image sensor chip using photolithography and etching processes;

[0029] An internal insulating layer is formed within the through-silicon via and on the back side of the image sensor chip;

[0030] An RDL reconstructed wiring layer is formed within the through-silicon via using a physical vapor deposition process.

[0031] A surface insulating layer is then applied to the back of the image sensor chip.

[0032] Several BGA / LGA pads are formed on the back side of the image sensor chip using BGA / LGA technology.

[0033] A Fourier Transform (FT) test method for a multi-chip integrated photoelectric sensor, used to perform FT tests on the multi-chip integrated photoelectric sensor as described above, includes the following steps:

[0034] A wafer containing a packaged image sensor chip is provided, and the wafer is peeled off from an organic film;

[0035] The wafer is transferred to the carrier disk of the FT test platform, and the BGA / LGA pads of the packaged image sensor chip are made in contact with the test probes on the FT test platform. A multi-chip simultaneous measurement method can be adopted. The front side of the packaged image sensor chip is connected to the optical test calibration to test various parameters of the photoelectric sensor, such as communication, power consumption and performance.

[0036] The multi-chip integrated photoelectric sensor provided by this invention significantly reduces the size of the product in the X and Y directions by directly bonding the light source chip to the surface of the CMOS image sensor, thereby reducing the required planar area of ​​the product. Furthermore, because the use of a PCB substrate is eliminated, the size in the Z direction is also reduced accordingly, thus reducing the overall thickness of the product and meeting the size requirements of the end product.

[0037] The manufacturing method of the multi-chip integrated photoelectric sensor provided by this invention belongs to the same inventive concept as the multi-chip integrated photoelectric sensor provided by this invention. Therefore, the manufacturing method of the multi-chip integrated photoelectric sensor provided by this invention has at least all the advantages of the multi-chip integrated photoelectric sensor provided by this invention, which will not be repeated here.

[0038] The FT testing method for the multi-chip integrated photoelectric sensor provided by this invention belongs to the same inventive concept as the multi-chip integrated photoelectric sensor provided by this invention. Therefore, the FT testing method for the multi-chip integrated photoelectric sensor provided by this invention has at least all the advantages of the multi-chip integrated photoelectric sensor provided by this invention, which will not be repeated here. For the integrated structure of the above-mentioned image sensor chip, FT testing can be performed using a wafer-level testing method, which is similar to Chip Probing (CP) testing after wafer fabrication, avoiding PCB substrate warping and greatly improving testing efficiency. Attached Figure Description

[0039] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:

[0040] Figure 1 This is a schematic diagram of the structure of a photoelectric sensor in the prior art;

[0041] Figure 2 This is a schematic diagram of the photoelectric sensor structure according to Embodiment 1 of the present invention;

[0042] Figure 3 This is a schematic diagram of the structure of Embodiment 2 of the present invention;

[0043] Figure 4 This is a schematic diagram of the structure of Embodiment 3 of the present invention;

[0044] Figure 5 This is a schematic diagram of the structure of Embodiment 4 of the present invention;

[0045] Figure 6 This is a structural schematic diagram of Embodiment 5 of the present invention;

[0046] Figure 7 This is a schematic diagram of a wafer undergoing FT testing according to an embodiment of the present invention;

[0047] Figure 8 This is a process flow diagram of Embodiment 1 of the present invention.

[0048] Appendix Figure 1 middle:

[0049] 100. Existing photoelectric sensor; 101. Back pad of PCB substrate; 102. PCB substrate; 103. Encapsulation cover plate; 104. Wire bond; 105. CIS chip pad; 106. CIS chip; 107. Front pad of PCB substrate; 108. Light source chip.

[0050] Appendix Figures 2 to 8 middle:

[0051] 200, Wafer; 300, Carrier disk; 400, Packaged image sensor chip; 500, Test probe; 600, Optical test calibration.

[0052] 1. Image sensor chip; 2. Cover plate structure; 3. Light source chip; 4. Photosensitive area; 5. Other metal layer pads; 6. Light-emitting area; 7. First bottom pad; 8. Second bottom pad; 9. Conductive adhesive; 10. Filter or lens; 11. Internal insulating layer; 12. RDL reconstruction wiring layer; 13. Surface insulating layer; 14. BGA / LGA pads; 15. First front pad; 16. Second front pad; 17. Carrier; 18. Enclosed cavity; 19. Glass cover plate; 20. Barrier; 21. Lens; 22. Pattern glass; 23. First light-transmitting film; 24. Second light-transmitting film; 25. Light-transmitting glass. Detailed Implementation

[0053] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0054] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; the term “at least two” is generally used to mean “two or more”; furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined with "first," "second," and "third" may explicitly or implicitly include one or at least two of those features. The term "proximal" typically refers to the end closer to the operator, and the term "distal" typically refers to the end closer to the patient. "One end" and "the other end," as well as "proximal" and "distal," generally refer to two corresponding parts, including not only endpoints. The terms "installed," "connected," and "linked" should be interpreted broadly. For example, they can be fixed connections, detachable connections, or integral connections; they can be mechanical connections or electrical connections; they can be direct connections or indirect connections through an intermediate medium; they can be internal connections between two elements or interactions between two elements. Furthermore, as used in this invention, the placement of one element on another element generally only indicates a connection, coupling, cooperation, or transmission relationship between the two elements, and the connection, coupling, cooperation, or transmission between the two elements can be direct or indirect through an intermediate element. It should not be construed as indicating or implying a spatial positional relationship between the two elements, i.e., one element can be located arbitrarily inside, outside, above, below, or to one side of another element, unless otherwise explicitly stated. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0055] Research has found that the rapid iteration and upgrading of terminal products, including mobile phones, smartwatches, smart bracelets, smart furniture, and IoT (Internet of Things) products, are pushing for extreme miniaturization. Packaging processes that use PCB substrates as carriers can no longer meet the demand for extreme miniaturization in terms of space.

[0056] To meet the needs of end customers, this invention directly dies the light source chip onto the surface of the CMOS image sensor chip, and adopts a wafer-level packaging method, which can significantly reduce the size of the product in the X and Y directions. Furthermore, by eliminating the use of a PCB substrate, the size in the Z direction is also reduced accordingly. In addition, wafer-level testing methods are used for FT testing, similar to chip probing (CP) testing after wafer fabrication, greatly improving testing efficiency.

[0057] Furthermore, based on this packaging method of directly bonding the light source chip to the surface of the CMOS image sensor chip, the present invention provides photoelectric sensors with various cover plate structures, which can select different cover plate structures according to the usage scenario of the terminal product, so that the photoelectric sensor has better performance and usage effect.

[0058] Example 1

[0059] For details, please refer to Figures 2-8 This is a schematic diagram of an embodiment of the present invention. Figure 2 As shown, a multi-chip integrated photoelectric sensor includes:

[0060] Image sensor chip 1, the front side of the image sensor chip 1 has a photosensitive area 4 and an edge area (not labeled), the photosensitive area 4 is provided with a light-transmitting component for filtering out interference light, the edge area is provided with a plurality of front pads, including a first front pad 15 and a second front pad 16, as well as other metal layer pads 5, for electrical signal transmission;

[0061] The light source chip 3 has a light-emitting area 6 on its top and a first bottom pad 7 and a second bottom pad 8 on its bottom, which are respectively connected to the two front pads of the image sensor chip 1. More preferably, the first bottom pad 7 and the second bottom pad 8 are respectively connected to the first front pad 15 and the second front pad 16.

[0062] RDL reconstructed wiring layer 12 extends through the image sensor chip 1 to transmit electrical signals from the front pads of the image sensor chip 1 to the back.

[0063] The cover structure 2 is disposed on the edge area to protect the front side of the image sensor chip 1.

[0064] The light source chip 3 is integrated onto the surface of the CMOS image sensor chip 1. To enable the light source chip 3 to be die-bonded onto the surface of the CMOS image sensor chip 1, the CMOS image sensor chip 1 is customized, and corresponding die-bonding positions for the light source chip 3 are reserved. More specifically, a first front-side pad 15 and a second front-side pad 16 are provided on the image sensor chip 1 for bonding with the light source chip 3. An RDL reconstruction wiring layer 12 is provided for signal transmission. A light-transmitting component is provided to protect and cover the photosensitive area 4 of the image sensor chip 1. The cover plate structure 2 protects the entire front side of the image sensor chip 1, and the cover plate structure 2 can also serve as a carrier for implementing the back-side process of the image sensor chip 1.

[0065] Correspondingly, the bottom of the light source chip 3 is provided with a first bottom pad 7 and a second bottom pad 8. The surface of the first bottom pad 7 is connected to the surface of the first front pad 15 of the image sensor chip 1, and the surface of the second bottom pad 8 is connected to the surface of the second front pad 16 of the image sensor chip 1. The second front pad 16 conducts electrical signals to the back side of the image sensor chip 1 through TSV (Through Silicon Via) technology. A BGA / LGA pad 14 is formed on the back side of the image sensor chip 1.

[0066] The light source chip 3 adopts a design with positive and negative pads on the same side and the light-emitting area 6 on the other side. The first bottom pad 7 and the second bottom pad 8 serve as the positive and negative pads of the light source chip 3. An area is reserved around the edge of the photosensitive area 4 of the image sensor chip 1 for supporting the cover structure 2. An area is reserved on one side of the photosensitive area 4 to place the light source chip 3, and a first front pad 15 and a second front pad 16 are provided in this area to connect the first bottom pad 7 and the second bottom pad 8. More preferably, conductive adhesive 9 is also provided between the first bottom pad 7 and the first front pad 15, and between the second bottom pad 8 and the second front pad 16. Ag Paste (silver paste) / ACA / ACP (anisotropic conductive adhesive) or ACF (anisotropic conductive film) materials are used as the conductive adhesive 9.

[0067] The RDL reconstructed wiring layer 12 is located on the back side of the image sensor chip 1 and is connected to a BGA / LGA pad 14. An internal insulating layer 11 is also provided between the RDL reconstructed wiring layer 12 and the image sensor chip 1. A surface insulating layer 13 covers the back side of the RDL reconstructed wiring layer 12. The BGA / LGA pad 14 is manufactured using BGA or LGA technology and has an organic film attached to it. By redistributing the input / output (I / O) pad contact positions of the chip through the RDL reconstructed wiring layer 12, critical signal paths are shortened.

[0068] Through Silicon Via (TSV) technology, the pads connecting the positive (or negative) electrode of the light source chip 3, as well as other required pads of the image sensor chip 1, are connected to the back side of the wafer of the image sensor chip 1. For example... Figure 2 The other metal layer pads 5 on the front of the image sensor chip 1 are connected to the BGA / LGA pads 14 through the RDL reconstructed wiring layer 12. Similarly, the chip front pads connected to the pads at the bottom of the light source chip 3 can also be connected to the BGA / LGA pads 14 through the RDL reconstructed wiring layer 12.

[0069] When forming the RDL reconstructed wiring layer 12, a deep silicon via (TSV) is first formed through the image sensor chip 1 using TSV technology. An internal insulating layer 11 is then placed inside the via and on the back side of the image sensor chip 1. Next, metal material is arranged to form the RDL reconstructed wiring layer 12. Subsequently, a surface insulating layer 13 is formed on the back side of the image sensor chip 1. BGA (Ball Grid Array) or LGA (Land Grid Array) packages are used to create BGA / LGA pads 14, similar to PCB substrate packages. An organic film, such as a blue film or UV film, is then attached to the BGA / LGA pads 14 for front-side processes of the image sensor chip 1, such as etching to form the cover plate structure 2.

[0070] In one embodiment, the light-transmitting component is a filter or lens 10, for example, made of resin material, and the cover structure 2 is a plurality of pillars disposed on the edge region. The pillars are also conventionally used DAM (Dam and Fill) retaining walls.

[0071] Understandably, the light-transmitting component can also be other forms of light-transmitting structure to filter out interfering light of wavelengths other than the light source, such as light-transmitting dry films, glass, and other highly light-transmitting materials. The cover structure 2, in conjunction with the structure of the light-transmitting component, can be a column structure or other forms of structure. This packaging method, which directly bonds the light source chip 3 to the surface of the CMOS image sensor chip, provides photoelectric sensors with various cover structure options. Different cover structures can be selected according to the usage scenario of the end product, enabling the photoelectric sensor to have better performance and usage effect.

[0072] Based on the same technical concept, this embodiment also provides a manufacturing method for a multi-chip integrated photoelectric sensor. It employs a wafer-level packaging process, customizing the image sensor chip 1, integrating the light source chip 3 onto the surface of the CIS image sensor chip 1, leaving space for the die bond of the light source chip 3, reducing the required planar area of ​​the product, and eliminating the need for a PCB substrate, thus reducing the overall product thickness and meeting the size requirements of the end product. (See...) Figure 8 Specifically, it includes the following steps:

[0073] S1, an image sensor chip 1 and a light source chip 3 are provided. The front side of the image sensor chip 1 has a photosensitive area 4 and an edge area. The edge area is provided with a plurality of front pads, including a first front pad 15 and a second front pad 16, as well as other metal layer pads 5. The top of the light source chip 3 is provided with a light-emitting area 6, and the bottom is provided with a first bottom pad 7 and a second bottom pad 8.

[0074] The position of the photosensitive area 4 of the image sensor chip 1 is determined, and the edge area is reserved for the support of the encapsulation cover structure 2. On the other side of the horizontal position of the photosensitive area 4, an area is reserved to place the light source chip 3. Two pads are designed on the surface of the image sensor chip 1, the first front pad 15 and the second front pad 16, which correspond to the positive and negative pads of the light source chip 3. The light source chip 3 adopts the form of positive and negative electrodes on the same side, that is, the first bottom pad 7 and the second bottom pad 8 are on the same side, and the light-emitting area 6 is designed on the other side.

[0075] S2, connect the two front pads of the image sensor chip 1 to the first bottom pad 7 and the second bottom pad 8 on the bottom of the light source chip 3 to form an electrical signal connection between the two chips. More preferably, connect the bottom of the light source chip 3 and the front of the image sensor chip 1 through the first front pad 15 and the second front pad 16.

[0076] On the wafer of image sensor chip 1 (usually an 8-inch or 12-inch wafer), the first step is to perform a die bond process for the light source chip 3. More preferably, Ag paste, ACA / ACP (anisotropic conductive adhesive), or ACF (anisotropic conductive film) materials are used to die bond the light source chip 3 to the wafer of image sensor chip 1, ensuring that each good chip (DIE) has a light source chip 3 mounted on it. Alternatively, SMT (Surface Mount Technology) and Reflow soldering processes can be used to mount the light source chip 3. During the die bond process, the first step is to apply an adhesive, including silver paste, ACA / ACP, or ACF, onto the image sensor chip 1. Then, the light source chip 3 is placed on top, or assembled using SMT. After assembly, it is reflow soldered through a tunnel called a temperature reflow tunnel, where the temperature can be adjusted over time to melt the adhesive or solder balls. Then, it is cooled to fix the light source chip 3 onto the image sensor chip 1.

[0077] Specifically, the edge region is provided with a first front pad 15, a second front pad 16 and other metal layer pads 5. Through chip bonding process or SMT assembly and then reflow soldering process, the first bottom pad 7, the second bottom pad 8 and the first front pad 15 and the second front pad 16 of the image sensor chip 1 are connected to each other. Conductive adhesive 9 is also provided between the first bottom pad 7 and the first front pad 15, the second bottom pad 8 and the second front pad 16.

[0078] S3, a light-transmitting component is provided on the photosensitive area 4 to filter out interfering light.

[0079] More preferably, setting a light-transmitting component on the photosensitive area 4 includes: setting a filter on the photosensitive area 4 by a chip bonding process, or fabricating a lens on the photosensitive area 4.

[0080] For example, in the photosensitive area 4 of the image sensor chip 1, a Die Bond filter or lens 10 is used to filter out interfering light of wavelengths other than the light source, or a lens made of resin or other materials is made. Resin lenses are usually made by molding. This step is optional depending on the product requirements.

[0081] S4, a carrier 17 is provided, the carrier 17 is etched to form an opening adapted to the photosensitive area 4 and the light source chip 3, and the side of the carrier 17 with the opening is pressed onto the front side of the image sensor chip 1 to form a cover structure 2.

[0082] Using a second silicon wafer of the same size as the image sensor chip 1, a DAM (Dam and Fill) barrier design is created through dry etching, exposing the light source chip 3 area and the photosensitive area 4. Sufficient process space is reserved to ensure that each image sensor chip 1 (DIE) on the wafer has the same DAM barrier design, similar to... Figure 2 In the middle cover structure 2, alignment marks need to be designed to ensure alignment for the subsequent bonding (interconnection) process.

[0083] The second silicon wafer and the wafer of the image sensor chip 1 are aligned and bonded using the alignment marks reserved in the previous step through a bonding bonding process, so that the cavity of the second silicon wafer coincides with the photosensitive area 4 and the light source chip 3 of the image sensor chip 1.

[0084] S5, thin the back side of the image sensor chip 1 to the required thickness. A second silicon wafer, acting as a carrier substrate, is used to grind the back side of the image sensor chip 1 wafer to the required thickness.

[0085] S6, using TSV technology, an RDL reconstruction wiring layer 12 is formed in the image sensor chip 1 to transmit electrical signals from the front side of the image sensor chip 1 to the back side. Through the TSV (Through Silicon Via) process, the pads connecting the positive (or negative) electrode of the light source chip 3 and other required pads of the image sensor chip 1 are connected to the back side of the wafer of the image sensor chip 1.

[0086] Specifically, forming the RDL reconstruction wiring layer 12 in the image sensor chip 1 using TSV technology includes:

[0087] Silicon vias are formed on the image sensor chip 1 using photolithography and etching processes. More preferably, silicon vias are formed using photolithography and dry etching processes.

[0088] An internal insulating layer 11 is formed inside the through-silicon via and on the back side of the image sensor chip 1. More preferably, a photolithography and curing process is used to form an internal insulating layer and a surface insulating layer 13 in the through-silicon via.

[0089] An RDL (Re-Distribution Layer) wiring layer 12 is formed within the via using a physical vapor deposition (PVD) process. The RDL wiring layer 12 is fabricated using PVD, photolithography, etching, and electroplating processes (the specific process requirements are determined based on the product characteristics). The RDL wiring layer 12 redistributes the positions of the chip's input / output (I / O) pads, shortening the paths of critical signals.

[0090] A surface insulating layer 13 is further covered on the back of the image sensor chip 1. More preferably, the surface insulating layer 13 is formed by photolithography and curing processes.

[0091] A plurality of BGA / LGA pads 14 are formed on the back side of the image sensor chip 1 using BGA / LGA technology. It is understood that by using BGA (Ball Grid Array) or LGA (Land Grid Array), it is possible to create BGA / LGA pads 14 in a form similar to that of a PCB substrate package.

[0092] Then, an organic film, such as a blue film / UV film, is attached to the surface of the BGA / LGA pad 14. The second silicon wafer is then ground and dry etched to create the DAM cover plate structure 2, exposing the light source chip 3 and the photosensitive area 4 of the image sensor chip 1.

[0093] By adopting a wafer-level packaging method, the light source chip is directly bonded to the surface of the CMOS image sensor chip, which greatly reduces the size of the product in the X and Y directions, reduces the size of the planar area required for the product, and reduces the size in the Z direction by eliminating the use of PCB substrate, thus reducing the overall thickness of the product and meeting the size requirements of the end product.

[0094] Based on the same technical concept, this embodiment also provides a FT testing method for a multi-chip integrated photoelectric sensor, such as... Figure 7 As shown, the steps for performing FT testing on a multi-chip integrated photoelectric sensor as described above include:

[0095] A wafer 200 containing a packaged image sensor chip 400 is provided, and the wafer 200 is peeled off from an organic film.

[0096] The wafer 200 is transferred to the carrier disk 300 of the FT test platform. The BGA / LGA pads 14 of the packaged image sensor chip 400 are made in contact with the test probes 500 on the FT test platform. The front side of the packaged image sensor chip 400 is connected to the optical test calibration 600 to test various parameters of the photoelectric sensor, including communication, power consumption and performance.

[0097] Specifically, the packaged wafer 200 is peeled off from the organic film. The blue film is peeled off, and the UV film is first deUVized and then peeled off. The wafer 200 is then transferred to the FT test platform and fixed using a ring contact method. Specifically, a retaining ring is used to fix the wafer 200 to the carrier tray 300 of the FT test equipment. The bottom BGA / LGA pads 14 of the packaged image sensor chip 400 contact the test probes 500 on the test platform. The test probes 500 are Pogo pins, which are spring-loaded probes formed by pre-pressing three basic components—a needle shaft, a spring, and a needle tube—using precision instruments. The surface of the packaged image sensor chip 400 (DIE) is connected to the optical test calibration 600. See [link to documentation]. Figure 7 This step tests various parameters of the product's communication, power consumption, and performance. It employs a wafer-level FT (Flat Test) scheme, similar to wafer-level CP (Chip Probing) testing, significantly improving testing efficiency. After testing, a Bin Mapping map of different bins on the wafer is generated. Additionally, ink dots can be applied to defective products. Alternatively, a traditional testing scheme can be used, performing FT testing after dicing the product into individual chips, but this is far less efficient than wafer-level FT.

[0098] After the Fourier Transform (FT) test is completed, an organic film (blue film / UV film) is applied to 200 wafers, which are then diced. Bins are removed according to the Bin Mapping diagram to obtain the tested, ultra-small packaged optical sensor product. For the integrated structure of the aforementioned image sensor chip, a wafer-level testing method can be used for FT testing. This method is similar to Chip Probing (CP) testing after wafer fabrication, avoiding PCB substrate warping and significantly improving testing efficiency.

[0099]

Example 2

[0100] Please refer to Figure 3 The present invention also provides another embodiment of a multi-chip integrated photoelectric sensor, which adopts a cover plate structure 2 different from that of Embodiment 1, and adopts a wafer-level packaged multi-chip integrated packaging structure, retaining the closed cavity 18. This structure still uses silicon material as the carrier 17 and retains the closed cavity 18. During manufacturing, the same process as the manufacturing steps of Embodiment 1 is adopted. An opening for placing the light-transmitting component and the light source chip 3 is made on another silicon wafer. The other silicon wafer is aligned and pressed onto the image sensor chip 1, and then the front-side process of the image sensor chip 1 is performed. When the carrier 17 is thinned in the subsequent process, the carrier 17 on the top of the light-transmitting component and the light source chip 3 is retained to form the closed cavity 18.

[0101] It should be noted that the wavelength of the light source needs to be greater than 1000nm to be sufficient to penetrate the silicon substrate 17 of a certain thickness. The test scheme and other manufacturing processes and FT test methods are the same as in Example 1, and will not be repeated here.

[0102]

Example 3

[0103] Please refer to Figure 4 The present invention also provides another embodiment of a multi-chip integrated photoelectric sensor, which adopts a cover plate structure 2 similar to that in embodiment two, still using a closed cavity 18. During manufacturing, a columnar DAM structure, i.e., a barrier wall 20, is formed, but a glass cover plate 19 is used. The glass cover plate 19 is made of high light transmittance glass, and the glass does not need to be ground. The DAM structure, i.e., the barrier wall 20, is made on the glass cover plate 19. The barrier wall 20 can be made of PCB, glass, or silicon wafer. PCB, glass, or silicon wafer has low transmittance to light sources, which plays the role of blocking light sources. The test scheme and other manufacturing processes and FT test methods of this embodiment are the same as those of embodiment one, and will not be repeated here.

[0104]

Example 4

[0105] Please refer to Figure 5 The present invention also provides another embodiment of a multi-chip integrated photoelectric sensor. Compared with the structure of the first embodiment, this embodiment uses high-transmittance glass instead of silicon wafers and does not use a DAM structure. The light-transmitting component adopts a composite structure of patterned glass 22, first light-transmitting film 23, and lens 21. The patterned glass 22 and the first light-transmitting film 23 have a certain thickness. After being cut, the light source chip 3 is exposed, which protects the image sensor chip 1.

[0106] The first light-transmitting film 23 is made of DAF (Die Attach Film) or dry film, the lens 21 is made of resin or glass, and the graphic glass 22 is made of high-transmittance glass with a graphic.

[0107] In this process, after the light source chip 3 is die-bonded to the image sensor chip 1 on the wafer, a glass wafer of the same size as the image sensor chip 1 is used. First, a high-transmittance DAF (Die Attach Film) film or dry film is attached to one side of the glass wafer. Then, the position of the light source chip 3 is processed (usually by laser cutting) to cut through the glass and DAF film / dry film at this position, so that after the glass wafer is bonded to the wafer of the image sensor chip 1, the light source chip 3 can be fully exposed. Considering the bonding accuracy and laser cutting accuracy, a certain amount of process space is reserved.

[0108] Similarly, the glass wafer is bonded to the wafer of the image sensor chip 1, and then a UV film is attached to the glass wafer. The glass wafer is used as a carrier to make TSV structure and LGA or BGA packaging. The process is the same as in Example 1.

[0109] If necessary, a lens 21 (made of glass or resin) can be attached to the photosensitive area 4 of the image sensor chip 1. A high-transmittance DAF film or dry film can be attached to the lens 21, and then wafer-level FT testing and wafer dicing can be performed. The testing scheme and other manufacturing processes and FT testing methods in this embodiment are the same as in Embodiment 1.

[0110] Example 5

[0111] Please refer to Figure 6 This invention also provides another embodiment of a multi-chip integrated photoelectric sensor. Compared to the structure of Embodiment 4, this embodiment does not use the Lens 21. Instead, a layer of high-transmittance transparent glass 25, the same size as the wafer, is bonded above the patterned glass 22 of Embodiment 4 as a cover plate to ensure the product's sealing and high reliability. The testing scheme and other manufacturing processes and FT testing methods of this embodiment are the same as those of Embodiment 1, and will not be repeated here.

[0112] Similarly, the first light-transmitting film 23 is a DAF (Die Attach Film) film or a dry film, the graphic glass 22 is a high-transmittance glass with a pattern, and a second light-transmitting film 24 is set above the graphic glass 22. The second light-transmitting film 24 is a DAF film or a dry film, and the top of the second light-transmitting film 24 is a light-transmitting glass 25, which is also a high-transmittance glass.

[0113] In the multi-chip integrated photoelectric sensor and its manufacturing method and FT testing method provided by this invention, a wafer-level packaging method is adopted, directly bonding the light source chip to the surface of the CMOS image sensor chip. This significantly reduces the size of the product in the X and Y directions, reduces the required planar area, and, because the use of a PCB substrate is eliminated, the size in the Z direction is also reduced accordingly, thus reducing the overall thickness of the product and meeting the size requirements of the end product. Furthermore, this packaging method of directly bonding the light source chip to the surface of the CMOS image sensor chip provides photoelectric sensors with various cover plate structures, allowing for the selection of different cover plate structures according to the application scenario of the end product, resulting in better performance and usability of the photoelectric sensor. In addition, for the integrated structure of the aforementioned image sensor chip, a wafer-level testing method can be used for FT testing, similar to Chip Probing (CP) testing after wafer fabrication, avoiding PCB substrate warping and greatly improving testing efficiency.

[0114] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.

Claims

1. A multi-chip integrated photoelectric sensor, characterized in that, include: An image sensor chip has a photosensitive area and an edge area on its front side. A light-transmitting component is provided on the photosensitive area to filter out interference light, and multiple front pads are provided on the edge area for electrical signal transmission. The light source chip has a light-emitting area on its top and a first bottom pad and a second bottom pad on its bottom, which are used to communicate with the two front pads of the image sensor chip respectively. The RDL reconstructed wiring layer extends through the image sensor chip to transmit electrical signals from the front pads of the image sensor chip to the back side. The RDL reconstructed wiring layer uses the TSV process to export the electrical signals to the back side of the image sensor chip. A cover plate structure is disposed on the edge area to protect the front side of the image sensor chip.

2. The multi-chip integrated photoelectric sensor according to claim 1, characterized in that, The surface of the first bottom pad is connected to the surface of the first front pad of the image sensor chip, the surface of the second bottom pad is connected to the surface of the second front pad of the image sensor chip, and the second front pad transmits electrical signals to the back of the image sensor chip through TSV process. BGA / LGA pads are formed on the back of the image sensor chip.

3. The multi-chip integrated photoelectric sensor according to claim 2, characterized in that, The RDL reconstructed wiring layer is located on the back side of the image sensor chip and is connected to the BGA / LGA pads. An internal insulating layer is provided between the RDL reconstructed wiring layer and the image sensor chip. A surface insulating layer is also provided on the back side of the RDL reconstructed wiring layer.

4. The multi-chip integrated photoelectric sensor according to claim 1, characterized in that, The light-transmitting component is a filter or lens, and the cover plate structure is a number of columns set on the edge area.

5. The multi-chip integrated photoelectric sensor according to claim 3, characterized in that, An organic film is attached to the BGA / LGA pads.

6. A method for manufacturing a multi-chip integrated photoelectric sensor, characterized in that, Includes the following steps: An image sensor chip and a light source chip are provided. The front side of the image sensor chip has a photosensitive area and an edge area. Multiple front pads are provided in the edge area. The top of the light source chip has a light-emitting area, and the bottom has a first bottom pad and a second bottom pad. The two front pads of the image sensor chip are connected to the first bottom pad and the second bottom pad of the light source chip to form an electrical signal connection between the two chips. A light-transmitting component is provided on the photosensitive area to filter out interfering light; A substrate is provided, the substrate is etched to form an opening that is adapted to the photosensitive area and the light source chip, and the side of the substrate with the opening is pressed against the front side of the image sensor chip to form a cover plate structure. Thin the back side of the image sensor chip to the required thickness; Using the TSV process, an RDL reconstruction wiring layer is formed in the image sensor chip to transmit electrical signals from the front side of the image sensor chip to the back side.

7. The method for manufacturing a multi-chip integrated photoelectric sensor according to claim 6, characterized in that, The edge region is provided with a first front pad, a second front pad, and other metal layer pads. Through chip bonding process or SMT assembly, and then reflow soldering process, the first bottom pad, the second bottom pad, and the first front pad and the second front pad of the image sensor chip are connected accordingly.

8. The method for manufacturing a multi-chip integrated photoelectric sensor according to claim 6, characterized in that, Setting a light-transmitting component on the photosensitive area includes: setting a filter on the photosensitive area by a chip bonding process, or fabricating a lens on the photosensitive area.

9. The method for manufacturing a multi-chip integrated photoelectric sensor according to claim 6, characterized in that, Forming an RDL reconstruction wiring layer in the image sensor chip using TSV technology includes: Through-silicon vias are formed on the image sensor chip using photolithography and etching processes; An internal insulating layer is formed within the through-silicon via and on the back side of the image sensor chip; An RDL reconstructed wiring layer is formed within the through-silicon via using a physical vapor deposition process. A surface insulating layer is then applied to the back of the image sensor chip. Several BGA / LGA pads are formed on the back side of the image sensor chip using BGA / LGA technology.

10. A method for FT testing of a multi-chip integrated photoelectric sensor, characterized in that, A method for performing Fourier transform (FT) testing on a multi-chip integrated photoelectric sensor as described in any one of claims 1-5 includes the following steps: A wafer containing a packaged image sensor chip is provided, and the wafer is peeled off from an organic film; The wafer is transferred to the carrier disk of the FT test platform. The BGA / LGA pads of the packaged image sensor chip are made in contact with the test probes on the FT test platform. The front side of the packaged image sensor chip is connected to the optical test calibration to test various parameters of the photoelectric sensor, including communication, power consumption and performance.

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