An image sensor and a method of manufacturing the same

Abstract

The application provides an image sensor and a preparation method thereof, which comprises the following steps: providing a device substrate, forming a photodiode layer, a first sacrificial layer, a first epitaxial layer, a second sacrificial layer and a second epitaxial layer on the device substrate; forming support columns which penetrate through the second epitaxial layer, the second sacrificial layer, the first epitaxial layer, the first sacrificial layer, the photodiode layer and extend into the device substrate; forming a release groove; removing the first sacrificial layer to form a first cavity and removing the second sacrificial layer to form a second cavity; forming a first isolation layer in the first cavity and a first light shielding structure in the second cavity; removing the support columns to form a second light shielding structure; forming a transistor on the second epitaxial layer; forming an interlayer dielectric layer covering the second epitaxial layer and the transistor; and bonding a support substrate and the interlayer dielectric layer.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to an image sensor and a preparation method thereof. BACKGROUND

[0002] The sensing technology of Complementary Metal Oxide Semiconductor (CMOS) image sensors (CIS) has been widely used in applications such as static digital cameras, digital video cameras, medical imaging devices, and vehicle imaging devices. CMOS image sensors are mainly divided into two structures: front side illumination CMOS image sensor (FSI) and backside illumination CMOS image sensor (BSI). Compared with FSI image sensors, BSI image sensors arrange the light-sensitive area containing photodiodes on the top of the circuit, reducing light loss such as metal line reflection, dielectric layer absorption, etc., significantly increasing the photoelectric conversion effect, and significantly improving the imaging quality.

[0003] However, with the development of advanced processes, the requirement for storing charge of BSI image sensors is also increasing. In the traditional BSI image sensor, there is a latch-up effect between the source and the drain of the transistor, which causes the same pixel to generate crosstalk in the working process, and the light passes through the photodiode (PD) region into the floating diffusion (FD) region. There is also a crosstalk problem between different pixels. At the same time, in the preparation process of the photodiode, the ion implantation method will cause damage to the photodiode, affecting the product quality. Therefore, how to improve the quality of the image sensor, improve the latch-up effect between the source and the drain of the transistor-free, and avoid the crosstalk problem between the pixels is a technical problem to be solved at present. SUMMARY

[0004] A series of simplified concepts are introduced in the summary section, which will be further described in detail in the specific embodiment section. The summary section of the present application does not mean to attempt to limit the key features and necessary technical features of the claimed technical solution, and even less to determine the protection scope of the claimed technical solution.

[0005] In view of the existing problems, the application provides a preparation method of an image sensor, which comprises the following steps: providing a device substrate, sequentially forming a photodiode layer, a first sacrificial layer, a first epitaxial layer, a second sacrificial layer and a second epitaxial layer on the device substrate; forming a plurality of support columns penetrating through the second epitaxial layer, the second sacrificial layer, the first epitaxial layer, the first sacrificial layer, the photodiode layer and extending into the device substrate; forming at least one release groove penetrating through the second epitaxial layer, the second sacrificial layer, the first epitaxial layer, the first sacrificial layer and the photodiode layer; etching and removing the first sacrificial layer to form a first cavity between the first epitaxial layer and the photodiode layer by taking the release groove as a release channel, and etching and removing the second sacrificial layer to form a second cavity between the first epitaxial layer and the second epitaxial layer; forming a first isolation layer in the first cavity and a first light shielding structure in the second cavity; removing the support columns to form an isolation groove, and forming a second light shielding structure in the isolation groove; forming a plurality of transistors on the second epitaxial layer, each transistor comprising a drain region formed in the second epitaxial layer; forming an interlayer dielectric layer covering the second epitaxial layer and the plurality of transistors; and providing a support substrate and bonding the support substrate and the interlayer dielectric layer.

[0006] Illustratively, the image sensor comprises a plurality of pixel units, each pixel unit comprising at least one photodiode region and at least two transistors, and the second light shielding structure is further arranged between any two adjacent transistors in each pixel unit.

[0007] Illustratively, the step of forming a first isolation layer in the first cavity and a first light shielding structure in the second cavity comprises the following steps: depositing an isolation material layer to form a first isolation layer in the first cavity, the first isolation layer filling the first cavity, and the isolation material layer is also deposited on a surface of the second epitaxial layer facing the first epitaxial layer to form a second isolation layer covering the surface of the second epitaxial layer facing the first epitaxial layer, and the isolation material layer is also deposited on a surface of the first epitaxial layer facing the second epitaxial layer to form a third isolation layer covering the surface of the first epitaxial layer facing the second epitaxial layer; and depositing a first light shielding layer to fill a portion of the second cavity between the second isolation layer and the third isolation layer, and the first light shielding structure comprises the first isolation layer, the second isolation layer and the first light shielding layer.

[0008] Exemplarily, before forming the plurality of transistors after forming the second light-shielding structure, the preparation method further comprises: forming a plurality of first conductive plugs sequentially penetrating through the second epitaxial layer, the first light-shielding structure, the first epitaxial layer and the first isolation layer, the plurality of first conductive plugs are arranged at intervals, and each of the first conductive plugs is electrically connected with one photodiode region in the photodiode layer; and the preparation method further comprises: forming a plurality of conductive interconnection structures in the interlayer dielectric layer, wherein each of the conductive interconnection structures is electrically connected with at least one of the first conductive plugs and at least one drain region of the transistors, respectively.

[0009] Exemplarily, the isolation material layer is also deposited on the sidewall of the release trench, and the first light-shielding layer fills the release trench.

[0010] Exemplarily, the first conductive plug is also arranged to extend along a first direction, wherein the image sensor comprises a plurality of pixel units, each of the pixel units comprises at least one photodiode region and at least two transistors, the second light-shielding structure is arranged between two adjacent pixel units in a second direction, and the second light-shielding structure is also arranged to extend along the first direction, the first direction being perpendicular to the thickness direction of the device substrate; each of the release trenches is arranged between two adjacent pixel units in the first direction, and the release trench also extends along the second direction; wherein the first direction, the second direction and the thickness direction of the device substrate are perpendicular to each other, the drain region of at least one transistor in each of the pixel units serves as a floating diffusion region, and the floating diffusion region and the photodiode region in each of the pixel units are arranged at intervals in the thickness direction of the device substrate.

[0011] Exemplarily, after the support substrate and the interlayer dielectric layer are bonded, the method further comprises: thinning the side of the device substrate away from the first epitaxial layer to expose one end of the second light-shielding structure away from the interlayer dielectric layer.

[0012] Exemplarily, the forming the second light-shielding structure in the isolation trench comprises: forming a fourth isolation layer on the sidewall and the bottom of the isolation trench; and depositing a second light-shielding layer to fill the isolation trench, the second light-shielding structure comprising the fourth isolation layer and the second light-shielding layer.

[0013] Exemplarily, the method further comprises: forming a passivation layer on a side of the device substrate away from the first isolation layer; forming a plurality of grid structures on the passivation layer, wherein a grid structure is arranged between adjacent pixel units, and a grid opening is formed between adjacent grid structures, and the grid opening exposes a surface of the passivation layer; embedding a color filter layer in the grid opening; and forming a plurality of microlenses on the color filter layer, and the plurality of microlenses correspond to the plurality of pixel units.

[0014] In another aspect, the present application provides an image sensor prepared by the above method

[0015] The image sensor and the preparation method thereof provided by the present application can effectively prevent the latch-up effect between the source and the drain of the transistor, avoid the crosstalk between the photodiode region and the floating diffusion region, and effectively avoid the crosstalk between different pixels by the second light shielding structure, thereby improving the quality of the image sensor. BRIEF DESCRIPTION OF DRAWINGS

[0016] The following drawings for the present application are hereby included as a part of the present application for understanding the present application. The embodiments of the present application and its description shown in the drawings are used to explain the principles of the present application.

[0017] In the drawings

[0018] Figure 1 A flow chart of the image sensor preparation method of the embodiment of the present application is shown in the figure;

[0019] Figure 2 A schematic diagram of the device obtained by sequentially implementing the image sensor preparation method in the related art is shown in the figure;

[0020] Figures 3 to 22 A schematic diagram of the device obtained by sequentially implementing the image sensor preparation method of the embodiment of the present application is shown in the figure. DETAILED DESCRIPTION

[0021] Next, the present application will be described in more detail by reference made to the drawings, wherein embodiments of the present application are shown. The present application may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the disclosure will be thorough and complete, and fully convey the scope of the application to those skilled in the art. In the drawings, the size and relative sizes of layers and regions can be exaggerated for clarity. Like reference numerals in the figures denote like elements throughout.

[0022] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

[0023] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0024] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0025] For a thorough understanding of the present application, reference should be made to the following detailed description together with the accompanying drawings, in which:

[0026] With the rapid development of semiconductor technology, the requirement for storing charge of BSI image sensors is also higher and higher. As shown in Figure 2 There is a latch-up effect between the source 110 and the drain 120 of the transistor in the conventional BSI image sensor (i.e. there is a latch-up effect between the photodiode and the floating diffusion region, as shown by the arrow in Figure 2 ), which causes crosstalk between the same pixels in the working process, and crosstalk between different pixels; meanwhile, the ion implantation method in the preparation process of the photodiode will cause damage to the photodiode, affecting the product quality. Therefore, how to improve the quality of the image sensor, improve the latch-up effect between the source and the drain of the transistor-free, and avoid the crosstalk problem between the pixels is a technical problem to be solved at present.

[0027] Therefore, in view of the foregoing technical problems, the present application proposes a preparation method of an image sensor, as shown in Figure 1 , which mainly comprises the following steps:

[0028] Step S1, providing a device substrate, sequentially forming a photodiode layer, a first sacrificial layer, a first epitaxial layer, a second sacrificial layer and a second epitaxial layer on the device substrate;

[0029] Step S2, forming a plurality of support columns penetrating through the second epitaxial layer, the second sacrificial layer, the first epitaxial layer, the first sacrificial layer, the photodiode layer and extending into the device substrate;

[0030] Step S3, forming at least one release groove penetrating through the second epitaxial layer, the second sacrificial layer, the first epitaxial layer, the first sacrificial layer and the photodiode layer;

[0031] Step S4, taking the release groove as a release channel, etching to remove the first sacrificial layer to form a first cavity between the first epitaxial layer and the photodiode layer, and etching to remove the second sacrificial layer to form a second cavity between the first epitaxial layer and the second epitaxial layer;

[0032] Step S5, forming a first isolation layer in the first cavity, and forming a first light shielding structure in the second cavity;

[0033] Step S6, removing the support columns to form an isolation groove, and forming a second light shielding structure in the isolation groove;

[0034] Step S7, forming a plurality of transistors on the second epitaxial layer, each transistor comprising a drain region formed in the second epitaxial layer;

[0035] Step S8, forming an interlayer dielectric layer covering the second epitaxial layer and the plurality of transistors;

[0036] Step S9, providing a support substrate, and bonding the support substrate and the interlayer dielectric layer.

[0037] The preparation method of the image sensor of the embodiment of the present application can effectively prevent the latch-up effect between the source and the drain of the transistor, avoid the crosstalk between the photodiode region and the floating diffusion region, and effectively avoid the crosstalk between different pixels through the second light shielding structure, thereby improving the quality of the image sensor.

[0038] Embodiment One

[0039] Hereinafter, the preparation method of the image sensor of the present application will be described in detail with reference to the accompanying drawings. Figure 1 and Figures 3 to 22 The preparation method of the image sensor of the present application will be described in detail, wherein, Figure 1 The flow chart of the preparation method of the image sensor of the embodiment of the present application is shown, Figures 3 to 22 The schematic diagram of the device obtained by sequentially implementing the preparation method of the image sensor of the embodiment of the present application is shown, wherein, the (a) of the drawing shows the top view schematic diagram of the device obtained by sequentially implementing the preparation method of the image sensor of the embodiment of the present application, and the (b) of the drawing shows the cross-sectional schematic diagram of the device obtained by sequentially implementing the preparation method of the image sensor of the embodiment of the present application.

[0040] Exemplarily, the preparation method of the image sensor of the present application includes the following steps:

[0041] Firstly, step S1 is performed to provide a device substrate, and a photodiode layer, a first sacrificial layer, a first epitaxial layer, a second sacrificial layer and a second epitaxial layer are sequentially formed on the device substrate.

[0042] In one example, as Figure 3As shown, a device substrate 201 is provided, and the material of the device substrate 201 includes, but is not limited to, at least one of the following materials: silicon (Si), germanium (Ge), silicon-germanium (SiGe), silicon carbide (SiC), silicon-germanium-carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), sapphire (Sapphire), or other III / V compound semiconductor, or silicon-on- insulator (SOI), silicon-on-silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), or double side polished wafers (DSP), ceramic substrate such as aluminum oxide, quartz or glass substrate, etc. Although several examples of materials that can form the device substrate are described herein, any material that can be used as a device substrate falls within the spirit and scope of the present application. In the present embodiment, the device substrate 201 is a silicon substrate.

[0043] In one example, as shown in FIG. 2, a photodiode layer 230 is formed on the device substrate 201. Exemplarily, the material of the photodiode layer 230 includes, but is not limited to, silicon, gallium arsenide, or other suitable material, and the photodiode layer 230 is formed on the device substrate 201 by an epitaxial process. By preparing the photodiode layer through an epitaxial process, damage caused by traditional ion implantation can be effectively avoided, and the quality of the image sensor can be improved. Figure 4 In one example, as shown in FIG. 3, a first sacrificial layer 202 is formed on the photodiode layer 230. Exemplarily, the material of the first sacrificial layer 202 includes, but is not limited to, amorphous silicon, polysilicon, silicon-germanium (SiGe), or other suitable material. The process method for forming the first sacrificial layer 202 can be selected as needed, for example, chemical vapor deposition (CVD), molecular beam epitaxy (MBE), or other suitable epitaxial technology, which is not specifically limited. In the present embodiment, the material of the first sacrificial layer 202 is silicon-germanium, and the first sacrificial layer 202 helps to form a first cavity between the photodiode layer 230 and a first epitaxial layer 203 later.

[0044] Figure 4 In one example, as shown in FIG. 4, a first epitaxial layer 203 is formed on the first sacrificial layer 202. Exemplarily, the material of the first epitaxial layer 203 includes, but is not limited to, silicon, gallium arsenide, or other suitable material, and the first epitaxial layer 203 is formed on the first sacrificial layer 202 by an epitaxial process. By preparing the first epitaxial layer 203 through an epitaxial process, damage caused by traditional ion implantation can be effectively avoided, and the quality of the image sensor can be improved.

[0045] In one example, as shown in FIG. 5, a second sacrificial layer 204 is formed on the first epitaxial layer 203. Exemplarily, the material of the second sacrificial layer 204 includes, but is not limited to, amorphous silicon, polysilicon, silicon-germanium (SiGe), or other suitable material. The process method for forming the second sacrificial layer 204 can be selected as needed, for example, chemical vapor deposition (CVD), molecular beam epitaxy (MBE), or other suitable epitaxial technology, which is not specifically limited. In the present embodiment, the material of the second sacrificial layer 204 is silicon-germanium, and the second sacrificial layer 204 helps to form a second cavity between the first epitaxial layer 203 and a second epitaxial layer 205 later. Figure 4 ​As shown, a first epitaxial layer 203 is formed on the first sacrificial layer 202. Exemplarily, the material of the first epitaxial layer 203 includes, but is not limited to, silicon, silicon germanium, silicon carbide, or other suitable epitaxial materials. The process method for forming the first epitaxial layer 203 can be selected as needed, for example, metal-organic chemical vapor deposition (MOCVD), low-pressure chemical vapor deposition (LPCVD), molecular beam epitaxy (MBE), or other suitable techniques, and is not specifically limited thereto. In this embodiment, the material of the first epitaxial layer 203 is silicon, the same as the material of the device substrate 201. Therefore, the silicon formed by epitaxial growth can have the same crystal structure and orientation as the device substrate, which helps to maintain high-quality electronic properties.

[0046] In one example, such as Figure 4 As shown, a second sacrificial layer 204 is formed on the first epitaxial layer 203. The material of the second sacrificial layer 204 is the same as or different from that of the first sacrificial layer 202. The process for forming the second sacrificial layer 204 is the same as that for the first sacrificial layer, and will not be described in detail here. Next, a second epitaxial layer 205 is formed on the second sacrificial layer 204. The material of the second epitaxial layer 205 is the same as that of the first epitaxial layer 203. The process for forming the second sacrificial layer 204 is the same as that for the first epitaxial layer, and will not be described in detail here. Alternatively, in some examples, the first epitaxial layer and the second epitaxial layer can be made of different semiconductor materials. In this embodiment, the material of the second sacrificial layer 204 is silicon-germanium, and the material of the second epitaxial layer 205 is silicon. The second sacrificial layer 204 facilitates the subsequent formation of a second cavity between the first epitaxial layer 203 and the second epitaxial layer 205.

[0047] Next, step S2 is performed to form multiple support pillars that penetrate the second epitaxial layer, the second sacrificial layer, the first epitaxial layer, the first sacrificial layer, the photodiode layer and extend into the device substrate.

[0048] In one example, such as Figure 5 and Figure 6 As shown, the step of forming a plurality of support pillars 207 that penetrate the second epitaxial layer 205, the second sacrificial layer 204, the first epitaxial layer 203, the first sacrificial layer 202, the photodiode layer 230, and extend into the device substrate 201 includes:

[0049] First, the second epitaxial layer 205, the second sacrificial layer 204, the first epitaxial layer 203, the first sacrificial layer 202, the photodiode layer 230 and the device substrate 201 are etched to form support grooves 206 penetrating through the second epitaxial layer 205, the second sacrificial layer 204, the first epitaxial layer 203, the first sacrificial layer 202, the photodiode layer 230 and extending into the device substrate 201, and the support grooves 206 extend along a first direction, which is perpendicular to the thickness direction of the device substrate 201. Specifically, a patterned photoresist layer is formed on the surface of the second epitaxial layer 205, the photoresist layer exposes the regions and positions corresponding to the support grooves 206, and the second epitaxial layer 205, the second sacrificial layer 204, the first epitaxial layer 203, the first sacrificial layer 202, the photodiode layer 230 and the device substrate 201 are etched with the photoresist layer as a mask to form a plurality of support grooves 206, each support groove 206 penetrating through the second epitaxial layer 205, the second sacrificial layer 204, the first epitaxial layer 203, the first sacrificial layer 202, the photodiode layer 230 and extending into the device substrate 201, and then the photoresist layer is removed; wherein the etching of the second epitaxial layer 205, the second sacrificial layer 204, the first epitaxial layer 203, the first sacrificial layer 202, the photodiode layer 230 and the device substrate 201 can be selected from dry etching, reactive ion etching (RIE), ion beam etching, plasma etching and other conventional etching processes. Optionally, the plurality of support grooves 206 can also be arranged at intervals in a second direction. Optionally, the photodiode layer 230 is divided into a plurality of photodiode regions by the plurality of support grooves 206 to serve as the light-sensing regions of a plurality of pixel units of the image sensor.

[0050] Next, support columns 207 are formed in the support grooves 206. Specifically, a support material is filled in the support grooves 206, wherein the support material includes but is not limited to silicon oxide, silicon nitride, polysilicon or other suitable materials. The process method for forming the support columns 207 includes but is not limited to chemical vapor deposition (CVD), atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDP-CVD) or physical vapor deposition (PVD), etc., without specific limitation. The formed support columns 207 are arranged to extend along a first direction, which is perpendicular to the thickness direction of the device substrate 201, and the positions of the support columns are used for subsequent formation of a second light-shielding structure. After forming the support columns 207, the support material can also be subjected to a planarization treatment, for example, chemical mechanical polishing (CMP) is used to remove the excess support material on the second epitaxial layer 205, so that the second epitaxial layer 205 has a flat surface. The number of support columns can be reasonably set according to the number of subsequent pixel units, one support column is arranged between adjacent pixel units, for example, it can be 1, 2, 3 or more.

[0051] Continue, execute step S3 to form at least one release trench penetrating the second epitaxial layer, the second sacrificial layer, the first epitaxial layer, the first sacrificial layer, and the photodiode layer.

[0052] In one example, such as Figure 7 As shown, the second epitaxial layer 205, the second sacrificial layer 204, the first epitaxial layer 203, the first sacrificial layer 202 and the photodiode layer 230 are etched to form at least one release trench 240, which also extends along the second direction. Specifically, a patterned photoresist layer is formed on the surface of the second epitaxial layer 205, exposing the area and position corresponding to the release trench 240 to be formed. Using the photoresist layer as a mask, the second epitaxial layer 205, the second sacrificial layer 204, the first epitaxial layer 203, the first sacrificial layer 202, and the photodiode layer 230 are etched to form at least one release trench 240 extending along the second direction. The photoresist layer is then removed. The etching of the second epitaxial layer 205, the second sacrificial layer 204, the first epitaxial layer 203, the first sacrificial layer 202, and the photodiode layer 230 can be performed using dry etching, reactive ion etching (RIE), ion beam etching, plasma etching, or other conventional etching processes; no specific limitation is made. The release trench 240 is also disposed between two adjacent pixel units formed subsequently in the first direction. The first direction is perpendicular to the thickness direction of the device substrate 201, and the second direction is perpendicular to both the first and second directions.

[0053] Next, step S4 is performed, using the release trench as a release channel, etching away the first sacrificial layer to form a first cavity between the first epitaxial layer and the photodiode layer, and etching away the second sacrificial layer to form a second cavity between the first epitaxial layer and the second epitaxial layer.

[0054] In one example, such as Figure 8As shown, the first sacrificial layer 202 is etched away using the release trench 240 as the release channel to form a first cavity 208 between the first epitaxial layer 203 and the photodiode layer 230, and the second sacrificial layer 204 is etched away to form a second cavity 209 between the first epitaxial layer 203 and the second epitaxial layer 205. Specifically, conventional etching processes such as dry etching, reactive ion etching (RIE), ion beam etching, plasma etching, and wet etching can be used to remove the first sacrificial layer 202 between the first epitaxial layer 203 and the photodiode layer 230, as well as the second sacrificial layer 204 between the first epitaxial layer 203 and the second epitaxial layer 205. For example, a gaseous hydrofluoric acid (VHF) etching process can be used to release the sacrificial layer, that is, gaseous hydrofluoric acid is introduced into a release trench, and the first sacrificial layer 202 and the second sacrificial layer 204 are removed by etching through the release trench, thereby forming a first cavity 208 between the first epitaxial layer 203 and the photodiode layer 230 and a second cavity 209 between the first epitaxial layer 203 and the second epitaxial layer 205.

[0055] Then, step S5 is performed to form a first isolation layer in the first cavity and a first light-shielding structure in the second cavity.

[0056] In one example, such as Figure 9 and Figure 10 As shown, the steps of forming a first isolation layer 210 in the first cavity 208 and a first light-shielding structure 211 in the second cavity 209 include:

[0057] First, an isolation material layer 20 is deposited, filling the first cavity 210 to form a first isolation layer 210. Second, the isolation material layer 20 is also deposited on the surface of the second epitaxial layer 205 facing the first epitaxial layer 203 to form a second isolation layer 2110 covering the surface of the second epitaxial layer 205 facing the first epitaxial layer 203. This isolation material layer 20 is also deposited on the surface of the first epitaxial layer 203 facing the second epitaxial layer 205 to form a third isolation layer 2111 covering the surface of the first epitaxial layer 203 facing the second epitaxial layer 205. The isolation material layer 20 is also deposited on a portion of the sidewalls of the support post 207 and the sidewalls of the release trench 240. Exemplarily, the material of the isolation material layer 20 includes, but is not limited to, oxides, such as silicon oxide, etc., and is not specifically limited thereto. The process methods for forming the first isolation layer 210, the second isolation layer 2110, and the third isolation layer 2111 include, but are not limited to, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD), etc., and are not specifically limited to these methods. The isolation layers can provide a physical barrier to prevent damage caused by subsequent processing, thereby improving the reliability and stability of the device, and they can also serve an insulating function.

[0058] Next, a first light-shielding layer 2112 is deposited to fill the portion of the second cavity 209 located between the second isolation layer 2110 and the third isolation layer 2111, wherein the first light-shielding layer 2112 also fills the release trench 240. Exemplarily, the material of the first light-shielding layer 2112 includes, but is not limited to, titanium nitride, tungsten, copper, aluminum, or other suitable light-shielding materials, and the first light-shielding layer 2112 is an opaque material or a reflective material. The process methods for forming the first light-shielding layer 2112 include, but are not limited to, physical vapor deposition (PVD), atomic layer deposition (ALD), or chemical vapor deposition (CVD), and are not specifically limited thereto. By forming the first isolation layer and the light-shielding structure between the subsequently formed photodiode region and the floating diffusion region, light can be prevented from incident on the floating diffusion region, effectively preventing latch-up effects between the source and drain of the transistor (i.e., latch-up effects between the photodiode region and the floating diffusion region), thereby avoiding crosstalk between the photodiode region and the floating diffusion region and improving the quality of the image sensor.

[0059] In one example, such as Figures 11 to 12 As shown, after forming the first light-shielding structure 211, the isolation material layer and the first light-shielding layer on the second epitaxial layer 205 are removed. Specifically, the isolation material layer and the first light-shielding layer on the second epitaxial layer 205 can be removed by, but not limited to, chemical mechanical polishing. Then, wet cleaning can be performed to remove the material remaining during the chemical mechanical polishing process to avoid affecting the performance of the device.

[0060] Continue, proceed to step S6, remove the support column to form an isolation trench, and form a second light-shielding structure in the isolation trench.

[0061] In one example, such as Figure 13 As shown, the support pillars 207 are removed to form the isolation trench 2071. Specifically, conventional etching processes such as dry etching, reactive ion etching (RIE), ion beam etching, plasma etching, and wet etching can be used to remove the support pillars 207, thereby forming the isolation trench 2071.

[0062] In one example, such as Figure 14As shown, a second light-shielding structure 250 is formed in the isolation trench 2071. Specifically, firstly, an isolation material is deposited, covering the bottom and sidewalls of the isolation trench 2071 to form a fourth isolation layer 251. Exemplarily, the isolation material includes, but is not limited to, oxides, such as silicon oxide, etc., and is not specifically limited thereto. The process methods for forming the fourth isolation layer 251 include, but are not limited to, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD), etc., and are not specifically limited thereto. The isolation layer can provide a physical barrier to prevent damage caused by subsequent processing, thereby improving the reliability and stability of the device, and it can also serve an insulating function. Secondly, a second light-shielding layer 252 is deposited to fill the isolation trench 2071. Exemplarily, the material of the second light-shielding layer 252 includes, but is not limited to, titanium nitride, tungsten, copper, aluminum, or other suitable light-shielding materials. The process for forming the second light-shielding layer 252 includes, but is not limited to, physical vapor deposition (PVD), atomic layer deposition (ALD), or chemical vapor deposition (CVD), and is not specifically limited thereto. The fourth isolation layer 251 and the second light-shielding layer 252 constitute a second light-shielding structure 250, which extends along a first direction perpendicular to the thickness direction of the device substrate 201. The second light-shielding structure 250 is disposed between two adjacent pixel units in the second direction, effectively preventing crosstalk between different pixels. In some examples, the second light-shielding structure 250 is also disposed between at least two adjacent transistors in each subsequently formed pixel unit, reducing electric field coupling between transistors and preventing signal interference between them.

[0063] In one example, such as Figure 15 As shown, the fabrication method of this application further includes: after forming the aforementioned second light-shielding structure and before forming the plurality of transistors, forming a plurality of first conductive plugs 213 that sequentially penetrate the second epitaxial layer 205, the first light-shielding structure 211, the first epitaxial layer 203, and the first isolation layer 210, the step specifically includes:

[0064] Firstly, the second epitaxial layer 205, the first light shielding structure 211, the first epitaxial layer 203 and the first isolation layer 210 are etched to form a plurality of contact holes, wherein the bottom of the contact hole exposes the surface of the part of the photodiode layer 230. Specifically, a patterned photoresist layer is formed on the second epitaxial layer 205, the photoresist layer exposes the area and position corresponding to the contact hole; the second epitaxial layer 205, the first light shielding structure 211, the first epitaxial layer 203 and the first isolation layer 210 are etched to form a plurality of contact holes with the photoresist layer as a mask, the formed contact holes 212 are arranged along the first direction, and then the photoresist layer is removed; wherein the etching of the second epitaxial layer 205, the first light shielding structure 211, the first epitaxial layer 203 and the first isolation layer 210 can be dry etching, reactive ion etching (RIE), ion beam etching, plasma etching and other conventional etching processes, which are not limited specifically. The first direction is perpendicular to the thickness direction of the device substrate 201, and the first direction and the second direction are perpendicular to each other. The formed contact hole is used for subsequent formation of the first conductive plug 213. Optionally, the top view shape of the contact hole is a long strip shape, a square shape, a circular shape or other suitable shapes.

[0065] Then, before forming the first conductive plug 213, the method of the application further comprises filling an insulating material in the contact hole, the insulating material covering the sidewall of the contact hole to form an insulating isolation layer 214, and the insulating material includes but is not limited to oxide, such as silicon oxide and the like, which is not limited specifically. The process method for forming the insulating isolation layer 214 includes but is not limited to chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD) and the like. The insulating isolation layer 214 can be used to electrically isolate the first conductive plug 213 and the epitaxial layer outside it.

[0066] Finally, the contact holes are filled with a conductive material to form a plurality of first conductive plugs 213, which are illustratively, but not exclusively, titanium nitride, tungsten, copper, aluminum, or other suitable conductive material. The process method for forming the first conductive plugs 213 includes, but is not limited to, physical vapor deposition (PVD), atomic layer deposition (ALD), or chemical vapor deposition (CVD), etc., without limitation. The conductive material fills the contact holes 212 to form the plurality of first conductive plugs 213, which extend through the second epitaxial layer 205, the first light shielding structure 211, the first epitaxial layer 203, and the first isolation layer 210 in the substrate thickness direction. The bottom of the first conductive plug 213 is in contact with the surface of the photodiode layer 230, and each first conductive plug 213 is subsequently used to electrically connect to one photodiode region 231 of the photodiode layer 230. After forming the first conductive plugs 213, a planarization process can also be performed to remove excess insulating material and conductive material on the second epitaxial layer 205, for example, using chemical mechanical polishing (CMP) to remove excess insulating material and conductive material on the second epitaxial layer 205, so that the second epitaxial layer 205 has a flat surface, improving the reliability of the device.

[0067] Next, step S7 is performed to form a plurality of transistors on the second epitaxial layer, each transistor including a drain region formed in the second epitaxial layer.

[0068] In one example, as shown in FIG. 2, the step of forming the transistors 215 can include: Figure 16

[0069] ​First, active regions are defined by shallow trench isolation (STI) or local oxidation of silicon (LOCOS) to isolate adjacent pixels, and the shallow trench isolation structure can be located between adjacent transistors; then, a gate structure 2150 is formed on the second epitaxial layer 205, specifically, first, a gate dielectric layer is formed on the second epitaxial layer 205, the material of the gate dielectric layer includes but is not limited to silicon dioxide and the like, and the method of forming the gate dielectric layer includes but is not limited to chemical vapor deposition (CVD) or thermal oxidation and the like; second, a gate electrode layer is formed on the gate dielectric layer, the material of the gate electrode layer includes but is not limited to polysilicon and the like, and the method of forming the gate electrode layer includes but is not limited to chemical vapor deposition (CVD) or physical vapor deposition (PVD) and the like; finally, a patterned photoresist layer is formed on the gate electrode layer, which defines the area and position of the gate structure, and the gate electrode layer and the gate dielectric layer are etched with the patterned photoresist layer as a mask to form the gate structure 2150 on the second epitaxial layer 205, and then the photoresist layer is removed; wherein the etching of the gate electrode layer and the gate dielectric layer can use dry etching, such as reactive ion etching (RIE), ion beam etching, plasma etching and the like, and no specific limitation is made thereto. After the formation of the gate structure, a sidewall (not shown) can also be formed on both sides of the gate structure, which is used to protect the edge of the gate structure from damage in subsequent processes, and the material of the sidewall includes but is not limited to silicon nitride and the like insulating materials. The gate structure is used to control the transfer of the accumulated charge in the photodiode to the floating diffusion region, thereby realizing a high-efficiency signal readout mechanism.

[0070] It is worth mentioning that the number of gate structures can be determined according to the number of transistors in the image sensor.

[0071] Next, a low-concentration impurity is introduced into the second epitaxial layer 205 below both sides of the gate structure 2150 by ion implantation to form a lightly doped region, which improves the short channel effect and improves the reliability of the device; then, a highly doped source region 2151 and a drain region 2152 are formed outside the lightly doped region to provide a low-resistance path and enhance the current driving capability, and the ion implantation concentration of the highly doped source region 2151 and the drain region 2152 is greater than that of the lightly doped region. After ion implantation, annealing is also performed, because the silicon lattice will be damaged during ion implantation, and annealing can repair these damages, in addition, annealing can also activate the implanted ions, thereby improving the performance of the image sensor. Optionally, the drain region of at least one transistor can be used as a floating diffusion region. Optionally, the drain region 2152 of at least one transistor can be electrically connected to the corresponding photodiode region.

[0072] Then, step S8 is performed to form an interlayer dielectric layer covering the second epitaxial layer and the plurality of transistors.

[0073] In one example, as Figure 17As shown, before forming the interlayer dielectric layer 218, it further comprises forming a dielectric layer 216 covering the transistors 215 and the second epitaxial layer 205. Exemplarily, the material of the dielectric layer 216 includes but is not limited to silicon dioxide, low dielectric constant material or other suitable dielectric material. The method of forming the dielectric layer 216 includes but is not limited to deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), without specific limitation.

[0074] Next, a plurality of second conductive plugs 217 are formed in the dielectric layer 216, each of the second conductive plugs 217 electrically connecting the drain region 2152 of the transistor 215. Specifically, a patterned photoresist layer is formed on the dielectric layer 216, the photoresist layer exposing the area and position corresponding to the second conductive plugs 217; the dielectric layer 216 is etched with the photoresist layer as a mask to form a plurality of etching holes penetrating through the dielectric layer 216, the etching holes being arranged along the first direction, and then the photoresist layer is removed; wherein the dielectric layer 216 can be etched by using dry etching, reactive ion etching (RIE), ion beam etching, plasma etching or other conventional etching process, without specific limitation. Then, the etching holes are filled with insulating material, the insulating material covering the sidewall of the etching holes to form an insulating layer, the insulating material including but not limited to oxide such as silicon oxide, without specific limitation, and the process method of forming the insulating layer includes but is not limited to chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD) and other methods. Finally, the etching holes are filled with conductive material to form the second conductive plugs 217, exemplarily, the conductive material includes but is not limited to titanium nitride, tungsten, copper, aluminum or other suitable conductive material, and the process method of forming the second conductive plugs 217 includes but is not limited to physical vapor deposition (PVD), atomic layer deposition (ALD) or chemical vapor deposition (CVD) and other methods, without specific limitation. The second conductive plugs 217 are arranged along the first direction, each of the second conductive plugs 217 electrically connecting the drain region 2152 of the transistor 215. After forming the second conductive plugs 217, a planarization process can be performed to remove the excess insulating material and conductive material on the dielectric layer 216, for example, using chemical mechanical polishing (CMP) to remove the excess insulating material and conductive material on the dielectric layer 216, so that the dielectric layer 216 has a flat surface, improving the reliability of the device. In one example, a conductive plug penetrating through the dielectric layer 216 and electrically connected with the first conductive plug 213 can be formed, which can be used as a part of the first conductive plug 213 to lead out the corresponding photodiode region.

[0075] Then, an interlayer dielectric layer 218 is formed on the dielectric layer 216, and the interlayer dielectric layer 218 can include a plurality of layers of interlayer dielectric material. The method of forming the interlayer dielectric layer 218 includes, but is not limited to, a deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), without being specifically limited. Next, a plurality of conductive interconnection structures 219 are formed in the interlayer dielectric layer 218, and each of the conductive interconnection structures 219 is electrically connected to at least one of the first conductive plugs 213 and at least one of the drain regions of the transistors, and specifically, each of the conductive interconnection structures 219 is further electrically connected to at least one of the second conductive plugs 217, the first conductive plugs 213 are electrically connected to the photodiode regions 231, and the second conductive plugs 217 are electrically connected to the drain regions 2152 of the transistors 215. Exemplarily, the material of the conductive interconnection structures 219 includes, but is not limited to, copper or aluminum, and the method of depositing the material of the conductive interconnection structures includes, but is not limited to, a process such as chemical vapor deposition (CVD), without being specifically limited.

[0076] It is worth mentioning that the conductive interconnection structures 219 can include a plurality of metal layers stacked in sequence, and a plug is arranged between adjacent metal layers to form the conductive interconnection structures 219 in a stacked structure. Specifically, the method of forming the conductive interconnection structures can be any suitable method, which is not specifically expanded herein.

[0077] Finally, step S9 is performed to provide a support substrate, and the support substrate is bonded to the interlayer dielectric layer.

[0078] In one example, as shown in FIG. 3, Figure 18 The support substrate 301 can be formed of at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), sapphire (Sapphire), or other III / V compound semiconductors, or silicon-on-dielectric (SOI), silicon-on-layered-dielectric (SSOI), silicon germanium-on-layered-dielectric (S-SiGeOI), silicon germanium-on-dielectric (SiGeOI), and germanium-on-dielectric (GeOI), or double side polished wafers (DSP), ceramic substrates such as aluminum oxide, quartz, or glass substrates, etc. Although several examples of the materials that can form the support substrate are described herein, any material that can be used as the support substrate falls within the spirit and scope of the present application. In the present embodiment, the support substrate 301 is a silicon substrate. The support substrate 301 and the interlayer dielectric layer 218 are bonded, and the method of bonding includes, but is not limited to, silicon-oxygen bonding or hybrid bonding, without being specifically limited.

[0079] In one example, as shown in FIG. 3,Figure 19 As shown, after bonding the support substrate 301 and the interlayer dielectric layer 218, the method further includes: thinning the side of the device substrate 201 opposite to the first epitaxial layer 203 to expose the end of the second light-shielding structure 250 away from the interlayer dielectric layer 218. Specifically, after bonding, the bonded structure is flipped, and the back side of the device substrate 201 (i.e., the side of the device substrate 201 opposite to the first epitaxial layer 203) is thinned to expose the end of the second light-shielding structure 250 away from the interlayer dielectric layer 218. The thinning method includes, but is not limited to, chemical mechanical polishing, and is not specifically limited thereto.

[0080] In one example, the image sensor includes multiple pixel units, each pixel unit including at least one photodiode region 231 and at least two transistors 215, wherein the drain region 2152 of at least one transistor 215 in each pixel unit serves as a floating diffusion region (FD), and each photodiode region 231 and floating diffusion region is spaced apart in the thickness direction of the device substrate 201. By vertically placing the photodiode region and the floating diffusion region, the area of ​​the photodiode region can be increased, thereby improving the photoelectric conversion efficiency. The floating diffusion region is used to collect the charge transferred from the photodiode region and convert it into a voltage signal for critical parts of the readout circuit processing.

[0081] In one example, such as Figure 20 As shown, a passivation layer 221 is formed on the side of the device substrate 201 opposite to the first isolation layer 210, and the passivation layer 221 covers the surface of the device substrate 201. Exemplarily, the material of the passivation layer 221 includes, but is not limited to, materials such as silicon dioxide or silicon oxynitride, and the method for forming the passivation layer 221 includes, but is not limited to, methods such as PECVD (plasma-enhanced chemical vapor deposition) or ALD (atomic layer deposition). The passivation layer helps reduce electrical crosstalk between adjacent pixels and reduces parasitic capacitance by optimizing the electrical properties of the metal layer, thereby improving signal transmission efficiency and image clarity.

[0082] In one example, such as Figure 20As shown, multiple grid structures 222 are formed on the passivation layer 221, and grid openings 223 are formed between each grid structure 222. A grid structure 222 is disposed between adjacent pixel units. Specifically, firstly, a grid material layer is formed on the passivation layer 221. The material of the grid material layer includes, but is not limited to, tungsten (W), nickel (Ni), or titanium (Ti). The methods for forming the grid material layer include, but are not limited to, molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), low-pressure chemical vapor deposition (LPCVD), and laser ablation deposition (LAD). Next, a patterned photoresist layer is formed on the grid material layer. This patterned photoresist layer defines the region and position of the grid structure 222. Using the patterned photoresist layer as a mask, the grid material layer is etched to form a grid structure 222 between adjacent pixel units. A grid opening 223 is formed between each grid structure 222, and the grid opening 223 exposes the surface of the passivation layer 221. Then, the photoresist layer is removed. The etching of the grid material layer can be performed using conventional etching processes such as dry etching, reactive ion etching (RIE), ion beam etching, and plasma etching, without specific limitations. The grid structure can enhance image performance by suppressing optical crosstalk.

[0083] In one example, such as Figure 21 As shown, a color filter layer 224 is embedded in each grid opening 223. The main function of the color filter layer 224 is to separate the incident light according to color (i.e., different wavelengths), so that each pixel can only receive light of a specific color (usually one of red, green, and blue). This is the basis for the color image sensor to generate color images. Specifically, the material of the color filter layer can be deposited in each grid opening 223 using methods such as spin coating or inkjet printing, and then subjected to processes such as baking to ensure its stability and optical performance, ultimately forming the color filter layer 224 embedded in the grid opening 223. The material of the color filter layer 224 includes, but is not limited to, dye-based resins, pigment-based resins, or inorganic materials.

[0084] In one example, such as Figure 22As shown, a plurality of microlenses 226 is formed on the color filter layer 224, and the plurality of microlenses 226 corresponds to a plurality of pixel units, for example, one pixel unit corresponds to one or more microlenses 226. Before forming the microlenses 226, an anti-reflection layer 225 is also formed on the color filter layer 224. Exemplarily, the anti-reflection layer 225 includes but is not limited to silicon dioxide or silicon nitride, etc., and the process method for forming the anti-reflection layer 225 includes but is not limited to PECVD (plasma enhanced chemical vapor deposition), atomic layer deposition (ALD), etc. When light enters from one medium to another medium (for example, microlens enters the color filter layer), if the difference of refractive index of the two is large, reflection loss will occur. The anti-reflection layer can effectively reduce the reflection loss at the interface by optimizing its refractive index and thickness, thereby increasing the effective light amount reaching the photodiode. By reducing the reflection loss, more incident light energy can be effectively utilized by the image sensor, which directly improves the quantum efficiency of the image sensor and the performance in low light environment, and the anti-reflection layer can also act as a transition layer to provide a flat surface for the microlens, facilitating its manufacture. In other examples, the anti-reflection layer can also not be formed, which is not specifically limited.

[0085] Finally, a plurality of microlenses 226 is formed on the color filter layer 224. Specifically, first, a layer of photosensitive material suitable for making microlenses (usually positive photoresist or high-temperature resin, etc.) is coated on the anti-reflection layer 225, a patterned photoresist layer is formed on the photosensitive material layer, and the patterned photoresist layer defines the area and position of the microlenses 226, and the photosensitive material layer is etched to form the basic structure of the microlenses with the patterned photoresist layer as a mask; second, the photoresist is heated to a certain temperature so that the remaining photoresist melts and naturally forms the required hemispherical or approximately spherical microlens structure due to surface tension; finally, the formed microlens structure is further cured, for example, ultraviolet curing or annealing, etc., to form the final microlens 226. The microlens focuses the incident light, so that more light can directly enter the photodiode, thereby compensating for the loss, improving light utilization, enhancing signal quality, and improving image quality.

[0086] It is worth mentioning that the above steps are only examples, and the order of the above steps can also be adjusted without conflict.

[0087] So far, the process steps of the image sensor preparation method according to the embodiment of the present application have been completed. It can be understood that the image sensor preparation method of the present embodiment not only includes the above steps, but also includes other required steps before, during or after the above steps, which are all included in the scope of the preparation method of the present embodiment.

[0088] In summary, the preparation method of the image sensor provided in the present application can effectively prevent the latch-up effect between the source and the drain of the transistor, avoid the crosstalk between the photodiode region and the floating diffusion region, and effectively avoid the crosstalk between different pixels through the second light shielding structure, thereby improving the quality of the image sensor.

[0089] The present application also provides an image sensor, which can be prepared by the method of the first embodiment or other suitable preparation method.

[0090] The image sensor provided in the present application can effectively prevent the latch-up effect between the source and the drain of the transistor, avoid the crosstalk between the photodiode region and the floating diffusion region, and effectively avoid the crosstalk between different pixels through the second light shielding structure, thereby improving the quality of the image sensor.

[0091] Although a number of embodiments have been described herein, it is understood that the skilled person would be able to conceive of numerous other modifications and embodiments which would fall within the spirit and scope of the inventive concept disclosed. More particularly, various modifications and changes in the arrangement of the subject combination of arrangements and / or components can be made within the scope of the present disclosure, the drawings, and the appended claims. In addition to modifications and changes in the components and / or arrangement, the use of alternative means would be apparent to the skilled person.

Claims

1. A method for fabricating an image sensor, characterized in that, include: A device substrate is provided, on which a photodiode layer, a first sacrificial layer, a first epitaxial layer, a second sacrificial layer, and a second epitaxial layer are sequentially formed; A plurality of support pillars are formed that penetrate the second epitaxial layer, the second sacrificial layer, the first epitaxial layer, the first sacrificial layer, the photodiode layer, and extend into the device substrate; At least one release trench is formed that extends through the second epitaxial layer, the second sacrificial layer, the first epitaxial layer, the first sacrificial layer, and the photodiode layer; Using the release trench as a release channel, the first sacrificial layer is etched away to form a first cavity between the first epitaxial layer and the photodiode layer, and the second sacrificial layer is etched away to form a second cavity between the first epitaxial layer and the second epitaxial layer. A first isolation layer is formed in the first cavity, and a first light-shielding structure is formed in the second cavity; Remove the support column to form an isolation trench, and form a second light-shielding structure in the isolation trench; A plurality of transistors are formed on the second epitaxial layer, each transistor including a drain region formed in the second epitaxial layer; An interlayer dielectric layer is formed covering the second epitaxial layer and the plurality of transistors; A support substrate is provided, and the support substrate and the interlayer dielectric layer are bonded together.

2. The preparation method according to claim 1, characterized in that, The image sensor includes multiple pixel units, each pixel unit including at least one photodiode region and at least two transistors, and a second light-shielding structure is disposed between any two adjacent transistors in each pixel unit.

3. The preparation method according to claim 1, characterized in that, The process of forming a first isolation layer in the first cavity and a first light-shielding structure in the second cavity includes: An isolation material layer is deposited to form a first isolation layer in the first cavity, the first isolation layer filling the first cavity, and the isolation material layer is also deposited on the surface of the second epitaxial layer facing the first epitaxial layer to form a second isolation layer covering the surface of the second epitaxial layer facing the first epitaxial layer, and the isolation material layer is also deposited on the surface of the first epitaxial layer facing the second epitaxial layer to form a third isolation layer covering the surface of the first epitaxial layer facing the second epitaxial layer; A first light-shielding layer is deposited to fill the portion of the second cavity located between the second isolation layer and the third isolation layer. The first light-shielding structure includes the first isolation layer, the second isolation layer, and the first light-shielding layer.

4. The preparation method according to claim 3, characterized in that, The insulating material layer is also deposited on the sidewall of the release trench, and the first light-shielding layer fills the release trench.

5. The preparation method according to claim 1, characterized in that, The fabrication method further includes, after forming the second light-shielding structure and before forming the plurality of transistors: A plurality of first conductive plugs are formed, sequentially penetrating the second epitaxial layer, the first light-shielding structure, the first epitaxial layer, and the first isolation layer. The plurality of first conductive plugs are spaced apart, and each first conductive plug is electrically connected to a photodiode region in the photodiode layer. The fabrication method further includes the step of forming a plurality of conductive interconnect structures in the interlayer dielectric layer, wherein each of the conductive interconnect structures is electrically connected to at least one of the first conductive plugs and at least one drain region of the transistor.

6. The preparation method according to claim 5, characterized in that, The first conductive plug further extends along a first direction, wherein the image sensor includes a plurality of pixel units, each pixel unit including at least one photodiode region and at least two transistors. A second light-shielding structure is provided between two adjacent pixel units in the second direction, and the second light-shielding structure also extends along a first direction, which is perpendicular to the thickness direction of the device substrate. Each of the release trenches is disposed between two adjacent pixel units in a first direction, and the release trenches also extend along a second direction; Wherein, the first direction, the second direction and the thickness direction of the device substrate are perpendicular to each other, the drain region of at least one transistor of each pixel unit is used as a floating diffusion region, and the floating diffusion region and the photodiode region of each pixel unit are spaced apart in the thickness direction of the device substrate.

7. The preparation method according to claim 1, characterized in that, After bonding the supporting substrate and the interlayer dielectric layer, the process further includes: The side of the device substrate opposite to the first epitaxial layer is thinned to expose the end of the second light-shielding structure away from the interlayer dielectric layer.

8. The preparation method according to claim 1, characterized in that, The formation of the second light-shielding structure in the isolation trench includes: A fourth isolation layer is formed on the sidewalls and bottom of the isolation trench; A second light-shielding layer is deposited to fill the isolation trench, the second light-shielding structure including the fourth isolation layer and the second light-shielding layer.

9. The preparation method according to claim 8, characterized in that, Also includes: A passivation layer is formed on the side of the device substrate opposite to the first isolation layer; Multiple grid structures are formed on the passivation layer, wherein a grid structure is disposed between adjacent pixel units, and a grid opening is formed between adjacent grid structures, the grid opening exposing the surface of the passivation layer; A color filter film layer is embedded in the grid opening; Multiple microlenses are formed on the color filter film layer, and the multiple microlenses correspond to multiple pixel units.

10. An image sensor, characterized in that, It is prepared by any one of the preparation methods described in claims 1 to 9.

Images