Semiconductor element and manufacturing method thereof
By adding ultra-high energy ion implantation and reducing the thickness of the epitaxial layer in the CMOS image sensor, a "凵"-shaped structure surrounding the photosensitive area is formed, solving the problems of white pixels and dark current and improving the performance of the image sensor.
Patent Information
- Application Number
- CN202410347611.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-25
- Publication Date
- 2025-10-03
AI Technical Summary
In existing CMOS image sensors, the formation of white pixels is mainly affected by the leakage current of the device itself, especially in the semiconductor substrate, shallow trench isolation area, deep trench isolation area and back side thinning process, which easily generates dark current, resulting in performance degradation.
Based on the traditional ion implantation process, an ultra-high energy ion implantation is added to form a third doped isolation region. By thinning the epitaxial layer of the semiconductor substrate, a "凵"-shaped structure surrounding the photosensitive region is formed, combined with a deep trench isolation structure to absorb the overflow charge of the photosensitive region.
It effectively reduces pixel crosstalk between adjacent photosensitive areas, reduces dark current and the formation of white pixels in the image sensor, and improves device performance.
Smart Images
Figure CN120751799A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of image sensors, and in particular to a semiconductor element for an image sensor and a method for manufacturing the semiconductor element. Background Art
[0002] With the rapid advancement of the intelligent era, cameras have become a familiar term to consumers. Camera performance is directly related to the CMOS image sensor (CIS) chip. The number of white pixels in a CIS chip is one of the main factors in evaluating device performance.
[0003] The causes of white pixels include dark current, noise, and signal algorithms. Dark current is the primary factor affecting white pixels. Its source is leakage current within the device itself, which is primarily caused by interface defects, lattice defects, and ion damage. Currently, common leakage locations in the pixel area of CIS chips include the semiconductor substrate, shallow trench isolation (STI), and deep trench isolation (DTI). Backside thinning during the CIS chip manufacturing process can also sometimes cause leakage in the pixel area. Summary of the Invention
[0004] In view of this, the present invention provides a method for preparing a semiconductor device, comprising:
[0005] A semiconductor substrate is provided, wherein a first surface of the semiconductor substrate is provided with a photosensitive region of a first ion type; a first energy ion implantation is performed on the first surface of the semiconductor substrate to form a third doped isolation region located below the photosensitive region; the semiconductor substrate is subjected to high-temperature repair; a second energy ion implantation is performed on the first surface of the semiconductor substrate to form a first doped isolation region and a second doped isolation region located between adjacent photosensitive regions; wherein the energy of the first energy ion implantation is greater than the energy of the second energy ion implantation; multiple thinning processes are performed on the second surface of the semiconductor substrate opposite to the first surface of the semiconductor substrate to make the thickness of the epitaxial layer of the semiconductor substrate reach a preset thickness; a deep trench isolation process is performed on the second surface of the semiconductor substrate to form a deep trench isolation structure located between adjacent photosensitive regions.
[0006] Optionally, the second surface of the semiconductor substrate opposite to the first surface of the semiconductor substrate is subjected to multiple thinning processes to make the thickness of the epitaxial layer of the semiconductor substrate reach a preset thickness, including: thinning the second surface of the semiconductor substrate for the first time to make the thickness of the epitaxial layer of the semiconductor substrate reach 4.7 to 5 microns; thinning the second surface of the semiconductor substrate for the second time to make the thickness of the epitaxial layer of the semiconductor substrate reach 3.3 to 3.4 microns; and thinning the second surface of the semiconductor substrate for the third time to make the thickness of the epitaxial layer of the semiconductor substrate reach 2.4 to 2.8 microns.
[0007] Optionally, the temperature of the high-temperature repair is 1050°C.
[0008] Optionally, the energy of the first energy ion implantation is 1600 KeV, and the energy of the second energy ion implantation is 100-950 KeV.
[0009] Optionally, the dosage of the first energy ion implantation is greater than the dosage of the second energy ion implantation.
[0010] The present invention also provides a semiconductor element for an image sensor formed based on the above-mentioned manufacturing method for preparing a semiconductor element, comprising: a semiconductor substrate having a first surface and a second surface arranged opposite to each other; a photosensitive region of a first ion type arranged on the first surface of the semiconductor substrate; a deep trench isolation structure located between adjacent photosensitive regions and extending from the second surface of the semiconductor substrate to the first surface of the semiconductor substrate; a doped isolation region of a second ion type arranged around the photosensitive region, the doped isolation region comprising a first doped isolation region, a second doped isolation region and a third doped isolation region arranged in sequence along the first surface of the semiconductor substrate pointing to the second surface of the semiconductor substrate, and the doping concentrations of the first doped isolation region, the second doped isolation region and the third doped isolation region gradually increase.
[0011] Optionally, the first ion type and the second ion type are opposite types.
[0012] Optionally, the epitaxial layer of the semiconductor substrate has a thickness of 2.4 to 2.8 microns.
[0013] Optionally, the length of the deep trench isolation structure is 1.5 to 1.7 microns.
[0014] Optionally, the semiconductor element further includes: a shallow trench isolation structure, located between adjacent photosensitive regions, and extending from the first surface of the semiconductor substrate to the second surface of the semiconductor substrate.
[0015] Compared with the prior art, the present invention has at least the following outstanding advantages:
[0016] In the embodiments of the present application, based on the conventional process of forming doped isolation regions by ion implantation, an additional ion implantation with ultra-high ion energy is added to form a third doped isolation region under the photosensitive region. The first doped isolation region and the second doped isolation region between the third doped isolation region and the adjacent photosensitive regions form a "U" - shaped structure surrounding the photosensitive region, further reducing the pixel crosstalk between adjacent photosensitive regions. At the same time, by thinning the epitaxial layer of the semiconductor substrate to a preset thickness, the doped isolation region with a higher concentration at the top of the deep trench isolation structure can absorb the overflow charge of the photosensitive region, reducing the dark current and the formation of white pixel points in the subsequent image sensor. Brief Description of the Drawings
[0017] Figure 1 is a process flow chart for fabricating a semiconductor device in an embodiment of the present invention;
[0018] Figure 2 is a schematic structural diagram after forming a photosensitive region in a semiconductor substrate in an embodiment of the present invention;
[0019] Figure 3 is a schematic structural diagram after forming a third doped isolation region in a semiconductor substrate in an embodiment of the present invention;
[0020] Figure 4 is a schematic structural diagram after forming a first doped isolation region and a second doped isolation region in a semiconductor substrate in an embodiment of the present invention;
[0021] Figure 5 is a schematic diagram showing the variation of the ion concentration corresponding to the first energy injection with the semiconductor depth;
[0022] Figure 6 is a schematic structural diagram after thinning the semiconductor substrate in an embodiment of the present invention;
[0023] Figure 7 is a schematic structural diagram after forming a deep trench isolation structure in a semiconductor substrate in an embodiment of the present invention;
[0024] Figure 8 is a schematic structural diagram after forming a shallow trench isolation structure in a semiconductor substrate in an embodiment of the present invention;
[0025] Figure 9 is a graph showing the simulation experimental results of the number of white pixel points of an image sensor with different epitaxial layer thicknesses of the semiconductor substrate and lengths of the deep trench isolation structure in an embodiment of the present invention.
[0026] Description of Component Labels
[0027] 10 Semiconductor device
[0028] 100 Semiconductor substrate
[0029] 110 photosensitive area
[0030] 120 shallow trench isolation structure
[0031] 130 Deep Trench Isolation Structure
[0032] 210 first ion doping region
[0033] 220 second ion doping region
[0034] 230 third ion doping region
[0035] X First side of semiconductor substrate
[0036] Y The second side of the semiconductor substrate DETAILED DESCRIPTION
[0037] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.
[0038] For example, when describing the embodiments of the present invention, cross-sectional views of device structures may be partially enlarged to scale for ease of explanation. Furthermore, these schematic views are merely illustrative and should not limit the scope of the present invention. Furthermore, in actual manufacturing, three-dimensional dimensions, including length, width, and depth, should be included.
[0039] For convenience, spatially relative terms such as "under," "below," "below," "below," "above," and "on" may be used herein to describe the relationship of one element or feature to other elements or features shown in the drawings. It will be understood that these spatially relative terms are intended to encompass orientations of the device in use or operation in addition to the orientation depicted in the drawings. Additionally, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
[0040] In the context of the present application, a structure described as a first feature being "above" a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features, such that the first and second features may not be in direct contact.
[0041] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.
[0042] The inventors discovered that the etching process of the deep trench isolation process can cause certain damage to the epitaxial layer of the semiconductor substrate, causing dark current in the image sensor and the formation of white pixels. However, a high concentration of P-type ion doping in the pixel periphery can improve dark current and white pixels. Therefore, this application adds an ultra-high ion energy ion implantation before the traditional P-type ion doping process, and thins the epitaxial layer of the semiconductor substrate to a predetermined thickness during the thinning process. This increases the ion concentration of the P-type ion doping region around the pixel periphery, thereby improving the dark current and white pixels of the image sensor.
[0043] Please refer to Figure 1 , Figure 1 The present application provides a method for preparing a semiconductor element, comprising the following steps:
[0044] S1: providing a semiconductor substrate, wherein a first surface of the semiconductor substrate is provided with a photosensitive region of a first ion type;
[0045] S2: performing first energy ion implantation on the first surface of the semiconductor substrate to form a third doped isolation region located below the photosensitive region;
[0046] S3: Perform high-temperature repair on the semiconductor substrate;
[0047] S4: performing second energy ion implantation on the first surface of the semiconductor substrate to form a first doped isolation region and a second doped isolation region located between adjacent photosensitive regions; wherein the energy of the first energy ion implantation is greater than the energy of the second energy ion implantation;
[0048] S5: performing multiple thinning processes on a second surface of the semiconductor substrate opposite to the first surface of the semiconductor substrate, so that the thickness of the epitaxial layer of the semiconductor substrate reaches a preset thickness;
[0049] S6: performing a deep trench isolation process on the second surface of the semiconductor substrate to form a deep trench isolation structure between adjacent photosensitive regions.
[0050] See Figures 2 to 6 , which is a schematic structural diagram of each step in preparing the semiconductor element 10 in this embodiment.
[0051] The following combination Figures 1 to 6 The preparation and structure of the semiconductor element 10 will be described.
[0052] First, see Figure 1 and Figure 2 , perform step S1, provide a semiconductor substrate 100, and the first surface X of the semiconductor substrate 100 is provided with a first ion type photosensitive region 110; specifically, in some embodiments, the semiconductor substrate 100 can be a single crystal silicon, single crystal germanium, or single crystal germanium silicon substrate; in other embodiments, the semiconductor substrate 100 can also be a semiconductor substrate formed by doping the above-mentioned single crystal silicon, single crystal germanium, or single crystal germanium silicon substrate with p-type ions or n-type ions. The material, size, and thickness of the semiconductor substrate 100 are not excessively limited herein; it can be understood that the photosensitive region 110 is an ion-doped region extending from the first surface X of the semiconductor substrate 100 along the second surface Y of the semiconductor substrate 100; specifically, the first ion type photosensitive region 110 is an N-type ion photosensitive region.
[0053] Next, see Figure 1 and Figure 3 , execute step S2, perform first energy ion implantation on the first surface X of the semiconductor substrate 100 to form a third doped isolation region 230 located below the photosensitive region 110; specifically, ion implantation is a method of accurately introducing impurities into a semiconductor, first ionizing the required impurities, and then accelerating them in an electric field to form a concentrated ion beam, which then hits the surface of the semiconductor substrate. These high-energy particles enter the crystal lattice and collide with some atoms in the semiconductor substrate and lose energy, eventually stopping at a certain depth, allowing the ions to penetrate and embed into the semiconductor substrate. Therefore, by using the first energy ion implantation, a third doped isolation region 230 located below the photosensitive region 110 can be formed; specifically, the first energy ion implantation is P-type ion implantation, that is, the third doped isolation region 230 is a P-type ion doped region.
[0054] Next, see Figure 1 and Figure 3 , execute step S3 to perform high-temperature repair on the semiconductor substrate 100; specifically, after high-energy ion implantation, the original lattice structure of the semiconductor substrate is destroyed, and the implanted ions also need to be located at the correct lattice points, so a high-temperature annealing process is required for repair; optionally, the temperature of the high-temperature repair can be set to 1050°C.
[0055] Next, see Figure 1 and Figure 4, executing step S4, performing second energy ion implantation on the first surface X of the semiconductor substrate 100 to form a first doped isolation region 210 and a second doped isolation region 220 located between adjacent photosensitive regions 110; wherein the energy of the first energy ion implantation is greater than the energy of the second energy ion implantation; optionally, the energy of the first energy ion implantation is 1600 KeV, and the energy of the second energy ion implantation is 100-950 KeV. Similarly, by using the second energy ion implantation, the first doped isolation region 210 and the second doped isolation region 220 located between adjacent photosensitive regions can be formed; Figure 5 This is a schematic diagram of the change of ion concentration corresponding to the first energy injection with the depth of the semiconductor. The horizontal axis is the depth of the semiconductor substrate, and the vertical axis is the doping ion concentration. Figure 5 It can be seen that, under the preset ion implantation energy and dopant dosage, the ion concentration varies with the depth of the semiconductor substrate in an arc-like manner. That is, as the depth of the semiconductor increases, the ion concentration first increases gradually. When the depth of the semiconductor substrate reaches the target depth, the ion concentration reaches its maximum, and then decreases gradually. Therefore, after the first surface X of the semiconductor substrate 100 is implanted with the first energy ion and the second energy ion, the doped isolation region diffused from the third doped isolation region 230 overlaps with the doped isolation region formed by the second energy ion implant, forming a second doped isolation region 220 with a higher doped ion concentration than the first doped isolation region 210. Through the two processes of the first energy ion implantation and the second energy ion implantation, the ion concentration of the doped isolation region surrounding the photosensitive region 110 is increased. Since the ion types of the doped isolation region and the photosensitive region are opposite, they can absorb the charge overflow of the photosensitive region, which is beneficial for reducing dark current and the formation of white pixels in the image sensor formed after the subsequent thinning process.
[0056] Next, see Figure 1 and Figure 5 , executing step S5, performing multiple thinning processes on the second surface Y of the semiconductor substrate 100 opposite to the first surface X of the semiconductor substrate 100, so that the thickness of the epitaxial layer of the semiconductor substrate 100 reaches a predetermined thickness; optionally, the multiple thinning processes include: a first thinning of the second surface Y of the semiconductor substrate 100, so that the thickness of the epitaxial layer of the semiconductor substrate 100 reaches 4.7 to 5 microns; a second thinning of the second surface Y of the semiconductor substrate 100, so that the thickness of the epitaxial layer of the semiconductor substrate 100 reaches 3.3 to 3.4 microns; and a third thinning of the second surface Y of the semiconductor substrate 100, so that the thickness of the epitaxial layer of the semiconductor substrate 100 reaches 2.4 to 2.8 microns. Optionally, the epitaxial layer of the semiconductor substrate 100 reaching the predetermined thickness means that the epitaxial layer of the semiconductor substrate 100 has a thickness of 2.4 to 2.8 microns.
[0057] Next, see Figure 1 and Figure 5 Step S6 is performed to carry out a deep trench isolation process on the second side Y of the semiconductor substrate 100 to form a deep trench isolation structure 130 between adjacent photosensitive regions 110. The deep trench isolation process includes etching and defining a trench on the second side of the semiconductor substrate, cleaning and removing the etching by-products, and then growing an oxide layer at high temperature to eliminate the damage to the silicon substrate caused by etching. Then, the trench is filled by chemical vapor deposition, and finally, unnecessary oxides are removed by chemical mechanical polishing to achieve planarization. The deep trench isolation structure is used to prevent signal interference between adjacent photosensitive regions and avoid the negative impact on pixel performance caused by the overflow of photosensitive charges. Optionally, the thickness of the deep trench isolation structure is 1.5 - 1.7 microns.
[0058] In a common image sensor, the thickness of the epitaxial layer of the semiconductor substrate is often more than 3 microns. However, the inventor's research shows that the thinner the semiconductor substrate, the higher the ion doping concentration in the doped isolation region at the top of the deep trench isolation structure, which can absorb the charge overflow of the photosensitive region. Therefore, further reducing the thickness of the semiconductor epitaxial layer in the thinning process is beneficial to reducing the dark current and the formation of white pixel points in the image sensor. The thickness of the epitaxial layer of the semiconductor substrate 100 being 2.4 - 2.8 microns is the limit value for the image sensor to absorb infrared light. Based on the thinning of the epitaxial layer of the semiconductor substrate, considering that the deep trench isolation structure may etch through the semiconductor epitaxial layer, the thickness of the deep trench isolation structure should also be correspondingly thinned. Figure 9 It is a simulation experimental result diagram of the number of white pixel points of an image sensor with different epitaxial layer thicknesses of the semiconductor substrate and different lengths of the deep trench isolation structure. Among them, the abscissa is the number of white pixel points, and the ordinate is the normal distribution number of white pixel points. It can be seen from the figure that compared with the epitaxial layer thickness of 3 microns, the number of white pixel points with an epitaxial layer thickness of 2.6 microns is less. For a 2-micron deep trench isolation structure in a 2.6-micron epitaxial layer, it may etch through the epitaxial layer. Therefore, corresponding to the epitaxial layer thickness of the semiconductor substrate of 2.4 - 2.8 microns, the deep trench isolation structure can be designed to be 1.5 - 1.7 microns.
[0059] In the embodiments of the present application, based on the traditional process of forming a doped isolation region by ion implantation, an additional ion implantation with ultra-high ion energy is added to form a third doped isolation region under the photosensitive region. The third doped isolation region and the first doped isolation region and the second doped isolation region form a "U" - shaped structure surrounding the photosensitive region, further reducing the pixel crosstalk between adjacent photosensitive regions. At the same time, by thinning the epitaxial layer of the semiconductor substrate to a preset thickness, the doped isolation region with a higher ion concentration at the top of the deep trench isolation structure can absorb the overflow charges of the photosensitive region, reducing the formation of dark current and white pixel points in the subsequent image sensor.
[0060] In some embodiments, such as Figure 8As shown, the provided semiconductor substrate 100 includes a shallow trench isolation structure 120. The shallow trench isolation structure 120 is located between adjacent photosensitive regions 110 and can be used to prevent signal interference between adjacent photosensitive regions and avoid the negative impact of photosensitive charge overflow on pixel performance. The shallow trench isolation process, before forming the photosensitive regions, has similar process steps to the deep trench isolation process and will not be repeated here.
[0061] The semiconductor element formed by the above semiconductor element manufacturing method is as follows Figure 7 As shown, the semiconductor element 10 includes:
[0062] The semiconductor substrate 100 has a first surface X and a second surface Y opposite to each other;
[0063] A first ion type photosensitive region 110 is disposed on the first surface X of the semiconductor substrate 100;
[0064] The deep trench isolation structure 130 is located between adjacent photosensitive regions 110 and extends from the second surface Y of the semiconductor substrate 100 to the first surface X of the semiconductor substrate 100;
[0065] A second ion type doped isolation region is arranged around the photosensitive region 110, and the doped isolation region includes a first doped isolation region 210, a second doped isolation region 220 and a third doped isolation region 230 arranged in sequence along the first surface X of the semiconductor substrate 100 pointing to the second surface Y of the semiconductor substrate 100, and the doping concentrations of the first doped isolation region 210, the second doped isolation region 220 and the third doped isolation region 230 gradually increase.
[0066] It can be understood that the first ion type and the second ion type are opposite types, which means that the ion doping types of the photosensitive area 110 and the doped isolation area are opposite, that is, when the photosensitive area 110 is an N-type ion, the doped isolation area is a P-type doped isolation area. The P-type doped isolation area is beneficial to reducing the charge crosstalk between adjacent N-type ion photosensitive areas 110.
[0067] Specifically, the doped isolation region is formed by a first doped isolation region, a second doped isolation region, and a third doped isolation region, each of which has a gradient increasing ion doping concentration. Since the photosensitive region subsequently needs to transfer electrons for quantization, the first doped isolation region with a lower concentration and the second doped isolation region with a higher concentration can improve the ion transfer efficiency of the photosensitive region while reducing pixel crosstalk between adjacent photosensitive regions. The higher ion concentration of the third doped isolation region is beneficial for further reducing dark current and the formation of white pixels in the image sensor.
[0068] Optionally, the thickness of the epitaxial layer of the semiconductor substrate 100 is 2.4 to 2.8 micrometers. It can be understood that the thickness of the epitaxial layer of the semiconductor substrate 100 here refers to the distance from the first surface X of the semiconductor substrate 100 to the second surface Y of the semiconductor substrate 100.
[0069] Optionally, the length of the deep trench isolation structure 130 is 1.5 to 1.7 micrometers. It can be understood that the length of the deep trench isolation structure 130 here refers to the dimension in the direction from the second surface Y of the semiconductor substrate 100 to the first surface X of the semiconductor substrate 100 along the deep trench isolation structure 130.
[0070] Reference Figure 8 , in some embodiments, the semiconductor device further includes: a shallow trench isolation structure 120, located between adjacent photosensitive regions 110, and extending from the first surface X of the semiconductor substrate 100 towards the second surface Y of the semiconductor substrate 100.
[0071] In the embodiments of the present application, based on the conventional process of forming a doped isolation region by ion implantation, an additional ion implantation with ultra-high ion energy is added to form a third doped isolation region under the photosensitive region. The third doped isolation region and the first doped isolation region and the second doped isolation region form a "U" - shaped structure surrounding the photosensitive region, further reducing the pixel crosstalk between adjacent photosensitive regions. At the same time, by thinning the epitaxial layer of the semiconductor substrate to a preset thickness, the doped isolation region with a higher doping ion concentration at the top of the deep trench isolation structure can absorb the overflow charge of the photosensitive region, reducing the formation of dark current and white pixel points in the subsequent image sensor.
[0072] The above content is a further detailed description of the present invention in combination with specific preferred embodiments. It cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention belongs, without departing from the concept of the present invention, several simple deductions or substitutions can still be made, and all should be regarded as belonging to the protection scope of the present invention.
Claims
1. A method for preparing a semiconductor element for an image sensor, characterized in that: include: Providing a semiconductor substrate, wherein a first surface of the semiconductor substrate is provided with a photosensitive region of a first ion type; Performing first energy ion implantation on the first surface of the semiconductor substrate to form a third doped isolation region located below the photosensitive region; performing high-temperature repair on the semiconductor substrate; Performing second energy ion implantation on the first surface of the semiconductor substrate to form a first doped isolation region and a second doped isolation region located between adjacent photosensitive regions; wherein the energy of the first energy ion implantation is greater than the energy of the second energy ion implantation; performing multiple thinning processes on a second surface of the semiconductor substrate opposite to the first surface of the semiconductor substrate so that the thickness of the epitaxial layer of the semiconductor substrate reaches a preset thickness; A deep trench isolation process is performed on the second surface of the semiconductor substrate to form a deep trench isolation structure located between adjacent photosensitive regions.
2. The method for manufacturing a semiconductor device according to claim 1, wherein The step of performing multiple thinning processes on the second surface of the semiconductor substrate opposite to the first surface of the semiconductor substrate so as to make the thickness of the epitaxial layer of the semiconductor substrate reach a preset thickness comprises: thinning the second surface of the semiconductor substrate for the first time so that the thickness of the epitaxial layer of the semiconductor substrate reaches 4.7 to 5 microns; thinning the second surface of the semiconductor substrate for a second time so that the thickness of the epitaxial layer of the semiconductor substrate reaches 3.3 to 3.4 microns; The second surface of the semiconductor substrate is thinned for the third time so that the thickness of the epitaxial layer of the semiconductor substrate reaches 2.4 to 2.8 microns.
3. The method for manufacturing a semiconductor device according to claim 1, wherein: The temperature of the high temperature repair is 1050°C.
4. The method for manufacturing a semiconductor device according to claim 1, wherein The energy of the first energy ion implantation is 1600 KeV, and the energy of the second energy ion implantation is 100-950 KeV.
5. The method for manufacturing a semiconductor device according to claim 1, wherein: The dosage of the first energy ion implantation is greater than the dosage of the second energy ion implantation.
6. A semiconductor element for an image sensor, characterized in that: include: A semiconductor substrate having a first surface and a second surface opposite to each other; A photosensitive region of a first ion type is provided on the first surface of the semiconductor substrate; a deep trench isolation structure, located between adjacent photosensitive regions and extending from the second surface of the semiconductor substrate to the first surface of the semiconductor substrate; A second ion type doped isolation region is arranged around the photosensitive region, and the doped isolation region includes a first doped isolation region, a second doped isolation region and a third doped isolation region which are arranged in sequence along the first surface of the semiconductor substrate in a direction pointing to the second surface of the semiconductor substrate, and the doping concentrations of the first doped isolation region, the second doped isolation region and the third doped isolation region gradually increase.
7. The semiconductor device according to claim 1, wherein The first ion type and the second ion type are opposite types.
8. The semiconductor device according to claim 1, wherein The thickness of the epitaxial layer of the semiconductor substrate is 2.4 to 2.8 microns.
9. The semiconductor device according to claim 1, wherein The length of the deep trench isolation structure is 1.5 to 1.7 microns.
10. The process for manufacturing a semiconductor device according to claim 1, wherein: The semiconductor element further includes: The shallow trench isolation structure is located between adjacent photosensitive regions and extends from the first surface of the semiconductor substrate to the second surface of the semiconductor substrate.