A solar cell and a photovoltaic module

Abstract

This application discloses a solar cell and a photovoltaic module, relating to the field of photovoltaic technology. The solar cell includes: a cell body including a first surface and a second surface disposed opposite to each other; a conductive barrier layer disposed on at least the first surface; and a plurality of first grid lines disposed on the conductive barrier layer, extending along a first direction and arranged along a second direction; the first grid lines are formed from a non-burn-through paste, the resistivity of the first grid lines is 6 μΩ·cm to 60 μΩ·cm, and the cross-sectional area of ​​the first grid lines is greater than or equal to 250 μm². 2 Along the thickness direction of the battery body, the height of the first grid line is h; the width of the first grid line is w, h / w is 0.1 to 0.5, and w ≥ 30 μm; the spacing between two adjacent first grid lines is 0.6 mm to 1.3 mm. To ensure the power generation performance of the solar cell while reducing the manufacturing cost, relatively inexpensive conductive metals such as copper paste can be added to the non-burn-through paste to further reduce the manufacturing cost of the grid lines.

Description

[0001] This application claims priority to the Chinese patent application No. 202510214993.0, filed on February 25, 2025, entitled "A solar cell and a photovoltaic module", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the field of photovoltaic technology, in particular to a solar cell and a photovoltaic module. BACKGROUND

[0003] At present, solar cells are used more and more widely as a new energy alternative. Among them, photovoltaic solar cells are devices that convert solar light energy into electrical energy. Specifically, solar cells use the photovoltaic principle to generate carriers, and then use electrodes to lead out the carriers, thereby facilitating the effective use of electrical energy.

[0004] With the continuous expansion of the photovoltaic industry market and production capacity, the demand for silver paste in the industry has also increased synchronously, and the price of silver paste has risen accordingly, with rising costs and increasingly squeezed profit margins. SUMMARY

[0005] The purpose of the present application is to provide a solar cell and a photovoltaic module to ensure the power generation performance of the solar cell while reducing the manufacturing cost of the solar cell.

[0006] In order to achieve the above-mentioned purpose, the present application provides the following technical solutions:

[0007] A solar cell, comprising:

[0008] a cell body comprising a first surface and a second surface arranged oppositely;

[0009] a conductive barrier layer arranged on at least the first surface;

[0010] a plurality of first grid lines arranged on the conductive barrier layer, extending along a first direction and arranged along a second direction, the first direction and the second direction intersecting; the first grid lines are formed by non-burn-through paste, the resistivity of the first grid lines is 6 μΩ·cm-60 μΩ·cm, and the cross-sectional area of the first grid lines along a plane perpendicular to the first direction is greater than or equal to 250 μm 2 ;

[0011] The height of the first grid lines along the thickness direction of the cell body is h, the width of the first grid lines is w, h / w is 0.1-0.5, and w≥30 μm;

[0012] The spacing between two adjacent first grid lines is 0.6 mm-1.3 mm.

[0013] This application uses a non-burn-through paste, which can incorporate relatively inexpensive conductive metals such as copper paste to reduce the manufacturing cost of the gate wire. Furthermore, addressing technical issues such as low gate wire current collection efficiency and high contact resistance, this application comprehensively considers various parameters, including the resistivity, cross-sectional area, aspect ratio (h / w), width (w), and spacing between adjacent gate wires, ensuring that these parameters are within reasonable ranges and mutually matched. This guarantees low collection efficiency and reduced contact resistance for the first gate wire. Simultaneously, to prevent the non-burn-through paste from damaging the passivation effect of the doped semiconductor layer, this application also includes a conductive barrier layer. This layer separates the first gate wire from the first doped semiconductor layer, ensuring both passivation and conductivity between the two layers.

[0014] A photovoltaic module includes a solar cell as described in any one of the above description and a first conductive element, the first conductive element extending along a second direction and electrically connected to a first grid line.

[0015] Compared with the prior art, the beneficial effects of the photovoltaic module provided in this application are the same as those of the solar cell described above, and will not be repeated here. Attached Figure Description

[0016] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0017] Figure 1 A top view of a solar cell provided in an embodiment of this application;

[0018] Figure 2 A partial cross-sectional view of a solar cell provided in an embodiment of this application;

[0019] Figure 3 A top-view SEM image of the first gate line provided in an embodiment of this application;

[0020] Figure 4 A top view of a solar cell provided in another embodiment of this application;

[0021] Figure 5 for Figure 4 A partial sectional view along the A1-A2 line;

[0022] Figure 6 A top view of a solar cell provided in another embodiment of this application;

[0023] Figure 7 SEM image of the conductive barrier layer provided in the embodiments of this application;

[0024] Figure 8 SEM image of the first gate line provided in the embodiments of this application;

[0025] Figure 9 SEM image of the modified layer provided in another embodiment of this application;

[0026] Figure 10 for Figure 9 A partial cross-sectional view;

[0027] Figure 11 for Figure 9 A magnified view of a portion of the image;

[0028] Figure 12 A partial cross-sectional view of a solar cell provided in another embodiment of this application;

[0029] Figure 13 A partial cross-sectional view of a solar cell provided in another embodiment of this application;

[0030] Figure 14 Cross-sectional SEM image of the conductive barrier layer and the first gate line provided in another embodiment of this application;

[0031] Figure 15 A top view of a solar cell provided in an embodiment of this application;

[0032] Figure 16 for Figure 15 A sectional view;

[0033] Figure 17 This is a schematic diagram of the connection between the first grid line and the main grid;

[0034] Figure 18 A top view of a solar cell provided in another embodiment of this application;

[0035] Figure 19 for Figure 18 A sectional view;

[0036] Figure 20 This is a schematic diagram of the connection between the first grid line and the solder strip.

[0037] Figure label:

[0038] 1-First gate line, 1a-Linear particle, 1b-Spherical particle, 1c-Flared particle, 1d-V-shaped particle, 1e-Thickened section, 101-Main body, 102-Spreading part, 2-Passivation layer, 2a-Opening, 2b-Heat affected region, 3-First doped semiconductor layer, 3a-Modified layer, 3a1-Pit, 3b-Metal crystal layer, 4-Semiconductor substrate, 5-Conductive barrier layer, 5a-Conductive material, 5b-Conductive channel, 5c-Pore, 6-Insulating block, 7-First conductive element, 7a-Side protrusion, 8-Second gate line, 9-First interface layer, 10-Second doped semiconductor layer, 11-Second interface layer, 12-Binding layer. Detailed Implementation

[0039] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0040] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0041] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise expressly specified. "Several" means one or more, unless otherwise expressly specified.

[0042] In the description of this application, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0043] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0044] In the manufacturing process of solar cells, the reliance on silver for grid lines has always been significant. Currently, the main method for forming electrode patterns is to use silver paste printed on a screen to create silver grid lines. Silver grid lines are a major limiting factor for cost reduction in solar cells or photovoltaic modules. Copper, as a metal element with decent electrical conductivity and low price, has received much attention. However, grid lines formed from copper paste currently suffer from problems such as low current collection efficiency and high contact resistance, which hinders the mass production of copper paste.

[0045] In light of the above, please refer to Figures 1-2 The solar cell provided in this application includes a cell body, a conductive barrier layer 5, and a plurality of first grid lines 1. The cell body includes opposing first and second surfaces, meaning that two opposing surfaces along the thickness direction of the cell body are respectively the first surface and the second surface. The first surface can correspond to the back surface of the solar cell, and the second surface can correspond to the light-facing surface of the solar cell; alternatively, the first surface can correspond to the light-facing surface of the solar cell, and the second surface can correspond to the back surface of the solar cell.

[0046] The battery body may include a semiconductor substrate 4, a first doped semiconductor layer 3, a second doped semiconductor layer 10, and a passivation layer 2. A conductive barrier layer 5 is disposed at least on the first surface, i.e., a conductive barrier layer 5 is disposed on the first surface; or a conductive barrier layer 5 is disposed on both the first and second surfaces. Specifically, the conductive barrier layer 5 may be partially disposed on the first surface. Multiple first gate lines 1 are disposed on the conductive barrier layer 5, i.e., the conductive barrier layer 5 is located between the battery body and the first gate lines 1. The function of the conductive barrier layer 5 is to separate the first gate lines 1 from the first doped semiconductor layer 3, while ensuring the conductivity between the first gate lines 1 and the first doped semiconductor layer 3.

[0047] like Figure 1As shown, multiple first grid lines 1 extend along a first direction and are arranged along a second direction, meaning the length of the first grid lines 1 is set along the first direction. The first and second directions intersect, meaning the first direction is different from the second direction, and the angle between the first and second directions can be an acute angle or a right angle. The first direction can be either the length direction of the battery body or the width direction of the battery body. When the first direction is the length direction of the battery body, the second direction is the width direction of the battery body; when the first direction is the width direction of the battery body, the second direction is the length direction of the battery body.

[0048] The first gate line 1 is formed from a non-burn-through paste, which may include one or more of low-temperature silver paste, copper paste, and aluminum paste. The first gate line 1 can be formed corresponding to the opening region 2a using processes such as screen printing, electroplating, sputtering, or vapor deposition. The non-burn-through paste refers to a paste that cannot directly penetrate the passivation layer 2 through sintering to achieve contact with the first doped semiconductor layer 3. Generally, the first gate line 1 formed from this non-burn-through paste ultimately retains a binder material, such as organic components.

[0049] The first grid line 1 formed by non-burn-through slurry generally has a high resistivity because it contains organic materials that cannot be sintered and volatilized. These organic materials can increase adhesion, but the resistivity of the first grid line 1 needs to be kept within a reduced range, for example, less than 80 μΩ·cm. In some embodiments, the resistivity of the first grid line 1 is 6 μΩ·cm to 60 μΩ·cm, so that the cross-sectional area of ​​the first grid line 1 can be kept within a reasonable range. This prevents the first grid line 1 from having an excessively high resistivity, which would result in a large cross-sectional area, wasting raw materials and causing severe light shading. At the same time, it avoids the first grid line 1 having an excessively low resistivity, which would require higher quality raw materials and increase the raw material cost of the first grid line 1.

[0050] In some embodiments, if the cross-sectional area of ​​the first gate line 1 is too small, it will result in excessive line resistance of the first gate line 1, affecting current transmission. Therefore, in this application, the cross-sectional area of ​​the first gate line 1 along the plane perpendicular to the first direction is greater than or equal to 250 μm. 2 For cross-sectional areas greater than or equal to 250 μm 2 When the resistivity of the first gate line 1 is matched to 6μΩ·cm to 60μΩ·cm, the gate line can achieve high current collection efficiency and ensure low transmission resistance.

[0051] Furthermore, along the thickness direction of the battery body, the height of the first gate line 1 is h; the width of the first gate line 1 is w, and h / w ​​is 0.1 to 0.5. When the aspect ratio of the first gate line 1 is less than 0.1, the width of the first gate line 1 needs to be wider, which leads to an increase in the light-shielding area of ​​the first gate line 1, reducing the light absorption utilization rate. At the same time, the area of ​​the passivation layer 2 opening 2a needs to be increased accordingly, and the damage to the first doped semiconductor layer 3 caused by the opening 2a process will also increase. When the aspect ratio of the first gate line 1 is greater than 0.5, the height of the first gate line 1 needs to be higher, which makes it easy for the gate to break during printing. Therefore, in order to balance the above two aspects, h / w is 0.1 to 0.5 in this application to reduce the light-shielding area and light loss, improve the light absorption utilization rate, reduce the damage to the first doped semiconductor layer 3, and reduce the risk of gate breakage during printing.

[0052] To ensure the cross-sectional area is greater than or equal to 250 μm 2 Furthermore, the height and width are between 0.1 and 0.5, and the width w of the first gate line 1 needs to be greater than or equal to 30 μm to ensure the transmission efficiency of the first gate line 1 and reduce the contact resistance of the first gate line 1.

[0053] Furthermore, the spacing between two adjacent first grid lines 1 also affects the light-transmitting area. If the spacing between two adjacent first grid lines 1 is too small, the light-transmitting area between them will be small, affecting the light absorption and utilization rate; if the spacing between two adjacent first grid lines 1 is too large, the current collection efficiency will be reduced. Therefore, in this application, the spacing between two adjacent first grid lines 1 is 0.6mm to 1.3mm to ensure a reasonable light-transmitting area between them and to guarantee the current collection efficiency while improving the current collection efficiency on both sides of the first grid line 1.

[0054] As can be seen from the above, this application uses a non-burn-through paste, which can incorporate relatively inexpensive conductive metals such as copper paste to reduce the manufacturing cost of the gate wire. Furthermore, addressing technical issues such as low current collection efficiency and high contact resistance of the gate wire, this application comprehensively considers various parameters, including the resistivity of the first gate wire 1, the cross-sectional area of ​​the first gate wire 1, the aspect ratio h / w of the first gate wire 1, the width w of the first gate wire 1, and the spacing between two adjacent first gate wires 1. This ensures that the resistivity, cross-sectional area, aspect ratio h / w, width w, and spacing between two adjacent first gate wires 1 are all within the aforementioned reasonable ranges and are mutually matched, thereby guaranteeing low current collection efficiency and reducing contact resistance of the first gate wire 1. Meanwhile, in order to prevent non-burn-through paste from damaging the passivation effect of the doped semiconductor layer, a conductive barrier layer 5 is also provided in this application. The conductive barrier layer 5 can separate the first gate line 1 and the first doped semiconductor layer 3, ensuring the passivation effect of the doped semiconductor layer while also ensuring the conductivity between the first gate line 1 and the first doped semiconductor layer 3.

[0055] Exemplarily, the resistivity of the first grid line 1 is 6 μΩ·cm, 8 μΩ·cm, 10 μΩ·cm, 12 μΩ·cm, 15 μΩ·cm, 18 μΩ·cm, 20 μΩ·cm, 22 μΩ·cm, 25 μΩ·c m, 28μΩ·cm, 30μΩ·cm, 32μΩ·cm, 35μΩ·cm, 38μΩ·cm, 40μΩ·cm, 45μΩ·cm, 50μΩ·cm, 55μΩ·cm or 60μΩ·cm, etc.

[0056] Along a plane perpendicular to the first direction, the cross-sectional area of ​​the first gate line 1 is 250 μm. 2 260μm 2 270μm 2 280μm 2 290μm 2 300μm 2 320μm 2 350μm 2 380μm 2 400μm 2 420μm 2 450μm 2 480μm 2 or 500μm 2 wait.

[0057] The aspect ratio h / w of the first grid line 1 is 0.1, 0.15, 0.2, 0.25, 0.3, 0.35, 0.4, 0.45, or 0.5, etc. Optionally, the aspect ratio h / w of the first grid line 1 is 0.1 to 0.25.

[0058] The width w of the first gate line 1 is 30μm, 40μm, 50μm, 60μm, 70μm, 80μm, 90μm, 100μm, 110μm, 120μm, 130μm, 140μm, 150μm, 160μm, 170μm or 180μm, etc.

[0059] The spacing between two adjacent first grid lines 1 can be 0.6mm, 0.7mm, 0.8mm, 0.9mm, 1mm, 1.1mm, 1.2mm or 1.3mm, etc.

[0060] The applicant selected the above-mentioned printable paste with the required resistivity to form the first grid line 1. The first grid line 1 is a fine grid with a spacing of 0.9 mm between adjacent first grid lines 1. The battery was tested using a 182 mm * 91 mm half-cell cell. The test results are shown in the table below:

[0061]

[0062]

[0063] As shown in the table above, when other parameters meet the requirements, the efficiency of solar cells can be maintained above 26% when the aspect ratio of the fine grid is between 0.1 and 0.5.

[0064] Considering that if the first gate line 1 is too wide, it will increase the light-blocking area and light loss, reducing the light absorption and utilization rate; if the first gate line 1 is too narrow, it will increase the contact resistance of the first gate line 1, reducing the photoelectric conversion efficiency. In view of these two situations, in this technical solution, the width w of the first gate line 1 is set within a reasonable range of 140μm ≥ w ≥ 30μm, in order to reduce the light-blocking area and light loss, improve the light absorption and utilization rate, and at the same time reduce the contact resistance of the first gate line 1, thereby improving the current transmission efficiency.

[0065] In other embodiments, considering that if the height of the first gate line 1 is too high, it is prone to gate breakage during printing, affecting product yield; if the height of the first gate line 1 is too small, the width of the first gate line 1 will need to be wider, which will lead to an increase in the light-blocking area of ​​the first gate line 1 and reduce the light absorption and utilization rate. In view of the above two situations, in this technical solution, the height h of the first gate line 1 is set within a reasonable range of 5μm≥h≥25μm, which reduces the light-blocking area and light loss while ensuring product yield.

[0066] For example, the height h of the first gate line 1 can be 5μm, 8μm, 10μm, 12μm, 15μm, 18μm, 20μm, 22μm or 25μm, etc.

[0067] In some embodiments, the first gate line 1 is made of copper paste material, and the cured first gate line 1 includes copper powder and organic matter. Copper has acceptable electrical conductivity and is inexpensive, so the inclusion of copper powder in the first gate line 1 in this technical solution reduces manufacturing costs compared to the prior art where the first gate line 1 only includes silver. Furthermore, the organic matter has good adhesion; the particles contained in the copper powder can be bonded together by the organic matter, and the organic matter can improve the adhesion between the first gate line 1 and the first surface, preventing the first gate line 1 from detaching from the first surface.

[0068] like Figure 8 As shown, the copper powder includes at least flake-shaped particles 1c and spherical particles 1b. The flake-shaped particles 1c are generally flat, and their edges can be rounded, serrated, or any irregular edge. The spherical particles 1b can be spherical, ellipsoidal, near-spherical, or near-ellipsoidal in shape. The flake-shaped particles 1c have a larger contact area with other conductive particles, which is beneficial for reducing contact resistance, while the spherical particles 1b have a larger contact area with organic matter, which is beneficial for the formation of the gate line. Therefore, in this technical solution, the copper powder includes both flake-shaped particles 1c and spherical particles 1b, which not only ensures that the first gate line 1 has a suitable resistivity but also facilitates the printing and forming of the first gate line 1.

[0069] like Figure 8 As shown, the copper powder may also include one or more of linear particles 1a, V-shaped particles 1d, polygonal particles, and cylindrical particles. Specifically, the copper powder may include particles of any shape. The various shapes of particles have more contact points, which is beneficial for the contact and conduction between adjacent conductive particles, thereby ensuring that the first gate line 1 has a suitable resistivity.

[0070] In some embodiments, if the diameter of the flake particles 1c is too large, it will prevent them from passing through the printing mesh during the printing process; if the diameter of the flake particles 1c is too small, the content of organic matter in the gaps between the particles will be insufficient, which is not conducive to the formation of the first grid line 1. Based on this, in this technical solution, the median diameter of the flake particles 1c is 0.8μm to 5μm. The diameter of the flake particles 1c can be an equivalent diameter, specifically, it can be a sieve equivalent diameter, a volume equivalent diameter, or a surface area equivalent diameter. Using this technical solution, the diameter of most of the flake particles 1c is within a reasonable range, which can prevent the flake particles 1c from being too large to pass through the mesh, and also ensure the content of organic matter in the gaps between the particles, thereby improving the adhesion of the first grid line 1.

[0071] For example, the median diameter of the sheet-like particles 1c is 0.8 μm, 1 μm, 1.2 μm, 1.5 μm, 1.8 μm, 2 μm, 2.2 μm, 2.5 μm, 2.8 μm, 3 μm, 3.2 μm, 3.5 μm, 3.8 μm, 4 μm, 4.2 μm, 4.5 μm, 5.8 μm, or 5 μm, etc.

[0072] Furthermore, the median thickness of the sheet-like particles 1c is between 100 nm and 500 nm, ensuring that the thickness of most sheet-like particles 1c is within a reasonable range. This guarantees low contact resistance between the sheet-like particles 1c and other conductive particles, while preventing excessively thin sheet-like particles 1c from having excessively high transmission resistance, thus resulting in a low transmission resistance of the sheet-like particles 1c themselves. For example, the median thickness of the sheet-like particles 1c can be 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, or 500 nm.

[0073] In some embodiments, if the spacing between spherical particles 1b is too large, the contact area between spherical particles 1b and other conductive particles will be further reduced, increasing the resistivity of the first grid line 1. If the spacing between spherical particles 1b is too small, the content of organic matter in the gaps between particles will be low, which is not conducive to the formation of the first grid line 1. Based on this, in this technical solution, the median particle size of the spherical particles 1b is 100nm to 500nm. The diameter of the spherical particles 1b can be an equivalent diameter, specifically, it can be a sieve equivalent diameter, a volume equivalent diameter, or a surface area equivalent diameter. Using this technical solution, the diameter of most spherical particles 1b is within a reasonable range, which not only keeps the resistivity of the first grid line 1 within a reasonable range but also ensures the content of organic matter in the gaps between particles, improving the adhesion of the first grid line 1.

[0074] For example, the median particle size of spherical particle 1b is 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, 400nm, 450nm or 500nm, etc.

[0075] In other embodiments, the mass percentage of the flake particles 1c is 35% to 60%, meaning that the mass percentage of the flake particles 1c in the slurry forming the first grid line 1 is 35% to 60% of the total slurry mass. This ensures that the content of the flake particles 1c in the slurry is within a reasonable range, and that the contact area between the flake particles 1c and other conductive particles is large, which is beneficial for reducing the resistivity of the first grid line 1 formed by the slurry. For example, the mass percentage of the flake particles 1c is 35%, 38%, 40%, 42%, 45%, 48%, 50%, 52%, 55%, 58%, or 60%, etc.

[0076] In other embodiments, the mass percentage of spherical particles 1b is 35% to 60%, meaning that the mass percentage of spherical particles 1b in the slurry forming the first grid line 1 is 35% to 60% of the total slurry mass. This ensures that the content of spherical particles 1b in the material is within a reasonable range, resulting in a larger contact area between the spherical particles 1b and the organic matter, which is beneficial for the formation of the first grid line 1. For example, the mass percentage of spherical particles 1b can be 35%, 38%, 40%, 42%, 45%, 48%, 50%, 52%, 55%, 58%, or 60%, etc.

[0077] In some embodiments, the tap density of the sheet-like particles 1c is 3 g / ml to 6 g / ml, which ensures the compactness of the sheet-like particles 1c and further guarantees the current transmission efficiency of the sheet-like particles 1c. For example, the tap density of the sheet-like particles 1c is 3 g / ml, 3.5 g / ml, 4 g / ml, 4.5 g / ml, 5 g / ml, 5.5 g / ml, or 6 g / ml.

[0078] In some embodiments, the tap density of the spherical particles 1b is 3.5 g / ml to 5.5 g / ml, thus ensuring the compactness of the spherical particles 1b. For example, the tap density of the spherical particles 1b is 3.5 g / ml, 4 g / ml, 4.5 g / ml, 5 g / ml, or 5.5 g / ml, etc.

[0079] Tap density, or bulk density of powder after compaction, refers to the density of powder after it has been packed into a specific container and the container has been vibrated to break up the voids in the powder and bring it into a tightly packed state. Measuring tap density can determine the flowability and porosity of the powder. It can be calculated by measuring the volume after 1000 vibrations using a BT-301 tap density meter.

[0080] Furthermore, the specific surface area of ​​the flaky particles 1c is 0.4 m². 2 / g~0.7m 2 / g, so that the plate-like particles 1c can have a reasonable contact area with other conductive particles, thereby reducing the resistivity of the first gate line 1. For example, the specific surface area of ​​the plate-like particles 1c is 0.4m². 2 / g, 0.45m 2 / g, 0.5m 2 / g, 0.55m 2 / g, 0.6m 2 / g, 0.65m 2 / g or 0.7m 2 / g etc.

[0081] The specific surface area of ​​spherical particle 1b is 1.5 m². 2 / g~3.5m 2 / g, so that the spherical particles 1b can have a larger contact area with the organic matter, thereby improving the adhesion of the first grid line 1. For example, the specific surface area of ​​the spherical particles 1b is 1.5m². 2 / g, 1.52m 2 / g, 1.55m 2 / g, 1.58m 2 / g、2m 2 / g, 2.2m 2 / g, 2.5m 2 / g, 2.8m 2 / g、3m 2 / g, 3.2m 2 / g or 3.5m 2 / g etc.

[0082] Specific surface area refers to the surface area per unit mass of porous solid material, which can be tested using conventional methods, such as GB / T 13390-2008, the method for determining the specific surface area of ​​metal powders.

[0083] In some embodiments, the organic material includes one or more of the following: saturated / unsaturated fatty acids containing 8-18 carbon atoms, silane coupling agents, PVP, and thiols. These organic materials have high adhesion and are reasonably priced, making them suitable for forming the first grid line 1.

[0084] like Figure 2 and 3 As shown, the first grid line 1 includes a main body portion 101 and a spreading portion 102 arranged along a second direction, and the main body portion 101 and the spreading portion 102 extend along a first direction. That is, the spreading portion 102 is formed on both sides of the main body portion 101. Specifically, during the grid line fabrication process, after slurry printing or laser transfer, and before the slurry cures, the slurry (such as one or more organic substances in the slurry) diffuses onto the battery cell surfaces on both sides of the main body portion 101, forming the spreading portion 102 on both sides of the main body portion 101. Using this technical solution, forming the spreading portion 102 on both sides of the main body portion 101 can increase the width of the root of the first grid line 1, thereby increasing the contact area between the first grid line 1 and the first surface, thus reducing the contact resistance of the first grid line 1, and simultaneously improving the adhesion between the first grid line 1 and the first surface, preventing the first grid line 1 from detaching.

[0085] In some embodiments, such as Figure 2As shown, along the second direction, the width W1 of the main body 101 is 30μm to 120μm, which facilitates controlling the cross-sectional area of ​​the first gate line 1 within a reasonable range based on the width W1 of the main body 101. For example, the width W1 of the main body 101 can be 30μm, 35μm, 40μm, 45μm, 50μm, 55μm, 60μm, 65μm, 70μm, 75μm, 80μm, 85μm, 90μm, 95μm, 100μm, 105μm, 110μm, 105μm, or 120μm, etc.

[0086] like Figure 2 As shown, considering that an excessively wide spreading portion 102 (W2) would extend into areas with opposite polarity, leading to leakage, and that an excessively small spreading portion 102 (W2) would reduce the adhesion between the first gate line 1 and the first surface, this technical solution uses a spreading portion 102 width of 1μm-60μm along the second direction to reduce the risk of leakage while ensuring adhesion between the first gate line 1 and the first surface. For example, the spreading portion 102 width (W2) can be 1μm, 5μm, 10μm, 15μm, 20μm, 25μm, 30μm, 35μm, 40μm, 45μm, 50μm, 55μm, or 60μm, etc.

[0087] Along the second direction, the width of the spreading portion 102 is 5%-50% of the width of the main body portion 101 to reduce the risk of leakage current while ensuring the adhesion between the first grid line 1 and the first surface. For example, the width of the spreading portion 102 is 5%, 10%, 15%, 20%, 25%, 30%, 35%, 40%, 45%, or 50% of the width of the main body portion 101.

[0088] It should be noted that, as mentioned above, the width of the first grid line 1 is the sum of the widths of the main body 101 and the spreading part 102. The height of the first grid line 1 is the same as the height of the main body 101.

[0089] like Figure 2 As shown, along the thickness direction of the battery body, the height h1 of the main body 101 is 8μm to 25μm to prevent the height h1 of the main body 101 from being too high, which would increase the risk of grid breakage, and at the same time to prevent the height of the main body 101 from being too low, which would affect the current transmission efficiency of the grid lines. For example, the height h1 of the main body 101 is 8μm, 10μm, 12μm, 15μm, 18μm, 20μm, 22μm, or 25μm, etc.

[0090] Along the thickness direction of the battery body, the height of the main body 101 is h1, and the height of the spreading part 102 is h2, where h2 ≤ 1 / 3h1. This technical solution ensures that the height h2 of the spreading part 102 and the height h1 of the main body 101 are in a reasonable ratio. This prevents the spreading part 102 from being too high, which would reduce the cross-sectional area of ​​the main body 101 and increase its resistivity, thereby guaranteeing the overall current transmission efficiency of the first grid line 1. For example, h2 can be 1 / 3h1, 0.3h1, 0.25h1, 0.2h1, 0.15h1, or 0.1h1, etc.

[0091] In some embodiments, the median particle size of the copper powder contained in the spreading portion 102 is smaller than the median particle size of the copper powder contained in the main body portion 101, wherein the copper powder particle size can also be an equivalent diameter. That is, the particle size of most of the copper powder contained in the spreading portion 102 is smaller than the particle size of most of the copper powder contained in the main body portion 101. This arrangement makes the particle size of the copper powder contained in the spreading portion 102 more closely match the thickness of the spreading portion 102, thereby improving the conductivity of the spreading portion 102.

[0092] In this embodiment, the battery body includes a semiconductor substrate 4, a first doped semiconductor layer 3, a second doped semiconductor layer 10, and a passivation layer 2. The first doped semiconductor layer 3 and the second doped semiconductor layer 10 have opposite conductivity types to collect and export electrons and holes respectively, which is beneficial for the formation of photocurrent. The two opposite sides of the semiconductor substrate 4 correspond to the first surface and the second surface, respectively. The first doped semiconductor layer 3 is disposed on the first surface of the semiconductor substrate 4. The first doped semiconductor layer 3 can be formed in the semiconductor substrate 4 by diffusion, ion implantation, or other methods, or it can also be additionally formed on the semiconductor substrate 4 by deposition technology. The passivation layer 2 at least covers the side of the first doped semiconductor layer 3 facing away from the semiconductor substrate 4. A conductive barrier layer 5 passes through the passivation layer 2 and is electrically connected to the first doped semiconductor layer 3. The charge carriers collected by the first doped semiconductor layer 3 are exported through the conductive barrier layer 5 and the first gate line 1.

[0093] The passivation layer 2 can be a single layer or multiple layers, including at least one of aluminum oxide, silicon oxide, and silicon nitride. The thickness of the passivation layer 2 is 50 nm to 400 nm, for example, 50 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, or 400 nm. The passivation layer 2 can passivate the surface of the battery body or the doped layer, reducing its carrier recombination rate and further improving the photoelectric conversion efficiency of the solar cell.

[0094] In some embodiments, such as Figure 12 As shown, the conductive barrier layer 5 can be discontinuously disposed along the first direction. This can appropriately reduce the consumption of raw materials for the conductive barrier layer 5, saving raw materials and reducing the manufacturing cost of the solar cell. Alternatively, as...Figure 13 As shown, the conductive barrier layer 5 can be continuously disposed along the first direction, which can increase the contact area between the conductive barrier layer 5 and the first gate line 1, and reduce the contact resistance and current transmission loss between the conductive barrier layer 5 and the first gate line 1.

[0095] In some embodiments, the passivation layer 2 has an opening 2a that exposes the first doped semiconductor layer 3; the first gate line 1 covers the opening 2a and is electrically connected to the first doped semiconductor layer 3 to facilitate the collection and discharge of carriers collected by the first doped semiconductor layer 3 by the first gate line 1.

[0096] Among them, such as Figure 4 As shown, multiple apertures 2a corresponding to the same gate line can be arranged in at least one row along the first direction, that is, multiple apertures 2a can be distributed in one row and arranged sequentially along the first direction. Alternatively, multiple apertures 2a can be distributed in multiple rows, with each row of apertures 2a arranged sequentially along the first direction. For example, multiple apertures 2a can also be distributed in two, three, or more rows. In this way, the distribution of multiple apertures 2a is more uniform, and the position distribution of the electrical connection between the first gate line 1 and the first doped semiconductor layer 3 is more uniform, which is beneficial for the first gate line 1 to conduct current from various positions of the first doped semiconductor layer 3 in a timely manner, avoiding local overheating. Or, as Figure 6 As shown, the opening 2a corresponding to the same gate line can be a strip-shaped opening. The orthographic projection of the opening 2a corresponding to the same gate line on the first surface is located inside the orthographic projection of the gate line on the first surface.

[0097] In some embodiments, direct contact between the copper paste in the first gate line 1 and the first doped semiconductor layer 3 reduces the passivation effect of the first doped semiconductor layer 3. Based on this, such as Figure 5 and Figure 7 As shown, in this technical solution, the conductive barrier layer 5 fills the opening 2a to completely separate the first doped semiconductor layer 3 and the first gate line 1, thereby improving the passivation effect of the first doped semiconductor layer 3. The thickness of the conductive barrier layer 5 can be greater than or equal to the thickness of the passivation layer 2 to ensure the isolation effect. During the manufacturing process, multiple through openings 2a can be formed on the passivation layer 2 using a patterning process (such as laser aperture forming process), and then the conductive barrier layer 5 can be formed through processes such as electroplating and chemical plating. The conductive barrier layer 5 can be a metal barrier material such as nickel, silver, or titanium.

[0098] In some embodiments, such as Figure 2As shown, the thickness of the portion of the conductive barrier layer 5 corresponding to the area of ​​the opening 2a is greater than the thickness of the passivation layer 2. With this configuration, the portion of the conductive barrier layer 5 extending beyond the opening 2a can extend to the side surface of the passivation layer 2 facing away from the semiconductor substrate 4, thereby increasing the width of the conductive barrier layer 5, which in turn increases the contact area between the conductive barrier layer 5 and the first gate line 1, and reduces the contact resistance and current transmission loss between the conductive barrier layer 5 and the first gate line 1.

[0099] On the one hand, if the thickness of the conductive barrier layer 5 is too large, it wastes raw materials and requires a longer processing time for electroplating, electroless plating, etc., reducing processing efficiency. On the other hand, if the thickness of the conductive barrier layer 5 is too small, it cannot effectively isolate the first gate line 1 and the first doped semiconductor layer 3, ensuring the passivation effect of the passivation layer 2. Therefore, in order to balance the above two aspects, in this technical solution, the thickness of the portion of the conductive barrier layer 5 corresponding to the area of ​​the opening 2a is set within a reasonable range of 0.5μm to 5μm. This effectively isolates the first gate line 1 and the first doped semiconductor layer 3, ensuring the passivation effect of the passivation layer 2, while reducing the waste of raw materials for the conductive barrier layer 5 and improving processing efficiency. For example, the thickness of the portion of the conductive barrier layer 5 corresponding to the area of ​​the opening 2a is 0.5μm, 1μm, 1.5μm, 2μm, 2.5μm, 3μm, 3.5μm, 4μm, 4.5μm, or 5μm, etc.

[0100] like Figure 5 As shown, the solar cell also includes a modified layer 3a. The modified layer 3a is formed in the region corresponding to the first doped semiconductor layer 3 and the opening 2a. Alternatively, the modified layer 3a can also be formed in the region surrounding the first doped semiconductor layer 3 and the opening 2a. This modified layer 3a can be formed under the influence of laser heat during the laser-induced opening 2a process. For example, Figure 9 A modified layer 3a is formed in the region corresponding to the first doped semiconductor layer 3 and the circular opening.

[0101] Among them, such as Figure 10 As shown, the roughness of the modified layer 3a is greater than that of the other parts of the first doped semiconductor layer 3. This configuration increases the contact area between the conductive barrier layer 5 and the modified layer 3a, improves the adhesion between them, and reduces the contact resistance.

[0102] The modified layer 3a has a lower degree of crystallinity than the first doped semiconductor layer 3 in other parts, thus enabling the modified layer 3a to better block copper paste. The degree of crystallinity includes indicators such as crystallinity, number of grains, and grain size.

[0103] The thickness of the modified layer 3a can be 5nm to 20nm, for example, the thickness of the modified layer 3a can be 5nm, 8nm, 10nm, 12nm, 15nm, 18nm or 20nm, etc.

[0104] In some embodiments, such as Figure 5 As shown, the passivation layer 2 has a heat-affected zone 2b surrounding the opening 2a. Specifically, during the laser-driven grooving process of the passivation layer 2, the area near the edge of the opening 2a, although not removed, is affected by laser heat and is called the heat-affected zone 2b. This heat-affected zone 2b surrounds the opening 2a. The shape of the opening 2a can be circular, elliptical, rectangular, or other shapes, and the surrounding shape of the heat-affected zone 2b also changes with the shape of the opening 2a; its annular shape can be a circular ring, an elliptical ring, or a rectangular ring, etc. The width of the modified layer 3a can reach the boundary of the heat-affected zone 2b.

[0105] In some embodiments, the width of the heat-affected zone 2b is D, where 1 μm ≤ D ≤ 5 μm. This avoids the heat-affected zone 2b being too wide, which would reduce the passivation effect. For example, D can be 1 μm, 2 μm, 3 μm, 4 μm, or 5 μm, etc.

[0106] In some embodiments, such as Figure 5 As shown, during the laser drilling of hole 2a, the laser energy at the edge position is appropriately increased, for example, to greater than 200 J / cm. 2 The passivation layer 2 material in the heat-affected zone 2b will be opened, forming multiple holes and / or cracks. The purpose of this arrangement is that if holes and / or cracks do not form in the heat-affected zone 2b, the thermal damage to the first doped semiconductor layer 3 corresponding to the location of the heat-affected zone 2b cannot be repaired. In this embodiment, the holes and / or cracks are filled with conductive material 5a, which is electrically connected to the first doped semiconductor layer 3. Specifically, the conductive material 5a within the holes and / or cracks can contact the modified layer 3a or other parts of the first doped semiconductor layer 3. With this arrangement, the first gate line 1, while passing through the opening 2a and electrically connecting to the first doped semiconductor layer 3, can also be electrically connected to the first doped semiconductor layer 3 through the conductive material 5a within the holes and / or cracks. Furthermore, the first doped semiconductor layer 3 at the location corresponding to the holes is also a heat concentration area with significant damage (heat concentration areas are prone to forming holes), and the conductive material 5a can repair the damage at this location. The conductive material 5a is distributed in granular form within the heat-affected zone 2b, and the granular conductive material 5a at the position furthest from the center of the opening 2a defines the width D of the heat-affected zone 2b. The conductive material 5a within the holes and / or cracks can be the same as the conductive barrier layer 5, and can be formed together with the conductive barrier layer 5 by electroplating or chemical plating.

[0107] On the one hand, if the total area of ​​the orthographic projection of the aperture 2a corresponding to the same first gate line 1 on the first surface is too large, it will increase the damage to the semiconductor substrate 4 during the aperture 2a opening process. On the other hand, if the total area of ​​the orthographic projection of the aperture 2a corresponding to the same first gate line 1 on the first surface is too small, it will result in an excessively large contact area of ​​the first gate line 1, affecting the current transmission efficiency. Considering both aspects, in this application, the total area of ​​the orthographic projection of the aperture 2a corresponding to the same first gate line 1 on the first surface is 20% to 80% of the orthographic projection area of ​​the first gate line 1 on the first surface, so as to reduce the damage to the semiconductor substrate 4 during the aperture 2a opening process while ensuring the current transmission efficiency of the first gate line 1.

[0108] In other embodiments, such as Figure 11 As shown, the region corresponding to the opening 2a in the first doped semiconductor layer 3 includes multiple pits 3a1, which can be of any shape, such as circular or elliptical. The inner diameter of the pit 3a1 is 0.5μm to 2μm, and can be the inner diameter of the largest position of the pit 3a1 or an equivalent inner diameter. For example, the inner diameter of the pit 3a1 is 0.5μm, 0.8μm, 1.0μm, 1.2μm, 1.5μm, 1.8μm, or 2μm. By adopting this technical solution, the setting of the pits 3a1 can also increase the surface area of ​​the region, thereby increasing the contact area between the conductive barrier layer 5 and the region, and further reducing the contact resistance.

[0109] In other embodiments, the conductive barrier layer 5 is electrically connected to the first doped semiconductor layer 3 by burning through the passivation layer 2. For example... Figure 12 As shown, the portion of the conductive barrier layer 5 that penetrates the passivation layer 2 includes multiple conductive channels 5b. That is, one end of the multiple conductive channels 5b (e.g., Figure 12 The upper middle end) is electrically connected to the first gate line 1, and the other end of the multiple conductive channels 5b (such as...) Figure 12 The lower end of the first gate line 1 is electrically connected to the first doped semiconductor layer 3 to achieve conductivity between the first gate line 1 and the first doped semiconductor layer 3 through multiple conductive channels 5b. Any two adjacent conductive channels 5b can be locally connected, meaning that parts of any two adjacent conductive channels 5b can be continuously arranged; or, any two adjacent conductive channels 5b can be unconnected, meaning that the multiple conductive channels 5b are independent and discretely distributed. This reduces the difficulty of forming multiple conductive channels 5b by burning through the passivation layer 2 in the conductive barrier layer 5, and improves processing efficiency.

[0110] When the conductive barrier layer 5 is electrically connected to the first doped semiconductor layer 3 by burning through the passivation layer 2, the passivation layer 2 below the conductive barrier layer 5 does not need to be patterned to create openings. The conductive barrier layer 5 can be formed using a burn-through paste, and can be formed by printing, transfer, or spraying. Specifically, it can be annealed at high temperature to allow the corrosive material in the conductive barrier layer 5 (e.g., glass frit in silver paste) to etch the passivation layer 2, thereby forming a conductive channel 5b in the passivation layer 2. The conductive channel 5b is the contact between the metal material of the conductive barrier layer 5 and the doped semiconductor layer through the passivation layer 2.

[0111] When the conductive barrier layer 5 is discontinuously disposed along the first direction, the conductive barrier layer 5 includes a plurality of sub-conductive barrier layers spaced apart along the first direction. Each sub-conductive barrier layer may include a plurality of conductive channels 5b.

[0112] On the one hand, if the minimum distance L between any two adjacent sub-conductive barrier layers along the first direction is too large, it will lead to a decrease in carrier transport efficiency; on the other hand, if the minimum distance L between any two adjacent sub-conductive barrier layers along the first direction is too small, it will increase the difficulty of forming the sub-conductive barrier layers, leading to a decrease in production efficiency. Therefore, in order to balance the above two aspects, in this technical solution, if... Figure 12 As shown, the minimum distance L between any two adjacent sub-conductive barrier layers along the first direction is set within a reasonable range of 0.2mm to 3mm. This improves carrier transport efficiency while reducing the manufacturing difficulty of the sub-conductive barrier layers and increasing production efficiency. It can be understood that the minimum distance L between any two adjacent sub-conductive barrier layers along the first direction refers to the distance between the closest points of the boundaries of the two adjacent sub-conductive barrier layers. For example, the minimum distance L between any two adjacent sub-conductive barrier layers along the first direction can be 0.2mm, 0.4mm, 0.5mm, 0.8mm, 1mm, 1.2mm, 1.4mm, 1.5mm, 1.8mm, 2mm, 2.2mm, 2.4mm, 2.5mm, 2.8mm, or 3mm.

[0113] In some embodiments, the orthographic projection of the sub-conductive barrier layer on the first surface is a circle, an ellipse, a strip, or a polygon, wherein the polygon can be a square, a triangle, a trapezoid, an irregular polygon, etc.

[0114] In some embodiments, the first doped semiconductor layer 3 further includes a metal crystal layer 3b located on the side of the conductive barrier layer 5 near the semiconductor substrate 4. For example, silver in the conductive barrier layer 5 forms an AgSi alloy phase with silicon, which has high thermal stability and mechanical strength. In this technical solution, the adhesion between the metal elements contained in the conductive barrier layer 5 and silicon is enhanced by chemical bonding in the metal crystal layer 3b, reducing the problem of peeling off the conductive barrier layer 5 due to thermal or mechanical stress; furthermore, the metal crystal layer 3b has high conductivity, and the presence of the metal crystal layer 3b can also improve the carrier transport efficiency between the conductive barrier layer 5 and the first doped semiconductor layer 3.

[0115] In some embodiments, the thickness of the metal crystal layer 3b along the thickness direction of the semiconductor substrate 4 is less than or equal to the thickness of the first doped semiconductor layer 3. In this technical solution, the metal crystal layer 3b is formed at least in the region near the surface of the first doped semiconductor layer 3 facing away from the semiconductor substrate 4, which improves the adhesion of the conductive barrier layer 5 and the carrier transport efficiency while reducing the processing difficulty of the metal crystal layer 3b. In some embodiments, a portion of the metal crystal layer 3b may abut against the interface layer (e.g., an oxide layer including first and second interface layers) between the first doped semiconductor layer 3 and the semiconductor substrate 4, or the distance between it and the interface layer may be less than 10 nm.

[0116] In some embodiments, the thickness of the metal crystal layer 3b along the thickness direction of the semiconductor substrate 4 is 2 / 3 of the thickness of the first doped semiconductor layer 3. This improves the adhesion and carrier transport efficiency of the conductive barrier layer 5 while preventing excessive heat from reaching the semiconductor substrate 4 and damaging it during burn-through. For example, the thickness of the metal crystal layer 3b can be 2 / 3, 1 / 3, 1 / 2, 3 / 5, etc., of the thickness of the first doped semiconductor layer 3.

[0117] In some embodiments, such as Figure 14 As shown, the conductive barrier layer 5 contains multiple pores 5c, and these pores 5c are free of organic matter and / or metal particles. This design improves the heat dissipation of the conductive barrier layer 5 and prevents localized overheating.

[0118] When the conductive barrier layer 5 is electrically connected to the first doped semiconductor layer 3 by burning through the passivation layer 2, the thickness of the conductive barrier layer 5 is 0.1 μm to 10 μm. This ensures that the conductive barrier layer 5 can burn through the passivation layer 2 while reducing the waste of raw materials for the conductive barrier layer 5 and improving processing efficiency. It can be understood that at the location of the conductive channel 5b, the thickness of the conductive barrier layer 5 is the distance from the side of the conductive barrier layer 5 facing away from the semiconductor substrate 4 to the end of the conductive channel 5b near the semiconductor substrate 4 along the thickness direction of the semiconductor substrate 4. For example, in this technical solution, the thickness of the conductive barrier layer 5 is 0.1 μm, 0.5 μm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, or 10 μm.

[0119] In some embodiments, the solar cell further includes a second doped semiconductor layer 10 and a plurality of second gate lines 8, wherein the second gate lines 8 are disposed on the side of the second doped semiconductor layer 10 facing away from the semiconductor substrate 4. The first gate line 1 and the second gate line 8 are made of the same material, and the polarities of the first gate line 1 and the second gate line 8 are opposite. The resistivity, cross-sectional area, height, width, and spacing between adjacent second gate lines 8 of the second gate line 8 can be referred to the description of the first gate line 1 above, and will not be repeated here.

[0120] In the case of a back-contact solar cell, both the first doped semiconductor layer 3 and the second doped semiconductor layer 10 are located on the first surface, and the first doped semiconductor layer 3 and the second doped semiconductor layer 10 are arranged at intervals along a second direction. Specifically, the second doped semiconductor layer 10 and the first doped semiconductor layer 3 can be arranged in alternating stripe patterns or in alternating interdigitated patterns. Both the first gate line 1 and the second gate line 8 are formed on the first surface. The first gate line 1 is electrically connected to the first doped semiconductor layer 3, and the second gate line 8 is electrically connected to the second doped semiconductor layer 10. The second gate line 8 also extends along the first direction and is arranged along the second direction, with multiple first gate lines 1 and multiple second gate lines 8 alternating along the second direction. In this technical solution, the passivation layer 2 can cover the side of the first doped semiconductor layer 3 and the second doped semiconductor layer 10 facing away from the semiconductor substrate 4. The first gate line 1 passes through the opening 2a of the passivation layer 2 and is electrically connected to the first doped semiconductor layer 3, and the second gate line 8 passes through the opening 2a of the passivation layer 2 and is electrically connected to the second doped semiconductor layer 10.

[0121] In the case of a bifacial solar cell, the first doped semiconductor layer 3 and the second doped semiconductor layer 10 are located on the first surface and the second surface, respectively, and the first gate line 1 is formed on the first surface and electrically connected to the first doped semiconductor layer 3, and the second gate line 8 is formed on the second surface and electrically connected to the second semiconductor layer.

[0122] In some embodiments, the passivation layer 2 further covers the side of the second doped semiconductor layer 10 facing away from the semiconductor substrate 4, and the conductive barrier layer 5 passes through the passivation layer 2 and is electrically connected to the second doped semiconductor layer 10. A plurality of second gate lines 8 are disposed on the conductive barrier layer 5. Specifically, a portion of the conductive barrier layer 5 passes through the passivation layer 2 and is electrically connected to the first doped semiconductor layer 3, and another portion of the conductive barrier layer 5 passes through the passivation layer 2 and is electrically connected to the second doped semiconductor layer 10. It is understood that the conductive barrier layer 5 electrically connected to the first doped semiconductor layer 3 and the conductive barrier layer 5 electrically connected to the second doped semiconductor layer 10 should not conduct electricity to prevent leakage. With this configuration, the conductive barrier layer 5 electrically connected to the second doped semiconductor layer 10 can separate the second gate lines 8 and the second doped semiconductor layer 10, ensuring both the passivation effect of the doped semiconductor layer and the conductivity between the second gate lines 8 and the second doped semiconductor layer 10.

[0123] The conductive barrier layer 5, which is electrically connected to the second doped semiconductor layer 10, can be electrically connected to the second doped semiconductor layer 10 by burning through or by opening a hole in the passivation layer 2. The technical characteristics of the conductive barrier layer 5, which is electrically connected to the second doped semiconductor layer 10, such as its material, thickness, and structure, can be referred to the description of the conductive barrier layer 5 electrically connected to the first doped semiconductor layer 3 above, and will not be repeated here.

[0124] When the conductive barrier layer 5 can be electrically connected to the first doped semiconductor layer 3 or the second doped semiconductor layer 10 through the passivation layer 2 by burning through, the first doped semiconductor layer 3 and the semiconductor substrate 4 have the same doping type. With this setting, the transmission resistance between the first doped semiconductor layer 3 and the semiconductor substrate 4 is lower, and the charge carriers can more easily pass through the interface between the first doped semiconductor layer 3 and the semiconductor substrate 4.

[0125] The conductive barrier layer 5 electrically connected to the first doped semiconductor layer 3 includes a plurality of sub-conductive barrier layers spaced apart along a first direction, with a minimum distance L1 between two adjacent sub-conductive barrier layers electrically connected to the first doped semiconductor layer 3 along the first direction; the conductive barrier layer 5 electrically connected to the second doped semiconductor layer 10 also includes a plurality of sub-conductive barrier layers spaced apart along the first direction, with a minimum distance L2 between two adjacent sub-conductive barrier layers electrically connected to the second doped semiconductor layer 10 along the first direction. Since the transmission resistance between the first doped semiconductor layer 3 and the semiconductor substrate 4 is lower than the transmission resistance between the second doped semiconductor layer 10 and the semiconductor substrate 4, in this technical solution, L2 < L1, so that the distance between the plurality of sub-conductive barrier layers electrically connected to the second doped semiconductor layer 10 is smaller, and the density of the plurality of sub-conductive barrier layers electrically connected to the second doped semiconductor layer 10 is greater, thereby balancing the transmission efficiency of charge carriers through the first doped semiconductor layer 3 and the second doped semiconductor layer 10, reducing the current difference of charge carriers through the first doped semiconductor layer 3 and the second doped semiconductor layer 10, and thus improving the overall power generation efficiency of the solar cell.

[0126] In some embodiments, the minimum distance between the plurality of sub-conductive barrier layers electrically connected to the first doped semiconductor layer 3 is set within a reasonable range of 1 mm ≤ L1 ≤ 3 mm, so as to improve the carrier transport efficiency while reducing the process difficulty of forming the sub-conductive barrier layers and improving production efficiency. For example, L1 can be 1 mm, 1.2 mm, 1.4 mm, 1.5 mm, 1.8 mm, 2 mm, 2.2 mm, 2.4 mm, 2.5 mm, 2.8 mm or 3 mm.

[0127] In some embodiments, the minimum distance between the plurality of sub-conductive barrier layers electrically connected to the second doped semiconductor layer 10 is set within a reasonable range of 0.2 mm ≤ L2 ≤ 2 mm, so as to improve the carrier transport efficiency while reducing the process difficulty of forming the sub-conductive barrier layers and improving production efficiency. For example, L2 can be 0.2 mm, 0.4 mm, 0.5 mm, 0.8 mm, 1 mm, 1.2 mm, 1.4 mm, 1.5 mm, 1.8 mm or 2 mm.

[0128] In practical applications, the semiconductor substrate 4 can be made of materials such as silicon (Si), germanium (Ge), or gallium arsenide (GaAs). Obviously, in terms of conductivity type, the semiconductor substrate 4 can be an intrinsically conductive substrate, an n-type conductive substrate, or a p-type conductive substrate. Optionally, the semiconductor substrate 4 can be a p-type conductive substrate or an n-type conductive substrate. Compared to an intrinsically conductive substrate, a p-type or n-type conductive substrate has better conductivity, resulting in a lower bulk resistivity in the final solar cell, thereby improving the efficiency of the solar cell.

[0129] For example, the semiconductor substrate 4 can be a p-type substrate or an n-type substrate. The n-type substrate has advantages such as high minority carrier lifetime, no light decay, and good performance in low light.

[0130] The first doped semiconductor layer 3 comprises one or more of polycrystalline silicon, amorphous silicon, nanocrystalline silicon, and microcrystalline silicon. In this case, the doped polycrystalline silicon layer has higher carrier transport characteristics, therefore, when the first doped semiconductor layer 3 is a doped polycrystalline silicon layer, the carrier transport efficiency is higher, which is beneficial to improving the photoelectric conversion efficiency of the solar cell. Of course, the first doped semiconductor layer 3 can also be one or more of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon. The second doped semiconductor layer 10 also comprises one or more of polycrystalline silicon, amorphous silicon, nanocrystalline silicon, and microcrystalline silicon.

[0131] In some embodiments, a first interface layer 9 is disposed between the first doped semiconductor layer 3 and the semiconductor substrate 4, and a second interface layer 11 is disposed between the second doped semiconductor layer 10 and the semiconductor substrate 4. The passivated contact structure composed of the interface layer and the semiconductor layer has excellent interface passivation effect and can achieve selective collection of charge carriers, reducing the carrier recombination rate in the region where the semiconductor layer is formed on the surface of the semiconductor substrate 4, and further improving the photoelectric conversion efficiency of the solar cell. The material and thickness of the first interface layer 9 can be set according to the material of the first doped semiconductor layer 3 and actual requirements, and the material and thickness of the second interface layer 11 can be set according to the material of the second doped semiconductor layer 10 and actual requirements; no specific limitations are made here.

[0132] For example, the first doped semiconductor layer 3 can be a doped polysilicon layer, and the first interface layer 9 can be a tunneling oxide layer. The second doped semiconductor layer 10 can be a doped polysilicon layer, and the second interface layer 11 can be a tunneling oxide layer.

[0133] Of course, when the first doped semiconductor layer 3 includes one or more of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon, the first interface layer 9 includes one or more of intrinsic amorphous silicon, intrinsic microcrystalline silicon, and intrinsic nanocrystalline silicon. When the second doped semiconductor layer 10 includes one or more of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon, the second interface layer 11 includes one or more of intrinsic amorphous silicon, intrinsic microcrystalline silicon, and intrinsic nanocrystalline silicon.

[0134] The materials of the first doped semiconductor layer 3 and the second doped semiconductor layer 10 can be silicon (Si), germanium (Ge), silicon carbide (SiCx), or gallium arsenide (GaAs), etc. Regarding the conductivity type, the first doped semiconductor layer 3 can be an n-type doped layer, and the second doped semiconductor layer 10 can be a p-type doped layer; or, the first doped semiconductor layer 3 can be a p-type doped layer, and the second doped semiconductor layer 10 can be an n-type doped layer.

[0135] It should be noted that the first gate line 1 can be a fine gate or a main gate.

[0136] For a gridless solar cell, the solar cell's grid includes a first grid and a second grid, and the first and second grids are arranged alternately along a second direction. The first grid can be the first grid line 1 mentioned above. In this embodiment, the first and second grids can be continuously and uninterruptedly arranged along the first direction or can be intermittently formed into multiple segments.

[0137] For a solar cell with a main grid, the solar cell's fine grid includes a first fine grid and a second fine grid, and the solar cell's main grid includes a first main grid and / or a second main grid. The first fine grid and / or the first main grid is the aforementioned first grid line 1. In this embodiment, the first fine grid and the second fine grid can be continuously and uninterruptedly arranged along a first direction or can be intermittently formed into multiple segments. In one case, there are multiple first main grids and multiple second main grids, which are sequentially spaced along the first direction. Any first fine grid and any second fine grid between adjacent first main grids and second main grids are continuously and uninterruptedly arranged along the first direction. All the multiple first fine grids are electrically connected to the first main grid, and all the multiple second fine grids are electrically connected to the second main grid. In another case, when there is only one first main grid and one second main grid, at least one first fine grid is electrically connected to the first main grid, and at least one second fine grid is electrically connected to the second main grid.

[0138] When the first grid line 1 is the main grid, the width of the first grid line 1 is greater than or equal to 400μm, for example, it can be 400μm, 420μm, 450μm, 480μm, 500μm, 520μm, 550μm, 580μm, or 600μm, etc. This can prevent the main grid width from being too small, causing the slurry of the main grid to flow into the gap between adjacent insulating blocks 6, resulting in the main grid breaking.

[0139] In the case of a back-contact solar cell, both the first grid line 1 and the second grid line 8 are formed on the first surface. The solar cell also includes a first conductive element 7 and a second conductive element. The first conductive element 7 is electrically connected to the plurality of first grid lines 1 and has an insulating block 6 between itself and the plurality of second grid lines 8; the second conductive element is electrically connected to the plurality of second grid lines 8 and has an insulating block 6 between itself and the plurality of first grid lines 1. This arrangement uses the insulating blocks 6 to separate the first conductive element 7 from the plurality of second grid lines 8, and at the same time separates the second conductive element from the plurality of first grid lines 1, reducing the risk of leakage.

[0140] Along the second direction, the spacing between adjacent insulating blocks 6 is greater than or equal to 100 μm. This sufficiently large distance between adjacent insulating blocks 6 provides a safe distance for slurry flow, preventing the slurry flowing to form the insulating blocks 6 from covering grid lines that shouldn't be covered. This ensures the stability of the electrical connections between the first grid line 1 and the first conductive element 7, and between the second grid line 8 and the second conductive element, thereby improving the stability of the solar cell's performance. For example, the spacing between adjacent insulating blocks 6 can be 100 μm, 110 μm, 120 μm, or 130 μm, etc.

[0141] Along the thickness direction of the cell body, the thickness of the insulating block 6 is less than or equal to 80 μm, for example, the thickness of the insulating block 6 is 80 μm, 70 μm, 60 μm, 50 μm, 40 μm, 30 μm, or 20 μm. This ensures the isolation effect of the insulating block 6 and prevents the paste forming the insulating block 6 from climbing up and covering the grid lines that it should not cover, thereby improving the stability of the solar cell performance.

[0142] like Figure 15 and Figure 16 As shown, when the first conductive element 7 is the main gate, the main gate can be directly physically contacted and electrically connected to the first gate line 1 (the first fine gate). Figure 17 As shown, the first conductive element 7 (main grid) has a side protrusion 7a protruding along a first direction at the intersection with the first grid line 1 (first fine grid). That is, along the first direction, the width of the position where the first conductive element 7 (main grid) has the side protrusion 7a is greater than the width of the other positions on the first conductive element 7. This arrangement increases the contact area between the first conductive element 7 (main grid) and the first grid line 1 (first fine grid), thereby reducing the transmission resistance between the first conductive element 7 and the first grid line 1, reducing current loss, and improving the photoelectric conversion efficiency of the solar cell. Furthermore, in this technical solution, when there are spreading portions 102 on both sides of the first grid line 1, the spreading portions 102 can limit the flow distance of the paste forming the first conductive element 7 along the first direction from being too large, thus preventing the formed side protrusion 7a from becoming too wide.

[0143] Furthermore, this application also provides a photovoltaic module, which includes a solar cell and a first conductive element 7 provided in any of the above embodiments. The first conductive element 7 extends along a second direction and is electrically connected to a first grid line 1. The first conductive element 7 and the first grid line 1 can be electrically connected through direct physical contact or through a bonding layer. Compared with the prior art, the beneficial effects of the photovoltaic module provided in this application are the same as those of the solar cell described above, and will not be repeated here.

[0144] In this photovoltaic module, such as Figure 18As shown, the first conductive component 7 is a solder ribbon, which connects at least two solar cells to form a cell structure (i.e., a cell string structure). In this case, the solar cell can be a gridless cell, such as... Figure 19 As shown, the solder ribbon is electrically connected to the first grid line 1 via the bonding layer 12. The bonding layer 12 can be specifically solder or conductive adhesive. Using this technical solution, the solder ribbon is directly electrically connected to the first grid line 1, achieving the effect of reducing shading and resistance loss. When the first conductive element 7 is the main grid, the photovoltaic module will also include a solder ribbon, which needs to be soldered to the main grid using a bonding material, thereby enabling multiple cells at the module end to be connected in series or parallel.

[0145] In some embodiments, such as Figure 20 As shown, the first grid line 1 includes thickened segments 1e spaced apart along a first direction. Along a second direction, the width of the thickened segments 1e is greater than the width of the rest of the first grid line 1. That is, the thickened segments 1e are provided at the location where the first grid line 1 connects to the first conductive element 7. These thickened segments 1e can be integrally formed with the rest of the first grid line 1 or formed separately. Using this technical solution, the thickened segments 1e increase the contact area between the first grid line 1 and the bonding layer 12, thereby reducing the transmission resistance between the bonding layer 12 and the first grid line 1, reducing current loss, and improving the photoelectric conversion efficiency of the solar cell.

[0146] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0147] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A solar cell, characterized in that, include: The battery body includes a first surface and a second surface disposed opposite to each other, and the battery body includes a semiconductor substrate, a first doped semiconductor layer and a passivation layer; The first doped semiconductor layer is disposed on the first surface of the semiconductor substrate, and the passivation layer covers the side of the first doped semiconductor layer away from the semiconductor substrate; A conductive barrier layer is disposed at least on the first surface; Multiple first gate lines are disposed on the conductive barrier layer, extending along a first direction and arranged along a second direction, the first and second directions intersecting each other; the first gate lines are formed of a non-burn-through paste, the resistivity of the first gate lines is 6 μΩ·cm to 60 μΩ·cm, and the cross-sectional area of ​​the first gate lines along a plane perpendicular to the first direction is greater than or equal to 250 μm². 2 ; Along the thickness direction of the battery body, the height of the first grid line is h; the width of the first grid line is w, h / w is 0.1~0.5, and w≥30μm; The spacing between two adjacent first gate lines is 0.6mm to 1.3mm; The conductive barrier layer includes a plurality of sub-conductive barrier layers spaced apart along a first direction; the same first gate line contacts the plurality of sub-conductive barrier layers spaced apart along the first direction; the sub-conductive barrier layers pass through the passivation layer and are electrically connected to the first doped semiconductor layer.

2. The solar cell according to claim 1, characterized in that, 140μm≥w≥30μm; and / or, 5μm≥h≥25μm.

3. The solar cell according to claim 1, characterized in that, The first gate line comprises copper powder and organic matter; The copper powder includes at least flaky particles and spherical particles.

4. The solar cell according to claim 3, characterized in that, The copper powder further includes one or more of linear particles, V-shaped particles, polygonal particles, and columnar particles; and / or, the median diameter of the sheet-like particles is 0.8 μm to 5 μm; and / or, the median thickness of the sheet-like particles is 100 nm to 500 nm; and / or, the median particle size of the spherical particles is 100 nm to 500 nm.

5. The solar cell according to claim 4, characterized in that, The mass percentage of the flake-shaped particles is 35% to 60%; and / or, the mass percentage of the spherical particles is 35% to 60%; and / or, the tapped density of the flake-shaped particles is 3 g / ml to 6 g / ml; and / or, the tapped density of the spherical particles is 3.5 g / ml to 5.5 g / ml; and / or, the specific surface area of ​​the flake-shaped particles is 0.4 m². 2 / g~0.7 m 2 / g; and / or, the specific surface area of ​​the spherical particles is 1.5m². 2 / g~3.5 m 2 / g; and / or, the organic compound includes one or more of the following: saturated / unsaturated fatty acids containing 8-18 carbons, silane coupling agents, PVP, and thiols.

6. The solar cell according to claim 1, characterized in that, The first grid line includes a main body portion and a spreading portion arranged along the second direction, the main body portion and the spreading portion extending along the first direction; Along the second direction, the width W1 of the main body portion is 30μm to 120μm; and / or, along the second direction, the width W2 of the spreading portion is 1μm to 60μm; and / or, along the second direction, the width of the spreading portion is 5% to 50% of the width of the main body portion; and / or, along the thickness direction of the battery body, the height h1 of the main body portion is 8μm to 25μm; and / or, along the thickness direction of the battery body, the height of the main body portion is h1, and the height of the spreading portion is h2. ; and / or, the median particle size of the copper powder contained in the spreading portion is smaller than the median particle size of the copper powder contained in the main body portion.

7. The solar cell according to claim 1, characterized in that, The passivation layer has an opening that exposes the first doped semiconductor layer; the first gate line covers the opening and is electrically connected to the first doped semiconductor layer.

8. The solar cell according to claim 7, characterized in that, The conductive barrier layer fills the opening; The thickness of the portion of the conductive barrier layer corresponding to the area of ​​the opening is greater than the thickness of the passivation layer; and / or, the thickness of the portion of the conductive barrier layer corresponding to the area of ​​the opening is 0.5 μm to 5 μm.

9. The solar cell according to claim 8, characterized in that, The first doped semiconductor layer forms a modified layer in the region corresponding to the opening; The roughness of the modified layer is greater than the roughness of the other parts of the first doped semiconductor layer, and / or the crystallization degree of the modified layer is lower than the crystallization degree of the other parts of the first doped semiconductor layer.

10. The solar cell according to claim 7, characterized in that, The passivation layer has a heat-affected zone surrounding the opening; The width of the heat-affected zone is D, 1μm≤D≤5μm; and / or, the heat-affected zone includes multiple holes and / or cracks, the holes and / or cracks are filled with conductive material, and the conductive material is electrically connected to the first doped semiconductor layer.

11. The solar cell according to claim 7, characterized in that, The total area of ​​the orthographic projection of the openings corresponding to the same first grid line on the first surface is 20% to 80% of the orthographic projection area of ​​the first grid line on the first surface; or, the number of openings corresponding to the same first grid line is multiple and distributed at intervals; or, the openings corresponding to the same first grid line are arranged in a strip shape.

12. The solar cell according to claim 7, characterized in that, The region corresponding to the opening in the first doped semiconductor layer includes multiple pits; the inner diameter of the pits is 0.5μm~2μm.

13. The solar cell according to claim 1, characterized in that, The conductive barrier layer is electrically connected to the first doped semiconductor layer by burning through the passivation layer.

14. The solar cell according to claim 13, characterized in that, The first doped semiconductor layer further includes a metal crystal layer located on the side of the conductive barrier layer near the semiconductor substrate; Along the thickness direction of the semiconductor substrate, the thickness of the metal crystal layer is less than or equal to the thickness of the first doped semiconductor layer; Alternatively, along the thickness direction of the semiconductor substrate, the thickness of the metal crystal layer is 2 / 3 of the thickness of the first doped semiconductor layer; or, along the thickness direction of the semiconductor substrate, the distance between the metal crystal layer and the interface layer between the first doped semiconductor layer and the semiconductor substrate is less than 10 nm.

15. The solar cell according to claim 13, characterized in that, The conductive barrier layer includes multiple pores; and / or the thickness of the conductive barrier layer is 0.1 μm to 10 μm.

16. The solar cell according to claim 1, characterized in that, The solar cell further includes a second doped semiconductor layer and a plurality of second gate lines. The second doped semiconductor layer has the opposite conductivity type to the first doped semiconductor layer, and the second gate lines are disposed on the side of the second doped semiconductor layer away from the semiconductor substrate. The first gate line and the second gate line are made of the same material, and the polarities of the first gate line and the second gate line are opposite. The second doped semiconductor layer and a plurality of second gate lines are disposed on the first surface, the plurality of second gate lines extend along a first direction and are arranged along a second direction, the first doped semiconductor layer and the second doped semiconductor layer are alternately distributed along the second direction, and the plurality of first gate lines and the second gate lines are alternately distributed along the second direction; or, the second doped semiconductor layer and a plurality of second gate lines are disposed on the second surface, the plurality of second gate lines extend along a first direction and are arranged along a second direction.

17. The solar cell according to claim 16, characterized in that, The passivation layer also covers the side of the second doped semiconductor layer away from the semiconductor substrate, and the conductive barrier layer also passes through the passivation layer and is electrically connected to the second doped semiconductor layer, with a plurality of second gate lines disposed on the conductive barrier layer.

18. The solar cell according to claim 17, characterized in that, The conductive barrier layer is electrically connected to the first doped semiconductor layer or the second doped semiconductor layer by burning through the passivation layer; the first doped semiconductor layer has the same doping type as the semiconductor substrate. Among the plurality of sub-conductive barrier layers electrically connected to the first doped semiconductor layer, the minimum distance between two adjacent sub-conductive barrier layers along the first direction is L1; among the plurality of sub-conductive barrier layers electrically connected to the second doped semiconductor layer, the minimum distance between two adjacent sub-conductive barrier layers along the first direction is L2. L2 < L1; and / or, 1mm ≤ L1 ≤ 3mm; and / or, 0.2mm ≤ L2 ≤ 2mm.

19. The solar cell according to claim 16, characterized in that, A plurality of second gate lines are disposed on the first surface, extending along a first direction and arranged along a second direction, with the plurality of first gate lines and second gate lines alternately distributed along the second direction; The solar cell further includes a first conductive element and a second conductive element, wherein the first conductive element is electrically connected to a plurality of first grid lines and has an insulating block between itself and a plurality of second grid lines; the second conductive element is electrically connected to a plurality of second grid lines and has an insulating block between itself and a plurality of first grid lines.

20. A photovoltaic module, characterized in that, It includes a solar cell and a first conductive element as described in any one of claims 1-19, wherein the first conductive element extends along the second direction and is electrically connected to the first grid line.

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