Crystalline silicon battery assembly capable of increasing output voltage and laminated battery assembly

Abstract

The embodiment of the invention provides a crystalline silicon battery assembly capable of increasing output voltage and a laminated battery assembly comprising the crystalline silicon battery assembly, and relates to the technical field of photovoltaics. The crystalline silicon battery assembly comprises a plurality of battery pieces which are connected in series, and each battery piece comprises a silicon wafer, a first film layer and a second film layer. The first film layer comprises a first part and a second part which are spaced by a gap, the second film layer comprises a third part and a fourth part which are spaced by a gap, a first grid line is arranged on the side, away from the silicon wafer, of the first part, a conductor is arranged on the side, away from the silicon wafer, of the fourth part, and a through hole penetrating through the silicon wafer in the thickness direction is formed in the silicon wafer; the through holes are filled with conducting media, and the first grid lines are electrically connected with the conductors through the conducting media. The output voltage of the crystalline silicon battery assembly can be increased, and the problem of voltage mismatch in a laminated battery assembly is solved.

Description

Technical Field

[0001] The present application relates to the field of photovoltaic technology, and in particular to a crystalline silicon battery assembly and a stacked battery assembly capable of increasing output voltage. Background Art

[0002] Perovskite cell modules have the advantages of high conversion efficiency, low preparation cost, and adjustable bandgap width. Among them, perovskite cell modules can be stacked with crystalline silicon cell modules and packaged to form a stacked cell module. The perovskite cell modules and crystalline silicon cell modules in the stacked cell module absorb light in different bands respectively, reducing light energy loss.

[0003] However, in the stacked cell modules where perovskite cell modules and crystalline silicon cell modules are connected in parallel, the voltage outputs of crystalline silicon cell modules and perovskite cell modules of the same size are different. The output voltage of the crystalline silicon cell modules is significantly lower than that of the perovskite cell modules. The serious voltage mismatch increases the difficulty of connecting the two in parallel.

[0004] Related technologies cut the cells in a crystalline silicon solar module into smaller cells, allowing more cells to be connected in series. This increases the module's output voltage and helps match the voltage of a perovskite module. However, this approach significantly increases the gaps between adjacent cells, reducing the overall effective power generation area and lowering the module's overall power output. Summary of the Invention

[0005] The present application provides a crystalline silicon cell assembly capable of increasing output voltage, and a stacked cell assembly including the crystalline silicon cell assembly, which can increase the output voltage of the crystalline silicon cell assembly without cutting the cell slice into multiple small cell slices.

[0006] To achieve the above objectives, this application adopts the following technical solutions:

[0007] In a first aspect of the present application, a crystalline silicon battery module capable of increasing output voltage is provided, the crystalline silicon battery module comprising a plurality of battery cells connected in series, each battery cell comprising a silicon wafer, a first film layer and a second film layer, the silicon wafer having a first surface and a second surface back to back in a thickness direction, the first film layer being arranged on the first surface, and the second film layer being arranged on the second surface; the first film layer comprising a first portion and a second portion separated by a gap, the second film layer comprising a third portion and a fourth portion separated by a gap, the orthographic projection of the first portion on the first surface and the orthographic projection of the third portion on the first surface at least partially overlapping, the orthographic projection of the second portion on the first surface and the orthographic projection of the fourth portion on the first surface at least partially overlapping, a first gate line being arranged on a side of the first portion facing away from the silicon wafer, a conductor being arranged on a side of the fourth portion facing away from the silicon wafer, a through hole being arranged on the silicon wafer that passes through the silicon wafer in a thickness direction, the through hole being filled with a conductive medium, and the first gate line being electrically connected to the conductor via the conductive medium.

[0008] The slits on the first film layer divide the first film layer into a first part and a second part, and the slits on the second film layer divide the second film layer into a third part and a fourth part. The orthographic projections of the first and third parts on the first surface have an overlapping portion, and the orthographic projections of the second and fourth parts on the first surface have an overlapping portion. That is, the first part, the third part, and the silicon wafer therebetween form one sub-cell, and the second part, the fourth part, and the silicon wafer therebetween form another sub-cell. By respectively cutting slits in the first and second film layers, the cell is divided into multiple sub-cells without having to cut the cell into multiple small cells. After the cell is divided into multiple sub-cells, a conductive medium is provided to electrically connect the first gate line and the conductor. That is, the positive and negative electrodes of two adjacent sub-cells are electrically connected by the first gate line, the conductive medium, and the conductor, so that the two adjacent sub-cells on the cell are connected in series, thereby increasing the output voltage of the crystalline silicon cell module.

[0009] In an optional embodiment, the orthographic projection of the first portion on the first surface partially overlaps with the orthographic projection of the fourth portion on the first surface, and the through hole passes through the first portion and the fourth portion.

[0010] The orthographic projections of the first portion and the fourth portion on the first surface overlap, that is, the first portion and the fourth portion overlap in the thickness direction. The through hole penetrates the silicon wafer while also penetrating the first and fourth portions. The through hole penetrating the first and fourth portions facilitates the connection of the conductive medium to the first gate line and the conductor. Furthermore, the overlap of the first and fourth portions in the thickness direction allows for a larger aperture of the through hole, thereby enhancing the series connection effect.

[0011] In an optional embodiment, the first part and the second part are distributed along the first direction, the gap between the first part and the second part extends along the second direction, the third part and the fourth part are distributed along the first direction, the gap between the third part and the fourth part extends along the second direction, and the first direction, the second direction and the thickness direction are perpendicular to each other.

[0012] The distribution direction of the first and second parts is consistent with the distribution direction of the third and fourth parts, making it easier to overlap the first and third parts, and also easier to overlap the second and fourth parts. In addition, two adjacent sub-cells on the battery cell are arranged in the same direction (for example, the first direction), making it easier to connect multiple sub-cells on the battery cell in series.

[0013] In an optional embodiment, the gap between the first part and the second part includes a first protruding section and a plurality of first connecting sections, the plurality of first connecting sections are distributed in the second direction and all extend along the second direction, the first protruding section is connected between two of the first connecting sections, the first protruding section protrudes toward the second part, and the first protruding section surrounds the through hole.

[0014] In each subcell, the active portion is the overlap between the film layers on either side of the silicon wafer. For example, the overlap between the first and third sections, along with the silicon wafer between these overlapping sections, constitutes the active portion of a subcell. Therefore, the greater the overlap between the film layers on either side of the silicon wafer, the more carriers can be transferred to the corresponding film layers, reducing losses incurred by dividing the cell into multiple subcells. Because the first and fourth sections overlap, the overlapping region between the first and third sections is located on the side of the gap facing away from the second section. In this case, the longer the first section extends beyond the third section, the greater the inactive area of ​​the first section. In the solution of this application, the gap bypasses the through-hole, allowing the portion of the first section pierced by the through-hole to protrude, while the remaining section does not protrude outward, minimizing the area of ​​the first section protruding beyond the third section. Furthermore, the outward protrusion of the first section means that both sides of the protruding section allow the second section to extend into the section, resulting in a larger overlap between the second and fourth sections. By reducing the inactive area of ​​the first section and increasing the active area of ​​the second section, cell losses can be reduced.

[0015] In an optional embodiment, the gap between the third part and the fourth part includes a second protruding segment and a plurality of second connecting segments, the plurality of second connecting segments are distributed in the second direction and all extend along the second direction, the second protruding segment is connected between two of the second connecting segments, the second protruding segment protrudes toward the third part, and the second protruding segment surrounds the through hole.

[0016] Since there is an overlapping portion between the first part and the fourth part, the overlapping area of ​​the second part and the fourth part is located on the side of the gap away from the first part. In this case, the longer the length of the fourth part exceeds the second part, the larger the ineffective area of ​​the fourth part. With the solution of the present application, the gap bypasses the through hole, so that the part of the fourth part that is penetrated by the through hole protrudes, and the remaining part does not need to protrude outward, so that the area of ​​the fourth part exceeding the second part is smaller. In addition, the existence of the outward protruding part of the fourth part means that both sides of the protruding part can be extended by the third part. In this way, the overlapping area between the third part and the first part is larger. By reducing the ineffective area of ​​the fourth part and increasing the effective area of ​​the third part, the loss of the battery cell can be reduced.

[0017] In an optional embodiment, the first protruding section and the second protruding section are both arc-shaped.

[0018] The first protruding section and the second protruding section are both arc-shaped, which can further reduce the ineffective area of ​​the first part and the fourth part, and further increase the effective area of ​​the second part and the third part, thereby further reducing the loss of the battery cell.

[0019] In an optional embodiment, the edge of the first part facing the multiple first connecting segments is flush with the edge of the third part facing the multiple second connecting segments in the thickness direction, and the edge of the second part facing the multiple first connecting segments is flush with the edge of the fourth part facing the multiple second connecting segments in the thickness direction.

[0020] The portion of the first section that is penetrated only by the through-holes protrudes beyond the third section, reducing the ineffective area of ​​the first section and increasing the effective area of ​​the second section. The portion of the fourth section that is penetrated only by the through-holes protrudes beyond the second section, reducing the ineffective area of ​​the fourth section and increasing the effective area of ​​the third section. By reducing the ineffective area of ​​the sub-cell, battery cell losses and material waste are further reduced.

[0021] In an optional embodiment, the conductor includes a second gate line, and an extension direction of the second gate line is parallel to an extension direction of the first gate line.

[0022] The use of a second gateline reduces the use of conductor material and facilitates the production and processing of the cell. The first and second gatelines are connected by a conductive medium, enabling the series connection of two adjacent sub-cells. Furthermore, the second gateline is parallel to the first gateline. When soldering ribbons need to be connected to the cell, the parallel first and second gatelines facilitate automated equipment to solder the ribbons to either the first or second gateline.

[0023] In an optional embodiment, the material of the conductive medium is the same as the material of the first gate line.

[0024] The material of the first gate line is the same as the conductive material, which facilitates production and processing. For example, when screen printing the first gate line, the material of the first gate line will sink into the through hole to fill the through hole. The material of the first gate line will continue to sink in the through hole and connect with the conductor below, thus achieving electrical connection between the first gate line and the conductor.

[0025] In an optional embodiment, an insulating layer is provided on the inner wall surface of the through hole formed by the silicon wafer.

[0026] An insulating layer is set on the inner wall surface of the silicon wafer exposed in the through hole, which can isolate the conductive material from the silicon wafer, reduce the possibility of contact between the conductive material and the silicon wafer, and reduce the possibility of short circuit between the sub-batteries in series. In other words, it reduces the possibility of short circuit inside the battery cell.

[0027] In a second aspect of the present application, a laminated battery assembly is provided, which includes a perovskite battery assembly and the above-mentioned crystalline silicon battery assembly, and the crystalline silicon battery assembly and the titanite battery assembly are connected in parallel.

[0028] The first part, the third part, and the silicon wafer between them form a sub-cell, and the second part, the fourth part, and the silicon wafer between them form another sub-cell. After a plurality of sub-cells are divided on the cell, the first gate line and the conductor are electrically connected by providing a conductive medium, thereby realizing the series connection of two adjacent sub-cells on the cell, thereby increasing the output voltage of the crystalline silicon cell assembly, enabling the output voltage of the crystalline silicon cell assembly to adapt to the output voltage of the perovskite cell assembly, and solving the problem of voltage mismatch in the stacked cell assembly. In addition, the stacked cell assembly provided by the present application includes the above-mentioned crystalline silicon cell assembly, so the stacked cell assembly provided by the present application and the crystalline silicon cell assembly of the above-mentioned technical solution can solve the same technical problems and have the same technical effects, which will not be repeated here.

[0029] In an optional embodiment, the perovskite cell assembly is a light-transmitting structure, the crystalline silicon cell assembly and the perovskite cell assembly are distributed along the thickness direction, and the first surface of the silicon wafer faces the perovskite cell assembly.

[0030] Perovskite solar cell modules have a light-transmitting structure. When light shines from one side of the perovskite solar cell module, some of the light passes through the perovskite solar cell module and shines on the crystalline silicon solar cell module. In the crystalline silicon solar cell module, the side of the solar cell with the first grid line faces the sunlight. The area to the side of the first grid line exposes the solar cell to the sunlight, allowing light to shine on the solar cell and generate electricity. When light shines on the stacked solar cell module, the perovskite solar cell module and the crystalline silicon solar cell module absorb light in different bands respectively, reducing the loss of light energy.

[0031] In an optional embodiment, the laminated battery assembly further includes insulating glue, and the insulating glue is provided between the crystalline silicon battery assembly and the perovskite battery assembly.

[0032] Crystalline silicon and perovskite cell modules are connected in parallel, so short circuits between them need to be prevented. This application fills the gap between the crystalline silicon and perovskite cell modules with insulating glue to isolate them from each other, reducing the possibility of short circuits and making the stacked cell module more stable.

[0033] In an optional embodiment, the perovskite battery assembly is electrically connected to a first positive lead and a first negative lead. Among the multiple battery cells connected in series, the battery cell at one end is connected to a second positive lead, and the battery cell at the other end is electrically connected to a second negative lead. The first positive lead is connected to the second positive lead, and the first negative lead is connected to the second negative lead.

[0034] The first positive lead of the perovskite battery assembly is connected to the second positive lead of the crystalline silicon battery assembly, and the first negative lead of the perovskite battery assembly is connected to the second negative lead of the crystalline silicon battery assembly, thereby realizing the mutual parallel connection between the crystalline silicon battery assembly and the perovskite battery assembly.

[0035] In an optional embodiment, the stacked cell assembly further includes a light-transmitting package, a back package and a packaging glue, the perovskite cell assembly is arranged on the light-transmitting package, the crystalline silicon cell assembly is arranged between the perovskite cell assembly and the back package, the packaging glue is arranged between the light-transmitting package and the back package, and the packaging glue surrounds the crystalline silicon cell assembly and the perovskite cell assembly.

[0036] When sunlight shines on the laminated cell assembly, it will shine on the light-transmitting package. The light-transmitting package allows light to pass through. The light that passes through the light-transmitting package illuminates the perovskite cell assembly, and some light passes through the perovskite cell assembly to illuminate the crystalline silicon cell assembly. The perovskite cell assembly and the crystalline silicon cell assembly absorb light in different bands respectively and output mutually adapted voltages. Because the perovskite cell assembly is relatively thin (for example, 1μm), the perovskite cell assembly needs to be placed on the light-transmitting package during processing, and the light-transmitting package acts as a liner. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A cross-sectional view of a laminated battery assembly provided in an embodiment of the present application;

[0038] Figure 2 A schematic diagram of the structure of a crystalline silicon battery assembly provided in an embodiment of the present application;

[0039] Figure 3 for Figure 2 Magnified view at point A in the middle;

[0040] Figure 4 A schematic structural diagram of a battery cell provided in an embodiment of the present application;

[0041] Figure 5 for Figure 4 Magnified view at point B in the middle;

[0042] Figure 6 A schematic structural diagram of the second film layer provided in an embodiment of the present application;

[0043] Figure 7 A schematic diagram of the structure of a through hole provided in an embodiment of the present application;

[0044] Figure 8 A schematic diagram of the structure of the gap between the first part and the second part provided in an embodiment of the present application;

[0045] Figure 9 for Figure 8 Enlarged view at center C;

[0046] Figure 10 A schematic diagram of the structure of the gap between the third part and the fourth part provided in an embodiment of the present application;

[0047] Figure 11 for Figure 10 Magnified view at point D in the middle;

[0048] Figure 12 A schematic structural diagram of another battery cell provided in an embodiment of the present application;

[0049] Figure 13 A side view of another battery cell provided in an embodiment of the present application;

[0050] Figure 14 A schematic structural diagram of another battery cell provided in an embodiment of the present application;

[0051] Figure 15 A schematic structural diagram of a perovskite battery assembly provided in an embodiment of the present application;

[0052] Figure 16 A cross-sectional view of a perovskite cell assembly provided in an embodiment of the present application.

[0053] Reference numerals:

[0054] 100 - laminated battery assembly; 110 - crystalline silicon battery assembly; 101 - battery cell; 102 - second positive lead; 103 - second negative lead; 104 - metal wire; 1 - silicon wafer; 11 - first surface; 12 - second surface; 13 - through hole; 131 - conductive material; 141 - first protruding section; 142 - first connecting section; 151 - second protruding section; 152 - second connecting section; 2 - first film layer; 21 - first portion; 211 - first convex edge; 212 - first straight edge; 22 - second portion; 221 - first concave edge; 222 - second straight edge ;23-first gate line;24-auxiliary gate line;3-second film layer;31-third part;311-second concave edge;312-third straight edge;32-fourth part;321-second convex edge;322-fourth straight edge;33-second gate line;120-perovskite battery assembly;4-first electrode layer;5-electron transport layer;6-perovskite layer;7-hole transport layer;8-second electrode layer;9-welding rod;91-first positive lead;92-first negative lead;130-insulating glue;140-light-transmitting packaging component;150-back packaging component;160-packaging glue. DETAILED DESCRIPTION

[0055] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0056] In this application, unless otherwise clearly specified and limited, the directions or positional relationships indicated by terms such as "upper" and "lower" may be defined, including but not limited to, the directions relative to the schematic placement of components in the accompanying drawings. These directional terms may be relative concepts, which are used for relative description and clarification, and may change accordingly according to changes in the directions in which components are placed in the accompanying drawings, and shall not be understood as limitations on this application.

[0057] In this application, the terms "first," "second," etc., are used solely for descriptive purposes to distinguish one element from another and should not be understood to indicate or imply relative importance or implicitly specify the quantity of the technical features indicated. Therefore, a feature specified as "first," "second," etc. may explicitly or implicitly include one or more of the features.

[0058] In this application, unless otherwise clearly defined or specified, “multiple” means two or more.

[0059] In this application, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediary; and internal communication between two components. A person of ordinary skill in the art will understand the specific meanings of these terms in this application based on the specific circumstances. The specific meanings should be understood in the context.

[0060] Furthermore, in this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0061] In the drawings of the embodiments of the present application, physical structures such as components and assemblies are represented by guide lines; hollow structures such as openings, holes, spaces, and cavities are represented by guide lines with arrows.

[0062] Perovskite solar cell modules offer advantages such as high theoretical conversion efficiency, low production cost, and highly adjustable bandgap width. However, commercialization of perovskite solar cell modules requires addressing issues such as efficient, large-area production, high conversion efficiency, and high stability. Among these, stacked solar cell modules, combining perovskite and crystalline silicon solar cells, can effectively overcome the Shockley-Queisser limit and improve the conversion efficiency of perovskite solar cell modules.

[0063] Perovskite and crystalline silicon solar cell modules have wide and narrow bandgap absorption layers, respectively, which can absorb short-wavelength and long-wavelength light, reducing thermal relaxation and energy loss. Currently, perovskite and crystalline silicon solar cell stacked modules are available in two formats: four-terminal output and two-terminal output. The two-terminal output only requires a subsequent electrical matching system, effectively reducing investment costs. The two-terminal output stacked module is further divided into series stacking and parallel stacking.

[0064] In a series stack, perovskite cell modules directly use crystalline silicon cell modules as substrates to achieve cell production. Series stacking requires current matching between the upper and lower cell modules. However, the sunlight shining on the earth exhibits different spectral distributions at different times, seasons, and locations. These can easily lead to current mismatch between perovskite cell modules and crystalline silicon cell modules, resulting in reduced output power. At the same time, the rough surface of crystalline silicon cell modules also increases the difficulty of perovskite cell module production.

[0065] In a parallel stack, perovskite and crystalline silicon cell modules are prepared separately. The positive and negative electrode output terminals of the perovskite and crystalline silicon cell modules are then connected positive-positive and negative-negatively to form a parallel structure. This approach has lower requirements for current matching and is therefore less sensitive to spectral changes. Furthermore, since the crystalline silicon and perovskite cell modules are prepared separately, the difficulty of preparing the perovskite cell module can be effectively reduced.

[0066] In the stack connected in parallel at both ends, the output voltage of the perovskite battery module with the same size as the crystalline silicon battery module is significantly higher than that of the crystalline silicon battery module. In some cases, it can even reach more than four times the output voltage of the crystalline silicon battery module. The serious voltage mismatch phenomenon makes parallel connection more difficult, so the above-mentioned voltage adaptation problem needs to be solved.

[0067] The present application embodiment provides a laminated battery assembly 100, referring to Figure 1 , Figure 1 A cross-sectional view of a stacked battery assembly 100 is shown as an example. The stacked battery assembly 100 includes a crystalline silicon battery assembly 110 and a perovskite battery assembly 120 connected in parallel. The perovskite battery assembly 120 is electrically connected to a first positive lead 91 and a first negative lead 92, and the crystalline silicon battery assembly 110 is electrically connected to a second positive lead 102 and a second negative lead 103. The first positive lead 91 is connected to the second positive lead 102, and the first negative lead 92 is connected to the second negative lead 103, thereby achieving mutual parallel connection between the crystalline silicon battery assembly 110 and the perovskite battery assembly 120.

[0068] Since the crystalline silicon battery assembly 110 and the perovskite battery assembly 120 are connected in parallel, it is necessary to prevent a short circuit between the two. Figure 1 The laminated battery assembly 100 also includes an insulating glue 130. There is a gap between the crystalline silicon battery assembly 110 and the perovskite battery assembly 120. The insulating glue 130 fills the gap to isolate the crystalline silicon battery assembly 110 and the perovskite battery assembly 120 from each other, reducing the possibility of a short circuit between the two. In this way, the laminated battery assembly 100 will be more stable.

[0069] The insulating adhesive 130 may be any adhesive structure having an insulating function, such as POE (Polyolefin Elastomer) adhesive film, EVA (Ethylene-vinyl Acetate Copolymer) adhesive film, etc., and this application does not impose any specific limitation on this.

[0070] In addition, the stacked battery assembly 100 also includes a structure for encapsulating the crystalline silicon battery assembly 110 and the perovskite battery assembly 120, referring to Figure 1 The laminated cell assembly 100 further includes a light-transmitting encapsulant 140, a back encapsulant 150, and a sealing adhesive 160. The crystalline silicon cell assembly 110 and the perovskite cell assembly 120 are both disposed between the light-transmitting encapsulant and the back encapsulant. The sealing adhesive 160 is also disposed between the light-transmitting encapsulant 140 and the back encapsulant 150. The sealing adhesive 160 surrounds the crystalline silicon cell assembly 110 and the perovskite cell assembly 120, providing a sealing and waterproofing effect.

[0071] Since the perovskite cell assembly 120 is relatively thin (e.g., 1 μm), the perovskite cell assembly 120 is disposed on a light-transmitting package 140, which serves as a backing plate for the perovskite cell assembly 120. The light-transmitting package 140 can be any light-transmitting package structure, for example, a substrate glass plate or a transparent plastic plate, and this application does not impose any specific restrictions on this.

[0072] The crystalline silicon cell assembly 110 is arranged between the perovskite cell assembly 120 and the back packaging component 150. For example, when the stacked cell assembly 100 is in use, the light-transmitting packaging component 140 is at the top, and the perovskite cell assembly 120 and the crystalline silicon cell assembly 110 are below in sequence (the perovskite cell assembly 120 is located above the crystalline silicon cell assembly 110), and the back packaging component 150 is at the bottom.

[0073] The structure of the back encapsulation member 150 can be selected as needed. For example, the back encapsulation member 150 can be a glass plate, a plastic plate, or an encapsulation plastic film, etc. The encapsulation adhesive 160 can be any edge sealant capable of encapsulating photovoltaic modules. For example, the encapsulation adhesive 160 can be a butyl-type photovoltaic module edge sealant, which has excellent water vapor barrier properties, adhesion, and long-term weather resistance, effectively delaying water vapor corrosion of the laminated cell module 100 in outdoor high temperature and high humidity environments.

[0074] The perovskite cell assembly 120 is a light-transmitting structure. When light shines on the laminated cell assembly 100, it also shines on the light-transmitting package 140. The light that passes through the light-transmitting package 140 shines on the perovskite cell assembly 120. Because the perovskite cell assembly 120 is light-transmitting, some light passes through the perovskite cell assembly 120 and then shines on the crystalline silicon cell assembly 110. The perovskite cell assembly 120 and the crystalline silicon cell assembly 110 absorb light in different wavelengths, respectively, reducing the loss of light energy.

[0075] The present application also provides a crystalline silicon battery assembly 110, referring to Figure 2 , Figure 2The structure of a crystalline silicon battery module 110 is shown as an example. The crystalline silicon battery module 110 includes a plurality of battery cells 101 (silicon battery cells) connected in series. Among the plurality of battery cells 101 connected in series, the battery cell 101 at one end (the series end) is connected to a second positive lead 102 (which can be connected to a bus bar), and the battery cell 101 at the other end (the series end) is electrically connected to a second negative lead 103 (which can be connected to a bus bar).

[0076] The above-mentioned multiple battery cells 101 can be connected in series in any suitable manner, for example, referring to Figure 3 , Figure 3 The exemplary embodiment shows the connection of multiple cells 101 in series by welding multiple metal wires 104 (e.g., welding ribbons). The metal wires 104 are in a "Z" shape and are used to weld the positive and negative electrodes of two adjacent cells 101. In other examples, shingling technology can also be used to connect two adjacent cells 101 in series, and this application does not impose specific limitations on this.

[0077] Figure 4 The structure of a single cell 101 is shown as an example. Figure 3 and Figure 4 In the crystalline silicon cell assembly 110, each cell 101 includes a silicon wafer 1, a first film layer 2, and a second film layer 3. Figure 5 , Figure 5 for Figure 4 In the enlarged view at point B, the silicon wafer 1 has a first surface 11 and a second surface 12 back to back in the thickness direction, a first film layer 2 is arranged (for example, deposited) on the first surface 11, and a second film layer 3 is arranged (for example, deposited) on the second surface 12. The first film layer 2 and the second film layer 3 are both used to separate the photogenerated carriers in the silicon wafer 1.

[0078] When the structure of the battery cell 101 used is different, the type of the silicon wafer 1, the structure of the first film layer 2 and the structure of the second film layer 3 in the battery cell 101 are all different.

[0079] In one example, cell 101 may be a Passivated Emitter Rear Cell (PERC), which uses a passivation film to passivate the back surface, thereby enhancing the internal back reflection of light in the silicon substrate and reducing the recombination rate on the back surface, thereby improving the efficiency of cell 101. In this example, silicon wafer 1 may be a p-type silicon wafer (or, a p-type base silicon layer), first film layer 2 may include a phosphorus emitter layer (or n+ layer), a front surface silicon nitride passivation layer, etc., and second film layer 3 may include a back passivation layer (for example, Al2O3 is negatively charged and serves as the back passivation layer of an n-type silicon wafer to suppress electrons).

[0080] In another example, cell 101 may be a Tunnel Oxide Passivated Contact (TOPCon) cell 101. In this example, silicon wafer 1 may be an n-type silicon wafer, first film layer 2 may include a thioboric acid emitter, and second film layer 3 may include ultra-thin (e.g., 1-2 nm) silicon oxide, phosphorus-doped polysilicon, silicon nitride, etc., together forming a passivated contact structure. This structure can prevent minority carrier-hole recombination, thereby increasing the open-circuit voltage and short-circuit current of cell 101.

[0081] In another example, the cell 101 may be an intrinsic thin film heterojunction cell (HJT) and include a corresponding silicon wafer 1, a first film layer 2, and a second film layer 3. The first film layer 2 may include an amorphous intrinsic silicon layer, a p-type amorphous silicon layer, and a transparent conductive oxide (TCO), and the second film layer 3 may include an amorphous intrinsic silicon layer, an n-type amorphous silicon layer, and a TCO.

[0082] Reference Figure 4 and Figure 5 , a plurality of lines (slits) are drawn on the first film layer 2 by laser or mechanical scribing, so that a plurality of slits (e.g. Figure 4 G1, G2 and G3 in ). Figure 6 , Figure 6 The structure of the other side of the battery cell 101 is shown as an example ( Figure 4 On different sides), a plurality of lines (slits) are drawn on the second film layer 3 by laser or mechanical scribing, so that a plurality of slits (e.g., attached) are formed on the second film layer 3. Figure 6 G4, G5, G6 in the .

[0083] The scribed first film layer 2 is formed into a plurality of parts, wherein Figure 4 and Figure 5 The first film layer 2 includes a first portion 21 and a second portion 22 separated by a gap (e.g., gap G1). The first portion 21 and the second portion 22 may be distributed along a first direction, and the gap G1 between the first portion 21 and the second portion 22 may extend along a second direction. The first direction, the second direction, and the thickness direction are perpendicular to each other. In addition, the gaps G2 and G3 may also extend along the second direction.

[0084] The second film layer 3 is also divided into multiple parts, wherein the reference Figure 5 and Figure 6The second film layer 3 includes a third portion 31 and a fourth portion 32 separated by a gap (e.g., gap G4). The third portion 31 and the fourth portion 32 are distributed along the first direction, and the gap G4 between the third portion 31 and the fourth portion 32 extends along the second direction. In addition, the gaps G5 and G6 may also extend along the second direction.

[0085] Reference Figure 5 The orthographic projection of the first portion 21 on the first surface 11 and the orthographic projection of the third portion 31 on the first surface 11 at least partially overlap, and the orthographic projection of the second portion 22 on the first surface 11 and the orthographic projection of the fourth portion 32 on the first surface 11 at least partially overlap, that is, the first portion 21, the third portion 31 and the silicon wafer 1 therebetween form a sub-cell, for example, Figure 4 In the subcell C1, the second portion 22, the fourth portion 32 and the silicon wafer 1 therebetween form another subcell, for example, Figure 4 Sub-battery C2 in.

[0086] In one example, referring to Figure 5 , the orthographic projection of the first portion 21 on the first surface 11 and the orthographic projection of the third portion 31 on the first surface 11 partially overlap, that is, there is a non-overlapping portion between the two projections. In other examples, the orthographic projection of the first portion 21 on the first surface 11 and the orthographic projection of the third portion 31 on the first surface 11 completely overlap. Similarly, in one example, referring to Figure 5 , the orthographic projection of the second portion 22 on the first surface 11 partially overlaps with the orthographic projection of the fourth portion 32 on the first surface 11. In other examples, the orthographic projection of the second portion 22 on the first surface 11 completely overlaps with the orthographic projection of the fourth portion 32 on the first surface 11.

[0087] In the present application, a plurality of slits are respectively cut on the first film layer 2 and the second film layer 3 to divide the cell 101 into a plurality of sub-cells, for example, Figure 4 In the sub-battery C1 , the sub-battery C2 , the sub-battery C3 and the sub-battery C4 , there is no need to cut the battery cell 101 into a plurality of small battery cells 101 .

[0088] In order to realize the series connection between adjacent sub-cells, for example, in order to realize the series connection between sub-cell C1 and sub-cell C2, refer to Figure 5 A first gate line 23 (which may be a main gate) is provided on the side of the first portion 21 facing away from the silicon wafer 1. The first gate line 23 may be a metal gate line, for example, a silver gate line. Figure 6 A conductor is provided on the side of the fourth portion 32 facing away from the silicon wafer 1. For example, the conductor includes a second gate line 33 (which can be a main gate). The second gate line 33 can be a metal gate line, such as a silver gate line. In other examples, the conductor can also be back silver or back aluminum provided on the back side of the fourth portion 32.

[0089] Figure 7 The series structure is shown as an example. Figure 7 The silicon wafer 1 is provided with a through hole 13 that penetrates the silicon wafer 1 along its thickness direction. The through hole 13 is filled with a conductive medium 131. The first gate line 23 is electrically connected to the conductor through the conductive medium 131. For example, the first gate line 23 is electrically connected to the second gate line 33 through the conductive medium 131. That is, one end of the conductive medium 131 is connected to the first gate line 23, and the other end is connected to the conductor (the second gate line 33).

[0090] In order to facilitate the conductive medium 131 to connect the first gate line 23 and the second gate line 33, refer to Figure 7 The orthographic projection of the first portion 21 on the first surface 11 and the orthographic projection of the fourth portion 32 on the first surface 11 overlap, that is, there is an overlap between the first portion 21 and the fourth portion 32. The through-hole 13 penetrates the silicon wafer 1 while also penetrating the first portion 21 and the fourth portion 32. The through-hole 13 penetrating the first portion 21 and the fourth portion 32 makes it easier to connect the first gate line 23 and the second gate line 33. Furthermore, the overlap of the first portion 21 and the fourth portion 32 in the thickness direction can also allow the aperture of the through-hole 13 to be larger, thereby better serving as a conductive series connection.

[0091] In other examples (not shown in the drawings), the orthographic projection of the first portion 21 on the first surface 11 and the orthographic projection of the fourth portion 32 on the first surface 11 do not overlap, that is, there is no overlap between the first portion 21 and the fourth portion 32. For example, the orthographic projection of the first portion 21 on the first surface 11 and the orthographic projection of the third portion 31 on the first surface 11 completely overlap, and the orthographic projection of the second portion 22 on the first surface 11 and the orthographic projection of the fourth portion 32 on the first surface 11 completely overlap. In this example, the port at one end of the through hole 13 is connected to the gap G1, and the port at the other end is connected to the gap G4, and the first gate line 23 and the conductor extend to both ends of the conductive medium 131, respectively.

[0092] By opening a through hole 13 and filling it with a conductive medium 131, the first gate line 23 and the conductor are electrically connected. That is, the positive and negative electrodes of two adjacent sub-cells are connected via the first gate line 23, the conductive medium 131, and the conductor, so that two adjacent sub-cells on the cell 101 are connected in series. This increases the output voltage of the crystalline silicon cell module 110, allowing it to adapt to the output voltage of the perovskite cell module 120, thus resolving the voltage mismatch problem in the stacked cell module 100.

[0093] In the example where the through hole 13 extends through the first portion 21 and the fourth portion 32, for ease of production, the material of the conductive medium 131 can be the same as the material of the first gate line 23. For example, the conductive medium 131 can be silver, and the first gate line 23 can be a silver gate line. When the first gate line 23 is screen-printed, the material of the first gate line 23 sinks into the through hole 13, filling the through hole 13. The material of the first gate line 23 continues to sink in the through hole 13, forming the conductive medium 131, which is then connected to the conductor below, thereby achieving electrical connection between the first gate line 23 and the conductor.

[0094] Furthermore, to reduce the possibility of internal short circuits within cell 101, an insulating layer (not shown in the drawings) is formed on the inner wall surface of through-hole 13 formed by silicon wafer 1. Specifically, the inner wall surface of silicon wafer 1 exposed in through-hole 13 is provided with an insulating layer, which serves to isolate conductive medium 131 from silicon wafer 1, thereby reducing the possibility of contact between conductive medium 131 and silicon wafer 1 and, consequently, the possibility of short circuits between series-connected sub-cells. The insulating layer can be any suitable layer structure, such as a silicon oxide layer, an aluminum oxide layer, a zirconium oxide layer, etc., and this application does not impose any specific limitations thereto.

[0095] In the example where the conductor includes the second gate line 33, refer to Figure 6 and Figure 7 The first gate lines 23 and the second gate lines 33 can both extend along the first direction. The first gate lines 23 and the second gate lines 33 can both be main gate lines. The first portion 21 can be provided with a plurality of first gate lines 23 spaced apart along the second direction. The fourth portion 32 can also be provided with a plurality of second gate lines 33 spaced apart along the second direction. In addition, a plurality of auxiliary gate lines 24 are connected to both sides of each first gate line 23 and each second gate line 33.

[0096] In other examples, a plurality of first gate lines 23 spaced apart along the second direction are provided on the first portion 21 , and a back-silver or back-aluminum coating covering the entire surface of the fourth portion 32 is provided on the fourth portion 32 .

[0097] There may also be multiple through holes 13 for connecting two adjacent sub-batteries (eg, sub-battery C1 and sub-battery C2) in series. Figure 7 , multiple through holes 13 are arranged at intervals along the second direction, each through hole 13 is filled with a conductive medium 131, and the conductive medium 131 in each through hole 13 connects a group of corresponding first gate lines 23 and second gate lines 33 (or other conductors such as back silver, back aluminum, etc.).

[0098] Reference Figure 7 The shape of the gap (G1) between the first part 21 and the second part 22 can be set according to needs. Similarly, the shape of the gap (G4) between the third part 31 and the fourth part 32 can also be set according to needs.

[0099] In an example provided in this application, Figure 8 The shapes of the plurality of slits on the first film layer 2 are shown as an example. The shapes of the plurality of slits can be the same, for example, Figure 8 The shapes of the gaps G1, G2 and G3 are the same. Figure 9 The partial shape of the gap G1 between the first portion 21 and the second portion 22 is exemplarily shown.

[0100] Reference Figure 9 The gap between the first portion 21 and the second portion 22 includes a first protruding segment 141 and a plurality of first connecting segments 142. The plurality of first connecting segments 142 are distributed in the second direction and extend along the second direction. The first protruding segment 141 is connected between two of the first connecting segments 142. The first protruding segment 141 protrudes from the two first connecting segments 142 connected thereto toward the second portion 22. That is, the first protruding segment 141 and the first connecting segments 142 on both sides jointly form a local straight gap on both sides of the middle protrusion. The local gap is part of the gap G1. The first protruding segment 141 surrounds the through hole 13.

[0101] The gap G1 forms a mutually fitting edge between the first portion 21 and the second portion 22. Figure 9 The edge of the first portion 21 facing the second portion 22 includes a first flange portion 211 (the edge of the first portion 21 facing the first protruding section 141) and a plurality of first straight edges 212 (the edge of the first portion 21 facing the first connecting section 142). The plurality of first straight edges 212 are distributed in the second direction and extend in the second direction. That is, the plurality of first straight edges 212 are flush in the second direction. The first flange portion 211 connects two of the first straight edges 212. The first flange portion 211 protrudes from the first straight edges 212 on both sides toward the second portion 22. The first flange portion 211 is arranged around the through hole 13.

[0102] Reference Figure 9 The edge of the second portion 22 facing the first portion 21 includes a first concave edge 221 (the edge of the second portion 22 facing the first protruding section 141) and multiple second straight edges 222 (the edges of the second portion 22 facing the first connecting section 142). The multiple second straight edges 222 are distributed in the second direction and extend in the second direction. In other words, the multiple second straight edges 222 are flush in the second direction. The first concave edge 221 connects between the two second straight edges 222. The first concave edge 221 is recessed from the first straight edges 212 on both sides toward the side facing away from the first portion 21. The first convex edge 211 extends into the space enclosed by the first concave edge 221.

[0103] Reference Figure 8 and Figure 9In the example where a plurality of through holes 13 pass through the first portion 21, the gap between the first portion 21 and the second portion 22 may include a plurality of first protruding segments 141, each of two adjacent first connecting segments 142 is connected to a first protruding segment 141, and each first protruding segment 141 is arranged around a through hole 13.

[0104] Figure 10 The shapes of the plurality of slits on the second film layer 3 are shown as an example. The shapes of the plurality of slits can be the same. Figure 10 The gaps G4, G5 and G6 in the same shape, Figure 11 The partial shape of the gap G4 between the third portion 31 and the fourth portion 32 is exemplarily shown.

[0105] Reference Figure 11 The gap between the third portion 31 and the fourth portion 32 includes a second protruding segment 151 and a plurality of second connecting segments 152. The plurality of second connecting segments 152 are distributed and extend in the second direction. The second protruding segment 151 is connected between two of the second connecting segments 152. The second protruding segment 151 protrudes from the two second connecting segments 152 it connects toward the third portion 31. In other words, the second protruding segment 151 and the second connecting segments 152 on either side together form a straight local gap on both sides of the central protrusion. This local gap constitutes a portion of the gap G4. The second protruding segment 151 surrounds the through hole 13.

[0106] The gap G4 forms a mutually fitting edge between the third portion 31 and the fourth portion 32. Figure 11 The edge of the third portion 31 facing the fourth portion 32 includes a second concave edge portion 311 (the edge of the third portion 31 facing the second protruding section 151) and a plurality of third straight edges 312 (the edge of the third portion 31 facing the second connecting section 152). The plurality of third straight edges 312 are distributed in the second direction and extend in the second direction. That is, the plurality of third straight edges 312 are flush in the second direction. The second concave edge portion 311 connects two of the third straight edges 312 and is recessed from the two third straight edges 312 toward the side facing away from the fourth portion 32.

[0107] Reference Figure 11The edge of the fourth portion 32 facing the third portion 31 includes a second convex edge portion 321 (the edge of the fourth portion 32 facing the second protruding section 151) and multiple fourth straight edges 322 (the edge of the fourth portion 32 facing the second connecting section 152). The multiple fourth straight edges 322 are distributed in the second direction and extend in the second direction. In other words, the multiple fourth straight edges 322 are flush in the second direction. The second convex edge portion 321 is connected between two of the fourth straight edges 322. The second convex edge portion 321 protrudes from the two fourth straight edges 322 it connects toward the third portion 31. The second convex edge portion 321 extends into the space enclosed by the second concave edge portion 311. The second convex edge portion 321 surrounds the through hole 13.

[0108] Reference Figure 10 and Figure 11 In the example where multiple through holes 13 pass through the fourth part 32, the gap between the third part 31 and the fourth part 32 may include multiple second protruding segments 151, and a second protruding segment 151 is connected between each adjacent second connecting segment 152, and each second protruding segment 151 is arranged around a through hole 13.

[0109] In each sub-cell, the effective part is the overlapped part of the film layers on both sides of the silicon wafer 1, for example, the overlapped part of the first part 21 and the third part 31, and the silicon wafer 1 between the overlapped parts, which constitute the effective part of the sub-cell C1. Figure 12 and attached Figure 13 The examples given make it easier to understand. Figure 12 Another structure of a battery cell 101 is shown as an example (part of the structure on the battery cell 101 is omitted). Figure 13 For attachment Figure 12 A partial side view of Figure 12 In the example shown, the gap G1 and the gap G2 are straight gaps extending along the second direction, and the overlapping portion of the first portion 21 and the third portion 31 is Figure 13 The portion between the dotted line L1 and the dotted line L2 is also the effective portion of the sub-battery C1 in this example. Figure 13 The portion between the middle dashed line L3 and the dashed line L4 is the overlapping portion of the second portion 22 and the fourth portion 32 , which is also the effective portion of the sub-cell C2 .

[0110] Therefore, the more overlapped the film layers on both sides of the silicon wafer 1 are, the more carriers can be moved to the corresponding film layers, and thus, the less loss is caused by dividing the cell 101 into multiple sub-cells. Figure 13Since there is an overlapping portion between the first portion 21 and the fourth portion 32, the overlapping area between the first portion 21 and the third portion 31 is located on the side of the gap G1 away from the second portion 22. In this case, the longer the length of the first portion 21 exceeds the third portion 31, the larger the ineffective area of ​​the first portion 21.

[0111] use Figure 9 In the solution, gap G1 bypasses through-hole 13, causing the portion of first portion 21 penetrated by through-hole 13 to protrude (for example, the portion indicated by shaded area S1 protrudes), while the remaining portion does not need to protrude outward. In other words, the area of ​​first portion 21 extending beyond third portion 31 is relatively small. Furthermore, since first portion 21 has an outwardly protruding portion (the portion indicated by shaded area S1), both sides of the protruding portion S1 can be accommodated by second portion 22. For example, the portion indicated by shaded area S2 extends into both sides of protruding portion S1. This results in a greater overlap between second portion 22 and fourth portion 32. This application reduces the loss of battery cell 101 by reducing the ineffective area of ​​first portion 21 and increasing the effective area of ​​second portion 22.

[0112] Similarly, with Figure 13 For example, since the first portion 21 and the fourth portion 32 overlap, the overlapping area of ​​the second portion 22 and the fourth portion 32 is located on the side of the gap G4 facing away from the first portion 21. In this case, the longer the fourth portion 32 extends beyond the second portion 22, the larger the inactive area of ​​the fourth portion 32.

[0113] use Figure 11 In the embodiment of the present invention, the gap G4 bypasses the through-hole 13, causing the portion of the fourth portion 32 penetrated by the through-hole 13 to protrude (for example, the portion indicated by the shadow S3 protrudes), while the remaining portion does not need to protrude outward. In other words, the area of ​​the fourth portion 32 that protrudes beyond the second portion 22 is relatively small. Furthermore, since the fourth portion 32 has an outwardly protruding portion (the portion indicated by the shadow S3), both sides of the protruding portion S3 can be accommodated by the third portion 31. For example, the portion indicated by the shadow S4 protrudes into both sides of the protruding portion S3. This increases the overlap area between the third portion 31 and the first portion 21. This application reduces the loss of the battery cell 101 by reducing the ineffective area of ​​the fourth portion 32 and increasing the effective area of ​​the third portion 31.

[0114] To further reduce losses, refer to Figure 9 and Figure 11The first protruding section 141 and the second protruding section 151 are both arc-shaped. That is, the first convex edge 211, the first concave edge 221, the second convex edge 321, and the second concave edge 311 are all arc-shaped. Compared to a zigzag-line slit, the arc-shaped first and second protruding sections 141 and 151 can further reduce the ineffective area of ​​the first portion 21 and the fourth portion 32, and further increase the effective area of ​​the second portion 22 and the third portion 31, further reducing the loss of the battery cell 101. Furthermore, compared to a zigzag-line slit, the arc-shaped first and second protruding sections 141 and 151 are also easier to manufacture and process.

[0115] In other examples, the first protruding section 141 and the second protruding section 151 may also both be in a broken line shape or an irregular shape.

[0116] In addition, refer to Figure 11 The edge of the first portion 21 facing the multiple first connecting segments 142 (for example, the first straight edge 212) is flush with the edge of the third portion 31 facing the multiple second connecting segments 152 (for example, the third straight edge 312) in the thickness direction, and the edge of the second portion 22 facing the multiple first connecting segments 142 (for example, the second straight edge 222) is flush with the edge of the fourth portion 32 facing the multiple second connecting segments 152 (for example, the fourth straight edge 322) in the thickness direction.

[0117] Through this design, the portion of the first portion 21 penetrated by the through hole 13 protrudes outside the third portion 31, reducing the ineffective area of ​​the first portion 21 and increasing the effective area of ​​the second portion 22. The portion of the fourth portion 32 penetrated by the through hole 13 protrudes outside the second portion 22, reducing the ineffective area of ​​the fourth portion 32 and increasing the effective area of ​​the third portion 31.

[0118] In other examples, the first straight side portion 212 and the third straight side portion 312 may not be flush, and the second straight side portion 222 and the fourth straight side portion 322 may not be flush.

[0119] In other examples, the battery cell 101 may also be Figure 12 The battery cell 101 is shown.

[0120] In other examples, the first film layer 2 of the cell 101 may be Figure 8 That is, each gap on the first film layer 2 includes a protruding section and a connecting section, and the second film layer 3 of the battery cell 101 can be drawn in the manner of Figure 12 That is, each gap on the second film layer 3 is a straight line gap. For example, the protruding portion of the first portion 21 coincides with the third portion 31, compared to the first film layer 2 and the second film layer 3, which are both in accordance with Figure 12Marking in this manner can also reduce the loss of the battery cell 101.

[0121] In the example provided in this application, the sub-battery C2 and the sub-battery C3 , and the sub-battery C3 and the sub-battery C4 can be connected in series by providing a through hole 13 and filling the through hole 131 .

[0122] In other examples, refer to Figure 14 , Figure 14 The structure of another battery cell 101 is shown as an example (part of the structure on the battery cell 101 is omitted), and the first film layer 2 and the second film layer 3 can also be Figure 14 Draw lines in this way to achieve Figure 14 The sub-battery C1 and the sub-battery C2 are connected in series, the sub-battery C2 and the sub-battery C3 are connected in series, and the sub-battery C3 and the sub-battery C4 are connected in series. The series connection of two adjacent sub-batteries is also the above-mentioned series connection method of the present application - the first gate line 23 is electrically connected to the conductor through the conductive medium 131 in the through hole 13.

[0123] In addition, the embodiment of the present application further provides a perovskite battery assembly 120, Figure 15 The structure of the perovskite battery assembly 120 is shown as an example. Figure 16 An example is shown Figure 15 The perovskite battery assembly 120 is a cross-sectional view of the perovskite battery assembly 120. The perovskite battery assembly 120 includes a first electrode layer 4, an electron transport layer 5, a perovskite layer 6, a hole transport layer 7, and a second electrode layer 8 in sequence. The first electrode layer 4 and the second electrode layer 8 are both transparent conductive oxides (TCO). The first electrode layer 4 is provided on the light-transmitting package 140 (refer to FIG. Figure 1 ).

[0124] The material chemical formula of the perovskite layer 6 is ABX3, where A + Including CH3NH3 + (MA + ), NH2CH=NH2 + (FA + ), Cs + , Rb + etc., B. 2+ Including Pb 2+ 、Sn 2+ Wait, X - Including Cl - Br - , I -Halogen ions, such as MAPbI3, can be used as the material of the perovskite layer 6. After absorbing light, the perovskite layer 6 generates electron-hole pairs, which move to the electron transport layer 5 and the hole transport layer 7 respectively under the action of the built-in electric field, and finally reach the electrode to produce a photovoltaic effect.

[0125] In an example provided in this application, referring to Figure 16 The perovskite cell assembly 120 has a bandgap of 1.40 eV to 2.2 eV. Laser scribing is used to connect the sub-cells in the perovskite cell assembly 120 in series, for example, lines P1, P2, and P3. The width of each sub-cell in the perovskite cell assembly 120 ranges from 3 to 10 mm. For example, each sub-cell in the perovskite cell assembly 120 has a width of 3 mm, 5 mm, or 10 mm.

[0126] Among them, reference Figure 16 The first electrode layer 4 and the second electrode layer 8 both extend outward for a distance, and the outward extending portion of the first electrode layer 4 and the outward extending portion of the second electrode are both provided with welding rods 9. Both welding rods 9 are set toward the crystalline silicon battery assembly 110, and the first positive lead 91 is connected to the welding rod 9 on the second electrode layer 8, and the first negative lead 92 is connected to the welding rod 9 on the first electrode layer 4.

[0127] The laminated battery assembly 100 of the present application can effectively increase the operating voltage of the crystalline silicon battery assembly 110 and match it with the operating voltage of the perovskite battery assembly 120 to achieve the highest power output. In addition, different types of crystalline silicon battery assemblies 110 have little effect on the preparation of the perovskite battery assembly 120, so that the perovskite battery assembly 120 can be prepared using a suitable method. In the laminated battery assembly 100, the perovskite battery assembly 120 and the crystalline silicon battery assembly 110 are physically separated, and the two components can be produced at the same time, and then the laminated battery assembly 100 is formed by co-packaging. Since the output voltage is less affected by the spectrum, the laminated battery assembly 100 of the present application has more stable electrical output characteristics.

[0128] In other examples, the crystalline silicon cell assembly 110 of the present application may also be combined with other cell assemblies (other cell assemblies other than the perovskite cell assembly 120 ) to form other types of stacked cell assemblies.

[0129] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A crystalline silicon battery assembly, characterized in that: It includes multiple battery cells connected in series. Each of the solar cells comprises a silicon wafer, a first film layer and a second film layer, wherein the silicon wafer has a first surface and a second surface back to back in the thickness direction, the first film layer is arranged on the first surface, and the second film layer is arranged on the second surface; The first film layer includes a first portion and a second portion separated by a gap, the second film layer includes a third portion and a fourth portion separated by a gap, an orthographic projection of the first portion on the first surface and an orthographic projection of the third portion on the first surface at least partially overlap, and an orthographic projection of the second portion on the first surface and an orthographic projection of the fourth portion on the first surface at least partially overlap, A first gate line is provided on a side of the first portion facing away from the silicon wafer, a conductor is provided on a side of the fourth portion facing away from the silicon wafer, a through hole is provided on the silicon wafer and penetrates the silicon wafer along the thickness direction, the through hole is filled with a conductive medium, and the first gate line is electrically connected to the conductor through the conductive medium.

2. The crystalline silicon battery assembly according to claim 1, characterized in that: The orthographic projection of the first portion on the first surface partially overlaps with the orthographic projection of the fourth portion on the first surface, and the through hole passes through the first portion and the fourth portion.

3. The crystalline silicon battery assembly according to claim 1 or 2, characterized in that: The first portion and the second portion are distributed along a first direction, and a gap between the first portion and the second portion extends along a second direction. The third portion and the fourth portion are distributed along the first direction, the gap between the third portion and the fourth portion extends along the second direction, and the first direction, the second direction and the thickness direction are perpendicular to each other.

4. The crystalline silicon battery assembly according to claim 3, characterized in that: The gap between the first part and the second part includes a first protruding segment and a plurality of first connecting segments, the plurality of first connecting segments are distributed in the second direction and extend along the second direction, the first protruding segment is connected between two of the first connecting segments, the first protruding segment protrudes toward the second part, and the first protruding segment surrounds the through hole.

5. The crystalline silicon battery assembly according to claim 4, characterized in that: The gap between the third part and the fourth part includes a second protruding segment and a plurality of second connecting segments, the plurality of second connecting segments are distributed in the second direction and extend along the second direction, the second protruding segment is connected between two of the second connecting segments, the second protruding segment protrudes toward the third part, and the second protruding segment surrounds the through hole.

6. The crystalline silicon battery assembly according to claim 5, characterized in that: The first protruding section and the second protruding section are both arc-shaped.

7. The crystalline silicon battery assembly according to claim 5 or 6, characterized in that: The edge of the first portion facing the plurality of first connecting segments is flush with the edge of the third portion facing the plurality of second connecting segments in the thickness direction. The side of the second portion facing the plurality of first connecting segments is flush with the side of the fourth portion facing the plurality of second connecting segments in the thickness direction.

8. The crystalline silicon cell assembly according to any one of claims 1 to 7, characterized in that: The conductor includes a second gate line, and an extending direction of the second gate line is parallel to an extending direction of the first gate line.

9. The crystalline silicon cell assembly according to any one of claims 1 to 8, characterized in that: The material of the conductive medium is the same as that of the first gate line.

10. The crystalline silicon battery assembly according to claim 9, characterized in that: An insulating layer is provided on the inner wall surface of the silicon wafer surrounding the through hole.

11. A laminated battery assembly, characterized in that: It comprises a perovskite cell assembly and a crystalline silicon cell assembly according to any one of claims 1 to 10, wherein the crystalline silicon cell assembly is connected in parallel with the titanite cell assembly.

12. The laminated battery assembly according to claim 11, characterized in that: The perovskite cell assembly is a light-transmitting structure, the crystalline silicon cell assembly and the perovskite cell assembly are distributed along the thickness direction, and the first surface of the silicon wafer faces the perovskite cell assembly.

13. The laminated battery assembly according to claim 12, wherein: The laminated battery assembly further includes insulating glue, which is disposed between the crystalline silicon battery assembly and the perovskite battery assembly.

14. The laminated battery assembly according to any one of claims 11 to 13, characterized in that: The perovskite battery assembly is electrically connected to a first positive electrode lead and a first negative electrode lead, Among the plurality of battery cells connected in series, the battery cell at one end is connected to a second positive lead, and the battery cell at the other end is electrically connected to a second negative lead. The first positive electrode lead is connected to the second positive electrode lead, and the first negative electrode lead is connected to the second negative electrode lead.

15. The laminated battery assembly according to any one of claims 11 to 14, characterized in that: The stacked cell assembly also includes a light-transmitting package, a back package and a packaging glue. The perovskite cell assembly is arranged on the light-transmitting package, the crystalline silicon cell assembly is arranged between the perovskite cell assembly and the back package, the packaging glue is arranged between the light-transmitting package and the back package, and the packaging glue surrounds the crystalline silicon cell assembly and the perovskite cell assembly.

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