Method for manufacturing a graphene-containing laminate

Abstract

There is provided a method for manufacturing a graphene-containing laminate (240), the method comprising: (i) providing a first wafer (220) comprising a first layer (205) on a first silicon support (200), where the first layer (205) is a dielectric layer and has an exposed growth surface (205 ') remote from the first silicon support (200), where the first layer (205) is a graphene layer and has an exposed growth surface (205') remote from the first silicon support (200); the first layer (205) has a first region (205c) extending downward from the exposed growth surface (205 ') by at least 2 nm, the first region satisfying the following conditions: a) a dislocation density of less than 5,000 cm-2 as measured by TEM; and b) a surface roughness (Ra) of less than 1 nm as measured by AFM; (ii) providing a second wafer (235), the second wafer comprising a second layer (230), where the second layer (230) has an exposed contact surface (230 '); (iii) forming a graphene layer structure (210) on the exposed growth surface of the first layer by CVD; (iv) wafer bonding the first wafer (220) to the exposed contact surface (230 ') of the second layer (230) to sandwich the graphene layer structure (210) between the first silicon support (200) and the second layer (230); and (v) removing the first silicon support (200) to leave a remaining portion of the first layer (205) formed from the first region (205c) and having a thickness of less than 20 nm.

Description

[0001] The present invention relates to a method for producing a graphene-containing laminate, as well as graphene-containing laminates and electronic devices obtainable therefrom. More particularly, the invention relates to a method comprising forming a graphene layer structure by CVD directly on a non-metallic surface of a wafer, whereby the layer of the wafer provided with the non-metallic surface remains incorporated into the resulting graphene-containing laminate, making it possible to produce electronic devices comprising said layer therefrom.

[0002] Two-dimensional (2D) materials, especially graphene, are currently the focus of global research and development. 2D materials have been shown to have extraordinary properties in both theory and practice, which has led to a large number of products incorporating such materials, including coatings, batteries, and sensors. Graphene is the most prominent and is being studied for a range of potential applications. The use of graphene in electronic devices and their components is the most noteworthy, and includes transistors, diodes, LEDs, photovoltaic cells, Hall-effect sensors, current sensors, biosensors, etc.

[0003] Thus, various electronic devices are known in the prior art that have integrated graphene layer structures (single or multilayer graphene) and / or other 2D materials as key materials for achieving improvements in such devices relative to earlier devices and electronic products. These include structural improvements through the use of thinner and lighter materials (which can result in flexible electronics), as well as performance improvements such as increased electrical and thermal conduction, resulting in higher operating efficiency.

[0004] The production of graphene over a sufficiently large area with high uniformity is a major problem in the art that has hindered its adoption in commercial processes and final electronic devices. The standard in the art is to produce graphene by CVD on copper foil or other catalytic metal substrates. Since then, a considerable portion of research and development has focused on the need to optimize the process by which graphene is transferred from such substrates to substrates of interest for electronic devices (i.e., non-metallic substrates, for example, semiconductors such as silicon and insulators such as sapphire).

[0005] However, the inventors discovered that graphene grown on copper is inevitably contaminated, if not by copper, then at least by additional materials necessary to affect the transfer process. These include the transfer polymer, such as PMMA, metal etchants, and solvents used to remove the polymer. However, polymer residues cannot be completely removed, and graphene produced by such methods cannot be free of transfer polymer and / or copper. Furthermore, the physical manipulation of graphene during transfer results in defects in the atomically thin material.

[0006] Nanomaterials, 2021, 11, 2837 “Graphene Transfer: A Physical Perspective” provides an updated review of graphene transfer methods.

[0007] Nature Communications, 2021, 12,917. “Large-area integration of two-dimensional materials and their heterostructures by wafer bonding” involves a method for transferring CVD graphene from copper foil to silicon wafers.

[0008] Adv.Mater.Technol.2023, 2201587 “Assessment of Wafer-Level Transfer Techniques of Graphene with Respect to Semiconductor Industry Requirements” is a recent example of wafer-level graphene transfer technology, and it was observed that both technologies resulted in significant copper contamination.

[0009] US 2013 / 240839 A1 relates to graphene channel-based devices and fabrication techniques thereof, which may include a wafer bonding step for forming an oxide-to-oxide bond between an oxide-coated graphene layer and a corresponding CMOS device wafer.

[0010] US2013 / 256629 A1 relates to a graphene semiconductor device and a method of manufacturing the same, which may include attaching a semiconductor layer of a laminate further including a sacrificial substrate and a sacrificial layer therebetween to a surface of a graphene layer; and etching the sacrificial layer to remove the sacrificial substrate.

[0011] It is also known in the art that graphene can be synthesized, manufactured, formed directly on the non-metallic surface of a substrate. The inventors have found that the most effective method for manufacturing high-quality graphene, in particular manufacturing high-quality graphene directly on such a non-metallic surface, is the method disclosed in WO 2017 / 029470 (the contents of which are incorporated herein by reference), which provides a two-dimensional material with multiple advantageous features, in particular graphene, including excellent crystal quality, large material grain size, minimal material defects, large sheet size, and no metal or organic polymer contamination. The method of WO 2017 / 029470 can be performed using a vapor phase epitaxy (VPE) system and a metal-organic chemical vapor deposition (MOCVD) reactor.

[0012] Although the method of WO 2017 / 029470 is capable of producing high-quality graphene with excellent uniformity and a constant number of layers (as needed) across the entire area on its substrate without additional carbon fragments or carbon islands, the inventors have found that this introduces problems when forming a dielectric layer on the graphene (e.g., by atomic layer deposition). Such problems are not encountered in the prior art of transferring graphene because defects that act as nucleation sites are inevitably present. Therefore, the inventors have found that there are significantly greater challenges associated with forming a dielectric layer on the initial surface of CVD-grown graphene.

[0013] WO 2022 / 175273 (the contents of which are incorporated herein by reference in their entirety) and corresponding GB 2603905 and TW202246175 are publications originating from the inventors, which relate to the formation of a thin graphene-containing conductive substrate obtainable by etching a sacrificial silicon wafer from a graphene layer structure formed on an insulating layer, which insulating layer itself is formed on a silicon wafer.

[0014] US2011 / 068320 A1 relates to an electronic device comprising a lower layer constructed of a highly ordered crystalline material with a high dielectric constant, an upper layer constructed of a crystalline material with a high dielectric constant, and a graphene layer positioned between the upper and lower layers. The document does not disclose a manufacturing method, but does disclose that these layers can be formed on a substrate material.

[0015] WO 2022 / 200351 A1 relates to a method for forming a graphene layer structure on a specific growth surface of a substrate (particularly YSZ) by CVD.

[0016] US 2012 / 175594 A1 relates to semiconductor structures, and in particular to a local dual-gate graphene-based device and a method of manufacturing the local dual-gate graphene-based device.

[0017] US 8785261 B relates to the field of microelectronic transistor fabrication, and more particularly to the formation of a graphene layer as a channel layer for a microelectronic transistor.

[0018] JP 2010153793 A (and corresponding US 2010 / 200839 A1) relates to graphene for use in electronic and optical device applications, more particularly to substrates having graphene layers grown thereon, and electro-optical integrated circuits formed in such substrates.

[0019] The present invention aims to overcome or at least reduce the combination of the above problems in the prior art to enable high-quality, defect-free and contamination-free graphene and high-quality dielectric wafer-scale integration into electronic devices, or at least provide a commercially viable alternative.

[0020] In a first aspect, the present invention provides a method for producing a graphene-containing laminate, the method comprising:

[0021] (i) providing a first wafer, the first wafer comprising a first layer on a first silicon support, wherein the first layer is a dielectric layer and has an exposed growth surface remote from the first silicon support, wherein the first layer has a first region extending downwardly by at least 2 nm from the exposed growth surface, the first region satisfying the following conditions:

[0022] a) less than 5,000 cm as measured by TEM -2 dislocation density; and

[0023] b) a surface roughness (Ra) of less than 1 nm as measured by AFM;

[0024] (ii) providing a second wafer, the second wafer comprising a second layer, wherein the second layer has an exposed contact surface;

[0025] (iii) forming a graphene layer structure on the exposed growth surface of the first layer by CVD, and optionally forming a further layer comprising a dielectric material on the graphene layer structure;

[0026] (iv) wafer bonding the first wafer to the exposed contact surface of the second layer to sandwich the graphene layer structure between the first silicon support and the second layer; and

[0027] (v) Removing the first silicon support and optionally removing portions of the first layer to leave remaining portions of the first layer formed from the first region and having a thickness of less than 20 nm.

[0028] The present disclosure will now be further described. In the following paragraphs, different aspects / embodiments of the present disclosure are defined in more detail. Each aspect / embodiment so defined may be combined with any other aspect / embodiment or multiple aspects / embodiments, unless clearly indicated to the contrary. In particular, any feature indicated as preferred or advantageous may be combined with any other feature or features indicated as preferred or advantageous.

[0029] The present invention relates to a method for manufacturing a graphene-containing laminate. As described in more detail herein, the graphene-containing laminate comprises a silicon support having a graphene layer structure sandwiched between a basic dielectric layer and an auxiliary dielectric layer thereon. Therefore, there is no intermediate layer between any given layer referred to as being "on" another layer. Graphene is a well-known two-dimensional material, which refers to an allotrope of carbon comprising a single layer of carbon atoms in a hexagonal lattice. As used herein, a graphene layer structure refers to one or more layers of graphene. Therefore, the present invention relates to the formation of single-layer graphene and multilayer graphene. The graphene layer structure preferably has from 1 to 10 graphene monolayers. In many subsequent applications of graphene-containing laminates for forming electronic devices, single-layer graphene is particularly preferred. Therefore, the graphene layer structure is preferably a graphene monolayer. However, multilayer graphene may be preferred for certain applications, and 2 or 3 layers of graphene may be preferred.

[0030] In the first step, both a first wafer and a second wafer are provided. In the field of semiconductor electronics manufacturing, wafer is a well-known term that can be used synonymously with, for example, substrate. Wafers are typically primarily formed from silicon and may then have multiple layers of thin films deposited on them and etched to manufacture electronic devices and integrated circuits.

[0031] The first wafer described herein comprises a first layer on a first silicon support, wherein the first layer is a dielectric layer. The second wafer comprises a second layer preferably disposed on a second silicon support, wherein the second layer of the second wafer provides an exposed contact surface (i.e., an exposed surface for contacting the first wafer in a subsequent step).

[0032] Throughout this specification, “first,” “second,” “basic,” “auxiliary,” etc. may be used to describe various layers and / or supports, but it should be understood that these features are not limited by these terms, but are only used to distinguish one layer and / or support from another layer and / or support.

[0033] The second wafer may consist of a second layer (i.e., may be a single material including silicon), or a second layer on a silicon support. As described herein, preferably, the first and second layers are non-metallic layers, preferably dielectric layers, and may consist of a single material or may be formed from multiple sub-layers.

[0034] The second wafer can be described as a target wafer or target substrate onto which the graphene layer structure is transferred, and is therefore not particularly limited. The second wafer is a wafer that can be incorporated into the manufacture of electronic devices from the resulting graphene-containing laminate. Therefore, the second wafer preferably includes a silicon support and / or can be a "CMOS" wafer. Such a wafer is typically a silicon wafer having associated circuits embedded in the wafer. The second wafer can also include an area or channel of embedded material, which is, for example, a waveguide material (such as silicon nitride embedded in silicon dioxide), which is suitable for electro-optical modulators and photodetectors. The exposed contact surface of the second layer can also be formed by areas of different materials. For example, the silicon support can have a surface including a patterned area of ​​silicon and an area of ​​embedded dielectric material. Such a wafer can be suitable for manufacturing graphene barriers. Preferably, the silicon support can be a "pure" silicon support (essentially consisting of doped or undoped silicon). When the second wafer including the second layer further includes a second silicon support, the exposed contact surface of the second layer is remote from the second silicon support (the opposite non-exposed surface of the second layer is the surface in contact with the support).

[0035] Since the second wafer is not particularly limited, it is advantageous that the second wafer can include metal contacts at the exposed second surface (along with associated circuitry embedded in the second layer, and optionally, an underlying support). This is particularly advantageous in the case of graphene layer structures grown using CVD, as it is undesirable to grow directly onto metal contacts rather than onto a non-metallic surface by an MOCVD process as described herein. Thus, the method allows the graphene formed by such a method to be incorporated into devices having underlying contacts.

[0036] In view of the subsequent method steps, the first wafer can be said to include a sacrificial silicon support. Therefore, preferably, the silicon support can be a "pure" silicon support. Similar to the second wafer, the first layer of the first wafer has an exposed growth surface away from the first silicon support. The term "growth" is used to refer to the exposed surface on which graphene is directly formed (i.e., grown) by CVD.

[0037] The thickness of the silicon support layer is typically much thicker than the thickness of the layer above it. When a support layer is present and where it is present, the support layer typically has a thickness of 250 μm to 1.5 mm, for example, from 400 μm to 1 mm. On the other hand, the thickness of the layer above it is substantially thinner. Preferably, the thickness of such a layer is at least 2 nm, preferably at least 5 nm, and / or less than 500 nm, preferably less than 100 nm. A suitable range of layer thickness is preferably 5 nm to 100 nm, preferably 10 nm to 50 nm. In some embodiments, very thin layers are preferred, and the thickness of the layer may preferably be from 2 nm to 10 nm. In some embodiments, the first layer and / or the second layer does not include native silicon oxide that can be removed from the surface of the silicon support before forming the layer.

[0038] In the present invention, the first layer further has a first region extending downward by at least 2 nm from the exposed growth surface, the first region satisfying the following conditions: a) less than 5,000 cm as measured by transmission electron microscopy (TEM); -2 and b) a surface roughness (Ra) of less than 1 nm as measured by atomic force microscopy (AFM).

[0039] The inventors have found that the uppermost region of the first layer formed on the silicon support has the highest quality, which generally increases with increasing thickness and is therefore most suitable for forming graphene thereon. The first layer can be grown to a sufficient thickness and, if necessary, by using sublayers to reduce the number of dislocations subsequently formed to provide the crystal (sub) layer of the first region. The first region is generally composed of a single material, but can also be multilayered. As described herein, a buffer layer can be used to reduce the lattice mismatch between silicon and the desired material forming the first region. In other embodiments, the first layer (and therefore the first region) is composed of a single material and can be grown thicker, whereby the density of dislocations at the interface with the silicon support is further reduced from the interface. Preferably, the first layer has a thickness from 2nm to 500nm, preferably from 5nm to 100nm.

[0040] Thus, the first region is characterized in that at least a portion of the first layer (which may be the entire first layer) has a thickness of at least 2 nm. The dislocation density is used to characterize the high degree of single crystallinity of the first region and can be measured using conventional techniques known to those skilled in the art, such as TEM (e.g., cross-sectional TEM). Although lower dislocation densities (such as less than 4,000 cm -2 , or less than 2,000cm -2) is generally preferred, but a minimum number of dislocations may still be desired because, without wishing to be bound by theory, these defect sites at the exposed surface of the first layer are believed to provide sites for graphene nucleation by CVD. Thus, the minimum defect density may be at least 1 cm -2 , at least 10cm -2 , or at least 100cm -2 .

[0041] The first region also has a surface roughness less than 1nm, which can be measured again by conventional techniques known to those skilled in the art (such as AFM). As will be understood, this is the measurement of the exposed growth surface of the first layer. Such low surface roughness is conducive to forming high-quality graphene by CVD. In some embodiments, the surface roughness can be less than 0.8nm, or less than 0.6nm. Surface roughness as used herein refers to arithmetic mean roughness, referred to as Ra.

[0042] Preferably, the first region of the first layer extends downward from the exposed growth surface by at least 5 nm, preferably at least 10 nm, preferably at least 20 nm. Dislocation density is a parameter known in the art, but is generally used to characterize significantly thicker layers (e.g., GaAs layers in LED structures). Dislocation density is generally measured by XRD, which provides an average dislocation density across the entire layer (which can be several microns thick). In the GaAs example above, the dislocation density across the entire layer is very important for the characteristics of the final device. On the contrary, the present invention utilizes a very thin uppermost region retained in the final laminate. TEM is a measurement technique that enables measurement of dislocation density close to the layer surface, although in practice accurately measuring the dislocation density in a region less than 2 nm becomes challenging. Therefore, for example, characterizing the first region with a thickness of at least 10 nm is preferred. Since the portion of the first layer retained in the resulting laminate is 20 nm or less, it is sufficient for the first region to extend downward from the exposed growth surface by at most 20 nm (e.g., from 2 nm to 20 nm, or from 10 nm to 20 nm) (although of course it can be extended further).

[0043] As described herein, the method may include removing a portion of the first layer (and optionally, the first region) to provide a thin layer of dielectric less than 20 nm. In some preferred embodiments, the thickness of the first layer and / or its first region is such that the method does not involve subsequent removal of a portion. For example, a first layer formed of a single material may have a thickness of approximately 5 nm, the entirety of the first layer meeting the requirements of the first region and the entire layer may be used as a layer in a final device without removing a portion thereof in subsequent steps described herein.

[0044] Dielectric materials for use in semiconductor manufacturing processes are well known. The specific materials of the first layer and the second layer (when the second layer includes a dielectric material) are not particularly limited, whereby the layer is provided with a first region having a desired dislocation density and surface roughness. The first layer is formed of a dielectric material suitable for subsequent formation of graphene by CVD. Therefore, it is preferred that the first region of the first layer is formed of aluminum nitride, magnesium fluoride, calcium fluoride, yttria-stabilized zirconium oxide (YSZ), yttria-stabilized hafnium oxide (YSH) and / or rare earth oxides, because the inventors have found that such materials not only provide the desired high crystallinity and uniformity, but also provide special benefits for promoting the growth of high-quality graphene layer structures. Preferably, the first layer is formed by molecular beam epitaxy and / or high-temperature sputtering. Such methods typically employ high temperatures, for example, from about 500°C to about 1000°C.

[0045] In some preferred embodiments, the growth surface has <111> Crystalline Orientation. The inventors have found that such an orientation (particularly for the preferred dielectric materials described above such as YSZ, YSH and rare earth oxides) is particularly suitable for forming high-quality graphene by CVD. <111> The growth surface can be obtained by <111> The inventors have found that <111> Orientation is preferred for graphene epitaxy because it provides, for example, <100> lower energy orientation and is more stable at higher temperatures. They were surprised to find that <111> Improved graphene crystallinity is achieved, which, without wishing to be bound by theory, is believed to be due to the three-fold rotational symmetry that favors better growth of hexagonal two-dimensional crystals of graphene. Scandium oxide is an example of a particularly preferred dielectric material and can be formed with a desired dislocation density and surface roughness without the use of a buffer layer. Furthermore, the inventors surprisingly found that these materials are unexpectedly stable to the high temperatures required for CVD, so that the dislocation density and surface roughness at the interface of the resulting graphene are essentially the same after CVD, thereby enabling high-quality dielectric layers (particularly their electrical properties) to be incorporated into the final device.

[0046] In some preferred embodiments, the first layer includes a buffer layer directly located on the first silicon support. The first layer can be composed of a buffer layer and another layer, whereby the first region is provided with another layer. The buffer layer can help alleviate the difference in lattice parameters and reduce the risk of defects forming in the first region of the layer. The buffer layer is an inorganic cubic material, typically a metal oxide, although CaF2 and MgF2 may also be preferred. Suitable metal oxides include zirconium, yttrium, hafnium, cerium, erbium, yttrium, dysprosium, praseodymium and / or magnesium oxide, strontium titanate (STO) and / or yttria-stabilized zirconium oxide (YSZ). The particularly preferred oxide for forming the buffer oxide layer is erbium oxide, yttrium oxide, zirconium oxide or a combination thereof because of their thermodynamic stability during the subsequent CVD growth of graphene. The buffer layer can be formed by one or more sublayers of such material.

[0047] Without wishing to be bound by theory, the interface of ZrO2 or YSZ with Si is believed to be less chemically stable than the interface of Er2O3, Y2O3 or Sc2O3 with Si due to the greater driving force for the formation of secondary phases (e.g., silicides such as ZrSi or silicates such as ZrSiO4), thereby providing advantages for erbium and / or yttrium oxides as buffer layers, particularly as layers directly on silicon in the case of multilayer buffer layers. Indeed, the invention in which the scandium oxide is directly on the silicon support layer is also a particular advantage, as the inventors have found that the interface between scandium oxide and silicon is the most chemically stable of these oxides. It is also believed that scandium oxide deposited directly on silicon as described herein can form an interface with scandium suboxides, thereby mitigating differences in lattice parameters that allow for high crystal quality, and / or that a 7×7 reconstruction of silicon heated under vacuum (in which the oxide is removed) produces a silicon surface with a different effective unit cell size that can better match the scandium oxide. The advantage of erbium oxide over other oxides is that it has better thermodynamic stability on silicon while being roughly equivalent in terms of lattice matching. One issue with erbium oxide is that, unlike other oxides, it is strongly paramagnetic, which could be a problem for the intended final electronic devices made from the resulting graphene substrate.

[0048] In some preferred embodiments, the buffer layer is composed of a single material. A second consideration is the lattice mismatch between silicon and the first layer. For example, when the first region is made of scandium oxide, YSZ has a small lattice mismatch between silicon and scandium oxide. That is, the lattice constant of silicon is And the lattice constant of scandium oxide is (where half of the lattice constant is approximately ). The lattice constant of zirconium oxide is And YSZ is about This produces a uniform lattice mismatch between silicon and scandium oxide of approximately 5% and approximately 4%, respectively (depending on the degree of yttrium oxide doping). ) are about 2% and about 7%. However, the inventors have found that pure binary zirconium oxide may be unstable with respect to the phase transition between its cubic and tetragonal phases at the temperatures required for CVD growth of graphene. YSZ is also less thermodynamically stable than the other preferred rare earth oxides (Er, Y and Sc), and therefore a YSZ buffer layer may not be suitable for very high graphene deposition temperatures, for example above 1,250°C. It is also believed that by using very thin zirconium oxide (or YSZ) layers (for example less than 10 nm, preferably less than 5 nm, more preferably less than 2 nm), the zirconium oxide layer is advantageously more resistant to phase transitions. Combinations of these oxides may be used, for example, a yttrium oxide layer may be formed on silicon, followed by a zirconium oxide or YSZ layer to form a multilayer buffer layer. The buffer layer may have the disadvantage that multiple layers with different thermal stabilities and expansion coefficients may increase the risk of delamination.

[0049] While the advantages of scandium oxide for graphene growth stem from its chemical stability, low surface energy, and stability to roughening at high temperatures, and in particular its surface crystal orientation, without wishing to be bound by theory, it is also believed that the lattice constant of scandium oxide is a substantially exact multiple of that of graphene (i.e., in ) further contributes to the formation of high-quality graphene.

[0050] The buffer layer (when present) may have a thickness of at least 2 nm, preferably at least 5 nm. A preferred range for the thickness of the buffer layer is 2 nm to 20 nm, more preferably at most 10 nm. In some embodiments, the first region may not form part of the buffer layer.

[0051] The inventors have unexpectedly discovered that growth surfaces formed from the preferred materials described herein, such as scandium oxide, are advantageous for graphene growth by CVD. Without wishing to be bound by theory, the inventors believe that scandium oxide has a particularly low carbon solubility at high temperatures (relative to known growth substrate materials), allowing for the growth of high-quality, uniform graphene during the high temperatures of CVD without the defects that can occur when grown directly on other known growth surfaces. For example, growth surfaces formed from materials such as silicon or III-V semiconductors are known to produce covalent bonding with carbon atoms during growth, leading to graphene defects.

[0052] The method includes the steps of forming a graphene layer structure on the exposed growth surface of the first layer by CVD. CVD generally refers to a series of chemical vapor deposition techniques, each of which involves deposition to produce thin film materials, such as two-dimensional crystalline materials similar to graphene. Volatile precursors (precursors in gaseous phase or suspended in a gas) are decomposed to release the nuclides required to form the desired material, which is carbon in the case of graphene. CVD as described herein is intended to refer to thermal CVD, so that the formation of graphene by the decomposition of a carbon-containing precursor is the result of the thermal decomposition of the carbon-containing precursor. Formation can be considered to be synonymous with synthesis, manufacture, production, deposition and growth.

[0053] Preferably, the method involves forming graphene by thermal CVD, such that heating of a carbon-containing precursor causes decomposition. Preferably, the temperature of the growth surface during CVD is from 700° C. to 1350° C., preferably from 800° C. to 1250° C., and more preferably from 1000° C. to 1250° C. The inventors have found that such temperatures are particularly effective for directly setting up graphene growth by CVD on a first wafer. Preferably, the CVD reaction chamber used in the method disclosed herein is a cold-wall reaction chamber, in which a heater coupled to the wafer is the only heat source for the chamber.

[0054] In a particularly preferred embodiment, the CVD reaction chamber comprises a close-coupled showerhead having a plurality of precursor entry points or an array of precursor entry points. Such CVD apparatus comprising a close-coupled showerhead is known to be used in MOCVD processes. Thus, the method may be said to be alternatively performed using an MOCVD reactor comprising a close-coupled showerhead. In either case, the showerhead is preferably configured to provide a minimum spacing between the surface of the substrate / wafer and the plurality of precursor entry points of less than 100 mm, more preferably less than 25 mm, even more preferably less than 10 mm. As will be understood, by constant spacing is meant that the minimum spacing between the surface of the substrate and each precursor entry point is substantially the same. Minimum spacing refers to the minimum spacing between the precursor entry point and the surface of the substrate. Thus, such an embodiment relates to a "vertical" arrangement, whereby the plane comprising the precursor entry points is substantially parallel to the plane of the substrate surface (i.e., the growth surface of the first wafer).

[0055] Preferably, the precursor entry points into the reaction chamber are cooled. The inlet or showerhead (when used) is preferably actively cooled by an external coolant (e.g., water) to maintain a relatively cool temperature at the precursor entry points so that the temperature of the precursor as it passes through the plurality of precursor entry points and enters the reaction chamber is less than 100° C., preferably less than 50° C. For the avoidance of doubt, adding precursors at temperatures above ambient does not constitute heating the chamber, as this will deplete the temperature in the chamber and is partially responsible for establishing a temperature gradient in the chamber.

[0056] Preferably, a combination of sufficiently small spacing between the growth surface and the plurality of precursor entry points and cooling of the precursor entry points, coupled with heating of the growth surface to reach a decomposition range of the precursors, generates a sufficiently steep thermal gradient extending from the surface to the precursor entry points to enable graphene to be formed on the surface. As disclosed in WO 2017 / 029470, very steep thermal gradients can be used to promote the formation of high quality and uniform graphene directly on such a non-metallic substrate, preferably across the entire surface of the substrate. The substrate / wafer may have a diameter of at least 5 cm (2 inches), at least 15 cm (6 inches) or at least 30 cm (12 inches). Apparatus particularly suitable for the methods described herein includes Close-Coupled Reactor and TurboDisk Reactor.

[0057] Therefore, in a particularly preferred embodiment, in which the method of the present invention involves forming a graphene layer structure on a growth surface by CVD using the method disclosed in WO 2017 / 029470, comprises:

[0058] positioning a first wafer on a heated susceptor in a close-coupled reaction chamber having a plurality of cooling inlets arranged such that, in use, the inlets are distributed across the growth surface and at a constant spacing from the first wafer;

[0059] Cool the inlet to below 100°C;

[0060] introducing a carbon-containing precursor in a gas phase and / or suspended in a gas through an inlet and into a close-coupled reaction chamber; and

[0061] heating the susceptor to achieve a growth surface temperature that is at least 50° C. above the decomposition temperature of the precursor to provide a sufficiently steep thermal gradient between the growth surface and the inlet to enable graphene formation from carbon released from the decomposed precursor;

[0062] Therein, the constant spacing is less than 100 mm, preferably less than 25 mm, even more preferably less than 10 mm.

[0063] In another particularly preferred embodiment, wherein the method involves using the method disclosed in WO 2019 / 138231 (the contents of which are incorporated herein in their entirety), forming a graphene layer structure on the growth surface by CVD comprises:

[0064] positioning a first wafer on a heated susceptor in a reaction chamber having a plurality of inlets arranged such that, in use, the inlets are distributed across the growth surface and at a constant spacing from the first wafer;

[0065] rotating the heated susceptor at a rotation rate of at least 600 rpm, preferably at most 3000 rpm;

[0066] introducing a carbon-containing precursor in a gas phase and / or suspended in a gas through an inlet and into the reaction chamber; and

[0067] heating the susceptor to achieve a growth surface temperature at least 50° C. above the decomposition temperature of the precursor;

[0068] Therein, the constant spacing is at least 12 cm, preferably at most 20 cm.

[0069] The most common carbon-containing precursor in the field of graphene growth is methane (CH4). The inventors have found that it is preferred that the carbon-containing precursor for forming graphene is an organic compound, i.e., a chemical compound or molecule containing a carbon-hydrogen covalent bond, which includes two or more carbon atoms. Such a precursor has a lower decomposition temperature than methane, which advantageously allows graphene to grow at a lower temperature when using the method described herein, which is particularly advantageous for growth on such non-metallic surfaces. Preferably, the precursor is a liquid when measured at 20°C and 1 bar pressure (i.e., under standard conditions according to IUPAC). Therefore, the precursor has a melting point below 20°C, preferably below 10°C, and has a boiling point above 20°C, preferably above 30°C. When compared with gaseous precursors that generally require high-pressure cylinders, liquid precursors are easier to store and handle. Due to their relatively low volatility when compared with gaseous precursors, they present a lower safety risk during large-scale manufacturing. Increasing the molecular weight of the compound to more than about C 10 , especially beyond about C 12 , generally reducing its volatility and suitability for CVD growth of graphene on non-metallic substrates (although graphene can be produced from solid organic compounds). Preferably, the organic compound consists of carbon and hydrogen and optionally oxygen, nitrogen, fluorine, chlorine and / or bromine.

[0070] As discussed above, the methods described herein preferably utilize carbon-containing precursors, which are organic compounds comprising two or more carbon atoms, i.e., C 2+ Organic compounds. Preferably, the carbon-containing precursor is a C3-C5 organic compound consisting of carbon and hydrogen and optionally oxygen, nitrogen, fluorine, chlorine and / or bromine. 12 Organic compounds. As described herein, C n An organic compound is a compound comprising "n" carbon atoms, and optionally, one or more additional heteroatoms of oxygen, nitrogen, fluorine, chlorine and / or bromine. Preferably, the organic compound comprises at most one heteroatom, since such organic compounds (e.g., ethers, amines and alkyl halides) are generally more readily available in high purity.

[0071] The carbon-containing precursor is preferably a C3-C5-C6-carbon precursor consisting of carbon and hydrogen and optionally oxygen, nitrogen, fluorine, chlorine and / or bromine. 10 Organic compounds, even more preferably C6-C9 organic compounds. In a preferred embodiment, the precursor does not include heteroatoms, such that the precursor consists of carbon and hydrogen. In other words, preferably, the carbon-containing precursor is a hydrocarbon, preferably an alkane.

[0072] Also preferably, the organic compound comprises at least two methyl groups (-CH3). Particularly preferred organic compounds for use as carbon-containing precursors and methods for forming graphene therefrom by CVD are described in GB 2604377 (the contents of which are incorporated herein in their entirety). The inventors have found that precursors other than the conventional hydrocarbons methane and acetylene allow the formation of even higher quality graphene when forming graphene directly on non-metallic substrates. Preferably, the precursor is C4-C 10 The organic compound, more preferably, is branched such that the organic compound has at least three methyl groups.

[0073] Without wishing to be bound by theory, the inventors believe that heavier organic compounds (i.e., greater than C 12 , or greater than C 10 Organic compounds that are solid under standard conditions) provide a "less pure" source of CH radicals. As the size and complexity of organic compounds increase, there is also an increase in the number of decomposition pathways and the possibility of a wider range of by-products, which may lead to graphene defects. Organic compounds as described herein provide a sufficiently large balance to deliver the required and desired high fraction of methyl groups under pyrolysis. However, organic compounds are small enough to be easy to purify, particularly when the precursor is a liquid, and have relatively simple pyrolysis chemistry and limited decomposition pathways. In addition, unlike heavier compounds, they do not condense so easily in the reactor pipe, which is a special shortcoming for the industrial production of graphene because the risk of reactor shutdown is greater.

[0074] In some embodiments, the method further comprises forming an additional layer comprising a dielectric material on the graphene layer structure. In other embodiments, no additional layer is formed on the graphene layer structure, which may be advantageous because it may allow the formation of a van der Waals heterostructure by the following steps of transferring the graphene to a suitable layer on a second wafer.

[0075] One advantage of the present invention is that it provides a high-quality dielectric on the initial graphene by avoiding the need to form a layer on the graphene. However, the present invention still allows for the formation of an additional layer on the graphene before the wafer bonding step, because the additional layer then simply forms part of the underlying support after "flipping". As described herein for the first and second layers, the additional layer may include one or more sub-layers.

[0076] The inventors have discovered that additional layers can be formed on the graphene layer structure to dope the graphene. Preferably, the additional layer comprises a dielectric metal oxide, preferably molybdenum oxide. Molybdenum oxide is a particularly preferred material, which the inventors have discovered is suitable for counter-doping CVD-grown graphene (which is typically n-type, while the intrinsic doping of the transferred graphene is typically p-type due to exposure to a catalytic metal substrate and / or a transfer polymer and / or wet processing chemicals).

[0077] The thickness of such a layer is preferably less than 5nm, more preferably less than 3nm, for example from 0.1nm to 5nm. The inventors have found that this thickness can be used to control the doping level of the graphene layer structure to achieve a desired charge carrier concentration, whereby a larger thickness results in more p-doping. The desired nominal thickness can be achieved by using a quartz crystal microbalance (QCM) during formation, which provides an in-situ measurement of the amount of deposited material for technicians when performing the method. Therefore, the thickness of the layer is the average thickness of the layer. Then, those skilled in the art can use conventional techniques (e.g., AFM) to easily determine the thickness. Additional layers can be deposited using conventional means in the art (e.g., PVD techniques such as sputtering or evaporation (e.g., thermal evaporation)).

[0078] Preferably, the charge carrier concentration of the graphene layer structure is less than 5×10 12 cm -2 , preferably less than 2×10 12 cm -2 , more preferably less than 10 12 cm -2 , as a result of the combination of materials and fabrication methods described herein. The charge carrier concentration is the charge carrier concentration measured at ambient conditions (e.g., 25° C.) after fabrication is complete. Devices can be fabricated to incorporate graphene-containing laminates, and therefore, the charge carrier concentration refers to the charge carrier concentration of the final fabricated laminate or device.

[0079] The method further includes the step of wafer bonding the first wafer to the exposed contact surface of the second layer to sandwich the graphene layer structure between the first silicon support and the second layer. Thus, the exposed contact surface provided by the second layer of the second wafer contacts the uppermost layer (e.g., the exposed graphene layer structure or another layer formed thereon) to bond the two wafers.

[0080] The method may further comprise the step of patterning the first wafer and / or the second wafer as described above, in particular the layers provided on the support (i.e. the first layer of the first wafer, the graphene layer structure and / or the optional further layer of dielectric material, and / or the second layer of the second wafer and / or the metal contacts). This may be performed using conventional lithography techniques or the like, and may also be used to provide metal contacts as described below. For example, the first wafer may be patterned prior to the wafer bonding step to pattern the graphene layer structure together with any further layers provided on the surface into the desired device shape (i.e. into an array of separate devices across the wafer), said any further layers preferably retaining the same shape as the graphene, thereby acting as a protective cover. The first layer below may also optionally be patterned at this stage, optionally into the same shape. Alternatively, as described in the exemplary embodiments herein, such patterning may be performed after the wafers are bonded and the silicon support is removed, but, as will be understood, the first layer then becomes "on" the graphene surface and any other layers that may have been deposited will be located below the graphene layer structure in the resulting laminate (when viewed through the second layer of the second wafer and / or the second support at the bottom of the resulting laminate).

[0081] The second layer of the second wafer may also be patterned before wafer bonding. In some preferred embodiments, the pattern is essentially a "negative" of the pattern of the first wafer to ensure conformal contact between the two patterned surfaces of the first wafer and the second wafer. Each wafer may also include patterned alignment marks to facilitate orientation and optical alignment of the two wafer surfaces for subsequent wafer bonding steps. In this way, a complete device structure may be obtained without the need for further patterning after removing the sacrificial first silicon support. As will be understood, additional layers and / or additional metal contacts (e.g., to provide gate contacts) may still be deposited and patterned after wafer bonding and removal of the silicon wafer.

[0082] A second wafer including exposed metal contacts can be used in embodiments that do not include the optional step of forming an additional layer including a dielectric material on the graphene layer structure, such that the uppermost layer of the first wafer is the exposed graphene layer structure that subsequently contacts the metal contacts during the wafer bonding step. However, when the graphene layer structure is the uppermost layer of the first wafer and is the exposed contact surface during wafer bonding, there is a risk of damaging the graphene layer structure.

[0083] Therefore, in some embodiments, it is also particularly preferred to form metal contacts to the graphene layer structure before wafer bonding, for example in combination with a step of forming one or more further layers of dielectric material. The contacts can be deposited during a patterning step (for example, before or after patterning the graphene layer structure into the desired shape of the device).

[0084] The exposed surfaces of the metal contacts on the first wafer and / or the second wafer can preferably be arranged to be coplanar with the exposed surfaces of the surrounding material of the additional dielectric layer (when present) and / or the second layer. In the absence of metal contacts, substantially flat layers are particularly preferred for wafer bonding to ensure good contact and bonding between the layers. Advantageously, complementary metal contacts (i.e., metal to metal) are generally easier to bond together during the wafer bonding step (e.g., requiring lower temperature and / or pressure, which helps to avoid excessive damage to other layers, and in particular the graphene layer structure). In other embodiments, the metal contacts of one of the two wafers can protrude from the exposed topmost surface. In such embodiments, for example, when the graphene layer structure is exposed without having another dielectric material layer formed thereon, the exposed surface is prevented from contacting the surface of the second wafer, thereby avoiding the risk of damage. Typically, the difference in height between the metal contact and the surface of the adjacent layer is less than 10 μm, more preferably less than 5 μm. The difference can also be at least 100 nm, at least 500 nm or at least 1 μm.

[0085] Wafer bonding processes are generally well known. Preferably, the step of wafer bonding is direct bonding (also referred to as melt bonding). Such a process is generally used to bond, for example, two dielectric oxide and / or metal contact layers, whereby the process results in the formation of a chemical bond between the two surfaces because the two surfaces have available bonding sites for hydrogen bonding and / or covalent bonding and are sufficiently clean and smooth. In some embodiments, the second layer is bonded to the exposed surface of the graphene layer structure, thereby generating bonding through van der Waals forces.

[0086] Such a step can be carried out in a conventional wafer bonding device. Typically, the process includes optionally heating the contacted wafers under the application of force. It is particularly preferred that the step is carried out under vacuum to exclude any oxygen and / or moisture from the surfaces of the two wafers as much as possible. The presence of oxygen-containing impurities may contaminate the initial graphene surface and hinder bonding. In a preferred embodiment, the wafer bonding step is carried out directly after the growth of the graphene layer structure, whereby the first wafer is maintained under an inert atmosphere between the steps, or is otherwise maintained under an inert atmosphere when any other layer and / or metal contact is deposited and patterned. Similarly, for example, when manufactured by depositing a second layer on a second silicon support, the second wafer can be maintained under an inert atmosphere before wafer bonding is about to be carried out. Alternatively, the second wafer can be obtained commercially and is subjected to annealing to clean the surface before wafer bonding.

[0087] Preferably, wafer bonding is performed at a temperature of from 100° C. to 850° C., preferably from 150° C. to 450° C., such as from 200° C. to 400° C. When additional layers (such as molybdenum oxide) are present, lower temperatures are generally preferred because this reduces the risk of damaging the graphene and the additional layers facilitate wafer bonding. On the other hand, the initial graphene may require higher temperatures and vacuum to provide effective bonding. A force of at least 100 N, such as at least 500 N, and / or in some embodiments up to 10 kN may be applied during wafer bonding.

[0088] There is no strict upper limit, but when the second wafer is a CMOS wafer, the maximum temperature is preferably 850° C. Typical second layers on the second silicon support (i.e., CMOS) include silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, etc., and as described herein, may also incorporate surface-exposed metal contacts and metal vias embedded therein.

[0089] In some preferred embodiments, the second layer can be provided by the uppermost sublayer, or include the uppermost sublayer, which is formed by a two-dimensional material for forming a van der Waals heterostructure. For example, the exposed contact surface of the second layer can be provided by h-BN, transition metal dichalcogenide (TMDC) or another graphene layer structure, preferably by h-BN, because the material has little effect on the electronic properties of the graphene layer structure. When the exposed contact surface is provided by a graphene layer structure, in particular a graphene monolayer, wafer bonding as described herein can be used to bond another graphene monolayer. Therefore, an embodiment is described herein in which the first wafer and the second wafer are substantially identical and include a graphene monolayer and the resulting laminate includes a graphene bilayer. The process of the present invention allows the graphene monolayer to be easily aligned, and in particular to be aligned at a twist angle of about 1.1° (i.e., to provide a stable sandwiched twisted bilayer graphene); such an angle is known to provide further unique electronic properties in bilayer graphene.

[0090] The method further comprises the step of removing the first silicon support and, optionally, a portion of the first layer to leave a remaining portion of the first layer formed from the first region and having a thickness of less than 20 nm.

[0091] In general, the method includes chemically etching the first silicon support to remove silicon and expose the dielectric layer. Any conventional silicon etchant can be used, for example, hydrogen fluoride, nitric acid, alkali metal hydroxide, ethylenediamine catechol or tetramethylammonium hydroxide, preferably sodium hydroxide or potassium hydroxide. It should be understood that such an etchant can be used for any typical formulation and solvent (for example, water or alcohol, such as methanol, ethanol or isopropanol). Such a process can be referred to as "wet etching". The first layer formed by the dielectric material resists the etching performed by the etchant. The method optionally includes removing a portion of the first layer (which will be understood as a portion away from the first region described herein). Preferably, the portion of the first layer is removed by reactive ion etching.

[0092] Preferably, removing the first silicon support comprises grinding, which can be combined with, and performed before, chemical etching, so that all of the silicon support is removed by chemical etching. Grinding is generally much faster than chemical etching and is more suitable for removing initial portions of a support having a greater initial thickness. For example, the support can be thinned by grinding to remove from 70% to 99% of the silicon support, followed by chemical etching.

[0093] Preferably, the retained portion of the first layer has a thickness of less than 10 nm, preferably less than 5 nm. Preferably, the retained portion has a thickness of at least 2 nm. Preferably, the thickness of the first region of the first layer is equal to or greater than the thickness of the retained portion of the first layer. Thus, the entire retained region can be formed by the first region of the first layer having an advantageously low dislocation density. Thus, the inventors surprisingly found that the method of the present invention allows the formation of a graphene-containing laminate comprising a dielectric layer having a higher crystal quality than that which can be grown by other conventional methods, in particular when combined with the quality of graphene obtained by direct growth by CVD.

[0094] In another aspect, the present invention relates to a graphene-containing laminate comprising, in order:

[0095] (i) a support (preferably silicon);

[0096] (ii) a base dielectric layer;

[0097] (iii) graphene layer structure;

[0098] (iv) an auxiliary dielectric layer having a thickness of less than 20 nm, wherein the auxiliary dielectric layer satisfies the following conditions:

[0099] a) less than 5,000 cm as measured by TEM -2 dislocation density; and

[0100] b) a surface roughness (Ra) of less than 1 nm as measured by AFM;

[0101] Optionally, one or more further dielectric layers are arranged between the base dielectric layer and the graphene layer structure.

[0102] Therefore, the graphene grown directly on the auxiliary dielectric layer by CVD avoids physical transfer processing.The physical transfer of graphene (usually from copper substrate) can introduce many defects, which has a negative impact on the physical and electronic properties of graphene.Therefore, those skilled in the art can easily determine graphene layer structure, and by extension, whether graphene-containing laminate is a graphene-containing laminate comprising the graphene layer structure grown by CVD, this graphene layer structure has been directly grown on a specific material using conventional techniques such as AFM and energy dispersive X-ray (energy dispersive X-ray, EDX) spectroscopy in this area. Graphene layer structure does not have metal (particularly copper) pollution, and does not have organic polymer residues, because these materials are not present in the process of obtaining graphene-containing laminate. In addition, such processing is not suitable for large-scale manufacturing (such as, on the CMOS substrate of a manufacturing plant). Unintentional doping, particularly unintentional doping from catalytic metal substrates and etching solution, also can cause the graphene produced to be consistent not between sample and sample, and this is what electronic devices commercial production requires.

[0103] In another aspect, the present invention provides a graphene-containing laminate comprising, in order:

[0104] (i) a support (preferably silicon);

[0105] (ii) a base dielectric layer;

[0106] (iii) graphene layer structure; and

[0107] (iv) an auxiliary dielectric layer having a thickness of less than 20 nm, and wherein the auxiliary dielectric layer has a thickness of less than 5,000 cm as measured by TEM. -2 dislocation density;

[0108] wherein the auxiliary dielectric layer is formed of aluminum nitride, magnesium fluoride, calcium fluoride, yttria-stabilized zirconium oxide (YSZ), yttria-stabilized hafnium oxide (YSH) and / or rare earth oxide (preferably scandium oxide); and

[0109] Optionally, one or more further dielectric layers are arranged between the base dielectric layer and the graphene layer structure.

[0110] Optional additional layers, such as molybdenum oxide, may be used during fabrication to counter-dope the CVD-grown graphene so that its final charge carrier concentration after wafer bonding and etching of the sacrificial silicon support to expose the auxiliary dielectric layer is less than 5×10 12 cm -2 .

[0111] Laminates are particularly advantageous for the manufacture of electronic devices, as the inventors have found that the methods described herein allow such products to include graphene of the quality obtained by direct CVD growth and a dielectric layer thereon that can be surprisingly thin while still exhibiting an extremely low dislocation density that cannot be achieved by direct growth on CVD-quality graphene. Preferably, the laminate consists of the described layers.

[0112] The manufacturing methods described herein produce unique laminates, particularly where the auxiliary dielectric layer has a thickness of less than 5,000 cm -2 The method can provide laminates with a high dislocation density, and such features obtainable by this method are not observed in other fabrication methods (e.g., those involving forming layers on graphene).

[0113] Dislocation density less than 5,000 cm -2 It will be understood to characterize an area extending at least 2 nm directly from the graphene layer structure of the laminate. Preferably, the area extends at least 10 nm from the graphene layer structure. Similarly, it will be understood that surface roughness refers to the surface in contact with the graphene layer structure.

[0114] In another aspect, the present invention relates to an electronic device comprising a graphene-containing laminate as described herein (ie a laminate according to another aspect of the invention and / or obtainable by the method of the first aspect).

[0115] In another aspect of the present invention, a kind of electronic device including graphene-containing laminate described herein is provided.That is, the graphene-containing laminate of method disclosed herein or gained can be used, conventional techniques are used to pattern and etch each layer as needed and deposit the contact (such as, via metal wire) for being connected to the electronic circuit to form an electronic device. As will be understood, large-area graphene-containing laminate (that is, such as a wafer having a diameter greater than or equal to 5 cm (2 inches)) can be processed to manufacture electronic device arrays on the common support below (the support of the second silicon support described about the manufacturing method). It can then be cut into separate devices so that the electronic device includes a part for a larger graphene-containing laminate. Thin devices can thus be manufactured by grinding and / or etching of silicon supports.

[0116] Typically, the contacts are metal contacts, such as metal contacts formed from chromium, titanium, aluminum, nickel and / or gold. Typically, the contacts are arranged in contact with a surface and / or an edge of the graphene layer structure of the graphene-containing laminate.

[0117] The architecture provided by the laminated structure of a silicon support with a primary dielectric, graphene, and an auxiliary dielectric thereon is particularly well suited for incorporating transistors etc. However, with appropriate further processing, the laminate can also be used to fabricate other devices such as capacitors, electro-optical devices, and diodes (including LEDs and solar cells as well as resonant tunneling diodes).

[0118] Preferably, the electronic device is a top-gate electronic device in which a gate contact is provided on a surface of an auxiliary dielectric layer away from the graphene layer structure. As will be understood in a vertical device configuration, the gate contact is provided above the graphene to modulate the electronic properties of the graphene (through the dielectric layer). The retained area of ​​the first layer described in the above method is provided with an auxiliary dielectric layer of the laminate according to this other aspect. Therefore, top-gate electronic devices (e.g., transistors) employ this high-quality dielectric material as a gate dielectric, which allows for improved device performance without the need for additional interface layers between the graphene and the gate.

[0119] In some embodiments, after forming an electronic device from the laminates described herein, the thickness of the silicon support can be reduced or the silicon support can be removed entirely, such that the present invention also provides an electronic device comprising a graphene-containing laminate comprising, in turn:

[0120] (i) an optional silicon support;

[0121] (ii) a base dielectric layer;

[0122] (iii) graphene layer structure; and

[0123] (iv) an auxiliary dielectric layer having a thickness of less than 20 nm, wherein the auxiliary dielectric layer satisfies the following conditions:

[0124] a) less than 5,000 cm as measured by TEM -2 dislocation density; and

[0125] b) a surface roughness (Ra) of less than 1 nm as measured by AFM;

[0126] Optionally, one or more further dielectric layers are arranged between the base dielectric layer and the graphene layer structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0127] The invention will now be further described with reference to the following exemplary and non-limiting drawings, in which:

[0128] Figure 1 An embodiment of the method according to the invention is shown.

[0129] Figure 2is a cross section of an embodiment of a first wafer before the wafer bonding step.

[0130] Figure 3 is a cross-section of an embodiment of a top-gate transistor including a graphene-containing laminate according to the present invention.

[0131] Figure 4 is a cross-section of an embodiment of a top gate barrier including a graphene-containing laminate according to the present invention.

[0132] Figure 5 is a cross-section of an embodiment of an electro-optic modulator according to the present invention comprising a graphene-containing laminate.

[0133] Figure 1 An exemplary method for making a graphene-containing laminate is shown, with each step illustrated in cross-section.

[0134] In a first step 100 , a commercially available silicon support 200 (ie substrate / wafer) having a diameter of at least 5 cm is provided and a first layer 205 , eg consisting essentially of scandium oxide, is formed on the surface of the silicon support 200 by molecular beam epitaxy.

[0135] In step 100, a first layer 205 is grown to a thickness between 5 nm and 50 nm, thereby creating an exposed surface 205′ distal from the silicon support 200 (i.e., opposite the surface of the first layer 205 that interfaces with the silicon support 200). The first layer 205 includes a first region that extends at least 2 nm downward from the exposed growth surface 205′ and may extend the entire thickness of the first layer 205. The first layer 205 is characterized by a thickness of less than 5,000 cm as measured by TEM. -2 The first layer 205 and the silicon support 200 may be collectively referred to as a first wafer 220 .

[0136] In a second step 105, a graphene monolayer 210 is grown on the exposed growth surface 205' in an MOCVD reactor, and in a third step 110, an additional layer 215 is formed on the exposed surface of the graphene monolayer 210. The additional layer can be selected to dope the graphene monolayer 210 to offset the intrinsic doping produced by the CVD growth. Preferably, the additional layer 215 is formed of molybdenum oxide having a thickness of up to about 5 nm. The silicon support 200, the first layer 205, the graphene monolayer 210, and the additional layer 215 can also be collectively referred to as a first wafer 220 for the wafer bonding step.

[0137] The method further includes providing a second wafer 235 for wafer bonding. In the present embodiment, the second wafer 235 is a conventional silicon-on-insulator wafer comprising a (second) silicon support 225 having a silicon oxide layer 230 thereon, the silicon oxide layer 230 having an exposed contact surface 230. The silicon oxide layer 230 typically has a thickness of tens to hundreds of nanometers.

[0138] In a fourth step 115, the first wafer 220 and the second wafer 235 are directly wafer-bonded by contacting the surface of the further layer 215 with the exposed contact surface 230' of the silicon oxide layer 230. Thus, the graphene monolayer 210 is sandwiched between the (first) silicon support 200 and the silicon oxide 230 (and the (second) silicon support 225). Such a step is performed in a vacuum, applying a small force and at a temperature of up to about 400°C.

[0139] In a fifth step 120, the (first) silicon support 200 is removed by first wafer grinding to remove most of the silicon support 200, and then chemically etching with an aqueous solution of an alkali metal hydroxide to expose the surface of the first layer 205 (i.e., the surface that interfaces with the silicon support 200), thereby forming a graphene-containing laminate 240. The first layer 205 can be etched by reactive ion etching to reduce its thickness to, for example, 10 nm or less. The quality of the first layer 205 of the laminate 240 is advantageously much greater than that which can be formed on directly grown CVD graphene, so that a thinner layer can be used as a dielectric layer between the graphene and the contact / electrode in an electronic device. Figures 3 to 5 An example of such a device is shown. In some embodiments, the thickness of the (second) silicon support 225 can be reduced, or the (second) silicon support 225 can be removed entirely, for example after formation of the electronic device (i.e., after formation of any further layers, contacts and patterning).

[0140] Figure 2 are methods that can be used in the present invention (e.g., Figure 1 1. The cross section of an exemplary first wafer 220 in the method shown in FIG. The first wafer 220 includes a silicon support 200 and a first layer 205 formed thereon by a first sub-layer 205a and a second sub-layer 205b.

[0141] The first sublayer 205a of the first layer 205 may be a buffer oxide layer that may be used to reduce defects in a dielectric layer formed thereon by minimizing lattice constant mismatch with the silicon support 200. In an example, the first sublayer is formed of yttrium oxide, which may have a thickness of 5 nm or less.

[0142] For example, the second sublayer 205b can be formed of yttria-stabilized zirconia (YSZ), yttria-stabilized hafnium oxide (YSH), or a rare earth oxide. The second sublayer can have a thickness of about 5 nm or greater and provide a first region 205c of the first layer 205, wherein the first region 205c is characterized by a thickness of less than 5,000 cm as measured by TEM. -2 The first wafer 220 further includes a graphene monolayer 210 on the first region 205 c and an additional layer 215 on the graphene monolayer 210 .

[0143] Figure 3 is a cross-section of an exemplary top-gate transistor 300 including a graphene-containing laminate according to the present invention. Transistor 300 is formed from a silicon support 325 and a silicon oxide layer 330 (which can originate from, for example, second wafer 235). A (primary) dielectric material layer 315, such as molybdenum oxide, is located on the silicon oxide layer. This dielectric material layer 315, along with a (secondary) dielectric material layer 305, sandwiches (i.e., directly) a graphene monolayer 310. The secondary dielectric layer 305 is patterned together with the graphene monolayer 310 to share a continuous edge (i.e., have the same shape).

[0144] Transistor 300 also includes first and second electrical contacts 345a, 345b, which are deposited to contact opposite edges of graphene monolayer 310. For example, for a transistor, graphene monolayer 310 can have a rectangular shape, with such contacts 345a, 345b positioned to contact relatively shorter edges. These contacts can serve as source and drain contacts.

[0145] The transistor 300 further comprises a third electrical contact 345c as a gate contact on the auxiliary dielectric layer 305. The quality of the auxiliary dielectric layer, in particular less than 5,000 cm as measured by TEM, is -2 The low dislocation density allows for extremely thin thicknesses, eg, 5 nm or less, which in turn allows for improved current modulation between the source and drain through the gate contact (ie, improved device performance).

[0146] Figure 4 is a cross-section of an exemplary top-gate barrier 400 including a graphene-containing laminate according to the present invention. Barrier 400 shares many similarities with transistor 300 and can be formed from substantially the same materials.

[0147] One difference is that the silicon support 425 includes an embedded region of a primary dielectric material 430 (e.g., silicon dioxide). The graphene monolayer 410 is patterned together with the auxiliary dielectric material 405 to reside on and across the surface of the primary dielectric 430 and the silicon support 425. A first electrical contact 445a (e.g., a source contact) is positioned so that it contacts the edge of the graphene monolayer on the region of the underlying substrate that includes the dielectric material 430. A second electrical contact 445b (e.g., a drain contact) is positioned on the silicon support, separated from the graphene monolayer. The second contacts 445b can be separated by a distance of at least 2 nm, preferably at least 5 nm, and the region therebetween is filled with a dielectric coating 450. The dielectric coating 450 can be, for example, an ALD layer of aluminum oxide.

[0148] The third electrical contact 445c is disposed on an auxiliary dielectric layer that is located above and spans the entire area of ​​the underlying graphene monolayer 410 on the semiconductor silicon support 425. Thus, the interface between the graphene monolayer 210 and the silicon support 425 provides a barrier to current flow, which can be modulated by the overlying third electrical contact 445c. This arrangement can be used to improve the current on / off ratio.

[0149] Figure 5 is a cross-section of an exemplary electro-optic modulator 500 including a graphene-containing laminate according to the present invention. The modulator 500 includes a base dielectric layer 530 formed of a silicon dioxide layer 530a, in which a channel of waveguide material 530b, such as silicon nitride, is embedded. The silicon dioxide layer 530a is also disposed on an underlying silicon support (not shown).

[0150] The graphene monolayer 510 is patterned along with an auxiliary dielectric material 505 to reside over and across the width of the waveguide 530b and the adjacent region of the silicon dioxide layer 530a. The modulator 500 also includes a second electrode 555, which can be formed, for example, of indium tin oxide (ITO), extending over and across the width of the underlying waveguide 530b. First and second electrical contacts 545a, 545b are provided to contact the graphene monolayer 510 and the second electrode 555, respectively. The graphene monolayer 510 and the second electrode 555 serve as electrodes that can be used to modulate the transmittance of light transmitted through the waveguide 530b (i.e., in a direction orthogonal to the illustrated cross-section). The electrodes can be coated with a dielectric coating 550, such as an ALD layer of aluminum oxide.

[0151] As used herein, the singular forms "a," "an," and "the" include plural referents unless the context clearly indicates otherwise. The use of the term "comprising" is intended to be interpreted as including such features but not excluding others, and is also intended to include the option of features that are necessarily limited to those described. In other words, unless the context clearly indicates otherwise, the term also includes the limitations of "consisting essentially of" (intended to mean that certain other components may be present as long as they do not materially affect the basic properties of the described features) and "consisting of" (intended to mean that no other features may be included, such that if the components were expressed in percentages in their proportions, these components would add up to 100%, taking into account any unavoidable impurities).

[0152] It should be understood that although the terms "first", "second", etc. may be used herein to describe different elements, layers and / or parts, these elements, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, layer or part from another or additional element, layer or part. It should be understood that the term "on..." is intended to mean "directly on...", so that when one material is said to be "on" another material, there is no intermediate layer between the two. For ease of description, spatially relative terms such as "under...", "below...", "below...", "above...", "above...", "above...", etc. may be used herein to describe the relationship between an element or feature and another element or feature. It should be understood that the spatially relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the drawings. For example, if the device described herein is flipped, the element described as "under" or "below" other elements or features will be oriented "above" or "above" other elements or features. Therefore, the example term "under..." can cover both above and below orientations. The device may be otherwise oriented and the spatially relative descriptors used herein interpreted accordingly.

[0153] The foregoing detailed description has been provided by way of illustration and example and is not intended to limit the scope of the appended claims. Many variations in the presently preferred embodiments shown herein will be apparent to those skilled in the art and still fall within the scope of the appended claims and their equivalents.

Claims

1. A method for producing a graphene-containing laminate, the method comprising: (i) providing a first wafer, the first wafer comprising a first layer on a first silicon support, wherein the first layer is a dielectric layer and has an exposed growth surface remote from the first silicon support, wherein the first layer has a first region extending downward by at least 2 nm from the exposed growth surface, the first region satisfying the following conditions: a) less than 5,000 cm as measured by TEM -2 dislocation density; and b) a surface roughness (Ra) of less than 1 nm as measured by AFM; (ii) providing a second wafer, the second wafer comprising a second layer, wherein the second layer has an exposed contact surface; (iii) forming a graphene layer structure on the exposed growth surface of the first layer by CVD, and optionally forming a further layer comprising a dielectric material on the graphene layer structure; (iv) wafer bonding the first silicon wafer to the exposed contact surface of the second layer to sandwich the graphene layer structure between the first silicon support and the second layer; and (v) removing the first silicon support and optionally portions of the first layer to leave a remaining portion of the first layer formed from the first region and having a thickness of less than 20 nm.

2. The method according to claim 1, wherein The wafer bonding is performed at a temperature from 100°C to 850°C, preferably from 150°C to 450°C.

3. The method according to claim 1 or claim 2, wherein: The second wafer including the second layer further includes a second silicon support, wherein the exposed contact surface of the second layer is distal from the second silicon support.

4. A method according to any preceding claim, wherein: The second layer is a second dielectric layer, preferably hexagonal boron nitride, silicon oxide and / or silicon nitride.

5. A method according to any preceding claim, wherein: The further layer comprises one or more sub-layers.

6. A method according to any preceding claim, wherein: The further layer comprises a dielectric metal oxide, preferably molybdenum oxide.

7. The method according to claim 6, wherein: The further layer consists of a molybdenum oxide layer having a thickness of less than 5 nm, preferably less than 3 nm.

8. A method according to any preceding claim, wherein: The first layer has a thickness of from 2 nm to 500 nm, preferably from 5 nm to 100 nm.

9. A method according to any preceding claim, wherein: The first region of the first layer extends down from the exposed growth surface by at least 5 nm, preferably at least 10 nm, preferably at least 20 nm.

10. A method according to any preceding claim, wherein: The remaining portion of the first layer has a thickness of less than 10 nm.

11. A method according to any preceding claim, wherein: The first region of the first layer has a thickness equal to or greater than a thickness of the remaining portion of the first layer.

12. A method according to any preceding claim, wherein: The graphene layer structure is a graphene single layer.

13. A method according to any preceding claim, wherein: The growth surface has <111> Crystal orientation.

14. A method according to any preceding claim, wherein: The first region of the first layer is formed of aluminum nitride, magnesium fluoride, calcium fluoride, yttria-stabilized zirconium oxide (YSZ), yttria-stabilized hafnium oxide (YSH) and / or rare earth oxide, preferably wherein the rare earth oxide is scandium oxide.

15. A method according to any preceding claim, wherein: The first layer comprises a buffer layer directly on the first silicon support, preferably wherein the buffer layer is formed of erbium oxide, yttrium oxide, zirconium oxide or a combination thereof.

16. A method according to any preceding claim, wherein: The first layer is formed by molecular beam epitaxy and / or high temperature sputtering.

17. A method according to any preceding claim, wherein: The step of removing the first silicon support comprises grinding and / or chemical etching.

18. The method according to claim 17, wherein The step of removing the first silicon support is done by chemical etching, and parts of the first layer are removed by reactive ion etching.

19. A method according to any preceding claim, wherein: The temperature of the growth surface during CVD is from 700°C to 1350°C, preferably from 800°C to 1250°C, more preferably from 1000°C to 1250°C.

20. A method according to any preceding claim, wherein: Forming the graphene layer structure on the growth surface by CVD includes: positioning the first wafer on a heated pedestal in a close-coupled reaction chamber having a plurality of cooling inlets arranged such that, in use, the inlets are distributed across the growth surface and at a constant spacing from the first wafer; Cooling the inlet to below 100° C. introducing a carbon-containing precursor in a gaseous phase and / or suspended in a gas through the inlet and into the close-coupled reaction chamber; and heating the susceptor to achieve a growth surface temperature that exceeds the decomposition temperature of the precursor by at least 50° C. to provide a sufficiently steep thermal gradient between the growth surface and the inlet to enable formation of graphene from carbon released from the decomposed precursor; The constant interval is less than 100 mm, preferably less than 25 mm, and even more preferably less than 10 mm.

21. A method according to any preceding claim, wherein: Forming the graphene layer structure on the growth surface by CVD includes: positioning the first wafer on a heated susceptor in a reaction chamber having a plurality of inlets arranged such that, in use, the inlets are distributed across the growth surface and at a constant spacing from the first wafer; rotating the heating base at a rotation rate of at least 600 rpm, preferably at most 3000 rpm; introducing a carbon-containing precursor in a gaseous phase and / or suspended in a gas through the inlet and into the reaction chamber; and heating the susceptor to achieve a growth surface temperature at least 50° C. above the decomposition temperature of the precursor; The constant interval is at least 12 cm, preferably at most 20 cm.

22. A graphene-containing laminate obtainable by the method of any preceding claim.

23. A graphene-containing laminate, comprising: (i) supports; (ii) a base dielectric layer; (iii) graphene layer structure; as well as (iv) an auxiliary dielectric layer, the auxiliary dielectric layer having a thickness of less than 20 nm, and wherein the auxiliary dielectric layer satisfies the following conditions: a) less than 5,000 cm as measured by TEM -2 dislocation density; and b) a surface roughness (Ra) of less than 1 nm as measured by AFM; Optionally, one or more additional dielectric layers are provided between the basic dielectric layer and the graphene layer structure.

24. An electronic device comprising the graphene-containing laminate according to claim 22 or claim 23.

25. The electronic device according to claim 24, wherein The electronic device is a top-gate electronic device, wherein a gate contact is provided on a surface of the auxiliary dielectric layer remote from the graphene layer structure.

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