FPGA-based optical fiber three-component detector data acquisition system and method

Abstract

The invention relates to an optical fiber three-component detector data acquisition system and method based on an FPGA, and the system is composed of a plurality of MON modules, a plurality of acquisition board cards, a control convergence board card, and an upper computer, and the MON modules and the acquisition board cards are equal in number and are connected in a one-to-one correspondence manner. The control convergence board card is connected with the acquisition board cards in a one-to-one correspondence manner through J30J rectangular connectors of which the number is equal to that of the acquisition board cards, and the control convergence board card is connected with the upper computer through a network port, a serial port and an I2C (Inter-Integrated Circuit) interface. According to the invention, stable and reliable connection between the acquisition control board card and the 16 acquisition board cards is realized through the J30J interface, accurate and synchronous acquisition of 16 paths of data is realized by using powerful functions of the FPGA chip, and the acquired data is efficiently converged and quickly transmitted to an upper computer system through the internet access, so that the data acquisition efficiency is improved. And meanwhile, different application scenes and expansion requirements are met by means of abundant interfaces.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of data acquisition, and particularly relates to a fiber-optic three-component detector data acquisition system and method based on FPGA. BACKGROUND

[0002] In the field of geophysical exploration such as seismic exploration, a fiber-optic three-component detector can obtain information of seismic waves in three mutually perpendicular directions, which is of great significance for accurately analyzing underground geological structure and exploring oil and gas resources. However, the existing fiber-optic three-component detector data acquisition system has many problems and cannot meet the growing demand for high-precision exploration.

[0003] On the one hand, the traditional interface connection mode may have problems such as unstable signal transmission and poor anti-interference ability, resulting in data loss or errors. On the other hand, the data synchronization accuracy between different acquisition board cards is difficult to guarantee, which affects the accuracy and reliability of the data. Meanwhile, the transmission rate and stability need to be improved during the data transmission to the host computer. Although there are some FPGA-based data acquisition schemes, there is still much room for improvement in terms of the rationality of the system architecture, the optimized use of the interface, and the efficiency of communication with the host computer. SUMMARY

[0004] The technical problem to be solved by the application is to provide a fiber-optic three-component detector data acquisition system and method based on FPGA, which realizes stable and reliable connection between the acquisition control board card and 16 acquisition board cards through the J30J interface, uses the powerful function of the FPGA chip to realize accurate synchronous acquisition of 16 channels of data, efficiently aggregates the acquired data, quickly transmits the data to the host computer system through the network port, and meets different application scenarios and expansion requirements with the help of rich interfaces (serial port, I2C interface, etc.).

[0005] The technical solution of the application is to provide a fiber-optic three-component detector data acquisition system based on FPGA, which comprises a plurality of MON modules, a plurality of acquisition board cards, one control aggregation board card, and a host computer. The MON modules are connected one by one in a one-to-one correspondence with the acquisition board cards. The control aggregation board card is connected one by one in a one-to-one correspondence with each acquisition board card through a J30J rectangular connector equal in number to the acquisition board cards. The control aggregation board card is connected to the host computer through a network port, a serial port, and an I2C interface. Wherein,

[0006] The MON module uses an internal photoelectric conversion device to convert the optical signal transmitted by the optical fiber into an electrical signal that can be processed by the subsequent circuit.

[0007] The acquisition board consists of a power supply circuit, an analog input interface, a conditioning circuit, an ADC acquisition chip, and a J30J interface circuit. The power supply circuit provides a stable operating voltage for each functional module of the acquisition board. The analog input interface receives the analog electrical signal after the photoelectric conversion of the MON module. The conditioning circuit is used to perform pre-processing such as amplification and filtering on the input analog electrical signal to meet the requirements of subsequent analog-to-digital conversion. The ADC acquisition chip performs analog-to-digital conversion on the signal processed by the conditioning circuit and converts it into a digital signal. The J30J interface circuit allows the acquisition board to communicate data with the control and convergence board through the J30J interface.

[0008] The control convergence board, whose core main control chip is a high-performance FPGA chip, includes a clock configuration module, an acquisition control module, a data cache module, a data transmission module and an interface communication module; the clock configuration module is used to generate the working clock required by each module; the acquisition control module, the FPGA is responsible for generating accurate clock signals and synchronization control signals, and sending them to each acquisition board through the J30J interface to ensure that they start and end data acquisition at the same time, thereby realizing the synchronization of multiple data channels; the data cache module uses the FIFO module to cache the data collected by multiple acquisition boards; the data transmission module aggregates the data collected by multiple acquisition boards, integrates them according to specific data formats and protocols, and transmits them to the host computer system through the network port; the interface communication module forwards instructions and parameters by implementing the serial port and I2C interface communication protocol between the host computer system and the control convergence board;

[0009] The host computer is responsible for receiving the data sent by the acquisition control board, and storing, analyzing and displaying it; and can parse the Ethernet data packets transmitted through the network port and extract the original data.

[0010] Preferably, the MON module has a signal preprocessing function, including preliminary amplification and filtering of the converted electrical signal.

[0011] Preferably, the host computer runs special data receiving and processing software, which has a data storage function and can store the collected data in a database or local file to facilitate subsequent query and analysis; and provides a user interface through which the user can set the collection parameters and send these settings to the control aggregation board through the serial port and I2C interface to achieve flexible control of the data collection process.

[0012] Preferably, the MON module uses the I-MON 256OEM model product of Ibesen Company; the AD acquisition chip of the acquisition board uses the ADC chip model AD7626; the FPGA chip of the control convergence board uses the XC7K325T series chip of Xilinx Company.

[0013] Preferably, the number of the MON modules and the number of the acquisition boards are both 16.

[0014] The present invention also provides a method for an optical fiber three-component detector data acquisition system based on FPGA, comprising the following steps:

[0015] S1. System power-on initialization: Start 16 MON modules, 16 acquisition boards, a control aggregation board, and a host computer to complete the initial configuration of power, clock, and command information. The MON modules implement photoelectric signal conversion, the acquisition boards implement analog-to-digital signal conversion, the control aggregation board implements data acquisition, caching, aggregation, and output, and the host computer displays, stores, or processes the data output by the electrical system.

[0016] S2. Host computer parameter setting: The host computer sends instructions to the control convergence board through the serial port or I2C interface to configure the parameter information of each acquisition board;

[0017] S3, Data Acquisition and Cache: Each acquisition board implements synchronous acquisition of 16 acquisition boards based on the acquisition clock, control signal, and start signal of the control convergence board, and transmits the data to the control convergence board via the data line of the J30J interface; the control convergence board caches the data uploaded by each acquisition board in the FIFO for subsequent data processing.

[0018] S4, data aggregation and output: The FPGA on the control aggregation board packages and aggregates the 16 channels of collected data according to a specific format and protocol. The Ethernet module transmits the aggregated data to the host computer through the network bus for display, storage or processing;

[0019] S5. Host computer storage and analysis: The host computer receives and processes data, parses Ethernet data packets transmitted through the network port, extracts the original data, and stores, analyzes, and displays it.

[0020] Preferably, in step S2, the parameter information includes channel enable, sampling range and sampling rate.

[0021] Compared with the prior art, the present invention has the following advantages:

[0022] Highly Synchronous Acquisition: Leveraging the precise timing control capabilities of the FPGA chip and the stable transmission characteristics of the J30J interface, high-precision synchronous acquisition of data from 16 acquisition boards is achieved. This ensures the temporal consistency of each channel's data, providing a reliable foundation for subsequent multi-channel data fusion analysis. This is particularly suitable for applications requiring extremely high synchronization.

[0023] Reliable and high-speed transmission: The J30J interface is used to connect the acquisition control board and 16 acquisition boards, making full use of the high reliability and anti-interference ability of the J30J interface, ensuring the stability and accuracy of multi-channel data transmission, and reducing data transmission errors and losses.

[0024] Flexible Configuration and Control: The user interface provided by the host system software enables users to easily configure and control the data acquisition process. Furthermore, the programmable nature of the FPGA chip allows users to reconfigure its internal logic functions according to different application scenarios, enabling the system to quickly adapt to diverse data acquisition needs and improving its flexibility and adaptability. Description of the drawings:

[0025] Figure 1 It is the overall block diagram of the acquisition system of the present invention;

[0026] Figure 2 This is a logic module diagram of the acquisition board of the present invention;

[0027] Figure 3 This is a logic module diagram of the control convergence board FPGA of the present invention;

[0028] Figure 4 It is the workflow diagram of the acquisition system of the present invention. Specific implementation method:

[0029] The present invention will be further described below with reference to the accompanying drawings:

[0030] As attached Figure 1 As shown in the figure, an FPGA-based optical fiber three-component detector data acquisition system is composed of 16 MON modules, 16 acquisition boards, 1 control aggregation board, and a host computer system. The 16 MON modules are connected to the 16 acquisition boards in a one-to-one correspondence. The control aggregation board is connected to the 16 acquisition boards through 16 J30J rectangular connectors. The control aggregation board is connected to the host computer system through the network port, serial port, and I2C interface.

[0031] As shown in Table 1, the 15-pin J30J interface pins between the control convergence board and each acquisition board are defined;

[0032] Table 1 Pin definition of the 15-pin J30J interface between the control convergence board and each acquisition board

[0033]

[0034]

[0035] As attached Figure 2 As shown in FIG, the acquisition board system block diagram of the present invention is composed of a power supply circuit, an analog input interface, a conditioning circuit, an ADC acquisition chip and a J30J interface circuit; wherein,

[0036] The power supply circuit provides stable operating voltage for each functional module of the acquisition board;

[0037] Analog input interface, which is used to connect the analog electrical signal after photoelectric conversion by the MON module;

[0038] MON module, I-MON 256OEM model product of Ibesen company is selected;

[0039] Conditioning circuit, used to amplify, filter and other pre-process the input analog electrical signal to meet the requirements of subsequent analog-to-digital conversion;

[0040] ADC acquisition chip, select ADC7626 model acquisition chip, perform analog-to-digital conversion on the signal processed by the conditioning circuit and convert it into a digital signal;

[0041] The J30J interface circuit allows the acquisition board to communicate with the control and aggregation board via the J30J interface. It receives the synchronous clock and control signals from the control and aggregation board, acquires data according to the instructions, and uploads the collected digital signals to the aggregation control board via the 8-pin data cable of the J30J interface.

[0042] As attached Figure 3 As shown in the figure, it is a logic module diagram of the control convergence board FPGA of the present invention, which consists of a clock configuration module, an acquisition control module, a data cache module, a data transmission module and an interface communication module;

[0043] In this embodiment, the FPGA chip of the control convergence board is selected from the XC7K325T series chip of Xilinx, which is used as the main control chip of the system and is responsible for the system's collection, logic control and convergence transmission work;

[0044] Clock configuration module, used to generate the working clock required by each module;

[0045] In the acquisition control module, the FPGA is responsible for generating precise clock signals and synchronization control signals, which are sent to the 16 acquisition boards through the J30J interface to ensure that they start and end data acquisition at the same time, thus achieving strict synchronization of the 16 channels of data.

[0046] The data cache module uses the FIFO module to cache the data collected by the 16-channel acquisition board;

[0047] The data transmission module aggregates and processes the data collected by the 16 acquisition boards, integrates them according to specific data formats and protocols, and transmits them to the host computer system through the network port;

[0048] The interface communication module forwards commands and parameters by implementing the serial port and I2C interface communication protocol between the host computer system and the control aggregation board.

[0049] like Figure 4 As shown in FIG, a working method of a multi-channel data acquisition system based on a J30J interface proposed by the present invention comprises the following steps:

[0050] S1. System power-on initialization: Start 16 MON modules, 16 acquisition boards, the control aggregation board, and the host computer system, and complete the initial configuration of power, clock, and command information. The MON modules implement photoelectric signal conversion, the acquisition boards implement analog-to-digital signal conversion, the control aggregation board implements data acquisition, caching, aggregation, and output, and the host computer system displays, stores, or processes the data output by the electrical system.

[0051] S2. Host computer parameter setting: The host computer sends instructions to the control convergence board through the serial port or I2C interface to configure the channel enable, sampling range, sampling rate and other parameter information of each acquisition board;

[0052] S3, Data Acquisition and Cache: Each acquisition board implements synchronous acquisition of 16 acquisition boards based on the acquisition clock, control signal, and start signal of the control convergence board, and transmits the data to the control convergence board via the data line of the J30J interface; the control convergence board caches the data uploaded by each acquisition board in the FIFO for subsequent data processing.

[0053] S4, data aggregation and output: The FPGA on the control aggregation board packages and aggregates the 16-channel collected data according to a specific format and protocol. The Ethernet module transmits the aggregated data to the host computer system through the network bus for display, storage or processing;

[0054] S5. Host computer storage and analysis: The host computer runs special data receiving and processing software, which can parse the Ethernet data packets transmitted through the network port, extract the original data, and store, analyze and display it.

[0055] The above description is only for the preferred embodiment of the present invention, which should not be understood as limiting the claims. Any equivalent process changes made using the present invention description are included in the patent protection scope of the present invention.

Claims

1. An FPGA-based fiber optic three-component detector data acquisition system, characterized by: It is composed of multiple MON modules, multiple acquisition boards, a control convergence board and a host computer. The number of the MON modules is equal to that of the acquisition boards and they are connected one-to-one. The control convergence board is connected to each acquisition board one-to-one through a J30J rectangular connector equal to the number of the acquisition boards. The control convergence board is connected to the host computer through a network port, a serial port and an I2C interface. The MON module uses an internal photoelectric conversion device to convert the optical signal transmitted by the optical fiber into an electrical signal that can be processed by the subsequent circuit; The acquisition board consists of a power supply circuit, an analog input interface, a conditioning circuit, an ADC acquisition chip, and a J30J interface circuit. The power supply circuit provides a stable operating voltage for each functional module of the acquisition board. The analog input interface receives the analog electrical signal after the photoelectric conversion of the MON module. The conditioning circuit is used to amplify and filter the input analog electrical signal to meet the requirements of subsequent analog-to-digital conversion. The ADC acquisition chip performs analog-to-digital conversion on the signal processed by the conditioning circuit and converts it into a digital signal. The J30J interface circuit allows the acquisition board to communicate data with the control and aggregation board through the J30J interface. The control convergence board, whose core main control chip is a high-performance FPGA chip, includes a clock configuration module, an acquisition control module, a data cache module, a data transmission module and an interface communication module; the clock configuration module is used to generate the working clock required by each module; the acquisition control module, the FPGA is responsible for generating accurate clock signals and synchronization control signals, and sending them to each acquisition board through the J30J interface to ensure that they start and end data acquisition at the same time, thereby realizing the synchronization of multiple data channels; the data cache module uses the FIFO module to cache the data collected by multiple acquisition boards; the data transmission module aggregates the data collected by multiple acquisition boards, integrates them according to specific data formats and protocols, and transmits them to the host computer system through the network port; the interface communication module forwards instructions and parameters by implementing the serial port and I2C interface communication protocol between the host computer system and the control convergence board; The host computer is responsible for receiving the data sent by the acquisition control board, and storing, analyzing and displaying it; and can parse the Ethernet data packets transmitted through the network port and extract the original data.

2. The FPGA-based optical fiber three-component detector data acquisition system according to claim 1, characterized in that: The MON module has a signal pre-processing function, including preliminary amplification and filtering of the converted electrical signal.

3. The FPGA-based fiber optic three-component detector data acquisition system according to claim 1, characterized in that: The host computer runs special data receiving and processing software, which has a data storage function and can store the collected data in a database or local file to facilitate subsequent query and analysis; and provides a user interface through which the user can set the collection parameters and send these settings to the control aggregation board through the serial port and I2C interface to achieve flexible control of the data collection process.

4. The FPGA-based fiber optic three-component detector data acquisition system according to claim 1, characterized in that: The MON module uses the I-MON 256OEM model product of Ibesen Company; the AD acquisition chip of the acquisition board uses the ADC chip model AD7626, and the FPGA chip of the control convergence board uses the XC7K325T series chip of Xilinx Company.

5. The FPGA-based optical fiber three-component detector data acquisition system according to claim 1, characterized in that: The number of the MON modules and the number of the acquisition boards are both 16.

6. A method for a fiber optic three-component detector data acquisition system based on FPGA according to any one of claims 1 to 5, characterized in that: The following steps are included: S1. System power-on initialization: Start 16 MON modules, 16 acquisition boards, a control aggregation board, and a host computer to complete the initial configuration of power, clock, and command information. The MON modules implement photoelectric signal conversion, the acquisition boards implement analog-to-digital signal conversion, the control aggregation board implements data acquisition, caching, aggregation, and output, and the host computer displays, stores, or processes the data output by the electrical system. S2. Host computer parameter setting: The host computer sends instructions to the control convergence board through the serial port or I2C interface to configure the parameter information of each acquisition board; S3, Data Acquisition and Cache: Each acquisition board implements synchronous acquisition of 16 acquisition boards based on the acquisition clock, control signal, and start signal of the control convergence board, and transmits the data to the control convergence board via the data line of the J30J interface; the control convergence board caches the data uploaded by each acquisition board in the FIFO for subsequent data processing. S4, data aggregation and output: The FPGA on the control aggregation board packages and aggregates the 16 channels of collected data according to a specific format and protocol. The Ethernet module transmits the aggregated data to the host computer through the network bus for display, storage or processing; S5. Host computer storage and analysis: The host computer receives and processes data, parses Ethernet data packets transmitted through the network port, extracts the original data, and stores, analyzes, and displays it.

7. The method of the FPGA-based optical fiber three-component detector data acquisition system according to claim 6, characterized in that: In step S2, the parameter information includes channel enable, sampling range and sampling rate.

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