A dual-channel GTX high-speed data transfer and storage system based on DDR3 + PCIe

Abstract

This application provides a dual-channel GTX high-speed data transmission and storage system based on DDR3 + PCIe, comprising: a GTX receiving module for receiving high-speed transmission data from the front-end systems (left and right systems); a data processing module for performing frame synchronization on the two data channels and multiplexing them according to priority; a large-capacity cache control module for scheduling and optimizing the read / write operations of the DDR3 controller and FIFO through a state machine to achieve large-capacity data caching; and a PCIe DMA control module for transferring the cached data to the PC's memory via the PCIe channel, completing real-time storage of high-speed data on the PC. The advantages of this application are: a storage rate of up to 10.24Gbps when storing data on the host computer; and the encapsulation of the large-capacity cache control block into a black-box-like form, allowing users to directly call this part of the design without modifying the code.

Description

Technical Field

[0001] This application belongs to the field of high-speed data transmission and large-capacity storage, specifically involving a dual-channel GTX high-speed data transmission and storage system based on DDR3+PCIE. Background Technology

[0002] In the spaceborne radar altimeter system, after the satellite is launched and put into orbit, events are injected by the satellite platform. The central electronics generates various working instructions based on the injected events and then transmits them to the left / right numerical control subsystems. The left / right numerical control subsystems generate various working timing sequences based on the working instructions, transmit intermediate frequency signals, perform ADC acquisition, and return the acquisition results to the central electronics.

[0003] The central electronic control system receives echo data from the left and right numerical control subsystems' ADCs at a total rate of up to 10Gbps (5Gbps for each system), requiring the ability to output the raw data to the satellite platform. While existing central electronic control systems can simultaneously receive two high-speed data streams, their storage rates are insufficient to match the received data; or, while some systems have a "buffer" capacity to match the data transmission speed, they lack real-time data storage functionality. Therefore, a system capable of simultaneously receiving and storing dual high-speed data streams in real time is urgently needed. Summary of the Invention

[0004] The purpose of this application is to overcome the shortcomings of existing technologies where storage speed and data transfer speed are mismatched.

[0005] To achieve the above objectives, this application proposes a dual-channel GTX high-speed data transmission and storage system based on DDR3 + PCIe, comprising: a GTX receiving module, a data processing module, a large-capacity cache control module, and a PCIe DMA control module; wherein,

[0006] The GTX receiving module is implemented by calling the GTX IP core. It is used to receive high-speed transmission data from the front-end system and send the left system GTX data and the right system GTX data to the data processing module.

[0007] The data processing module is used to perform frame synchronization on the two received data streams, and to perform multiplexing according to the set priority before sending them to the large-capacity buffer control module.

[0008] The large-capacity cache control module uses a state machine to schedule and optimize the read and write operations of the DDR3 controller and FIFO, thereby achieving data caching.

[0009] The PCIe DMA control module is used to move cached data to the PC's memory through the PCIe channel, thereby completing the real-time storage of high-speed data on the PC.

[0010] As an improvement to the above system, the data processing module includes a frame synchronization module and a multiplexing module; wherein,

[0011] The frame synchronization module adopts a fixed-length frame synchronization strategy. After the frame synchronization module finds the frame header, it identifies the system ID to determine whether the current data comes from the left system or the right system, and outputs the synchronized data to the multiplexing module according to the set frame length.

[0012] The multiplexing module is used to send the synchronized left system data and right system data to their respective buffer FIFOs, and output the multiplexed frame and the multiplexed frame enable to the large-capacity buffer control module.

[0013] As an improvement to the above system, the process by which the multiplexing module sends data to the buffer FIFO includes:

[0014] First, check if there is enough data in the left / right buffer FIFO for one frame, with the left buffer having higher priority than the right buffer. If the left buffer FIFO has more readable data than one frame, start reading data from the left buffer FIFO; otherwise, check if the right buffer FIFO has enough data for one frame.

[0015] Once the left buffer FIFO has read enough for one frame, check if the right buffer FIFO has enough for one frame. If the right buffer FIFO has more readable data than one frame, start reading data from the right buffer FIFO. Otherwise, continue checking if the left buffer FIFO has more readable data than one frame, and so on.

[0016] Once the right buffer FIFO has read enough frames, it continues to check whether the left buffer FIFO has stored enough frames, and so on.

[0017] Finally, the multiple frames resulting from the multiplexing of the frames from the left system and the right system, along with the frame enable, are output to the large-capacity buffer control module.

[0018] As an improvement to the aforementioned system, the large-capacity cache control module includes a user FIFO, a write-ahead FIFO, a DDR3 controller, a read-ahead FIFO, and a PCIe interactive FIFO; wherein,

[0019] The user FIFO is used to complete the cross-clock domain processing and bit width conversion of the multiplexed data, as well as the flow control between it and the pre-write FIFO; the read enable of the user FIFO is also the write enable of the pre-write FIFO, which is when the current user FIFO is not empty and the pre-write FIFO is not full; when the user FIFO is read enabled, the data is read and output to the pre-write FIFO.

[0020] The pre-write FIFO is used to complete the flow control with the user FIFO in the previous stage and the read / write control of the DDR3 controller in the subsequent stage; the read data bit width of the pre-write FIFO matches the input data app_wdf_data bit width of the MIG IP core; the read enable of the pre-write FIFO is initiated by the state machine of the DDR3 controller in the subsequent stage.

[0021] The DDR3 controller, based on the MIG IP core, uses a state machine to complete read and write operations and state switching between the pre-write FIFO and the pre-read FIFO, and implements the MIG IP core's read and write control of DDR3 according to the DDR3 user interface read and write timing requirements;

[0022] The prefetch FIFO is used to complete the read and write control with the front-end DDR3 controller and the rear-end PCIe interactive FIFO; the write data bit width of the prefetch FIFO matches the output data app_rd_data bit width of the MIG IP core; the output data bit width of the prefetch FIFO matches the write data bit width of the PCIe interactive FIFO; the write enable of the prefetch FIFO is DDR3 read data valid enable app_rd_data_valid; the read enable of the prefetch FIFO is also the write enable of the PCIe interactive FIFO, which is when the prefetch FIFO is not empty and the rear-end PCIe interactive FIFO is not full;

[0023] The PCIE interactive FIFO is used to complete the flow control of the front-end pre-read FIFO and the back-end PCIE DMA control module.

[0024] As an improvement to the above system, when it is necessary to match the clock and data bit width of the multiplexed data, this can be accomplished by modifying the write clock and write data bit width of the user FIFO, without modifying the pre-write FIFO, DDR3 controller, pre-read FIFO and PCIe interactive FIFO.

[0025] As an improvement to the above system, the state machine of the DDR3 controller includes 9 states:

[0026] The S0 state is the initial state, used to detect whether DDR3 initialization is complete. When DDR3 initialization is complete, it jumps to the S1 state.

[0027] In state S1, DDR3 writability is checked by detecting whether there is data of a set length in the pre-write FIFO that can be written to DDR3. If there is, the process jumps to state S2; otherwise, it jumps to state S5.

[0028] In S2 state, the write command is initiated. According to the set timing requirements, before app_rdy arrives, app_cmd is assigned the value 0 to indicate the write command, and the enable app_en of address app_addr is pulled high. At the same time, the process jumps to S3 state.

[0029] In state S3, when writing data, if app_rdy goes high, the write enable app_wdf_wren is pulled high, and the process jumps to state S4; otherwise, the process remains in state S3, and the write enable app_wdf_wren is pulled low.

[0030] In state S4, check the write data block. If the DDR3 has continuously written the set length of data, jump to state S5. If the set length of data has not been written, check if the write preparation signal app_wdf_rdy is high. If the write preparation signal app_wdf_rdy is high, return to state S2 to continue writing. Otherwise, stay in state S4.

[0031] In state S5, a DDR3 readability check is performed. If the prefetch FIFO has a set length of writable space and the DDR3 has a set length of readable data, then jump to state S6; otherwise, return to state S1 to continue checking whether the DDR3 is writable.

[0032] In state S6, the read command is initiated. According to the set timing requirements, before app_rdy arrives, app_cmd is assigned the value 1 to indicate the read command, and the enable app_en of address app_addr is pulled high. At the same time, the process jumps to state S7.

[0033] In state S7, read data. If app_rdy goes high, jump to state S8; otherwise, stay in state S7.

[0034] In state S8, a data block check is performed. If the DDR3 reads the set length of data continuously, it jumps to state S1; otherwise, it jumps to state S7 to continue reading.

[0035] As an improvement to the above system, the PCIe DMA control module is implemented based on the PCIe IP core and is used to complete high-speed data transmission on the PCIe bus, directly transmitting data to the PC's memory; a fixed length of data is transmitted each time during data transmission.

[0036] As an improvement to the above system, the system also includes a data storage speed self-test mode for testing the system's maximum storage rate;

[0037] The data storage speed self-test mode is as follows: The PC writes a register representing the frequency control word to the FPGA. Using the DDS principle, different frequency control words are set to generate clocks of different frequencies. An accumulated number is generated under this clock as test data. This accumulated number is transmitted to the PC for storage. By analyzing whether there is any data loss in the stored file, the maximum storage rate of the system is verified.

[0038] Compared with existing technologies, the advantages of this application are:

[0039] 1. This invention proposes a dual-channel GTX high-speed data transmission and storage system based on DDR3+PCIE, which is suitable for applications such as massive data transmission and storage, and high-speed AD acquisition and playback; it has been verified that the storage rate is as high as 10.24Gbps when the data is stored on the host computer disk.

[0040] 2. This invention optimizes the read and write operations of DDR3, improving the read and write efficiency of DDR3, and encapsulates the large-capacity cache control block into a black-box-like form, allowing users to directly call this part of the design without modifying the code.

[0041] 3. The present invention uses DMA to transfer data to the PC, which is independent of the CPU hardware controller and directly manages the data transfer process, greatly improving system efficiency.

[0042] 4. This invention provides a simple method for self-testing system storage speed. This method utilizes the principle of DDS and flexibly generates clocks of different frequencies by modifying the frequency control word online on the host computer, thereby testing the system's data transmission and storage capabilities.

[0043] 5. The system of the present invention not only supports dual-channel high-speed data transmission and storage scenarios, but also is compatible with single-channel high-speed data transmission and storage scenarios without requiring configuration modifications. Attached Figure Description

[0044] Figure 1 The diagram shows the structural block diagram of a dual-channel GTX high-speed data transmission and storage system based on DDR3+PCIE.

[0045] Figure 2 The image shows the frame format of the transmission frames in the left / right system.

[0046] Figure 3 The diagram shown is a schematic of the DDR3 memory controller interface;

[0047] Figure 4 The diagram shown is the state transition diagram of the DDR3 controller;

[0048] Figure 5 The image shows the DMA host computer's operating interface. Detailed Implementation

[0049] The technical solution of this application will be described in detail below with reference to the accompanying drawings.

[0050] Example 1

[0051] In most cases, the internal RAM of an FPGA is relatively small, requiring external high-capacity chips (such as DDR3) to store data. The internal chip RAM is called static RAM, which is simple to read and write, has a moderate speed, but its disadvantage is its small storage space.

[0052] FPGAs can be programmed to control DDR memory access. This application provides a dual-channel GTX (GT, Gigabyte Transceiver, supported by all Xilinx 7 series FPGAs, commonly referred to as SerDes, high-speed transceiver, GT, or specific models such as GTX) high-speed data transmission and storage system based on DDR3 + PCIe. Implemented using a high-performance Xilinx Kintex-7 series board as the main controller, it is suitable for applications such as massive data transmission and storage, and high-speed AD acquisition and playback. The system includes: a GTX receiving module, a data processing module, a large-capacity cache control module, and a PCIe DMA control module. Figure 1 The diagram shows the structure of a dual-channel GTX high-speed data transfer and storage system based on DDR3+PCIE, illustrating the connection relationships between the various components.

[0053] The GTX receiving module is implemented by calling the GTX IP core. The GTX IP core is configured with the following parameters according to the agreed data transmission protocol: 8B / 10B encoding, K-code K28.1, external interface data width of 32 bits, RX Line Rate of 5Gbps, and RXUSRCLK of 125MHz. The GTX receiving module receives data from the left and right CNC subsystems respectively and sends the data to the data processing module according to the set data transmission protocol.

[0054] The data processing module includes two frame synchronization modules and a multiplexing module.

[0055] Both frame synchronization modules employ a fixed-length frame synchronization strategy. Figure 2 The frame format information is provided. The frame header is 32'h1ACFFC1D, and a 4-byte system ID is used to distinguish the data from the left and right systems. The left system ID is 32'hAAAAAAAA, and the right system ID is 32'hBBBBBBBB. The two frame synchronization modules receive the data sent by the GTX receiving module and output data of length FrameLength according to the frame length agreed upon with the sending end, and then send it to the multiplexing module.

[0056] The multiplexing module is used to send the synchronized left system data and right system data to their respective buffer FIFOs. The depth of the buffer FIFO is at least 2 * FrameLength, and the read and write bit width of the buffer FIFO is 32 bits. The state machine switches between writing and reading the two buffer FIFOs according to priority: 1) First, it checks whether there is enough data in the left / right FIFO for one frame, with the left having higher priority than the right. If the data that can be read from the left buffer FIFO is greater than one frame, then it starts reading the data in the left buffer FIFO; otherwise, it checks whether there is enough data in the right buffer FIFO for one frame. 2) After the left buffer FIFO has read enough data for one frame, it checks the right buffer FIFO. If the right buffer FIFO has enough data to store one frame, then start reading the data in the right buffer FIFO; otherwise (if the right buffer FIFO has enough data to store one frame), then jump back to 1) and continue to check if the left buffer FIFO has enough data to store one frame, and so on; 3) after the right buffer FIFO has enough data to store one frame, continue to check if the left buffer FIFO has enough data to store one frame, and so on, and finally output the multi-frame Mult_Frame after multiplexing the frames of the left system and the frames of the right system and the frame enable Mult_Frame_en to the large capacity buffer control module. In Example 1, the width of the frame data after multiplexing is 32 bits.

[0057] The large-capacity cache control module uses a state machine to schedule and optimize the read and write operations of the DDR3 controller and FIFO, thereby achieving large-capacity data caching. This includes the user FIFO, write-ahead FIFO, DDR3 controller, read-ahead FIFO, and PCIe interactive FIFO.

[0058] The user FIFO is used to perform cross-clock domain processing and bit width conversion (32-bit to 64-bit) of the multiplexed data, as well as flow control with the pre-write FIFO. The read enable of the user FIFO, userfifo_rd_en (which is also the write enable of the pre-write FIFO, fifo_wrreq_ddr3_us), is set when the current user FIFO is not empty and the pre-write FIFO is not full. When the user FIFO is read, the data is read and output to the pre-write FIFO.

[0059] The pre-write FIFO is used to complete flow control with the front-end user FIFO and read / write control of the back-end DDR3 controller. The read data bit width of the pre-write FIFO matches the input data app_wdf_data bit width of the MIG IP core. The read enable of the pre-write FIFO is initiated by the state machine of the back-end DDR3 controller. In this embodiment, the read data fifo_q_ddr3_us of the pre-write FIFO has a bit width of 512 bits; the read enable of the pre-write FIFO fifo_rdreq_ddr3_us is initiated by the state machine of the back-end DDR3 controller.

[0060] The DDR3 controller, based on the MIG (Memory Interface Generators) IP core, integrates a memory control module to implement the control flow for DDR read and write operations. The MIG IP core provides two sets of interfaces: one side connects to the DDR3 physical chip interface, and the other side is the user logic control interface (UserFPGALogic). Correctly controlling DDR3 read and write operations requires proper configuration of the MIG IP and the correct user logic control interface. The main user logic control interfaces include: rst, clk, app_addr, app_cmd, app_en, app_wdf_data, app_wdf_end, app_wdf_wren, app_rdy, app_rd_data, app_rd_data_end, app_rd_data_valid, and app_wdf_rdy.

[0061] The main configuration parameters for the MIG IP core are:

[0062] Controller type: DDR3 SDRAM;

[0063] The master clock frequency is 800MHz;

[0064] The PHYtoController ClockRatio determines the ratio of the physical layer clock frequency to the controller and user interface clock frequencies. In this embodiment, a ratio of 4:1 is selected, which means that the bit width is 8 times the bit width of the physical layer interface.

[0065] For the memory part, select MT41J128M16XX-125-WZL according to the board schematic.

[0066] In memory address mapping, the priority is to change the column first, then the bank, and then the row.

[0067] The state machine handles read / write operations and state transitions between the pre-write FIFO and the pre-read FIFO, implementing MIG IP core read / write control of DDR3 according to the DDR3 user interface read / write timing requirements, and improving DDR3 read / write efficiency. A schematic diagram of the DDR3 memory controller interface is shown below. Figure 3 As shown in the diagram, the DDR3 controller's state machine transition diagram has 9 states, as follows: Figure 4 As shown, where:

[0068] State S0 is the initial state, used to detect whether DDR3 initialization is complete. When DDR3 initialization is complete, i.e., when init_calib_complete goes high, the state machine jumps to state S1.

[0069] In state S1, DDR3 writability is checked by detecting whether there is data of length (set to 128 in this embodiment) in the pre-write FIFO that can be written to DDR3. If there is, the process jumps to state S2; otherwise, it jumps to state S5 to determine whether DDR3 is readable.

[0070] In state S2, the write command is initiated. According to the timing requirements in the manual, before app_rdy arrives, app_cmd is assigned the value 0 to indicate the write command, and the enable app_en of address app_addr is pulled high. At the same time, the process jumps to state S3.

[0071] In state S3, when writing data, if app_rdy goes high, the write enable app_wdf_wren is pulled high, and the process jumps to state S4; otherwise, the process remains in state S3, and the write enable app_wdf_wren is pulled low.

[0072] In state S4, check the write data block. If the DDR3 has continuously written a data block of length, jump to state S5. If the data block of length has not been written, check if the write preparation signal app_wdf_rdy is high. If the write preparation signal app_wdf_rdy is high, return to state S2 to continue writing; otherwise, remain in state S4.

[0073] In state S5, a DDR3 readability check is performed. If the pre-read FIFO has a space of length that can be written and there is a data amount of length that can be read in DDR3, the state jumps to state S6; otherwise, it returns to state S1 to continue checking whether DDR3 is writable.

[0074] In state S6, the read command is initiated. According to the timing requirements in the manual, before app_rdy arrives, app_cmd is assigned the value 1 to indicate the read command, and the enable app_en of address app_addr is pulled high. At the same time, the process jumps to state S7.

[0075] In state S7, read data. If app_rdy goes high, jump to state S8; otherwise, stay in state S7.

[0076] In state S8, a data block check is performed. If the DDR3 reads a complete block of data of length size, the process jumps to state S1; otherwise, it jumps to state S7 to continue reading.

[0077] To improve the read and write efficiency of DDR3, the following measures can be taken: sequential read and write by address, reducing the frequency of read and write switching (adopting a strategy of writing data of length continuously and then reading data of length continuously), and increasing the main clock frequency of the MIG IP core configuration.

[0078] The prefetch FIFO is used to control the read and write operations with the front-end DDR3 controller and the rear-end PCIe interactive FIFO. The write data width of the prefetch FIFO matches the output data width of the MIG IP core (app_rd_data). The output data width of the prefetch FIFO matches the write data width of the PCIe interactive FIFO. The write enable of the prefetch FIFO is enabled by DDR3 read data valid (app_rd_data_valid). In this embodiment, the write data width of the prefetch FIFO is 512 bits, and the output data width is 64 bits. The write enable of the prefetch FIFO is enabled by DDR read data valid (app_rd_data_valid), and the read enable of the prefetch FIFO (which is also the write enable of the PCIe interactive FIFO) is that the prefetch FIFO is not empty and the rear-end PCIe interactive FIFO is not full.

[0079] The PCIe interactive FIFO is used to complete the flow control between the front-end pre-read FIFO and the back-end PCIe DMA control module. The write data width of the PCIe interactive FIFO is 64 bits, and the read data width is 128 bits, which are sent to the back-end PCIe DMA control module.

[0080] The PCIe DMA control module is implemented based on a PCIe IP core and uses DMA for data exchange. The PCIe link rate is 5Gb / s, the link width is x8, and the interface width is 128 bits. DMA is used to complete high-speed data transfer on the PCIe bus, directly moving data to the PC's memory. DMA transfers are in fixed-size increments, with a selectable range of 4KB to 131072KB. The PC-side program controls the FPGA's operating mode through read / write registers, both of which have a 32-bit width. Figure 5 The DMA host computer operating interface of this invention is provided, including:

[0081] 1) Data storage path: Named according to "year / month / day / hour / minute / second".

[0082] 2) DMA size: Optional range 4KB to 131072KB.

[0083] 3) Link speed / width: PCIe link speed is 5G, 8 lanes.

[0084] 4) Speed / Time: Transmission speed and transmission time are displayed in real time.

[0085] 5) Received / Remaining Space: Received data size and remaining disk space.

[0086] 6) Register read / write: Register write can be used to configure test data rate and reset DDR3, etc., while register read can be used for process debugging.

[0087] In this system, when it is necessary to match the clock and data bit width of the multiplexed data, it is only necessary to modify the write clock and write data bit width of the user FIFO, without modifying the write-ahead FIFO, DDR3 controller, read-ahead FIFO and PCIe interactive FIFO.

[0088] This system is also compatible with scenarios requiring high-speed data transmission and storage for a single data stream. When there is only a single data stream (left or right system), since there is only one GTX data input, the frame synchronization module also outputs only one data stream, meaning the multiplexing module only inputs one data stream into the buffer FIFO. In this case, the operation flow of the multiplexing module remains unchanged; however, the buffer FIFO corresponding to the system lacking data will always be empty and will never store a full frame.

[0089] Example 2

[0090] The following test uses the data storage speed self-test mode of Example 2 to test the highest storage rate that the system can adapt to. For example... Figure 5 As shown, the PC writes the value 32'd2748779069 to register address user_reg_read_0x30 as the frequency control word for the DDS (Direct Digital Synthesizer, an IP core in an FPGA that can be directly called; its clock frequency, frequency control word, output frequency, and phase are configured to achieve corresponding frequency and phase outputs). The DDS's drive clock is 250MHz. When the phase output by the DDS is less than the first-level delay of that phase, an overflow enable is generated at a frequency of 160MHz. When the enable is active, a 64-bit wide accumulation number is generated, resulting in an output data rate of 160e6*64 = 10.24Gbps in self-test mode. This signal is then connected to the user FIFO described in Example 1. The DMA size is set, and "Start Reception" is clicked to begin data storage. When the remaining disk space is insufficient to handle the amount of data transferred by the DMA in one operation, "Stop Reception" is clicked, and the host computer interface is closed. In the corresponding disk directory, use BES or other data processing software to open the saved data, analyze whether there is any data loss, and test the highest transfer rate under the disk saving conditions. It has been verified that in Example 2, when the DMA size is selected as 16384K and the data is saved on the host computer, the storage rate reaches as high as 10.24Gbps.

[0091] It should be noted that, Figure 5The transfer speed displayed on the host computer interface is the current transfer speed. Different DMA size settings, different DDR3 cache capacities, and disk performance will all affect the final storage speed.

[0092] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application and are not intended to limit it. Although this application has been described in detail with reference to the embodiments, those skilled in the art should understand that modifications or equivalent substitutions to the technical solutions of this application do not depart from the spirit and scope of the technical solutions of this application, and should all be covered within the scope of the claims of this application.

Claims

1. A DDR3+PCIE-based dual-path GTX high-speed data transmission storage system, characterized in that, include: The GTX receiver module, data processing module, large-capacity buffer control module, and PCIe DMA control module; among them, The GTX receiving module is implemented by calling the GTX IP core. It is used to receive high-speed transmission data from the front-end system and send the left system GTX data and the right system GTX data to the data processing module. The data processing module is used to perform frame synchronization on the two received data streams, and to perform multiplexing according to the set priority before sending them to the large-capacity buffer control module. The large-capacity cache control module uses a state machine to schedule and optimize the read and write operations of the DDR3 controller and FIFO, thereby achieving data caching. The PCIe DMA control module is used to move cached data to the PC's memory through the PCIe channel, thereby completing the real-time storage of high-speed data on the PC. The large-capacity cache control module includes a user FIFO, a write-ahead FIFO, a DDR3 controller, a read-ahead FIFO, and a PCIe interactive FIFO; among which, The user FIFO is used to complete the cross-clock domain processing and bit width conversion of the multiplexed data, as well as the flow control between it and the pre-write FIFO; the read enable of the user FIFO is also the write enable of the pre-write FIFO, which is when the current user FIFO is not empty and the pre-write FIFO is not full; when the user FIFO is read enabled, the data is read and output to the pre-write FIFO. The pre-write FIFO is used to complete the flow control with the user FIFO in the previous stage and the read / write control of the DDR3 controller in the subsequent stage; the read data bit width of the pre-write FIFO matches the input data app_wdf_data bit width of the MIG IP core; the read enable of the pre-write FIFO is initiated by the state machine of the DDR3 controller in the subsequent stage. The DDR3 controller, based on the MIG IP core, uses a state machine to complete read and write operations and state switching between the pre-write FIFO and the pre-read FIFO, and implements the MIG IP core's read and write control of DDR3 according to the DDR3 user interface read and write timing requirements; The prefetch FIFO is used to complete the read and write control with the front-end DDR3 controller and the rear-end PCIe interactive FIFO; the write data bit width of the prefetch FIFO matches the output data app_rd_data bit width of the MIG IP core; the output data bit width of the prefetch FIFO matches the write data bit width of the PCIe interactive FIFO; the write enable of the prefetch FIFO is DDR3 read data valid enable app_rd_data_valid; the read enable of the prefetch FIFO is also the write enable of the PCIe interactive FIFO, which is when the prefetch FIFO is not empty and the rear-end PCIe interactive FIFO is not full; The PCIE interactive FIFO is used to complete the flow control of the front-end pre-read FIFO and the back-end PCIE DMA control module.

2. The DDR3+PCIE-based dual-path GTX high-speed data transmission memory system according to claim 1, wherein, The data processing module includes a frame synchronization module and a multiplexing module; wherein... The frame synchronization module adopts a fixed length frame synchronization strategy; after the frame synchronization module searches for a frame header, it identifies a system ID to determine whether the current data comes from a left system or a right system, and outputs frame-synchronized data to the combining and multiplexing module according to a set frame length; The combining and multiplexing module is configured to send the frame-synchronized left system data and right system data to respective buffer FIFOs, and output a combined and multiplexed frame and a multiplexed frame enable to the large capacity buffer control module.

3. The DDR3+PCIE-based dual-path GTX high-speed data transmission memory system according to claim 2, characterized in that, The process in which the combining and multiplexing module sends data to the buffer FIFOs includes: First, it is detected whether the data in the left / right buffer FIFOs is enough for one frame, with the priority being that the left is higher than the right; if the readable data in the left buffer FIFO is greater than one frame, the data in the left buffer FIFO is read; otherwise, it is detected whether the readable data in the right buffer FIFO is enough for one frame; When the readable data in the left buffer FIFO is enough for one frame, it is detected whether the readable data in the right buffer FIFO is enough for one frame; if the readable data in the right buffer FIFO is greater than one frame, the data in the right buffer FIFO is read; otherwise, it is continuously detected whether the readable data in the left buffer FIFO is greater than one frame, and the process is repeated; When the readable data in the right buffer FIFO is enough for one frame, it is continuously detected whether the readable data in the left buffer FIFO is enough for one frame, and the process is repeated; Finally, the combined and multiplexed frames of the left system and the right system and the frame enable are output to the large capacity buffer control module.

4. The DDR3+PCIE-based dual-path GTX high-speed data transmission memory system according to claim 1, wherein, When it is necessary to match the clock and the data bit width of the combined and multiplexed data, the write clock and the bit width of the write data of the user FIFO are modified to complete the matching, without modifying the pre-write FIFO, the DDR3 controller, the pre-read FIFO and the PCIE interaction FIFO.

5. The DDR3+PCIE-based dual-path GTX high-speed data transmission memory system according to claim 1, wherein, The state machine of the DDR3 controller includes nine states: The S0 state is an initial state, and is configured to detect whether the DDR3 is initialized; when the DDR3 is initialized, the state is switched to the S1 state; The S1 state is configured to detect whether the data of the set length in the pre-write FIFO can be written into the DDR3; if yes, the state is switched to the S2 state; otherwise, the state is switched to the S5 state; The S2 state is configured to start a write command; before the app_rdy arrives, the app_cmd is assigned as 0 to indicate the write command, the enable app_en of the address app_addr is pulled high, and the state is switched to the S3 state; The S3 state is configured to write data; when the app_rdy is pulled high, the write enable app_wdf_wren is pulled high, and the state is switched to the S4 state; otherwise, the write enable app_wdf_wren is pulled low, and the state remains in the S3 state; The S4 state is configured to check the write data block; if the DDR3 continuously writes the data of the set length, the state is switched to the S5 state; if the data of the set length is not written, it is judged whether the write preparation signal app_wdf_rdy is pulled high; if yes, the state returns to the S2 state to continue writing; otherwise, the state remains in the S4 state; S5 state, DDR3 readable judgment is carried out, if pre-read FIFO has set length space writable and DDR3 has set length data amount readable, jump to S6 state; otherwise, return to S1 state to continue to judge whether DDR3 is writable; S6 state, start read command, according to the set timing requirement, app_cmd is assigned as 1 before app_rdy arrives, indicating read command, and the enablement app_en of address app_addr is pulled high, and jump to S7 state; S7 state, read data, if app_rdy is pulled high, jump to S8 state; Otherwise, stay in S7 state; And S8 state, read data block check is carried out, if DDR3 continuously reads set length data, jump to S1 state; Otherwise, jump to S7 state to continue to read.

6. The DDR3+PCIE-based dual-path GTX high-speed data transmission memory system according to claim 1, characterized in that, The PCIE DMA control module is realized based on PCIE IP core, is used for completing high speed transmission of data on PCIE bus, and directly transmits data to the memory of PC. Fixed length data is transmitted each time during data transmission.

7. The DDR3+PCIE-based dual-path GTX high-speed data transmission memory system according to claim 1, wherein, The system further includes data storage speed self-checking mode, used for testing the highest storage rate of the system; The data storage speed self-checking mode is that: the PC end writes the register indicating frequency control word to FPGA, utilizes DDS principle, sets different frequency control words, generates different frequency clock, generates cumulative number as test data under the clock, and the cumulative number is transmitted to PC to store; Whether the stored file has data loss is analyzed, and the highest storage rate of the system is verified.

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