A method, product, apparatus, and readable storage medium for layout of printed circuit boards

Abstract

The application discloses a printed circuit board layout method, product, equipment and readable storage medium, relates to the technical field of PCB design, and includes decoupling position layout and rotation angle optimization, optimizing separation into independent stages executed in sequence, avoiding mutual interference of two types of decisions, greatly reducing search space, and improving convergence efficiency. After placing each new component, all placed components on the current board are optimized in rotation, the cumulative influence of early component default direction deviation on subsequent layout is eliminated, the optimal solution is gradually approached through multiple iterations, the total length of the line network of the final layout is reduced, and the signal transmission performance of the PCB circuit is significantly improved, thereby solving the problem that early decisions cause irreversible influence on subsequent layout, and achieving the beneficial effects of improving layout quality and optimizing PCB circuit performance.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of PCB design, and in particular to a layout method of a printed circuit board, a product, an apparatus and a readable storage medium. BACKGROUND

[0002] A PCB (Printed Circuit Board) is used to carry various electronic components to realize circuit functions. The main stages of PCB design include schematic design and layout design, and the layout design is divided into two key steps of layout and routing. The quality of the layout directly affects the complexity and quality of the routing, and also affects the area utilization, power consumption and heat dissipation performance of the PCB. In the current layout scheme, once the direction of a component is determined in the placement process, it cannot be modified in the subsequent stage, and the suboptimality of the direction selection of the previous component will affect the overall layout quality.

[0003] Therefore, how to provide a scheme to solve the above technical problems is a problem that those skilled in the art need to solve at present. SUMMARY

[0004] The present application provides a layout method of a printed circuit board, a product, an apparatus and a readable storage medium to at least solve the problem that early decisions cause irreversible effects on subsequent layout in the related art.

[0005] The present application provides a layout method of a printed circuit board, comprising: selecting a to-be-placed component from a set of unplaced components in a current iteration based on a layout state of a printed circuit board in the current iteration, and determining a placement position of the to-be-placed component on the printed circuit board; placing the to-be-placed component in the placement position in a default direction, updating the layout state; for each to-be-optimized component in the updated layout state, determining an optimal rotation angle of the to-be-optimized component, rotating the to-be-optimized component from a current placement direction by the optimal rotation angle to obtain an optimal placement direction, and updating the layout state to enter a next iteration; outputting the placement position and the placement direction of each component in the last iteration as a final layout scheme of the printed circuit board, and the set of unplaced components in the last iteration is empty.

[0006] The present application also provides a computer program product comprising a computer program, which, when executed by a processor, implements the steps of any of the above layout methods of a printed circuit board.

[0007] The present application also provides an electronic device comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above layout methods of a printed circuit board when executing the computer program.

[0008] The application further provides a computer readable storage medium, and the computer readable storage medium stores a computer program.

[0009] According to the application, since the position layout and the rotation angle are decoupled, the optimization is separated into independent stages which are sequentially executed, the search space is greatly reduced, and the convergence efficiency is improved. After each new component is placed, the rotation optimization is performed on all the placed components on the current board, the cumulative influence of the default direction deviation of the early components on the subsequent layout is eliminated, the optimal solution is gradually approached through multiple iterations, the total length of the line net of the final layout is reduced, and the signal transmission performance of the PCB circuit is significantly improved, thereby solving the problem that the early decision causes irreversible influence on the subsequent layout, and achieving the beneficial effects of improving the layout quality and optimizing the performance of the PCB circuit. BRIEF DESCRIPTION OF DRAWINGS

[0010] In order to more clearly illustrate the embodiments of the application, the drawings needed in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0011] Figure 1 A step flow chart of a layout method of a printed circuit board provided by the embodiments of the application.

[0012] Figure 2 A placing direction schematic diagram provided by the embodiments of the application.

[0013] Figure 3 A node expansion schematic diagram provided by the embodiments of the application.

[0014] Figure 4 A pin feature construction schematic diagram provided by the embodiments of the application.

[0015] Figure 5 A structure schematic diagram of a layout device of a printed circuit board provided by the embodiments of the application. DETAILED DESCRIPTION

[0016] The technical solutions in the embodiments of the application will be clearly and completely described below with reference to the drawings in the embodiments of the application. Obviously, the described embodiments are only some of the embodiments of the application, but not all the embodiments. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the application.

[0017] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0018] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0019] Embodiments of this application provide a layout method for a printed circuit board, combined with Figure 1 The layout method of the printed circuit board is described in detail.

[0020] S101: Based on the layout state of the printed circuit board in the current iteration, select the component to be placed from the set of unplaced components in the current iteration, and determine the placement position of the component on the printed circuit board.

[0021] First, relevant information about the printed circuit board (PCB) will be explained. This information includes at least the PCB size. The PCB can be discretized into grid points. In this embodiment, Defined as the set of locations after the printed circuit board is discretized. For example, the printed circuit board is discretized as follows: The grid, then The components are positioned in orientation O on the printed circuit board, and each component can be adjusted in one of the following four orientations, including but not limited to: , representing the default orientation of the component and its orientation after rotating it clockwise by different angles, respectively. 0 indicates the use of the default orientation from the package technology library, 90 indicates rotating the default orientation 90 degrees clockwise, and so on. The following text will use ( ) The component's position on the printed circuit board is represented by the form , and its orientation on the printed circuit board is represented by rot (including but not limited to one of the following: using the default orientation from the package library, using the default orientation rotated 90 degrees clockwise, using the default orientation rotated 180 degrees clockwise, or using the default orientation rotated 270 degrees clockwise, such as...). Figure 2 (As shown).

[0022] It is understandable that, in order to improve the reliability of component layout on the printed circuit board, this embodiment adopts an iterative approach to update the placement position and orientation of each component on the printed circuit board. Before iterating, relevant information of the printed circuit board, component list, and netlist are first obtained. The component list includes size information (height, width) and pin information, and the netlist consists of several nets, each net including a drive pin and one or more load pins.

[0023] First, determine the layout state of the printed circuit board in the current iteration. and unlaid-out component sets , This indicates the iteration number. If the current iteration is the first iteration, then... The layout of the printed circuit board is as follows: ,initialization N is the total number of components in the component list. If the current iteration is the fifth iteration, then... The layout of the printed circuit board is as follows: The set of unlaid-out components is The layout state of the printed circuit board includes the set of all placed components on the printed circuit board in the current iteration, including their positions and orientations. Its initial state ( The unplaced component set refers to the set of components that have not yet been placed on the printed circuit board in the current iteration. Its initial state is the complete set of all components to be placed.

[0024] Based on the layout state of the printed circuit board in the current iteration From non-empty Select a component c to be placed and determine the placement position of component c on the printed circuit board. The placement position is determined by the discretized grid coordinates ( () represents a grid system on a printed circuit board where x and y are integers representing the specific location of the component c to be placed. (From a non-empty) When selecting a component c to be placed, the selection can be made according to a preset optimization strategy or randomly. This embodiment does not make specific limitations here.

[0025] For example, suppose we are currently in the first iteration ( ), map status The board is empty and no component set has been placed. It contains three components, namely The goal of this step is to... Select a component as the component to be placed, such as a resistor R, and determine its placement position. The output of this step is that the component to be placed is a resistor R, and its placement position is... .

[0026] S102: Place the to-be-placed component in the default direction on the placement position, and update the layout state.

[0027] It can be understood that the default direction refers to the initial orientation of the to-be-placed component defined in the packaging library, usually denoted as a rotation angle , representing the standard placement posture of the component without any rotation transformation. After placing the to-be-placed component c in the default direction on its corresponding placement position, it is equivalent to updating the component layout on the printed circuit board, adding a component placed in the default direction on the printed circuit board. At this time, the layout state is updated, and the updated layout state is . The process of updating the layout state includes but is not limited to adding the (component ID, placement position ( ) and placement direction ) of the to-be-placed component c to the layout state .

[0028] For example, assume that the to-be-placed component c is a resistor R, and its placement position is ( ). This step first places the resistor R in its default direction (rotation angle ) on the ( ) coordinate grid point of the printed circuit board. Then, the layout state update operation is performed, and the identifier (R) of the component, the position ( ) and the direction ( ) are added to the layout state as a new record entry, obtaining . At the same time, the component R is removed from the un-laid component set ( ). For example, if the un-laid component set , is empty before updating, then the un-laid component set , after updating. It can be understood that the updated in this embodiment is used as the un-laid component set in the next iteration, i.e., the th iteration.

[0029] In this embodiment, the selected to-be-placed component is initially placed in the default direction, providing a stable and reasonable starting point for subsequent fine direction optimization, avoiding optimization difficulties caused by improper initial direction. At the same time, updating the layout state in real time ensures that each decision is based on the latest global information, maintaining the data integrity of the iteration process and providing a foundation for efficient and automated layout process.

[0030] S103: For each element to be optimized in the updated layout state, determine the optimal rotation angle of the element to be optimized, rotate the element to be optimized from the current placement direction by the optimal rotation angle to obtain the preferred placement direction, update the layout state, and enter the next iteration.

[0031] In this embodiment, considering that a new component c is added to the updated layout, meaning that component c is newly placed on the printed circuit board, the component layout on the printed circuit board has changed. At this time, the components already placed on the printed circuit board may need to be readjusted to achieve the optimal layout strategy. Therefore, this embodiment will update the layout state... Each component included is defined as a component to be optimized. The optimal rotation angle for each component to be optimized is determined sequentially. The component to be optimized is then rotated from its current placement direction by the optimal rotation angle to obtain its preferred placement direction in the current iteration. Once all components to be optimized are placed according to their preferred placement directions, the layout update of the printed circuit board for the current iteration is complete. At this point, the updated layout state is obtained. As the next iteration, i.e. the th The layout state in the next iteration.

[0032] Taking the first iteration as an example, since only one component c is placed, after placing component c in the default orientation, the layout state is updated as follows: At this point, since there is only one component to be optimized (i.e., component c to be placed) on the printed circuit board, after adjusting the placement orientation of the component to be optimized, the layout state is updated to obtain... , Compared to Adjusted The orientation of the components, for example Based on this step, the preferred placement orientation of resistor R is determined to be rotated from the default orientation. ,but It can be understood that for the component c to be placed, its current placement orientation is the default orientation, and for other components already placed on the printed circuit board in the current iteration, their current placement orientation is the preferred placement orientation determined in the previous iteration.

[0033] In this embodiment, the placement orientation of components already placed on the printed circuit board is adjusted to the preferred placement orientation with each iteration to support the backtracking of orientation decisions, thereby avoiding the adverse effects of early orientation decisions on the overall layout quality, and thus continuously approaching the overall optimal solution during the iteration process.

[0034] S104: Output the placement position and orientation of each component in the last iteration as the final layout scheme of the printed circuit board. The set of unplaced components in the last iteration is empty.

[0035] In the embodiment, when the iteration process meets the termination condition, i.e., the set of unplaced components in the current iteration is an empty set, the current iteration is the last iteration, at this time all components are placed on the printed circuit board, the iteration is terminated and the final layout scheme is output.

[0036] It can be understood that the final layout scheme is defined by the layout state updated by the last iteration, which records the coordinates of the final placement position of each component and the final preferred placement direction. The embodiment ensures that the output is a complete and optimized layout scheme through iteration optimization and termination condition judgment, not only meets the physical constraints of component placement, but also through multiple direction and position optimization, realizes high-quality solution under multi-objective trade-off of wiring length, signal integrity, heat dissipation performance and neatness, and the machine readability and structured characteristics of the output result significantly improve the conversion efficiency from design to production, reduce manual intervention and improve the efficiency of full-automatic layout of printed circuit boards.

[0037] In an example embodiment, the process of selecting a to-be-placed component from the set of unplaced components in the current iteration based on the layout state of the printed circuit board in the current iteration includes: taking the layout state of the printed circuit board in the current iteration and the set of unplaced components as node attributes to construct a first root node; creating at least one child node for the first root node based on at least one unplaced component in the set of unplaced components; performing a first search loop operation starting from the first root node to update the selection times of each child node under the first root node; when the execution times of the first search loop operation reach a preset number, sampling in a probability distribution determined based on the selection times of each child node under the first root node to obtain the to-be-placed component.

[0038] For ease of understanding, the process of determining the to-be-placed component in one iteration is described in the embodiment, and the same applies to other iterations.

[0039] In the embodiment, the to-be-placed component can be obtained by the first intelligent agent P. The decision-making process of the first intelligent agent P is as follows: first, taking the layout state of the printed circuit board in the current iteration and the set of unplaced components as node attributes to construct a first root node, the first root node is a node in the search tree as a starting point for searching, which contains initial layout state and set of unplaced components and other information. Thus, the component selection process can fully consider the overall progress and remaining possibilities of the layout process, avoiding the limitations of isolated decision-making. Based on the number of components in the set of unplaced components, a corresponding number of child nodes are created for the first root node, each child node corresponds to an unplaced component. For example, it is assumed that the current is the first iteration (n=1), the layout state ) is an empty board, and the set of unplaced components contains three components: component 1, component 2 and component 3. comprises three elements, i.e. The attribute of the first root node r1 comprises and Three child nodes are created for the first root node, i.e. a first child node v1 corresponding to the selection of a resistor, a second child node v2 corresponding to the selection of a capacitor, and a third child node v3 corresponding to the selection of an inductor. By creating child nodes for the first root node representing different element selection schemes, the selection problem is converted into a structured search space, making the decision process clear, manageable and optimizable.

[0040] The first agent P performs a first search loop operation (e.g. Monte Carlo tree search) starting from the first root node for a preset number of times, each loop comprising at least four stages of selection, expansion, simulation and backtracking. By performing the first search loop operation for a preset number of times, the selection frequency of each selection scheme (child node) is updated, so that the final decision is not dependent on single calculation or random guess, but is based on the statistical evidence accumulated by multiple simulation evaluations, improving the reliability and robustness of the decision.

[0041] When the number of search loop executions reaches the preset number, the probability distribution is calculated based on the access frequency of each child node under the first root node, sampling is performed, and the element to be placed is finally determined. According to the probability distribution formed by the selection frequency of each child node, sampling is performed, which not only tends to select the best-performing (most selected) scheme in history, but also retains a certain randomness to explore other potential preferred options, thereby achieving a good balance between using known good schemes and exploring possibly better schemes.

[0042] For example, assume that the set of elements not yet laid out in the current iteration is [capacitor C, inductor L], and the layout state is a layout of a resistor R already placed. After constructing the first root node, two child nodes are created for it, i.e. a first child node (selecting capacitor C) and a second child node (selecting inductor L). After 10 first search loop operations, the first child node is accessed 6 times and the second child node B is accessed 4 times, the probability of selecting capacitor C is and the probability of selecting inductor L is 0.4. The element to be placed is sampled in the corresponding probability interval.

[0043] The first search loop operation includes: selecting a first optimal node from all child nodes under the first root node according to the selected values of the child nodes under the first root node in the current first search loop operation, and updating the access times of the first root node and the selection times of the child nodes under the first root node; if the first optimal node is a leaf node, determining the placement position of the first optimal node on the printed circuit board through a first preset neural network strategy, placing the un-laid component corresponding to the first optimal node on the placement position corresponding to the first optimal node to obtain a first intermediate layout state; optimizing and adjusting the placement direction of the components in the first intermediate layout state by using a second preset heuristic strategy to obtain a second intermediate layout state; removing the un-laid component corresponding to the first optimal node from the un-laid component set to obtain a new un-laid component set; taking the second intermediate layout state and the new un-laid component set as node attributes, constructing a first intermediate node, and adding the first intermediate node to the child node of the first optimal node; if the new un-laid component set is not empty, creating at least one first intermediate child node for the first intermediate node based on at least one un-laid component in the new un-laid component set; determining the placement position and the placement direction of the un-laid component corresponding to the first intermediate child node on the printed circuit board through the first preset neural network strategy, the first preset heuristic strategy and the second preset heuristic strategy; determining a first intermediate layout based on the placement position and the placement direction of each un-laid component in the un-laid component set in the current iteration, calculating the evaluation value of the first intermediate layout; and updating the selected value of each child node under the first root node by using the evaluation value, so as to enter the next first search loop operation.

[0044] In this embodiment, the strategy of the first intelligent agent P can be formalized as wherein, represents a certain layout state in the current iteration, represents a component set that has not been placed in the current iteration, is a first preset neural network strategy for position decision, is a learnable parameter, is a heuristic strategy for determining the layout order (such as preferentially selecting a component with a large area), is a heuristic strategy for adjusting the direction of the placed component (for example: rotating the component that can improve the optimization target f the most each time until it cannot be further improved).

[0045] The first search loop operation in this embodiment refers to an iterative search process based on a tree structure, and the core steps include selection, expansion, simulation and backtracking. The first first search loop operation is described below, and the same applies to each subsequent first search loop operation.

[0046] The printed circuit board layout method, before selecting the first optimal node from all child nodes under the first root node based on the selection value of each child node under the first root node in the current first search cycle, further includes: if the current first search cycle is the first first search cycle, then the selection value of the child nodes under the first root node is 0; if the current first search cycle is not the first first search cycle, then the selection value of the child nodes under the first root node is the selection value updated based on the evaluation value in the previous first search cycle; the process of selecting the first optimal node from all child nodes under the first root node based on the selection value of each child node under the first root node in the current first search cycle includes: for each child node under the first root node, obtaining the decision value of the child node under the first root node based on the selection value of the child node under the first root node in the current first search cycle and the search reward value; the search reward value is determined based on the number of visits to the first root node that has not been updated in the current first search cycle and the number of selections of the child nodes under the first root node; the child node with the largest decision value is determined as the first optimal node.

[0047] For example, suppose we are currently in the first iteration ( ), map status The board is empty and no component set has been placed. It contains three components, namely Initialize the first root node r1, which contains the initial layout state. (The layout is empty at this point) and a collection of unplaced components. The first search loop begins, selecting the first optimal node based on the selection value of each child node under the first root node r1. Assume the first root node has three child nodes, each representing a different layout decision direction, and each child node corresponds to the first child node of the selected resistor. The second child node corresponding to the selected capacitor The third child node corresponding to the selected inductor Through calculation , and The value of being chosen, from , and Select one child node as the first optimal node.

[0048] Specifically, the first optimal node can be selected based on the first relation, where the first relation is: ; It is the first optimal node. The set of child nodes of the first root node (in the example above, including...) 、 and ), is the selected value of a certain child node vri under the first root node r1, is the search reward value of a certain child node vri under the first root node r1, wherein, , is the exploration reward coefficient, is the number of visits of the first root node r1, is the number of times of selecting a certain child node vri under the first root node r1, that is, the selection number of the child node vri.

[0049] Considering that in the first first search loop operation, the number of visits of r1 is 0, the number of times of selection , the number of times of selection and the number of times of selection are all 0, therefore, the decision value of , the decision value of and the decision value of are equal. Then the first optimal child node can be randomly selected from , and , if is selected, the number of times of selection is incremented by 1, and the number of visits of r1 is also incremented by 1. When the second first search loop operation is performed, the number of visits of r1 is updated by 1 to 1, the number of times of selection is updated to 1, and the number of times of selection is still 0, and the decision values of the child nodes are calculated based on the updated values to select the first optimal child node in the second search loop operation.

[0050] If the first optimal node is a leaf node, that is, a node not including an expansion node, the placement position of the corresponding unplaced element of the first optimal node on the printed circuit board is determined by the first preset neural network strategy , specifically based on the prediction . For example, the neural network model calculates that the element should be placed at the top-left corner of the layout according to the current layout state and element characteristics and the like, and then places the element at the position The first intermediate layout state is obtained.

[0051] Then a second preset heuristic strategy is used to perform an optimal adjustment of the placement direction of the elements in the first intermediate layout state, for example, for the just-placed elements, the heuristic strategy is used to perform a rotation adjustment, the optimal target value is calculated after each rotation, the rotation direction that maximizes the optimal target value is selected, and the process is terminated when the optimal target value cannot be further improved, to obtain a second intermediate layout state.

[0052] The unplaced elements corresponding to the first optimal node are removed from the unplaced element set to obtain a new unplaced element set. The second intermediate layout state and the new unplaced element set are used as node attributes to construct a first intermediate node, and the first intermediate node is added to the child nodes of the first optimal node. If the new unplaced element set is not empty, a first intermediate child node is created for the first intermediate node based on the unplaced elements in the new unplaced element set. The placement position and the placement direction of each unplaced element in the new unplaced element set on the printed circuit board are determined by a first preset neural network strategy , a first preset heuristic strategy and a first preset heuristic strategy , wherein the next first intermediate child node is selected by the first preset heuristic strategy , the placement position of the selected first intermediate child node is determined by , and the placement direction of the selected first intermediate child node is adjusted by the second preset heuristic strategy .

[0053] A first intermediate layout is determined based on the placement position and the placement direction of each unplaced element in the unplaced element set of the current iteration, and an evaluation value of the first intermediate layout is calculated. The evaluation value is used to update the selected value of each child node under the first root node, so as to enter the next first search loop operation.

[0054] As shown in Figure 3 , assuming is the root node (r), the initial layout state in the current iteration can be , the unplaced element set under includes , and the child nodes under correspond to the selected elements , correspond to the selected elements , correspond to the selected elements .Corresponding selection element , Sub-nodes under the selection element Corresponding selection element , The first optimal node selected in the first search loop operation is the first optimal node selected in the first search loop operation, and the decision corresponding to the node is to select and place the element , The corresponding element is removed from the set of unplaced elements to obtain a new set of unplaced elements . The first intermediate node is constructed with the second intermediate layout state and the new set of unplaced elements as node attributes , and the first intermediate node is added to the child nodes of the first root node, and if the first intermediate node is a node that has not been expanded, the first intermediate node is expanded to obtain the sub-nodes of the first intermediate node , and so on.

[0055] The above steps are repeated several times, and each execution of the first search loop operation will select the first optimal node according to the current layout state and the set of unplaced elements, place and adjust the elements, and calculate and update the evaluation value, gradually optimizing the layout of the entire printed circuit board until the preset end condition is met, such as reaching the preset number of iterations or the layout evaluation value reaching a satisfactory level. In this embodiment, the intelligent optimization of printed circuit board layout is realized by combining tree structure search, neural network strategy and heuristic strategy, which can automatically select the optimal element placement order, position and direction, significantly improving the layout efficiency and quality. The iterative optimization process can dynamically update the node value and evaluation result in each search loop, gradually approaching the global optimal solution, effectively reducing manual intervention, improving the automation level, and being suitable for complex and variable actual engineering scenarios.

[0056] As an optional embodiment, if the first root node or the first intermediate node is not expanded, and the depth (distance from the first root node) does not exceed the threshold value (preset hyperparameter), and the set of unplaced elements corresponding to the first root node or the first intermediate node is not empty, the expansion operation of the node is performed.

[0057] In an example embodiment, the process of updating the selected values of the child nodes under the first root node by using the evaluation values comprises: determining the nodes to be updated on the search path of the current first search loop operation; for each node to be updated, obtaining the selected value of the node to be updated after the current first search loop operation based on the evaluation value, the access times of the node to be updated, and the selected value of the node to be updated when the node to be updated is not updated in the current first search loop operation.

[0058] In the embodiment, each pair of nodes to be updated on the search path path is updated in turn, t is the index of the edge in path, and the search path is the sequence of nodes from the root node to the leaf node in a first search loop operation. In the embodiment, each pair of nodes to be updated on the search path path is updated in turn, t is the index of the edge in path, and the search path is the sequence of nodes from the root node to the leaf node in a first search loop operation.

[0059] .

[0060] .

[0061] .

[0062] For example: In the above example, the root node is represented by , the selection of the resistor as the first layout component is represented by , the state after placing the resistor is represented by , the selection of the capacitor as the second layout component is represented by , and the state after placing the capacitor is represented by , which is the leaf node. At this time, the value of t is 0 or 1. Starting from the leaf node, each pair of nodes on the path is updated in turn. The first step is to update , and the second step is to update . In the embodiment, k represents the current number of search loop operations, , which is the first search loop operation, , which is the second search loop operation, , and k represents the last search loop operation, k is a preset number, and the same applies to the other search loop operations.

[0063] In an example embodiment, when the number of executions of the first search loop operation reaches a preset number, the process of sampling from the probability distribution determined based on the selection times of the child nodes under the first root node to obtain the component to be placed comprises: when the number of executions of the first search loop operation reaches a preset number, sampling from the probability distribution obtained after transforming the selection times of the child nodes under the first root node according to the temperature coefficient to obtain the component to be placed.

[0064] ​In this embodiment, when k searches are completed, the sampling is performed from the child nodes of the first root node r1 according to the following distribution: ; wherein, is a temperature coefficient for controlling exploration and exploitation, is the selection number of the currently selected child node vr1 under the first root node r1, is the selection number of each child node of the first root node r1, the element corresponding to the sampled node v is the selected element to be placed.

[0065] In this embodiment, by combining the neural network strategy and the heuristic strategy, the placement position and direction of the element can be quickly determined, which greatly improves the efficiency of the layout and shortens the design cycle of the printed circuit board compared with the traditional pure artificial layout or simple heuristic layout method. The neural network strategy can learn a large amount of layout data, thereby better understanding the mutual relationship between elements and the global characteristics of the layout, and generating a more optimal layout scheme. At the same time, the heuristic strategy also plays an important role in local optimization, such as preferentially laying large elements and fine adjustment of the direction of the element, etc., which further improves the quality of the layout, makes the final layout more compact and reasonable, reduces the connection length between elements, improves the efficiency of signal transmission, and reduces electromagnetic interference, etc.

[0066] In an example embodiment, the process of determining the placement position of the element to be placed on the printed circuit board comprises: determining the placement position of the element to be placed on the printed circuit board by using a first preset neural network strategy, wherein the first preset neural network strategy comprises: representing the layout state of the printed circuit board in the current iteration as a binary image; the pixel value of the pixel position in the binary image represents the occupation state of the pixel position; using an image encoder to extract high-level features of the binary image to obtain a global representation vector; for each pixel position in the binary image, calculating the target function change amount when the element to be placed is placed at the pixel position; obtaining a target change map based on all target function change amounts, dividing the target change map into a plurality of blocks, and each block includes a plurality of pixel positions; encoding each block to obtain a feature vector of the block; based on the correlation between the global representation vector and the feature vector of each block, and the target function change amount corresponding to each pixel position, calculating the probability distribution of the placement position of the element to be placed; and determining the placement position of the element to be placed according to the probability distribution.

[0067] In this embodiment, the first preset neural network strategy is used to predict the placement position of the element to be placed , and the final returned result is: the element and its placement position. ​

[0068] The first preset neural network strategy is described below, The goal is to predict the optimal placement position of component i in the layout of the printed circuit board given the current layout state s and the component i to be placed.

[0069] First, the current layout state s is represented as a binary image img with the same dimensions as the layout space. The pixel value of 0 in the binary image img indicates that the corresponding position is not occupied, and the pixel value of 1 indicates that the corresponding position is occupied by other components. Then, a high-level feature is extracted from the binary image img using an image encoder (such as a residual network ResNet), and a global representation vector of the current layout state s is obtained. .

[0070] The decision-making process is as follows: construct a feature map, and for pixel position , consider placing the center point of component i at this position, calculate the change in the objective function: ; where is the objective function value under the current layout state s, is the objective function value after placing component i at pixel position , and thus a target change map with the same size as the layout can be obtained.

[0071] Divide the target change map into several small blocks of fixed size (i.e. tiles in this embodiment), each block is denoted as p, and each block p contains multiple pixel points. For each block p, flatten it into a vector .

[0072] Calculate the block feature, introduce a learnable feedforward neural network FNN to encode the representation of each block and obtain its feature vector .

[0073] Calculate the position distribution: ; where p is the block containing pixel position , the first half of the formula is the probability of selecting block p, and the second half is the probability of selecting pixel position in block p, is a learnable linear mapping matrix, represents each block in all blocks, is each pixel position in block p.

[0074] By encoding the layout state into a binary image and using a deep encoder to extract global features, the system can understand the overall structural features and constraint relationships of the layout space, providing context information for position decision-making. By calculating the target function change for each pixel position and generating a target change map, the abstract optimization target is converted into a concrete target change map, achieving a direct mapping between the optimization target and the spatial position. Finally, by dividing the target change map into tiles and encoding them separately, and then calculating the correlation with the global features, both the fine gradient information of the local region and the semantic information of the global layout are retained. The final probability distribution not only reflects the immediate benefits of the local position, but also embodies the long-term value of the position in the global layout, thereby balancing the solution accuracy and computational efficiency while ensuring the quality of the layout.

[0075] In an example embodiment, for each to-be-optimized element in the updated layout state, the process of determining the optimal rotation angle of the to-be-optimized element includes: determining a set of unoptimized elements in the updated layout state; when the set of unoptimized elements is empty, outputting a rotation trajectory, the rotation trajectory including the to-be-optimized element selected each time and the optimal rotation angle corresponding to the to-be-optimized element; when the set of unoptimized elements is not empty, selecting an unoptimized element from the set of unoptimized elements as the to-be-optimized element of the current rotation operation, determining the optimal rotation angle of the to-be-optimized element, removing the to-be-optimized element of the current rotation operation from the set of unoptimized elements, and updating the layout state, and repeating the operation of determining the set of unoptimized elements in the updated layout state.

[0076] In this embodiment, the to-be-optimized element refers to an element in the updated layout state after placing the selected element on the printed circuit board in the default direction, whose optimal rotation angle in the current iteration has not been determined. The rotation angle of these elements needs to be determined through the optimization process to achieve better layout results. The set of unoptimized elements is a set containing all to-be-optimized elements. In the optimization process, an element is selected from this set each time for rotation angle optimization until the set of unoptimized elements is empty, indicating that the rotation angles of all elements in the current iteration have been optimized.

[0077] It can be understood that the optimal rotation angle is the most suitable rotation angle calculated for each to-be-optimized element through a certain optimization strategy, which can make the layout state reach the best or better state in terms of certain optimization targets (such as layout compactness, signal integrity, etc.).

[0078] The optimal rotation angle in this embodiment can be obtained based on the second agent R decision. The strategy of the second agent R is formalized as wherein, a layout state in the current iteration. The set of elements for which rotation has not yet been performed in the current iteration. For the neural network strategy used for direction decision, These are learnable parameters.

[0079] The policy output of the second agent R is ;in, exist The number of components already placed on top, This indicates the element selected in the 0th rotation operation. express The optimal rotation angle in the current iteration, and so on.

[0080] The main decision-making process is as follows: S1: If If empty, go to S3. If not empty, proceed to S2. S2: Invoking the sub-decision process: from Select component j and determine its optimal rotation angle. Remove element j from the queue Remove from the middle, and get Update the map state and return to S1; S3: Return to the rotation trajectory .

[0081] In an exemplary embodiment, the process of selecting an unoptimized element from the set of unoptimized elements as the element to be optimized in the current rotation operation includes: constructing a second root node using the layout state corresponding to the current rotation operation and the set of unoptimized elements as node attributes; creating at least one child node for the second root node based on at least one unoptimized element in the set of unoptimized elements; executing a second search loop operation starting from the second root node to update the selection count of each child node under the second root node; and when the number of executions of the second search loop operation reaches a preset number, sampling is performed in the probability distribution determined based on the selection count of each child node under the second root node to obtain the element to be optimized in the current rotation operation.

[0082] It is understandable that the difference between the process of selecting the next element to be optimized from the set of unoptimized elements and the process of selecting the next element to be placed from the set of unlaid elements lies in the second search loop operation and the preset neural network strategy used to select the element to be optimized. As for the selection process, the two are basically the same. Please refer to the process of selecting the next element to be placed from the set of unlaid elements above. It will not be repeated here.

[0083] The second search loop operation includes: selecting a second optimal node from all the child nodes of the second root node according to the selected values of the child nodes of the second root node in the current second search loop operation, updating the access times of the second root node and the selection times of the child nodes of the second root node, and determining the optimal rotation angle of the second optimal node on the printed circuit board through the second preset neural network strategy if the second optimal node is a leaf node, adjusting the placement direction of the unoptimized element corresponding to the second optimal node in the placement position thereof according to the optimal rotation angle of the second optimal node on the printed circuit board, obtaining a third intermediate layout state, removing the unoptimized element corresponding to the second optimal node from the unoptimized element set to obtain a new unoptimized element set, taking the third intermediate layout state and the new unoptimized element set as node attributes, constructing a second intermediate node, adding the second intermediate node to the child node of the second optimal node, creating at least one second intermediate child node for the second intermediate node based on at least one unoptimized element in the new unoptimized element set if the new unoptimized element set is not empty, determining the placement direction of the unoptimized element corresponding to the second intermediate child node on the printed circuit board through the second preset neural network strategy, determining a second intermediate layout based on the placement direction of each unoptimized element in the unoptimized element set corresponding to the current rotation operation, calculating a second evaluation value of the second intermediate layout, and updating the selected values of each child node of the second root node by using the second evaluation value, so as to enter the next second search loop operation.

[0084] In the embodiment, the difference between the second search loop operation and the first search loop operation is that the optimal rotation angle of the element is determined based on the second preset neural network strategy, and other processes are the same as those of the first search loop operation. Therefore, the embodiment will not be described herein.

[0085] In an example embodiment, the process of determining the optimal rotation angle of the element to be optimized comprises: determining the optimal rotation angle of the element to be optimized based on a second preset neural network strategy, wherein the second preset neural network strategy comprises: constructing a first pin set based on all pins of the element to be optimized; for each pin in the first pin set, determining all other pins belonging to the same wire net as the pin, and constructing an associated pin set of the pin; for each pin in the first pin set, constructing a feature vector of the pin, and a feature vector of each associated pin in the associated pin set corresponding to the pin, using an attention mechanism, calculating the attention weight of each associated pin corresponding to the pin based on the feature vector of the pin and the feature vector of each associated pin corresponding to the pin, according to the attention weight, weighting and aggregating the feature vectors of all associated pins corresponding to the pin to obtain the encoding representation of the pin, based on the encoding representation of the pin and the learnable vector corresponding to each candidate rotation angle, calculating the probability that the pin supports each candidate rotation angle; fusing the probabilities of all pins to obtain the final probability distribution of the element to be optimized using each candidate rotation angle; and determining the optimal rotation angle of the element to be optimized according to the final probability distribution.

[0086] The process of determining the optimal rotation angle of the element to be optimized by the second preset neural network strategy will be described below.

[0087] Second preset neural network strategy The goal is to predict the optimal rotation angle o of the element j according to the current layout state s and the target element j, .

[0088] First, the pin feature construction is performed, and the set composed of all pins of the element j is denoted as For any pin , the remaining pins belonging to the same wire net as the pin are defined as the set For each , , the feature vector thereof is constructed as ; wherein, represents the Euclidean distance between and , represents the angle (see ) of relative to the polar coordinate system constructed with Figure 4 as the origin, represents the area of the element to which the pin belongs, represents the type of the element to which the pin belongs.

[0089] In order to unify the representation, the feature vector of the pin q itself is defined as To model the relative relationship between pins, the embodiment introduces an attention mechanism to assign an attention weight to each . Wherein, , , are learnable matrices, for each pin in the set .

[0090] According to the above attention weight, the adjacent pin information of is aggregated to obtain its encoding representation ; the direction probability at the pin level is calculated, and for each candidate rotation angle , a learnable vector is set. The pin adopts the candidate rotation angle o probability: ; wherein, is a learnable matrix, for each candidate rotation angle in O.

[0091] For the element level rotation decision fusion, the decision results of all pins are averaged to obtain the final probability of the element j adopting each candidate rotation angle as follows: .

[0092] In the embodiment, a detailed pin feature vector is first constructed, including the Euclidean distance between pins, relative angle, element area and type information, etc. These rich features enable the model to comprehensively understand the mutual relationship and layout characteristics between pins. By introducing an attention mechanism, the model can dynamically assign weights to each pin, thereby more accurately aggregating the information of adjacent pins to obtain the encoding representation of each pin. This attention-based aggregation method can highlight important pin relationships and avoid the shortcomings of traditional methods that treat all pins equally. Further, by calculating the probability of each candidate rotation angle supported by the pin and fusing the probabilities of all pins, the final probability distribution of the element adopting each candidate rotation angle is obtained, thereby determining the optimal rotation angle. This method not only considers the optimal rotation direction of a single pin, but also considers the overall layout effect of the element, making the rotation angle of the element more consistent with the optimization goal of the overall layout. The embodiment can significantly improve the efficiency and quality of the layout, reduce design time and labor cost, and improve the performance and reliability of the circuit board.

[0093] In an exemplary embodiment, after outputting the placement position and orientation of each component in the last iteration as the final layout scheme of the printed circuit board, the layout method further includes: classifying all components into at least one category based on the electrical connection relationship and / or physical properties of the components; calculating the layout deviation value between the two components in any pair of components belonging to the same category, the layout deviation value including positional deviation and / or rotation angle deviation; and calculating the neatness evaluation index of the final layout scheme based on the layout deviation values ​​between all pairs of components belonging to the same category.

[0094] To encourage good alignment in the layout, this embodiment introduces a neatness reward term to quantify the consistency of elements in position and orientation. Inputs include... The position and rotation angle of all components, as well as component classification labels. Category labels are used to record components. Category. One possible classification method is to divide based on the pin arrangement direction of the core component, grouping components that are on the same side as the core component's pins and have a connection relationship into the same category.

[0095] The reward calculation process is as follows: First, initialize the element pair set, let the initial set be... For all satisfying The component pair, if Then add it to the set. ; Calculate the deviation value for each pair of components, for For each element pair in the equation, the deviation of its position from its angle is defined as follows: The positional deviation is defined as follows: ; Angle deviation is defined as . and This is a hyperparameter used to control the relative weights of position and angle deviations.

[0096] Calculate the neatness reward signal .

[0097] As an optional embodiment, the neural network strategy in the first agent P Neural network policy of R in the agent The joint training process is explained below. The final layout objective function value is used as the global reward to guide the two agents to jointly optimize the layout and rotation strategies.

[0098] For the first intelligent agent P The second agent R The training process is as follows: S11: Initialize parameters, randomly initialize parameters. and S12: Repeat the following process until the maximum number of iterations is reached: S121: Initialize the layout state and set the initial time step. Initialize empty layout Initialize the queue of components to be placed. S122: Place the next element, sample the element to be placed and its position: S123: Update layout and construct the element to be placed. The middle layout after Update the queue of components to be placed: That is, the updated queue of components to be placed. For the queue Remove the component to be placed from the middle. The resulting queue. S124: Call the rotating agent for orientation optimization and invoke the rotation strategy. Adjust the orientation of components on the layout and record their paths: ;in, The rotation angle corresponding to the l-th rotated element. , The rotated layout; S125: Let , S126: If Then return to S122 to place the next component; S127: Record the complete layout trajectory. The trajectory recorded during the entire layout process includes: placement trajectory: Rotation trajectory: S128: Evaluate the benefit of this trajectory based on the final layout results. Calculate the objective function value This value will be used as the global reward signal for reinforcement learning. S128: Parameter update, update as follows ;renew as follows: ,in, and This is the learning rate.

[0099] In summary, the application proposes a PCB layout optimization method based on double agents. Compared with the existing single-agent-based routing algorithm, the application introduces two agents to be responsible for the position and direction decision of components, effectively reducing the action space of each agent, thereby reducing the difficulty of strategy learning, improving the training efficiency and stability. Whenever a component is placed, the application can globally adjust the direction of all placed components in the layout, overcoming the limitation that the direction cannot be modified once determined in traditional layout methods, and significantly improving the global layout quality. Each agent combines heuristic strategy and neural network strategy, with the heuristic strategy used to determine the component processing order and the neural strategy used to determine the position or direction. The heuristic strategy for determining the component processing order can be adaptively optimized with the neural network strategy. The application guides the layout to optimize towards a structured direction by designing a neatness evaluation index, thereby improving the layout aesthetics and engineering readability.

[0100] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be realized by means of software and the necessary general hardware platform, of course, it can also be realized by hardware, but in many cases the former is a better implementation.

[0101] Please refer to Figure 5 The embodiment of the application also provides a layout device of a printed circuit board, comprising: a first determination module 11, configured to select a to-be-placed component from a set of un-laid components in a current iteration based on a layout state of the printed circuit board in the current iteration, and determine a placement position of the to-be-placed component on the printed circuit board; a first layout module 12, configured to place the to-be-placed component on the placement position in a default direction, and update the layout state; a second layout module 13, configured to, for each to-be-optimized component in the updated layout state, determine an optimal rotation angle of the to-be-optimized component, rotate the to-be-optimized component from a current placement direction by the optimal rotation angle to obtain an optimal placement direction, and update the layout state to enter a next iteration; and a layout output module 14, configured to output the placement position and the placement direction of each component in the last iteration as a final layout scheme of the printed circuit board, and the set of un-laid components in the last iteration is empty.

[0102] In an example embodiment, the process of selecting the to-be-placed component from the set of unplaced components in the current iteration based on the layout state of the printed circuit board in the current iteration comprises: constructing a first root node with the layout state of the printed circuit board in the current iteration and the set of unplaced components as node attributes; creating at least one child node for the first root node based on at least one unplaced component in the set of unplaced components; performing a first search loop operation starting from the first root node to update the selection times of each child node under the first root node; when the number of execution times of the first search loop operation reaches a preset number, sampling in a probability distribution determined based on the selection times of each child node under the first root node to obtain the to-be-placed component.

[0103] In an example embodiment, the first search loop operation comprises: selecting a first optimal node from all child nodes under the first root node according to the selected values of each child node under the first root node in the current first search loop operation, and updating the access times of the first root node and the selection times of each child node under the first root node; if the first optimal node is a leaf node, determining the placement position of the first optimal node on the printed circuit board by a first preset neural network strategy, placing the unplaced component corresponding to the first optimal node on the placement position corresponding to the first optimal node to obtain a first intermediate layout state; optimizing and adjusting the placement direction of the components in the first intermediate layout state by a second preset heuristic strategy to obtain a second intermediate layout state; removing the unplaced component corresponding to the first optimal node from the set of unplaced components to obtain a new set of unplaced components; constructing a first intermediate node with the second intermediate layout state and the new set of unplaced components as node attributes, and adding the first intermediate node to the child node of the first optimal node; if the new set of unplaced components is not empty, creating at least one first intermediate child node for the first intermediate node based on at least one unplaced component in the new set of unplaced components; determining the placement position and placement direction of the unplaced component corresponding to the first intermediate child node on the printed circuit board by the first preset neural network strategy, the first preset heuristic strategy and the second preset heuristic strategy; determining a first intermediate layout based on the placement position and placement direction of each unplaced component in the set of unplaced components in the current iteration, and calculating an evaluation value of the first intermediate layout; updating the selected values of each child node under the first root node by the evaluation value so as to enter the next first search loop operation.

[0104] In an example embodiment, the layout device of the printed circuit board is further configured to: if the current first search loop operation is the first first search loop operation, the selected value of each child node under the first root node is 0; if the current first search loop operation is not the first first search loop operation, the selected value of each child node under the first root node is the selected value of each child node under the first root node updated based on the evaluation value in the last first search loop operation; and the process of selecting the first optimal node from all child nodes under the first root node based on the selected value of each child node under the first root node in the current first search loop operation includes: for each child node under the first root node, obtaining a decision value of the child node under the first root node based on the selected value of the child node under the first root node in the current first search loop operation and a search reward value; the search reward value is determined based on the number of visits of the first root node by the child node under the first root node in the current first search loop operation and the number of selections of the child node under the first root node; and determining the child node with the largest decision value as the first optimal node.

[0105] In an example embodiment, the process of updating the selected value of each child node under the first root node based on the evaluation value includes: determining the nodes to be updated on the search path in the current first search loop operation; for each node to be updated, obtaining the selected value of the node to be updated in the current first search loop operation based on the evaluation value, the number of visits of the node to be updated, and the selected value of the node to be updated in the current first search loop operation when the selected value of the node to be updated is not updated.

[0106] In an example embodiment, when the number of executions of the first search loop operation reaches a preset number, the process of sampling the probability distribution based on the number of selections of each child node under the first root node to obtain the component to be placed includes: when the number of executions of the first search loop operation reaches the preset number, sampling each child node under the first root node according to the obtained probability distribution after the number of selections of each child node under the first root node is transformed based on the temperature coefficient to obtain the component to be placed.

[0107] In an example embodiment, the process of determining the placement position of the to-be-placed component on the printed circuit board comprises: determining the placement position of the to-be-placed component on the printed circuit board by using a first preset neural network strategy, wherein the first preset neural network strategy comprises: representing the layout state of the printed circuit board in the current iteration as a binary image; the pixel value of a pixel position in the binary image represents the occupation state of the pixel position; using an image encoder to extract high-level features of the binary image to obtain a global representation vector; for each pixel position in the binary image, calculating the target function change amount when the to-be-placed component is placed at the pixel position; obtaining a target change map based on all target function change amounts, dividing the target change map into a plurality of blocks, and each block comprising a plurality of pixel positions; encoding each block to obtain a feature vector of the block; calculating the probability distribution of the placement position of the to-be-placed component based on the correlation between the global representation vector and the feature vectors of the blocks, and the target function change amount corresponding to each pixel position; and determining the placement position of the to-be-placed component according to the probability distribution.

[0108] In an example embodiment, the process of determining the optimal rotation angle of the to-be-optimized component in the updated layout state comprises: determining a set of unoptimized components in the updated layout state; when the set of unoptimized components is empty, outputting a rotation trajectory, the rotation trajectory comprising the to-be-optimized component selected in each rotation and the optimal rotation angle corresponding to the to-be-optimized component; when the set of unoptimized components is not empty, selecting an unoptimized component from the set of unoptimized components as the to-be-optimized component of the current rotation operation, determining the optimal rotation angle of the to-be-optimized component, removing the to-be-optimized component of the current rotation operation from the set of unoptimized components, and updating the layout state, and repeating the operation of determining the set of unoptimized components in the updated layout state.

[0109] In an example embodiment, the process of selecting an unoptimized component from the set of unoptimized components as the to-be-optimized component of the current rotation operation comprises: taking the layout state corresponding to the current rotation operation and the set of unoptimized components as node attributes to construct a second root node; creating at least one child node for the second root node based on at least one unoptimized component in the set of unoptimized components; performing a second search loop operation starting from the second root node to update the selection times of each child node under the second root node; when the execution times of the second search loop operation reach a preset number, sampling in the probability distribution determined based on the selection times of each child node under the second root node to obtain the to-be-optimized component of the current rotation operation.

[0110] In an example embodiment, the second search loop operation comprises: selecting a second optimal node from all the child nodes under the second root node according to the selected values of the child nodes under the second root node in the current second search loop operation, and updating the access times of the second root node and the selection times of the child nodes under the second root node; if the second optimal node is a leaf node, determining an optimal rotation angle of the second optimal node on the printed circuit board by using the second preset neural network strategy, adjusting the placement direction of the unoptimized component corresponding to the second optimal node at the placement position thereof according to the optimal rotation angle of the second optimal node on the printed circuit board, and obtaining a third intermediate layout state; removing the unoptimized component corresponding to the second optimal node from the unoptimized component set to obtain a new unoptimized component set; constructing a second intermediate node by taking the third intermediate layout state and the new unoptimized component set as node attributes, and adding the second intermediate node to the child node of the second optimal node; if the new unoptimized component set is not empty, creating at least one second intermediate child node for the second intermediate node based on at least one unoptimized component in the new unoptimized component set; determining the placement direction of the unoptimized component corresponding to the second intermediate child node on the printed circuit board by using the second preset neural network strategy; determining a second intermediate layout based on the placement direction of each unoptimized component in the unoptimized component set corresponding to the current rotation operation, and calculating a second evaluation value of the second intermediate layout; and updating the selected values of each child node under the second root node by using the second evaluation value, so as to enter the next second search loop operation.

[0111] In an example embodiment, the process of determining the optimal rotation angle of the unoptimized component comprises: determining the optimal rotation angle of the unoptimized component based on a second preset neural network strategy, wherein the second preset neural network strategy comprises: constructing a first pin set based on all the pins of the unoptimized component; for each pin in the first pin set, determining all the other pins belonging to the same net as the pin, and constructing an associated pin set of the pin; for each pin in the first pin set, constructing a feature vector of the pin and a feature vector of each associated pin in the associated pin set corresponding to the pin, calculating the attention weight of each associated pin corresponding to the pin based on the feature vector of the pin and the feature vector of each associated pin corresponding to the pin by using an attention mechanism, and obtaining the encoding representation of the pin by weighting and aggregating the feature vectors of all the associated pins corresponding to the pin according to the attention weight; and calculating the probability that each candidate rotation angle is supported by the pin based on the encoding representation of the pin and the learnable vector corresponding to each candidate rotation angle; fusing the probabilities of all the pins to obtain the final probability distribution of each candidate rotation angle adopted by the unoptimized component; and determining the optimal rotation angle of the unoptimized component according to the final probability distribution.

[0112] In an example embodiment, the layout device is further configured to: divide all the components into at least one category based on the electrical connection relationship and / or the physical attribute of the components; calculate a layout deviation value between any two components in a component pair belonging to the same category, the layout deviation value including a position deviation amount and / or a rotation angle deviation amount; and calculate an evaluation index of the neatness of the final layout scheme based on the layout deviation values between all the component pairs belonging to the same category.

[0113] The features of the embodiments of the layout device of the printed circuit board can be referred to the related descriptions of the embodiments of the layout method of the printed circuit board, which will not be repeated here.

[0114] The embodiments of the present application also provide an electronic device, including a memory and a processor, the memory stores a computer program, and the processor is configured to run the computer program to perform the steps in any of the above embodiments of the layout method of the printed circuit board.

[0115] The embodiments of the present application also provide a computer readable storage medium, which stores a computer program, wherein the computer program is configured to perform the steps in any of the above embodiments of the layout method of the printed circuit board when running.

[0116] In an example embodiment, the above computer readable storage medium can include, but is not limited to, a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store computer programs.

[0117] The embodiments of the present application also provide a computer program product, which includes a computer program, and the computer program is executed by a processor to implement the steps in any of the above embodiments of the layout method of the printed circuit board.

[0118] The embodiments of the present application also provide another computer program product, which includes a non-volatile computer readable storage medium, and the non-volatile computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the steps in any of the above embodiments of the layout method of the printed circuit board.

[0119] Those skilled in the art will further realize that the mere concepts, teachings, and embodiments described herein are merely meant to provide an enabling description of the claimed application. Accordingly, modifications and / or additions, other than those explicitly described herein, can be obvious to those skilled in the art in the light of this disclosure. The claimed application is intended to embrace all such modifications and / or additions.

[0120] The layout method, product, device and readable storage medium of the printed circuit board are described in detail above. The principles and implementation manners of the present application are described by applying specific examples in the present application. The above description of the embodiments is only used to help understand the method of the present application and its core idea. It should be pointed out that, for those skilled in the art, without departing from the principles of the present application, some improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A method of placing a printed circuit board, characterized by, The method comprises the following steps: selecting a to-be-placed component from a set of unplaced components in a current iteration based on a layout state of a printed circuit board in the current iteration, and determining a placement position of the to-be-placed component on the printed circuit board; placing the to-be-placed component in the placement position in a default direction, and updating the layout state; for each to-be-optimized component in the updated layout state, determining an optimal rotation angle of the to-be-optimized component, rotating the to-be-optimized component from a current placement direction by the optimal rotation angle to obtain a preferred placement direction, updating the layout state, and entering a next iteration; outputting the placement position and the placement direction of each component in the last iteration as a final layout scheme of the printed circuit board, wherein the set of unplaced components in the last iteration is empty; The process of determining the optimal rotation angle of the to-be-optimized component comprises: determining the optimal rotation angle of the to-be-optimized component based on a second preset neural network strategy, wherein the second preset neural network strategy comprises: constructing a first pin set based on all pins of the to-be-optimized component; for each pin in the first pin set, determining all other pins belonging to the same wire net as the pin, and constructing an associated pin set of the pin; for each pin in the first pin set, constructing a feature vector of the pin and a feature vector of each associated pin in the associated pin set corresponding to the pin, calculating an attention weight of each associated pin corresponding to the pin based on the feature vector of the pin and the feature vector of each associated pin corresponding to the pin by using an attention mechanism, weighting and aggregating the feature vectors of all associated pins corresponding to the pin according to the attention weight to obtain an encoding representation of the pin, and calculating a probability that the pin supports each candidate rotation angle based on the encoding representation of the pin and a learnable vector corresponding to each candidate rotation angle; fusing the probabilities of all pins to obtain a final probability distribution of the to-be-optimized component adopting each candidate rotation angle; and determining the optimal rotation angle of the to-be-optimized component according to the final probability distribution.

2. The layout method of a printed circuit board according to claim 1, characterized by, The process of selecting a to-be-placed component from a set of unplaced components in a current iteration based on a layout state of a printed circuit board in the current iteration comprises: constructing a first root node based on the layout state and the set of unplaced components of the printed circuit board in the current iteration; creating at least one child node for the first root node based on at least one unplaced component in the set of unplaced components; performing a first search loop operation starting from the first root node to update the selection times of each child node under the first root node; when the execution times of the first search loop operation reach a preset number, sampling in a probability distribution determined based on the selection times of each child node under the first root node to obtain a to-be-placed component.

3. The layout method of a printed circuit board according to claim 2, wherein, The first search loop operation comprises: selecting a first optimal node from all the child nodes under the first root node according to the selected values of each child node under the first root node in the current first search loop operation, and updating the access times of the first root node and the selection times of each child node under the first root node; if the first optimal node is a leaf node, determining a placement position of the first optimal node on the printed circuit board by using a first preset neural network strategy, placing an unplaced component corresponding to the first optimal node on the placement position corresponding to the first optimal node, and obtaining a first intermediate layout state; optimizing and adjusting the placement direction of the components in the first intermediate layout state by using a second preset heuristic strategy, and obtaining a second intermediate layout state; eliminating the unplaced component corresponding to the first optimal node from the unplaced component set, and obtaining a new unplaced component set; taking the second intermediate layout state and the new unplaced component set as node attributes, constructing a first intermediate node, and adding the first intermediate node to the child node of the first optimal node; if the new unplaced component set is not empty, creating at least one first intermediate child node for the first intermediate node based on at least one unplaced component in the new unplaced component set; determining the placement position and the placement direction of the unplaced component corresponding to the first intermediate child node on the printed circuit board by using the first preset neural network strategy, the first preset heuristic strategy and the second preset heuristic strategy; determining a first intermediate layout based on the placement position and the placement direction of each unplaced component in the unplaced component set in the current iteration, and calculating an evaluation value of the first intermediate layout; updating the selected values of each child node under the first root node by using the evaluation value, so as to enter the next first search loop operation.

4. The layout method of a printed circuit board according to claim 3, wherein Before selecting the first optimal node from all the child nodes under the first root node according to the selected values of each child node under the first root node in the current first search loop operation, the layout method of the printed circuit board further comprises: if the current first search loop operation is the first first search loop operation, the selected value of the child node under the first root node is 0; if the current first search loop operation is not the first first search loop operation, the selected value of the child node under the first root node is the selected value updated based on the evaluation value in the last first search loop operation; the process of selecting the first optimal node from all the child nodes under the first root node according to the selected values of each child node under the first root node in the current first search loop operation comprises: for each child node under the first root node, obtaining a decision value of the child node under the first root node based on the selected value of the child node under the first root node in the current first search loop operation and a search reward value; the search reward value is determined based on the access times of the first root node which is not updated in the current first search loop operation and the selection times of the child node under the first root node; Determine the sub-node with the maximum decision value as a first optimal node.

5. The layout method of a printed circuit board according to claim 3, wherein, The process of updating the selected values of the sub-nodes under the first root node using the evaluation values comprises: Determine the nodes to be updated on the search path of the current first search loop operation; For each of the nodes to be updated, obtain the selected value of the node to be updated after the current first search loop operation based on the evaluation value, the number of visits of the node to be updated, and the selected value of the node to be updated when the node to be updated is not updated in the current first search loop operation.

6. The printed circuit board layout method according to claim 2, wherein, When the number of executions of the first search loop operation reaches a preset number, sample in the probability distribution determined based on the number of selections of the sub-nodes under the first root node to obtain the component to be placed. When the number of executions of the first search loop operation reaches a preset number, sample in the probability distribution obtained after the number of selections of the sub-nodes under the first root node is transformed according to the temperature coefficient to obtain the component to be placed.

7. The printed circuit board layout method according to Claim 1, characterized by, The process of determining the placement position of the component to be placed on the printed circuit board comprises: Determine the placement position of the component to be placed on the printed circuit board using a first preset neural network strategy, wherein the first preset neural network strategy comprises: Represent the layout state of the printed circuit board in the current iteration as a binary image; the pixel value of a pixel position in the binary image represents the occupation state of the pixel position; Extract high-level features of the binary image using an image encoder to obtain a global representation vector; For each pixel position in the binary image, calculate the change amount of the objective function when the component to be placed is placed at the pixel position; Based on all the change amounts of the objective function, obtain a target change map, and divide the target change map into a plurality of blocks, each of which comprises a plurality of pixel positions; Encode each of the blocks to obtain a feature vector of the block; Based on the correlation between the global representation vector and the feature vectors of the blocks, and the change amount of the objective function corresponding to each pixel position, calculate the probability distribution of the placement position of the component to be placed; Determine the placement position of the component to be placed according to the probability distribution.

8. The printed circuit board layout method according to Claim 1, characterized by, The process of determining the optimal rotation angle of each of the components to be optimized in the updated layout state comprises: Determine the set of unoptimized components in the updated layout state; When the set of unoptimized components is empty, output a rotation trajectory, which comprises the component to be optimized selected each time and the optimal rotation angle corresponding to the component to be optimized; When the set of unoptimized components is not empty, select an unoptimized component from the set of unoptimized components as the component to be optimized in the current rotation operation, determine the optimal rotation angle of the component to be optimized, remove the component to be optimized in the current rotation operation from the set of unoptimized components, and update the layout state, and repeat the operation of determining the set of unoptimized components in the updated layout state.

9. The layout method of a printed circuit board according to claim 8, wherein, The process of selecting an unoptimized element from the unoptimized element set as the to-be-optimized element of the current rotation operation includes: constructing a second root node with the layout state corresponding to the current rotation operation and the unoptimized element set as node attributes; creating at least one child node for the second root node based on at least one unoptimized element in the unoptimized element set; performing a second search loop operation starting from the second root node to update the selection times of each child node under the second root node; when the execution times of the second search loop operation reach a preset number, sampling in a probability distribution determined based on the selection times of each child node under the second root node to obtain the to-be-optimized element of the current rotation operation.

10. The layout method of a printed circuit board according to claim 9, wherein, The second search loop operation includes: selecting a second optimal node from all child nodes under the second root node according to the selection values of each child node under the second root node in the current second search loop operation, and updating the access times of the second root node and the selection times of each child node under the second root node; if the second optimal node is a leaf node, determining an optimal rotation angle of the second optimal node on the printed circuit board through a second preset neural network strategy, adjusting the placement direction of the unoptimized element corresponding to the second optimal node in its placement position according to the optimal rotation angle of the second optimal node on the printed circuit board to obtain a third intermediate layout state; eliminating the unoptimized element corresponding to the second optimal node from the unoptimized element set to obtain a new unoptimized element set; constructing a second intermediate node with the third intermediate layout state and the new unoptimized element set as node attributes, and adding the second intermediate node to the child node of the second optimal node; if the new unoptimized element set is not empty, creating at least one second intermediate child node for the second intermediate node based on at least one unoptimized element in the new unoptimized element set; determining the placement direction of the unoptimized element corresponding to the second intermediate child node on the printed circuit board through the second preset neural network strategy; determining a second intermediate layout based on the placement direction of each unoptimized element in the unoptimized element set corresponding to the current rotation operation, and calculating a second evaluation value of the second intermediate layout; updating the selection values of each child node under the second root node using the second evaluation value so as to enter the next second search loop operation.

11. The method of placing a printed circuit board according to any one of claims 1-10, wherein, After outputting the placement positions and placement directions of each element in the last iteration as the final layout scheme of the printed circuit board, the layout method further includes: dividing all the elements into at least one category based on the electrical connection relationship and / or physical attributes of the elements; calculating a layout deviation value between two elements in an element pair composed of any two elements belonging to the same category, the layout deviation value including a position deviation amount and / or a rotation angle deviation amount; calculating a neatness evaluation index of the final layout scheme based on the layout deviation values between element pairs belonging to the same category.

12. A computer program product comprising computer programs / instructions, characterized in that, The computer program / instruction, when executed by a processor, implements the steps of the layout method of the printed circuit board according to any one of claims 1-11.

13. An electronic device, comprising: Comprise: a memory for storing a computer program; a processor for executing the computer program to implement the steps of the layout method of the printed circuit board according to any one of claims 1-11.

14. A computer-readable storage medium, characterized in that, The computer program is stored on the computer readable storage medium, and when executed by a processor, implements the steps of the layout method of the printed circuit board according to any one of claims 1-11.

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