An etching method and semiconductor processing apparatus

Abstract

The application provides an etching method and a semiconductor process equipment, and relates to the technical field of semiconductors. The etching method is designed to solve the problem that, after etching a metal hard mask layer, rework processing is needed due to overlay error in photolithography, the critical dimension of a weak point region is rapidly reduced during the rework processing, and the yield is reduced. The etching method comprises the following steps: providing a semiconductor device, wherein the semiconductor device comprises a photoresist layer, an antireflection layer, a first dielectric layer, a metal hard mask layer, a second dielectric layer and an ultra-low dielectric constant material layer which are sequentially stacked; etching the antireflection layer with the photoresist layer as a mask to expose the first dielectric layer; and a deposition step, wherein the process gas used in the deposition step comprises methane. The application increases the critical dimension of the bottom of the weak point region, thereby expanding the process window after rework processing, so as to ensure that no deviation occurs when etching a vertical interconnection channel subsequently, thereby improving the yield after rework processing.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to an etching method and semiconductor process equipment. Background Technology

[0002] As chip integration density increases, the critical dimensions of semiconductor devices are shrinking, and the number of metal layers is constantly increasing. This leads to increased resistance in metal interconnects, parasitic capacitance between metal interconnects, and parasitic capacitance between metal interconnect layers, resulting in increased signal delay time. To improve chip speed, low-resistivity copper and ultra-low dielectric constant materials are being used for back-end metal interconnects. Since photoresists have low selectivity and poor etching directionality for these ultra-low dielectric constant materials, hard metal masks are chosen as the mask material, and dry etching processes are employed to improve the accuracy of pattern transfer.

[0003] Specifically, a second dielectric layer, a metal hard mask layer, a first dielectric layer, an anti-reflection layer, and a photoresist layer are sequentially disposed on an ultra-low dielectric constant material layer. First, the anti-reflection layer and the second dielectric layer are etched downwards using the photoresist layer as a mask, transferring the pattern to the metal hard mask layer. Then, the metal hard mask layer is used as a mask to etch downwards again to obtain a semiconductor device with the desired pattern. However, if overlay errors occur during photolithography after etching the metal hard mask layer, rework is required. The rework process may modify the sidewalls of the metal hard mask layer, causing its angle to change and creating protrusions. Since the weak point region is ring-shaped, protrusions are more likely to be generated under plasma bombardment, rapidly reducing critical dimensions and hindering subsequent etching of vertical interconnect channels, leading to a decrease in yield. Summary of the Invention

[0004] The first objective of this invention is to provide an etching method to solve the technical problem that after etching a metal hard mask layer, rework is required due to overlay errors in photolithography, and the critical dimensions of the weak point area are rapidly reduced during the rework process, resulting in a decrease in yield.

[0005] The etching method provided by this invention includes:

[0006] A semiconductor device is provided, the semiconductor device comprising a photoresist layer, an anti-reflection layer, a first dielectric layer, a metal hard mask layer, a second dielectric layer and an ultra-low dielectric constant material layer stacked sequentially;

[0007] The anti-reflection layer etching step involves etching the anti-reflection layer using the photoresist layer as a mask, thereby exposing the first dielectric layer; and

[0008] The deposition step, wherein the process gas used in the deposition step includes methane.

[0009] Furthermore, in the deposition step, the process pressure is 3–10 mtorr; the upper electrode power is 500–700 W, the lower electrode power is 0 V, the current ratio of the upper electrode to the lower electrode is 0.4–0.6; the methane flow rate is 10–30 sccm; the process gas used in the deposition step also includes argon, with an argon flow rate of 100–150 sccm; and the process time is 6–10 s.

[0010] Furthermore, prior to the antireflective layer etching step, a photoresist residue removal step is included; wherein the process pressure is 3–10 mtorr; the upper electrode power is 200–500 W, the lower electrode power is 10–30 V, and the current ratio of the upper electrode to the lower electrode is 0.55–0.7; the process gases include oxygen and argon, with an oxygen flow rate of 5–10 sccm and an argon flow rate of 50–100 sccm; and the process time is 5–7 s.

[0011] Furthermore, in the anti-reflection layer etching step, the process pressure is 3–10 mtorr; the upper electrode power is 500–700 W, the lower electrode power is 30–60 V, and the current ratio of the upper electrode to the lower electrode is 0.4–0.6; the process gases include oxygen, argon, and nitrogen, with an oxygen flow rate of 20–40 sccm, an argon flow rate of 30–60 sccm, and a nitrogen flow rate of 30–60 sccm; the process time is 15–50 s.

[0012] Furthermore, following the deposition step, the process further includes: a first dielectric layer etching step; wherein the process pressure is 3–10 mtorr; the upper electrode power is 300–600 W, the lower electrode power is 100–160 V, and the current ratio of the upper electrode to the lower electrode is 0.4–0.6; the process gases include carbon tetrafluoride and trifluoromethane, the flow rate of carbon tetrafluoride is 40–80 sccm, and the flow rate of trifluoromethane is 20–40 sccm; the process time is 6–10 s.

[0013] Furthermore, after the first dielectric layer etching step, the process further includes a metal hard mask layer etching step; wherein the process pressure is 10–20 mtorr; the upper electrode power is 500–700 W, the lower electrode power is 60–100 V, and the current ratio of the upper electrode to the lower electrode is 0.4–0.6; the process gases include chlorine, methane, and argon, with a chlorine flow rate of 50–100 sccm, a methane flow rate of 30–50 sccm, and an argon flow rate of 100–200 sccm; and the process time is 5–8 s.

[0014] Furthermore, after the metal hard mask layer etching step, the process further includes: a first over-etching step to completely expose the second dielectric layer; the process time of the first over-etching step is 15% to 25% of the process time of the metal hard mask layer etching step.

[0015] Furthermore, after the etching step of the metal hard mask layer, the process further includes: a second over-etching step to partially etch the second dielectric layer; wherein the process pressure is 5-10 mtorr; the upper electrode power is 500-700 W, the lower electrode power is 60-100 V, and the current ratio of the upper electrode to the lower electrode is 0.4-0.6; the process gases include silicon tetrachloride, methane, nitrogen trifluoride, and chlorine, the flow rate of silicon tetrachloride is 80-150 sccm, the flow rate of methane is 10-20 sccm, the flow rate of nitrogen trifluoride is 100-300 sccm, and the flow rate of chlorine is 50-100 sccm; the process time is 6-10 s.

[0016] Furthermore, after the etching step, the process further includes a residual material removal step for removing the remaining photoresist layer and the remaining antireflective layer; wherein the process pressure is 10–20 mtorr; the upper electrode power is 1000–1500 W, the lower electrode power is 80–150 V, and the current ratio of the upper electrode to the lower electrode is 0.4–0.6; the process gases include oxygen and nitrogen, with an oxygen flow rate of 100–300 sccm and a nitrogen flow rate of 30–80 sccm; and the process time is 30–50 s.

[0017] The beneficial effects of the etching method of this invention are:

[0018] In this etching method, a deposition step is added after the anti-reflection layer etching step, using methane as the process gas. The methane decomposes into carbon and hydrogen radicals in a plasma environment, forming an amorphous carbon film. Because the weak point regions are relatively sparse while the conventional point regions are relatively dense, the amorphous carbon film formed is more easily deposited on top of the weak point regions, increasing the thickness of the anti-reflection layer and causing an angle tilt. During the etching of the semiconductor device, the vertical incident direction of the plasma produces a shadowing effect due to the tilted sidewalls, causing the plasma to bombard the bottom of the trench more easily than the sidewalls. This increases the lateral etching rate, thereby increasing the critical dimension at the bottom of the trench, i.e., increasing the critical dimension at the bottom of the weak point region. This expands the process window after rework, ensuring no deviation occurs during subsequent etching of vertical interconnect channels, thus improving the yield after rework.

[0019] The second objective of this invention is to provide a semiconductor process apparatus to solve the technical problem that after etching the metal hard mask layer, rework is required due to overlay errors in photolithography, which leads to a rapid reduction in critical dimensions and a decrease in yield during the rework process.

[0020] The semiconductor process equipment provided by the present invention includes a process chamber, an inlet assembly, an upper electrode assembly, a lower electrode assembly, and a controller. The controller includes at least one processor and at least one memory. The memory stores a computer program, which, when executed by the processor, implements the etching method described above.

[0021] The beneficial effects of the semiconductor process equipment of this invention are:

[0022] This semiconductor process equipment can implement the above etching method, and accordingly, it has all the advantages of the above etching method, which will not be elaborated here. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0024] Figure 1 This is a cross-sectional view of a semiconductor device manufactured according to an etching method provided by related technology at a conventional point location, wherein (a) is a schematic diagram of the initial state of the semiconductor device; (b) is a schematic diagram after etching the anti-reflection layer; (d) is a schematic diagram after etching the first dielectric layer; (e) is a schematic diagram after etching the metal hard mask layer; and (f) is a schematic diagram after partially etching the second dielectric layer. The dimensions in each figure represent the bottom critical dimensions of the trenches obtained by etching at the conventional point location.

[0025] Figure 2 This is a cross-sectional view of a semiconductor device manufactured according to an etching method provided by related technology at a weak point, wherein (a) is a schematic diagram of the initial state of the semiconductor device; (b) is a schematic diagram after etching the anti-reflection layer; (d) is a schematic diagram after etching the first dielectric layer; (e) is a schematic diagram after etching the metal hard mask layer; and (f) is a schematic diagram after partially etching the second dielectric layer. The dimensions in each figure represent the bottom critical dimensions of the trenches obtained by etching at the weak point.

[0026] Figure 3 A flowchart of the etching method provided in an embodiment of the present invention;

[0027] Figure 4 This is a microscopic schematic diagram of a semiconductor device under an electron microscope, where (a) represents a typical point and (b) represents a weak point.

[0028] Figure 5The figures are cross-sectional views of a semiconductor device manufactured using the etching method provided by the present invention at a conventional point location, wherein (a) is a schematic diagram of the initial state of the semiconductor device; (b) is a schematic diagram after etching the anti-reflection layer; (c) is a schematic diagram after methane deposition; (d) is a schematic diagram after etching the first dielectric layer; (e) is a schematic diagram after etching the metal hard mask layer; and (f) is a schematic diagram after partial etching of the second dielectric layer. The dimensions in each figure represent the bottom critical dimensions of the trenches obtained by etching at the conventional point location.

[0029] Figure 6 The figures show cross-sectional views of a semiconductor device manufactured using the etching method provided by the present invention at a weak point location, wherein (a) is a schematic diagram of the initial state of the semiconductor device; (b) is a schematic diagram after etching the anti-reflection layer; (c) is a schematic diagram after methane deposition; (d) is a schematic diagram after etching the first dielectric layer; (e) is a schematic diagram after etching the metal hard mask layer; and (f) is a schematic diagram after partial etching of the second dielectric layer. The dimensions in each figure represent the critical bottom dimensions of the trenches obtained by etching the weak point location.

[0030] Figure 7 This diagram illustrates the yield of the metal hard mask layer after etching, where (a) indicates no rework; (b) indicates no methane deposition and rework; and (c) indicates methane deposition and rework.

[0031] Figure 8 A flowchart of another etching method provided in an embodiment of the present invention;

[0032] Figure 9 This is a schematic diagram of the structure of a semiconductor process equipment provided in an embodiment of the present invention.

[0033] Explanation of reference numerals in the attached figures:

[0034] 101' - Photoresist layer; 102' - Anti-reflective layer; 103' - First dielectric layer; 104' - Metal hard mask layer; 105' - Second dielectric layer; 106' - Ultra-low dielectric material layer; 107' - Third dielectric layer; 108' - Etching stop layer;

[0035] 101-Photoresist layer; 102-Antireflective layer; 103-First dielectric layer; 104-Metal hard mask layer; 105-Second dielectric layer; 106-Ultra-low dielectric constant material layer; 107-Third dielectric layer; 108-Etching stop layer;

[0036] 201 - First carbon-containing sacrificial layer; 202 - Second carbon-containing sacrificial layer;

[0037] 100 - Plasma; 200 - Semiconductor process equipment; 20 - Process chamber; 20A - Inlet assembly; 20B - Upper electrode assembly; 20C - Lower electrode assembly; 20D - Evacuation assembly;

[0038] 21-RF coil; 22-Wafer carrier; 23-Upper RF power supply; 24-Lower RF power supply; 25-Upper matching unit; 26-Lower matching unit. Detailed Implementation

[0039] To improve the accuracy of image transfer, hard metal masks are currently used as the mask material. Specifically, such as... Figure 1 (a) and Figure 2 As shown in (a), the semiconductor device includes a photoresist layer 101', an anti-reflection layer 102', a first dielectric layer 103', a metal hard mask layer 104', a second dielectric layer 105', an ultra-low dielectric constant material layer 106', a third dielectric layer 107', and an etch stop layer 108' stacked sequentially; the critical dimension of the trench bottom at a conventional point is 50 nm, and the critical dimension of the trench bottom at a weak point is 225 nm.

[0040] like Figure 1 (b) and Figure 2 As shown in (b), after the anti-reflection layer 102' is etched, the photoresist forming the photoresist layer 101' is relatively soft, and its top will become rounded after being bombarded by plasma. As the etching process proceeds, the rounded corner shape of the top of the photoresist layer 101' will be transferred downward to the anti-reflection layer 102', causing the sidewall of the anti-reflection layer 102' to have an inclined shape. At this time, the critical dimension of the bottom of the trench at the conventional point becomes 40nm, and the critical dimension of the bottom of the trench at the weak point becomes 230nm.

[0041] like Figure 1 (d) and Figure 2 As shown in (d), after the etching step of the first dielectric layer 103', the process window expands. At this time, the critical dimension of the trench bottom at the regular point becomes 46nm, and the critical dimension of the trench bottom at the weak point becomes 232nm.

[0042] like Figure 1 (e) and Figure 2 As shown in (e), after the etching step of the metal hard mask layer 104', the critical dimension of the trench bottom at the regular point becomes 47nm, and the critical dimension of the trench bottom at the weak point is 232nm.

[0043] like Figure 1 (f) and Figure 2 As shown in (f), in order to ensure that the metal hard mask layer 104' is fully opened, the etching step continues. At this time, the second dielectric layer 105' is partially etched, the critical dimension of the trench bottom at the regular point becomes 54nm, and the critical dimension of the trench bottom at the weak point becomes 235nm.

[0044] After the above etching process, the critical dimension at the bottom of the trench at the weak point increases only slightly. In subsequent rework, the protrusion caused by the modification of the sidewall of the metal hard mask layer 104' will reduce the critical dimension at the bottom of the trench at the weak point, thus hindering the etching of the vertical interconnect channel and resulting in a decrease in yield.

[0045] Therefore, the purpose of this invention is to provide an etching method and semiconductor process equipment to solve the technical problem that after etching the metal hard mask layer, rework is required due to overlay errors in photolithography, and the critical dimensions of the weak point area are rapidly reduced during the rework process, resulting in a decrease in yield.

[0046] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0047] like Figure 3 As shown, this embodiment provides an etching method, including:

[0048] Step S100: Provide a semiconductor device, such as Figure 5 (a) and Figure 6 As shown in (a), the semiconductor device includes a photoresist layer 101, an anti-reflection layer 102, a first dielectric layer 103, a metal hard mask layer 104, a second dielectric layer 105, and an ultra-low dielectric constant material layer 106, which are stacked sequentially.

[0049] In the aforementioned semiconductor device, the metal hard mask layer 104 can be made of titanium nitride, and a first dielectric layer 103 is disposed on top of it, which can protect the metal hard mask layer 104 from the top and allow for rework without damaging the underlying film layer if etching is incomplete. Simultaneously, a second dielectric layer 105 is disposed at the bottom of the metal hard mask layer 104, which can isolate the metal hard mask layer 104 from the underlying device structure, preventing current short circuits or signal interference. An anti-reflection layer 102 is located on top of the first dielectric layer 103, used to reduce light reflection during photolithography, suppress interference between incident and reflected light to prevent standing waves, and improve light transmission efficiency. A photoresist layer 101 is located on top of the anti-reflection layer 102, and is formed into line patterns from a relatively soft photoresist through photolithography processes such as development and fixing.

[0050] Please continue to refer to Figure 5 (a) and Figure 6In (a), the semiconductor device further includes a third dielectric layer 107 located at the bottom of the ultra-low dielectric constant material layer 106 and an etch stop layer 108 located at the bottom of the third dielectric layer 107. The third dielectric layer 107 can isolate the ultra-low dielectric constant material layer 106 at the bottom. The etch stop layer 108 can precisely control the end point of the etching to prevent over-etching or under-etching, so as to ensure the geometric accuracy of the device.

[0051] Typically, the critical dimensions of semiconductor devices after etching include conventional point critical dimensions and weak point critical dimensions, such as... Figure 4 As shown in (a), the critical dimension of a conventional point refers to the design target dimension of the structure after ideal etching. It usually corresponds to the graphic size of a region with uniform density in the microscopic image, reflecting the process limit capability. Its detection location is mostly a region with uniform graphic density and stable etching conditions; such as Figure 4 As shown in (b), the critical dimension of the weak point refers to the area that is prone to dimensional deviation after etching due to process fluctuations or design sensitivity issues.

[0052] Please continue to refer to Figure 5 (a) and Figure 6 In (a), under the initial state, the critical dimension of the trench bottom at the normal point is 50 nm, and the critical dimension of the trench bottom at the weak point is 225 nm.

[0053] Step S300: As Figure 5 (b) and Figure 6 As shown in (b), in the anti-reflection layer 102 etching step, the anti-reflection layer 102 is etched using the photoresist layer 101 as a mask, and the first dielectric layer 103 is exposed.

[0054] In this step, the upper surface of the first dielectric layer 103 is used as the etching stop surface. When the longitudinal etching contacts the first dielectric layer 103, the longitudinal etching stops, and the first dielectric layer 103 is exposed. After this anti-reflection layer 102 etching step, the photoresist layer 101 is at least partially consumed, and the rounded corners of the photoresist layer 101 are transferred to the anti-reflection layer 102, causing the sidewalls of the anti-reflection layer 102 to have an inclined morphology. The critical dimension of the trench bottom at the conventional point becomes 40nm, and the critical dimension of the trench bottom at the weak point becomes 230nm.

[0055] In the 102 etching step of the anti-reflective layer, the process pressure is 3–10 mtorr; the upper electrode power is 500–700 W, the lower electrode power is 30–60 V, and the current ratio of the upper electrode to the lower electrode is 0.4–0.6; the process gases include oxygen, argon, and nitrogen, with an oxygen flow rate of 20–40 sccm, an argon flow rate of 30–60 sccm, and a nitrogen flow rate of 30–60 sccm; the process time is 15–50 s.

[0056] By selecting a lower process pressure in the etching step of the anti-reflection layer 102, the mean free path of gas molecules can be increased, energy dissipation can be reduced, and the generated high-energy ions can bombard the anti-reflection layer 102 with higher energy, thereby improving etching efficiency.

[0057] By setting the upper electrode power to 500–700 W in the etching step of the antireflective layer 102, the plasma density can be significantly increased to more efficiently decompose the etching gas, thereby further improving the etching efficiency of the antireflective layer 102. By setting the lower electrode power to 30–60 V, the plasma energy can be prevented from being too high, avoiding excessive damage to the wafer surface, and also helping to maintain anisotropy during the etching process. By setting the current ratio of the upper electrode to the lower electrode to 0.4–0.6, the plasma can form a more uniform distribution in the process chamber, avoiding excessively high or low local plasma density, thereby preventing excessive tilting or concavity of the sidewalls of the antireflective layer 102 and obtaining a near-vertical sidewall morphology.

[0058] In the etching step of the antireflective layer 102, oxygen with a flow rate of 20-40 sccm is introduced as the main etching gas, which can reduce oxygen consumption while ensuring high etching efficiency of the antireflective layer 102. Argon with a flow rate of 30-60 sccm is introduced as the bombardment gas, which helps to control the morphology of the sidewalls of the antireflective layer 102, reduce tilting and depression, and ensure etching accuracy and consistency. Nitrogen with a flow rate of 30-60 sccm is introduced as the dilution gas, which can remove byproducts in the etching process.

[0059] Specifically, the main components of the anti-reflective layer 102 are C and N. The main reactions that occur during the etching step of the anti-reflective layer 102 are as follows:

[0060] C + O₂ → CO₂↑ (1)

[0061] N + O2 → NO2↑ (2)

[0062] In other words, the main byproducts generated in the anti-reflective layer 102 etching step are CO2 and NO2, which can be carried away by the dilution effect of nitrogen.

[0063] By setting the etching time of the anti-reflective layer 102 to 15–50 seconds, it is possible to ensure that the anti-reflective layer 102 is fully opened to expose the first dielectric layer 103. The etching time of the anti-reflective layer 102 can be controlled by an EPD (End Point Detection) system.

[0064] Step S400: Deposition step, wherein the process gas used in the deposition step includes methane.

[0065] By adding a deposition step after the etching step of the antireflective layer 102, and using methane as the process gas, the methane decomposes into carbon and hydrogen free radicals in a plasma environment, forming an amorphous carbon film. Because the weak point regions are relatively sparse while the conventional point regions are relatively dense, the amorphous carbon film formed above is more easily deposited on top of the weak point regions, increasing the thickness of the antireflective layer 102 and causing an angled phenomenon, specifically as follows... Figure 5 (c) and Figure 6 As shown in (c), a first carbon-containing sacrificial layer 201 is formed at a conventional point, and a second carbon-containing sacrificial layer 202 is formed at a weak point, wherein the thickness of the second carbon-containing sacrificial layer 202 is greater than the thickness of the first carbon-containing sacrificial layer 201.

[0066] When etching the aforementioned semiconductor device, the vertical incident direction of the plasma will produce a shadowing effect due to the tilted sidewalls, making it easier for the plasma to bombard the bottom of the trench rather than the sidewalls. This increases the lateral etching rate, thereby increasing the critical dimension at the bottom of the trench. In other words, it increases the critical dimension at the bottom of the weak point region, thus expanding the process window after rework to ensure that there will be no deviation when etching the vertical interconnect channel in the future, thereby improving the yield after rework.

[0067] like Figure 7 As shown in (a), the yield of the semiconductor device is 96.8% without rework; it is 83.5% without methane deposition and after rework; and it is 96.7% after methane deposition and rework. That is, by adding a deposition step after the anti-reflective layer 102 etching step, the critical dimension at the bottom of the weak point trench can be increased, expanding the process window after rework and making the yield after rework almost no longer decrease.

[0068] Please continue to refer to Figure 5 (c) and Figure 6 As shown in (c), after the deposition step, the critical dimensions of the trench bottom at the conventional points and the critical dimensions of the trench bottom at the weak points remain unchanged, still 40 nm and 230 nm, respectively.

[0069] In the above deposition step, the process pressure is 3–10 mtorr; the upper electrode power is 500–700 W, the lower electrode power is 0 V, the current ratio of the upper electrode to the lower electrode is 0.4–0.6; the flow rate of methane is 10–30 sccm; the process gas used in the deposition step also includes argon, with a flow rate of 100–150 sccm; the process time is 6–10 s.

[0070] By selecting a lower process pressure in the deposition step, it is helpful to reduce the collision frequency between gas molecules, thereby increasing the mean free path of the deposited ions, so that the deposited ions can reach the surface of the photoresist layer 101 more directly to form the first carbon-containing sacrificial layer 201 and the second carbon-containing sacrificial layer 202.

[0071] By using only the upper radio frequency (RF) and not the lower RF during the deposition step, plasma bombardment of the photoresist layer 101 can be prevented from deforming it, reducing damage and temperature rise to the photoresist layer 101 and maintaining its integrity. Furthermore, by setting the current ratio of the upper electrode to the lower electrode to 0.4–0.6, the plasma energy is prevented from becoming excessively high, thereby reducing lattice damage and surface modification of the semiconductor device caused by high-energy ions.

[0072] By setting the methane flow rate to 10–30 sccm, on the one hand, it can prevent the deposition efficiency from being too low due to the methane flow rate being too low as the main deposition gas, and on the other hand, it can also prevent the deposition rate from being too fast due to the methane flow rate being too high, thereby resulting in a large roughness in the first carbon-containing sacrificial layer 201 and the second carbon-containing sacrificial layer 202.

[0073] In the deposition step, the process gas also includes argon, which is used as a dilution gas at a flow rate of 100–150 sccm. By using argon at this flow rate as a dilution gas, it is possible to ensure that the main deposition gas, methane, is evenly distributed within the process chamber, avoiding excessively high or low local concentrations and thus ensuring good consistency in the deposition rate.

[0074] By setting the deposition step time to 6-10 seconds, it is possible to prevent the first carbon-containing sacrificial layer 201 and the second carbon-containing sacrificial layer 202 from being too thin due to a short deposition time. It is also possible to avoid the first carbon-containing sacrificial layer 201 and the second carbon-containing sacrificial layer 202 from being too thick due to a long deposition time, which would increase the time required to open the first carbon-containing sacrificial layer 201 and the second carbon-containing sacrificial layer 202 in the future.

[0075] like Figure 8 As shown, before the etching step of the antireflective layer 102, a photoresist layer 101 residual resist removal step may also be included; wherein, the process pressure is 3-10 mtorr; the upper electrode power is 200-500W, the lower electrode power is 10-30V, the current ratio of the upper electrode to the lower electrode is 0.55-0.7; the process gases include oxygen and argon, the oxygen flow rate is 5-10 sccm, and the argon flow rate is 50-100 sccm; the process time is 5-7s.

[0076] By adding a photoresist layer 101 residual removal step before the anti-reflective layer 102 etching step, photoresist burrs or fine debris appearing on the surface of the photoresist layer 101 due to development, pre-baking, and other environmental factors can be removed, ensuring that its top is horizontal and its sidewalls are vertical. By setting the process pressure to 3–10 mtorr, a moderate collision frequency between gas molecules is achieved, preventing excessively frequent molecular collisions due to excessive pressure from reducing reaction efficiency, and preventing uneven distribution of reactants due to excessively low pressure.

[0077] By setting the upper electrode power to 200–500 W, the plasma density and activity can be significantly improved, enabling more effective decomposition of organic molecules in the photoresist layer 101. By setting the lower electrode power to 10–30 V, the surface roughening caused by excessive bombardment can be avoided, ensuring the removal of residual adhesive while protecting the device structure. By setting the current ratio of the upper electrode to the lower electrode to 0.55–0.7, both high plasma energy density and excessive bombardment of the photoresist layer 101 by the lower electrode assembly can be ensured.

[0078] In the photoresist layer 101 residual adhesive removal step, the process gases include oxygen with a flow rate of 5-10 sccm and argon with a flow rate of 50-100 sccm. Oxygen, as an etching gas, can clean the slag on the photoresist layer 101 to remove burrs and fine debris. By setting the oxygen flow rate to 5-10 sccm, the waste of oxygen can be reduced while ensuring the effective removal of residual adhesive from the photoresist layer 101. Argon, as a bombardment gas, is also used to clean the slag on the photoresist layer 101. By setting the argon flow rate to 50-100 sccm, the removal efficiency of the slag can be ensured, thereby shortening the process time and improving production efficiency.

[0079] By setting the process time for removing residual photoresist from photoresist layer 101 to 5-7 seconds, it is possible to avoid incomplete removal of residual photoresist due to insufficient etching time, and also to avoid prolonged process time due to excessive etching time.

[0080] Please continue to refer to Figure 8 In this embodiment, after the deposition step, the method further includes: Figure 5 (d) and Figure 6 As shown in (d), the first dielectric layer 103 is etched; wherein, the process pressure is 3-10 mtorr; the upper electrode power is 300-600 W, the lower electrode power is 100-160 V, the current ratio of the upper electrode to the lower electrode is 0.4-0.6; the process gas includes carbon tetrafluoride and trifluoromethane, the flow rate of carbon tetrafluoride is 40-80 sccm, the flow rate of trifluoromethane is 20-40 sccm; the process time is 6-10 s.

[0081] In the etching step of the first dielectric layer 103, by setting the process pressure to 3 to 10 mtorr, the collisions between gas molecules can be reduced, thereby reducing energy dissipation and enabling high-energy ions to bombard the first dielectric layer 103 with higher energy, thus improving the etching efficiency of the first dielectric layer 103.

[0082] In the etching step of the first dielectric layer 103, carbon tetrafluoride with a flow rate of 40-80 sccm and trifluoromethane with a flow rate of 20-40 sccm are introduced as the main etching gases. The use of a larger flow rate of carbon tetrafluoride can increase the number of fluorine free radicals to ensure higher etching efficiency. The use of a smaller flow rate of trifluoromethane can form a protective layer on the sidewall of the first dielectric layer 103, reducing excessive etching of the sidewall and improving anisotropy during the etching process.

[0083] Specifically, the main reactions performed in the first dielectric layer 103 etching step are as follows:

[0084] SiO2 + 4F → SiF4↑ + O2↑ (3)

[0085] SiO2+2CF2→SiF4↑+2CO↑ (4)

[0086] By setting the power of the upper electrode of the first dielectric layer 103 to 300-600W, the fluorine radicals in the etching gas can be more fully dissociated, thereby improving the etching efficiency. By setting the power of the lower electrode to 100-160V, the plasma can be uniformly covered on the wafer surface, thus ensuring etching uniformity. By setting the current ratio of the upper electrode to the lower electrode to 0.4-0.6, the plasma can be more uniformly distributed in the process chamber, avoiding excessively high or low local plasma density, thereby preventing the sidewalls of the first dielectric layer 103 from tilting or sinking excessively during the etching process.

[0087] By setting the process time to 6 to 10 seconds, not only can the first dielectric layer 103 be fully opened to expose the metal hard mask layer 104, but also the efficiency can be avoided due to excessively long process time.

[0088] Specifically, please continue to refer to Figure 5 (c) and Figure 6 In step (c), after the first dielectric layer etching step 103, the critical dimension at the bottom of the trench at conventional points is increased to 48nm, which is higher than that in related technologies. Figure 1 (d) 46nm; the critical dimension at the bottom of the trench at the weak point is increased to 241nm, which is higher than that in related technologies. Figure 2 In (d), the 232nm process window is effectively expanded.

[0089] Please continue to refer to Figure 8In this embodiment, after the etching step of the first dielectric layer 103, the method further includes: Figure 5 (e) and Figure 6 As shown in (e), the metal hard mask layer is etched in 104 steps; the process pressure is 10–20 mtorr; the upper electrode power is 500–700 W, the lower electrode power is 60–100 V, and the current ratio of the upper electrode to the lower electrode is 0.4–0.6; the process gases include chlorine, methane, and argon, with a chlorine flow rate of 50–100 sccm, a methane flow rate of 30–50 sccm, and an argon flow rate of 100–200 sccm; the process time is 5–8 s.

[0090] By setting a metal hard mask layer 104 in a semiconductor device, subsequent metal layers can be etched in one step, avoiding multiple damages to the ultra-low dielectric constant material layer 106, and also improving the distortion and roughness in the metal interconnect process.

[0091] By increasing the process pressure to 10–20 mtorr, the ion energy can be reduced, thereby enhancing the chemical reaction during the etching process and improving the etching uniformity.

[0092] By setting the upper RF power to 500–700W, a higher plasma density can be provided, ensuring that the plasma can uniformly cover the entire wafer surface, thereby improving etching uniformity. By setting the lower electrode power to 60–100V, the plasma bombardment energy can be kept within a moderate range, avoiding material damage caused by excessive energy, while also ensuring etching efficiency. By setting the current ratio of the upper electrode to the lower electrode to 0.4–0.6, the plasma can form a more uniform distribution in the process chamber, avoiding excessively high or low local plasma density, thereby preventing the sidewalls of the metal hard mask layer 104 from tilting or sinking excessively during the etching process.

[0093] In the 104 etching step of the metal hard mask layer, chlorine gas with a flow rate of 50-100 sccm is introduced as the main etching gas. The volatile titanium tetrachloride and nitrogen gas are eventually generated and pumped away. The main reactions are as follows:

[0094] Ti3N4+6Cl2→3TiCl4↑+2N2↑ (5)

[0095] Methane with a flow rate of 30-50 sccm is used as an etching protective gas. Under the action of plasma, methane can react with substances such as titanium and oxygen in the process chamber to generate non-volatile byproducts that adhere to the sidewalls of the metal hard mask layer 104, thereby protecting the sidewalls of the metal hard mask layer 104 and preventing the sidewalls of the metal hard mask layer 104 from becoming concave.

[0096] By setting the methane flow rate to 30–50 sccm, on the one hand, it can prevent the byproduct thickness from being insufficient due to too low a methane flow rate, thus failing to provide adequate protection for the sidewalls of the metal hard mask layer 104. On the other hand, it can also prevent byproduct accumulation due to too high a methane flow rate, which would not only cause the titanium nitride etching to be non-perpendicular, but also increase the etching rate difference between sparse and dense patterned regions, thereby affecting the consistency of critical dimensions.

[0097] In the etching step 104 of the metal hard mask layer, argon gas with a flow rate of 100-200 sccm is also introduced as a dilution and bombardment gas, which helps to ensure etching efficiency and remove by-products from the material surface, thereby reducing the impact of deposits on etching uniformity.

[0098] By setting the process time to 5–8 seconds, sufficient etching of the metal hard mask layer 104 can be ensured.

[0099] Please continue to refer to Figure 8 Optionally, after the etching step of the metal hard mask layer 104, a first over-etching step may be included to fully expose the second dielectric layer 105; wherein the process time of the first over-etching step is 15% to 25% of the process time of the etching step of the metal hard mask layer 104.

[0100] By using the first over-etching step, the metal hard mask layer 104 that was not completely etched in the previous etching step can be etched again to ensure that the metal hard mask layer 104 is fully opened.

[0101] Specifically, the process conditions for the first etching step are the same as those for the etching step of the metal hard mask layer 104, only the process time is different.

[0102] It should be noted that in other embodiments, the effect of fully opening the metal hard mask layer 104 can also be achieved by optimizing the EPD algorithm in the etching step of the metal hard mask layer 104.

[0103] Please continue to refer to Figure 8 In this embodiment, after the etching step of the metal hard mask layer 104, the method further includes: Figure 5 (f) and Figure 6As shown in (f), in the second etching step, the second dielectric layer 105 is partially etched; wherein, the process pressure is 5-10 mtorr; the upper electrode power is 500-700 W, the lower electrode power is 60-100 V, and the current ratio of the upper electrode to the lower electrode is 0.4-0.6; the process gases include silicon tetrachloride, methane, nitrogen trifluoride, and chlorine, the flow rate of silicon tetrachloride is 80-150 sccm, the flow rate of methane is 10-20 sccm, the flow rate of nitrogen trifluoride is 100-300 sccm, and the flow rate of chlorine is 50-100 sccm; the process time is 6-10 s.

[0104] By setting the process pressure to 5–10 mtorr, compared to the 10–20 mtorr process pressure in the etching step of the metal hard mask layer 104, the decrease in pressure can increase the mean free path of the plasma, thereby increasing the bombardment energy of the plasma, thus increasing the etching rate of the second dielectric layer 105, and improving the plasma anisotropy, so that more plasma can move vertically downward to avoid etching the sidewalls of the metal hard mask layer 104.

[0105] By setting the power of the upper electrode to 500–700W, a higher plasma density can be provided, ensuring that the plasma can uniformly cover the entire wafer surface, thereby improving etching uniformity. By setting the power of the lower electrode to 60–100V, the bombardment energy of the plasma can be kept within a moderate range, avoiding material damage caused by excessive energy, while also ensuring etching efficiency. By setting the current ratio of the upper electrode to the lower electrode to 0.4–0.6, the plasma can form a more uniform distribution in the process chamber, avoiding excessively high or low local plasma density, thereby preventing the sidewalls of the second dielectric layer 105 from tilting or sinking excessively during the etching process.

[0106] In the second etching step, nitrogen trifluoride with a flow rate of 100-300 sccm and chlorine gas with a flow rate of 50-100 sccm are introduced as etching gases. By selecting a larger flow rate of nitrogen trifluoride, the etching rate can be increased; by selecting a smaller flow rate of chlorine gas, it is helpful to reduce metal residue and improve the cleanliness of the etched surface.

[0107] Silicon tetrachloride (80–150 sccm) and methane (10–20 sccm) are introduced as etching protective gases. Silicon tetrachloride decomposes in a plasma environment to produce chlorine atoms, which are highly chemically reactive and can react with the silicon surface to form a thin, relatively stable silicon chloride layer, providing some passivation protection. Methane decomposes in a plasma environment to produce carbon and hydrogen atoms. The carbon atoms can deposit on the surface to form a carbon-containing film, improving resistance to the etchant. By setting the methane flow rate lower than that of silicon tetrachloride, the thickness of the dense carbon-containing film can be reduced, avoiding prolonged etching time due to excessive carbon film deposition.

[0108] By setting the process time of the second etching step to 6 to 10 seconds, on the one hand, it can avoid the metal hard mask layer 104 from not being fully opened due to a short etching time, and on the other hand, it can also avoid the second dielectric layer 105 from being over-etched due to a long etching time.

[0109] Please continue to refer to Figure 5 (f) and Figure 6 In (f), after the second etching step, the critical dimension at the bottom of the trench at the conventional point becomes 56nm, which is larger than that in related technologies. Figure 1 The 54nm in the middle (f) section; the critical dimension at the bottom of the trench at the weak point becomes 249nm, which is larger than that in related technologies. Figure 2 The 235nm process window in (f) is significantly expanded.

[0110] Please continue to refer to Figure 8 In this embodiment, the etching method may further include step S900: a residual material removal step, used to remove the remaining photoresist layer 101 and the remaining antireflective layer 102; wherein, the process pressure is 10-20 mtorr; the upper electrode power is 1000-1500 W, the lower electrode power is 80-150 V, and the current ratio of the upper electrode to the lower electrode is 0.4-0.6; the process gas includes oxygen and nitrogen, the oxygen flow rate is 100-300 sccm, and the nitrogen flow rate is 30-80 sccm; the process time is 30-50 s.

[0111] Please continue to refer to Figure 5 (f) and Figure 6In step (f), after the second etching step, since a second dielectric layer 105 remains on top of the ultra-low dielectric constant material layer 106, and the second dielectric layer 105 protects the ultra-low dielectric constant material layer 106, oxygen can be used to etch the remaining photoresist layer 101 and anti-reflection layer 102 without causing damage to the ultra-low dielectric constant material layer 106 and affecting device performance. By setting the oxygen flow rate to 100–300 sccm, etching efficiency can be ensured while reducing oxygen waste. Furthermore, in this step, nitrogen gas at 30–80 sccm is introduced as a dilution gas to remove byproducts generated during the etching process.

[0112] In step S900, by setting the process pressure to 10-20 mtorr, the ion energy can be reduced, thereby enhancing the chemical action during the etching process and improving the etching uniformity of the photoresist layer 101 and the anti-reflection layer 102. This ensures that the remaining photoresist layer 101 and anti-reflection layer 102 in various parts of the device can be effectively removed.

[0113] By setting the power of the upper electrode to 1000–1500W, a denser and higher-energy plasma can be generated to improve the etching rate; by setting the power of the lower electrode to 80–150V, the ion energy can be kept in a medium to high range to enhance the anisotropy during the etching process; by setting the current ratio of the upper electrode to the lower electrode to 0.4–0.6, the plasma can be more uniformly distributed in the process chamber, avoiding excessively high or low local plasma density.

[0114] In step S900, by setting the process time to 30-50s, the etching effect on the photoresist layer 101 and the anti-reflection layer 102 can be guaranteed, and the residue of the photoresist layer 101 and the anti-reflection layer 102 can be avoided.

[0115] like Figure 9 As shown, this embodiment also provides a semiconductor process apparatus 200, including a process chamber 20, an air intake assembly 20A, an upper electrode assembly 20B, a lower electrode assembly 20C, and a controller. The controller includes at least one processor and at least one memory, in which a computer program is stored. When the computer program is executed by the processor, it implements the above-described etching method.

[0116] The semiconductor process equipment 200 is capable of performing the above-mentioned etching method. Accordingly, the semiconductor process equipment 200 has all the advantages of the above-mentioned etching method, which will not be elaborated here.

[0117] For example, the controller can be a host computer or a slave computer. The controller can open the valve of the inlet assembly 20A to introduce the corresponding process gas into the process chamber 20; the controller can also control the flow rate of the process gas by controlling the opening degree of the valve of the inlet assembly 20A. The controller can also control the evacuation assembly 20D to evacuate the process chamber 20, for example, by controlling the valve opening degree of the evacuation assembly 20D or the speed of the evacuation pump, to control the pressure inside the process chamber 20 and remove reaction byproducts.

[0118] The upper electrode assembly 20B may include an RF coil 21, an upper RF power supply 23, and an upper matching unit 25. The controller is also used to control the upper RF power supply 23 to provide upper RF power to the RF coil 21 through the upper matching unit 25, so that the RF coil 21 excites the process gas inside the process chamber 20 to generate plasma 100.

[0119] The lower electrode assembly 20C may include a wafer carrier 22, a lower RF power supply 24, and a lower matching unit 26. The controller is also configured to control the lower RF power supply 24 to provide lower RF power to the wafer carrier 22 through the lower matching unit 26 to provide RF bias. The wafer carrier 22 may be an electrostatic chuck, a mechanical chuck, or a vacuum suction chuck.

[0120] The semiconductor process equipment 200 in this embodiment can be an ICP (Inductively Coupled Plasma) etching machine. The frequency of the upper RF power supply 23 and the frequency of the lower RF power supply 24 are 13.56MHz. The power application method is continuous wave. During the process, the temperature of the electrostatic chuck is 25-40°C, the electrostatic adsorption voltage is 2200-2600V, and the helium pressure on the back of the wafer is 6-10 Torr.

[0121] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

[0122] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the term "comprising" or any other variations thereof is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0123] In the above embodiments, descriptions of directions such as "up", "down", and "side" are based on the accompanying drawings.

[0124] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An etching method, characterized in that, include: A semiconductor device is provided, the semiconductor device comprising a photoresist layer (101), an anti-reflection layer (102), a first dielectric layer (103), a metal hard mask layer (104), a second dielectric layer (105), and an ultra-low dielectric constant material layer (106) stacked sequentially. The anti-reflection layer (102) etching step involves etching the anti-reflection layer (102) using the photoresist layer (101) as a mask, thereby exposing the first dielectric layer (103); and A deposition step is used to increase the thickness of the antireflective layer (102) and to introduce an angular tilt, wherein the process gas used in the deposition step includes methane.

2. The etching method according to claim 1, characterized in that, In the deposition step, the process pressure is 3–10 mtorr; the upper electrode power is 500–700 W, the lower electrode power is 0 V, and the current ratio of the upper electrode to the lower electrode is 0.4–0.6; the methane flow rate is 10–30 sccm; the process gas used in the deposition step also includes argon, with an argon flow rate of 100–150 sccm; and the process time is 6–10 s.

3. The etching method according to claim 1, characterized in that, Before the etching step of the antireflective layer (102), the process further includes: a photoresist layer (101) residual adhesive removal step; wherein, the process pressure is 3 to 10 mtorr; the upper electrode power is 200 to 500 W, the lower electrode power is 10 to 30 V, the current ratio of the upper electrode to the lower electrode is 0.55 to 0.7; the process gas includes oxygen and argon, the oxygen flow rate is 5 to 10 sccm, the argon flow rate is 50 to 100 sccm; and the process time is 5 to 7 s.

4. The etching method according to claim 1, characterized in that, In the etching step of the anti-reflective layer (102), the process pressure is 3-10 mtorr; the upper electrode power is 500-700 W, the lower electrode power is 30-60 V, and the current ratio of the upper electrode to the lower electrode is 0.4-0.6; the process gases include oxygen, argon and nitrogen, the oxygen flow rate is 20-40 sccm, the argon flow rate is 30-60 sccm, and the nitrogen flow rate is 30-60 sccm; the process time is 15-50 s.

5. The etching method according to claim 1, characterized in that, Following the deposition step, the process further includes: a first dielectric layer (103) etching step; wherein the process pressure is 3-10 mtorr; the upper electrode power is 300-600 W, the lower electrode power is 100-160 V, and the current ratio of the upper electrode to the lower electrode is 0.4-0.6; the process gas includes carbon tetrafluoride and trifluoromethane, the flow rate of carbon tetrafluoride is 40-80 sccm, and the flow rate of trifluoromethane is 20-40 sccm; the process time is 6-10 s.

6. The etching method according to claim 5, characterized in that, After the first dielectric layer (103) etching step, the process further includes: a metal hard mask layer (104) etching step; wherein, the process pressure is 10-20 mtorr; the upper electrode power is 500-700 W, the lower electrode power is 60-100 V, and the current ratio of the upper electrode to the lower electrode is 0.4-0.6; the process gases include chlorine, methane, and argon, the flow rate of chlorine is 50-100 sccm, the flow rate of methane is 30-50 sccm, and the flow rate of argon is 100-200 sccm; the process time is 5-8 s.

7. The etching method according to claim 6, characterized in that, After the etching step of the metal hard mask layer (104), the process further includes: a first over-etching step to completely expose the second dielectric layer (105); the process time of the first over-etching step is 15% to 25% of the process time of the etching step of the metal hard mask layer (104).

8. The etching method according to claim 6, characterized in that, Following the etching step of the metal hard mask layer (104), the process further includes a second over-etching step to partially etch the second dielectric layer (105); wherein the process pressure is 5-10 mtorr; the upper electrode power is 500-700 W, the lower electrode power is 60-100 V, and the current ratio of the upper electrode to the lower electrode is 0.4-0.6; the process gases include silicon tetrachloride, methane, nitrogen trifluoride, and chlorine, the flow rate of silicon tetrachloride is 80-150 sccm, the flow rate of methane is 10-20 sccm, the flow rate of nitrogen trifluoride is 100-300 sccm, and the flow rate of chlorine is 50-100 sccm; and the process time is 6-10 s.

9. The etching method according to claim 8, characterized in that, Following the etching step, the process further includes a residual material removal step, used to remove the remaining photoresist layer (101) and the remaining antireflective layer (102); wherein the process pressure is 10-20 mtorr; the upper electrode power is 1000-1500 W, the lower electrode power is 80-150 V, and the current ratio of the upper electrode to the lower electrode is 0.4-0.6; the process gases include oxygen and nitrogen, the oxygen flow rate is 100-300 sccm, and the nitrogen flow rate is 30-80 sccm; the process time is 30-50 s.

10. A semiconductor process apparatus, comprising a process chamber (20), an inlet assembly (20A), an upper electrode assembly (20B), a lower electrode assembly (20C), and a controller, characterized in that, The controller includes at least one processor and at least one memory, the memory storing a computer program that, when executed by the processor, implements the etching method as described in any one of claims 1-9.

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